JP2011119027A - Thin film magnetic material storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin-film magnetic material storage device that simultaneously and stably transfers multi-bit data. <P>SOLUTION: The thin-film magnetic material storage device includes N memory banks MB1 to MBN, M (M>N) data read circuits RDV1 to RDVM and M data write circuits WDV1 to WDVM. During data read, each of the data read circuits RDV1 to RDVM operates to read M-bit data in parallel. During data write, only N of the M data read circuits RDV1 to RDVM operate to write N-bit data in parallel. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a thin film magnetic memory device, and more particularly to a random access memory including a memory cell having a magnetic tunnel junction (MTJ).

  An MRAM (Magnetic Random Access Memory) device has attracted attention as a storage device that can store nonvolatile data with low power consumption. An MRAM device is a storage device that performs non-volatile data storage using a plurality of thin film magnetic bodies formed in a semiconductor integrated circuit and allows random access to each of the thin film magnetic bodies.

  In particular, in recent years, it has been announced that the performance of an MRAM device will be dramatically improved by using a thin film magnetic material using a magnetic tunnel junction (MTJ) as a memory cell. For MRAM devices with memory cells with magnetic tunnel junctions, see “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC Digest of Technical Papers, TA7.2, Feb 2000. and “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, TA7.3, Feb. 2000.

  FIG. 14 is a schematic diagram showing a configuration of a memory cell having a magnetic tunnel junction (hereinafter also simply referred to as “MTJ memory cell”).

  Referring to FIG. 14, the MTJ memory cell forms a tunnel magnetoresistive element TMR whose electrical resistance changes according to the stored data level and a path of sense current Is passing through tunnel magnetoresistive element TMR during data reading. Access transistor ATR. Access transistor ATR is formed of a field effect transistor, for example, and is coupled between tunneling magneto-resistance element TMR and a fixed voltage (ground voltage Vss).

  For MTJ memory cells, a write word line WWL for instructing data writing, a read word line RWL for executing data reading, and a data level of stored data at the time of data reading and data writing A bit line BL, which is a data line for transmitting an electrical signal corresponding to, is arranged.

  FIG. 15 is a conceptual diagram illustrating a data read operation from the MTJ memory cell. Referring to FIG. 15, tunneling magneto-resistance element TMR includes a ferromagnetic layer (hereinafter, also simply referred to as “fixed magnetization layer”) FL having a certain magnetization direction and a direction corresponding to a magnetic field applied from the outside. And a ferromagnetic layer (hereinafter also simply referred to as “free magnetic layer”) VL. A tunnel barrier TB formed of an insulating film is provided between the fixed magnetic layer FL and the free magnetic layer VL. Free magnetic layer VL is magnetized in the same direction as the fixed magnetic layer or in a different direction from fixed magnetic layer FL, depending on the data level of the stored data.

  At the time of data reading, access transistor ATR is turned on in response to activation of read word line RWL. As a result, the sense current Is can flow through the current path of the bit line BL, the tunnel magnetoresistive element TMR, the access transistor ATR, and the ground voltage Vss.

  The electric resistance of tunneling magneto-resistance element TMR changes according to the relative relationship between the magnetization directions of fixed magnetic layer FL and free magnetic layer VL. Specifically, when the magnetization direction of the fixed magnetization layer FL and the magnetization direction written in the free magnetization layer VL are parallel to each other, the tunnel magnetoresistance is compared to the case where the magnetization directions of both are opposite directions. The electric resistance of the element TMR is reduced. Hereinafter, in this specification, the electric resistances of tunneling magneto-resistance elements TMR corresponding to the stored data “1” and “0”, respectively, are denoted by R1 and R0, respectively. However, it is assumed that R1> R0.

  Thus, the tunnel magnetoresistive element TMR changes its electric resistance according to the magnetization direction. Therefore, data storage can be executed by associating the two magnetization directions of free magnetic layer VL in tunneling magneto-resistance element TMR with the levels (“1” and “0”) of stored data.

  The voltage change caused in the tunnel magnetoresistive element TMR by the sense current Is differs depending on the magnetization direction of the free magnetic layer, that is, the stored data level. Therefore, for example, if the sense current Is is passed through the tunnel magnetoresistive element TMR after the bit line BL is precharged to a constant voltage, the stored data of the MTJ memory cell is detected by detecting the change in the voltage level of the bit line BL. Can be read out.

FIG. 16 is a conceptual diagram illustrating a data write operation for the MTJ memory cell.
Referring to FIG. 16, at the time of data writing, read word line RWL is inactivated and access transistor ATR is turned off. In this state, a data write current for magnetizing free magnetic layer VL in the direction corresponding to the write data is supplied to write word line WWL and bit line BL. The magnetization direction of free magnetic layer VL is determined by the combination of the directions of data write currents flowing through write word line WWL and bit line BL, respectively.

  FIG. 17 is a conceptual diagram illustrating the relationship between the direction of data write current and the magnetization direction during data writing.

  Referring to FIG. 17, horizontal axis Hx represents the direction of data write magnetic field H (BL) generated by the data write current flowing through bit line BL. On the other hand, the vertical axis Hy represents the direction of the data write magnetic field H (WWL) generated by the data write current flowing through the write word line WWL.

  The magnetization direction of the free magnetic layer VL is newly rewritten only when the sum of the data write magnetic fields H (BL) and H (WWL) reaches a region outside the asteroid characteristic line shown in the figure. Can do.

  That is, when the applied data write magnetic field has a strength corresponding to the region inside the asteroid characteristic line, the magnetization direction of the free magnetic layer VL does not change. Therefore, in order to update the storage data of the MTJ memory cell, it is necessary to pass a current of a predetermined level or more to both the write word line WWL and the bit line BL. The magnetization direction once written in the tunnel magnetoresistive element, that is, data stored in the MTJ memory cell is held in a nonvolatile manner until new data writing is executed.

  Even during data reading, sense current Is flows through bit line BL. However, since the sense current Is is generally set to be about 1 to 2 digits smaller than the data write current described above, the stored data in the MTJ memory cell is erroneously read at the time of data reading due to the influence of the sense current Is. The possibility of rewriting is small.

  The above-described technical literature discloses a technique for forming a random access memory MRAM device by integrating such MTJ memory cells on a semiconductor substrate.

FIG. 18 is a conceptual diagram showing MTJ memory cells integrated and arranged in a matrix.
By arranging MTJ memory cells in a matrix on a semiconductor substrate, a highly integrated MRAM device can be realized. FIG. 18 shows a configuration in which MTJ memory cells are arranged in n rows × m columns (n, m: natural numbers). As already described, it is necessary to arrange the bit line BL, the write word line WWL, and the read word line RWL for each MTJ memory cell. Therefore, n write word lines WWL1 to WWLn and read word lines RWL1 to RWLn and m bit lines BL1 to BLm are arranged for n × m MTJ memory cells arranged in a matrix. The

  The supply of the data read current at the time of data read, that is, the sense current Is is executed by the data read circuit 500 arranged adjacent to the memory array. Data read circuit 500 includes a current supply unit 510 shared by bit lines BL1 to BLm, a data bus DB, and column selection gates CSG1 to CSGm provided corresponding to the memory cell columns, respectively.

  The current supply unit 510 supplies the sense current Is to the data bus DB. Data bus DB is coupled to bit lines BL1-BLm via column selection gates CSG1-CSGm.

  Column selection lines CSL1 to CSLm are provided corresponding to the memory cell columns, respectively, and are selectively activated according to the column selection result. Similarly, one of read word lines RWL1 to RWLn that is selected according to the row selection result is selectively activated. A combination of such a row selection result and a column selection result designates a selected memory cell that is a data read target.

  With this configuration, the current supply unit 510 shared by the entire memory array 10 selectively supplies the sense current Is to the bit line pulled down by the selected memory cell, so that the selected memory cell Sense current Is can be passed through tunneling magneto-resistance element TMR. As a result, the data stored in the selected memory cell can be read by detecting the voltage change of the data bus DB.

Roy Scheuerlein and 6 others, “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Using FET Switches and Magnetic Tunnel Junctions in Each Cell Junction and FET Switch in each Cell), (USA), 2000 IEICE International Solid Circuit Conference and Technical Papers TA7.2 (2000 IEEE ISSCC Digest of Technical Papers, TA7.2), p. 128-129 D. Durlam and five others, “Nonvolatile RAM based on Magnetic Tunnel Junction Elements” (USA), 2000 International Solid State Circuit Conference / Technology of the Institute of Electrical and Electronics Engineers, 2000 Proceedings TA7.3 (2000 IEEE ISSCC Digest of Technical Papers, TA7.3), p. 130-131

  However, the tunnel magnetoresistive element in the MTJ memory cell is a resistor having a relatively high electric resistance of about 10 KΩ. On the other hand, the data bus DB arranged so as to be shared by the entire memory array 10 has a relatively large parasitic capacitance. Therefore, as shown in FIG. 18, in the configuration in which the selected memory cell is coupled to data bus DB via bit line BL and data reading is performed by detecting the voltage change of data bus DB, the sense current Is path This increases the RC time constant, which may hinder the speed of data reading.

  Further, in order to pass the sense current Is to the selected MTJ memory cell, it is necessary to apply a bias voltage across the tunnel magnetoresistive element TMR as shown in FIG. However, if this bias voltage is large, an excessive electric field acts on the tunnel barrier TB to cause breakdown of the insulating film, which may impair the reliability of the MTJ memory cell.

  On the other hand, in recent years, memory devices are required to handle multi-bit data simultaneously in parallel. Typically, in a data processing field or the like, a memory applied to a system LSI (Large Scale Integrated Circuit) integrated on the same semiconductor chip as a logic such as a processor in order to process data at high speed and with low power consumption The apparatus is required to execute data exchange with the logic in a multi-bit / parallel manner.

  However, in the data writing to the MRAM device, since it is necessary to generate a data write magnetic field for rewriting the magnetization direction of the MTJ memory cell, it is necessary to pass a relatively large current through the bit line BL and the write word line WWL. is there. Therefore, when the MRAM device is applied to such a system LSI, if the multi-bit data is simply written in parallel, the current consumption, especially the peak current value becomes excessive, and therefore the power supply system And the risk of malfunction may occur due to the influence of fluctuations in the power supply voltage.

  The present invention has been made to solve such problems, and an object of the present invention is to provide a configuration of a thin-film magnetic memory device that achieves both high reliability of MTJ memory cells and high-speed data reading. Is to provide.

  Another object of the present invention is to provide a configuration of a thin film magnetic memory device that stably performs multi-bit data exchange at the same time.

  A thin film magnetic memory device according to the present invention includes a plurality of memory cells each for holding stored data. Each memory cell includes a magnetic memory portion whose electrical resistance changes according to the level of stored data, and an access gate that is selectively turned on at the time of data reading. A thin film magnetic memory device includes a decoding unit for designating a selected memory cell selected as a data read or data write target from a plurality of memory cells according to an address signal, and a predetermined section of the plurality of memory cells. The bit line coupled to the first voltage via the magnetic memory portion of the selected memory cell in response to the turn-on of the access gate of the selected memory cell at the time of data reading, and the bit at the time of data reading A bit line driver for electrically coupling the line to a second voltage determined such that the applied voltage across the selected memory cell is less than or equal to a predetermined voltage, and is shared by the plurality of memory cells; Driving power corresponding to the voltage of the read data line for transmitting read data from the selected memory cell and the voltage of the read data line in accordance with the voltage of the bit line coupled to the selected memory cell Therefore, further comprising a read gate circuit for driving the fixed voltage, the voltage of the read data lines to detect and amplify the data read circuit for generating read data.

  Preferably, the magnetic storage unit includes a fixed magnetization layer having a fixed magnetization direction, a free magnetization layer magnetized in a direction according to a level of stored data by a magnetic field generated by a data write current, and a fixed magnetization layer And a free magnetic layer, and a tunnel film layer for allowing a data read current to pass therethrough. The electric resistance changes according to the relative relationship between the magnetization directions of the fixed magnetic layer and the free magnetic layer, and the predetermined voltage is determined in consideration of the reliability of the tunnel film layer.

  Preferably, the plurality of memory cells are arranged in a matrix, and a bit line is provided for each column of the plurality of memory cells. The bit line driving unit includes a column selection gate provided for each column and electrically coupled between the corresponding bit line and the second voltage, and the column selection gate is in accordance with an instruction from the decoding circuit. ON when the corresponding column includes the selected memory cell.

  Preferably, the plurality of memory cells are arranged in a matrix, and the bit line is provided for each column of the plurality of memory cells. A thin-film magnetic memory device is provided for each column, a write data line for transmitting a data write current, a data write circuit for supplying a data write current to the write data line, and each column When a column to be included includes a selected memory cell, a write column select gate for electrically coupling a corresponding bit line with a write data line is further provided. The bit line driver has a pull-up circuit for coupling the write data line and the second voltage at the time of data reading. The pull-up circuit disconnects the write data line and the second voltage at the time of data writing.

  Alternatively, preferably, the data read circuit operates by being supplied with the third voltage, and the third voltage is higher than the second voltage.

  Preferably, the first voltage is a ground voltage, and the bit line is precharged to the ground voltage before data reading. .

  A thin film magnetic memory device according to another configuration of the present invention includes a plurality of memory cells each for holding stored data. Each memory cell is magnetized in a direction corresponding to the level of stored data by a magnetic field generated by a data write current, and a magnetic memory portion whose electric resistance changes according to the direction of magnetization, and is selectively selected at the time of data reading And an access gate that turns on. The thin film magnetic memory device includes a decoding unit for selecting a selected memory cell selected for data reading or data writing from a plurality of memory cells in accordance with an address signal, and an electric power corresponding to the level of stored data. A first voltage is arranged for each predetermined section of a plurality of memory cells for transmitting a signal, and at the time of data reading, in response to turn-on of an access gate of the selected memory cell, the first voltage is passed through the magnetic memory portion of the selected memory cell. A bit line coupled to the second voltage, and a bit line driver for electrically coupling to a second voltage determined so that an applied voltage across the selected memory cell is equal to or lower than a predetermined voltage during data reading A read data line for transmitting read data from the selected memory cell, which is shared by the plurality of memory cells, and a voltage of the read data line are selected with the selected memory cell. A read gate circuit for driving to a fixed voltage with a driving force according to the voltage of the combined bit line, a data read circuit for detecting and amplifying the voltage of the read data line to generate read data, and A data write circuit that operates by receiving a third voltage higher than the voltage of 2 and supplies a data write current to the bit line corresponding to the selected memory cell at the time of data writing; Prepare.

  Preferably, the magnetic memory unit includes a fixed magnetization layer having a fixed magnetization direction, a free magnetization layer magnetized in a direction according to a magnetic field generated by the data write current, and a fixed magnetization layer and a free magnetization layer. And a tunnel film layer for allowing a data read current to pass therethrough. The electric resistance changes according to the relative relationship between the magnetization directions of the fixed magnetic layer and the free magnetic layer, and the predetermined voltage is determined in consideration of the reliability of the tunnel film layer.

  Preferably, an external power supply voltage supplied from the outside of the thin film magnetic memory device is directly applied as the third voltage.

  Alternatively, preferably, the data read circuit operates by being supplied with the fourth voltage, and the fourth voltage is lower than the third voltage and higher than the second voltage.

A thin film magnetic memory device according to still another configuration of the present invention includes a plurality of memory cells arranged in a matrix. Each memory cell is magnetized in a direction according to the level of stored data by a magnetic field generated by a data write current, and a magnetic memory unit whose electric resistance changes according to the direction of magnetization, and selectively at the time of data reading And an access gate for turning on and allowing a data read current to flow through the magnetic memory portion. The thin film magnetic memory device further includes a plurality of bit lines respectively arranged corresponding to the memory cell columns for transmitting an electrical signal corresponding to the level of stored data, and each of the selected memory cells A plurality of read data lines for transmitting read data between them, a plurality of write data lines for transmitting write data to and from each selected memory cell, and a plurality of read data lines for data reading And a control circuit for instructing parallel data reading of M bits (M: an integer of 2 or more) using at least a part of the read data lines. At the time of data writing, the control circuit instructs parallel data writing of N bits (N: a natural number represented by N <M) using a part of the plurality of write data lines.

  Preferably, the plurality of read data lines and the plurality of write data lines are arranged in a direction along the plurality of bit lines.

  Alternatively, preferably, the plurality of read data lines and the plurality of write data lines are arranged in the same number, and each read data line and each write data line use a data bus arranged for each predetermined section of the plurality of memory cells. Thus, they are formed as the same wiring. The thin-film magnetic memory device is further provided for each data bus, provided for each data bus, selectively activated at the time of data reading, and for reading data in accordance with the voltage of the data bus. And a data write circuit which is selectively activated at the time of data writing and supplies a data write current to the corresponding data bus. The control circuit activates M data read circuits when reading data and selectively activates N data write circuits when writing data.

  More preferably, a total of M data buses are arranged. The control circuit activates each data reading circuit at the time of data reading and selectively activates N of the M data writing circuits at the time of data writing.

  Preferably, each of the plurality of read data lines is arranged for each of K (K: integer of 2 or more) memory cell columns, and each of the plurality of write data lines is L (L: L> K). (Integer shown) is arranged for each memory cell column. The control circuit activates M data read circuits when reading data and activates N data write circuits when writing data.

  More preferably, a plurality of write data lines are arranged in total, M a plurality of read data lines are arranged in total, and the control circuit activates each data read circuit during data reading, Each data writing circuit is activated at the time of data writing.

  Preferably, the M bit is an integer multiple of N bits, and the control circuit instructs to write N bits in parallel (M / N) times in response to one data write command. To do.

  The thin film magnetic memory device according to claim 1 and 2 does not include a read data line having a large parasitic capacitance in a path of a data read current flowing through the selected memory cell, and a read data line (read gate) is formed by a read gate circuit (read gate). Since the potential of the read data bus) is driven, the RC load on the sense current path can be reduced. Furthermore, since the voltage applied to both ends of the magnetic memory portion (tunnel magnetoresistive element) in the MTJ memory cell is suppressed to a predetermined voltage or less in consideration of the reliability of the tunnel film layer (tunnel barrier), the MTJ memory cell It is possible to increase the speed of data reading while ensuring operation reliability.

  Since the thin film magnetic memory device according to claim 3 selectively drives only the bit line corresponding to the selected column, the power consumption can be reduced in addition to the effect exhibited by the thin film magnetic memory device according to claim 1. .

  The thin film magnetic memory device according to claim 4 can selectively drive only the bit line corresponding to the selected column at the time of data reading by sharing a column selection gate for executing column selection at the time of data writing. Therefore, in addition to the effect exhibited by the thin film magnetic memory device according to the first aspect, it is possible to reduce the power consumption and the chip area.

  The thin film magnetic memory device according to the fifth aspect can increase the amplitude voltage of the read data line and increase the data reading speed in addition to the effect exhibited by the thin film magnetic memory device according to the first aspect.

  The thin film magnetic memory device according to a sixth aspect of the invention reduces the current consumption by preventing the generation of the discharge current in the bit line of the non-selected column in addition to the effect exhibited by the thin film magnetic memory device according to the first aspect. Can be planned.

  The thin film magnetic memory device according to claim 7 and 8 includes a read data line (read gate) by a read gate circuit (read gate) without including a read data line having a large parasitic capacitance in a path of a data read current flowing through the selected memory cell. Since the potential of the read data bus) is driven, the RC load on the sense current path can be reduced. Further, the voltage applied to both ends of the magnetic memory unit (tunnel magnetoresistive element) in the MTJ memory cell is suppressed to a predetermined voltage or less in consideration of the reliability of the tunnel film layer (tunnel barrier), while data writing is performed. The power supply voltage of the circuit is set high to supply a sufficient data write current. Therefore, it is possible to increase the speed of data writing and data reading while ensuring the operational reliability of the MTJ memory cell.

  The thin film magnetic memory device according to claim 9 can efficiently supply the power supply voltage of the data write circuit, in addition to the effect exhibited by the thin film magnetic memory device according to claim 7.

  The thin film magnetic memory device according to the tenth aspect can increase the voltage amplitude of the read data line and increase the data reading speed in addition to the effect exhibited by the thin film magnetic memory device according to the seventh aspect.

  15. The thin film magnetic memory device according to claim 11 can read a plurality of bits of data in parallel at the time of data reading, while the number of parallel writing bits at the time of data writing is smaller than that at the time of data reading. Also set a smaller value. Therefore, a configuration suitable for a system LSI or the like mixed on the same chip as the logic can be obtained, and an increase in peak current consumption during data writing can be suppressed to stabilize the operation.

  The thin film magnetic memory device according to the fifteenth aspect can reduce the chip area because the number of data write circuits can be reduced in addition to the effect of the thin film magnetic memory device according to the eleventh aspect.

  In the thin film magnetic memory device according to claim 16, in addition to the effect exerted by the thin film magnetic memory device according to claim 15, it is not necessary to perform selection control of activation in the data write circuit and the data read circuit. The configuration of the control circuit can be simplified.

  The thin film magnetic memory device according to claim 17 has the effect of the thin film magnetic memory device according to claim 11 in addition to the word length (number of bits) of one data read command and one data write. The command word length (number of bits) can be aligned.

1 is a schematic block diagram showing an overall configuration of an MRAM device 1 according to an embodiment of the present invention. FIG. 3 is a circuit diagram for illustrating in detail a configuration according to the first embodiment of the memory array and its peripheral circuits. FIG. 3 is a circuit diagram showing a configuration of a data reading circuit shown in FIG. 2. FIG. 4 is a circuit diagram showing another configuration example of the data read circuit shown in FIG. 2. FIG. 3 is a circuit diagram showing a configuration of a data write circuit shown in FIG. 2. 5 is a timing chart for illustrating data read and data write operations in the MRAM device according to the first embodiment. FIG. 7 is a circuit diagram for illustrating in detail a configuration according to a modification of the first embodiment of the memory array and its peripheral circuits. FIG. 8 is a circuit diagram illustrating a configuration of a data write circuit shown in FIG. 7. 6 is a timing chart illustrating a data write operation and a data read operation according to a modification of the first embodiment. It is a schematic block diagram explaining the structure according to Embodiment 2 of a memory array and its peripheral circuit. FIG. 11 is a circuit diagram illustrating an arrangement of data bus pairs shown in FIG. 10. 5 is a timing chart illustrating operation control of the data read circuit and the data write circuit by the control circuit. FIG. 12 is a schematic block diagram showing a configuration according to a modification of the second embodiment of the memory array and its peripheral circuits. It is the schematic which shows the structure of an MTJ memory cell. It is a conceptual diagram explaining the data read-out operation | movement from an MTJ memory cell. It is a conceptual diagram explaining the data write-in operation | movement with respect to an MTJ memory cell. It is a conceptual diagram explaining the relationship between the direction of the data write current at the time of data writing, and the magnetization direction. It is a conceptual diagram which shows the MTJ memory cell integratedly arranged by the matrix form.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol in a figure shall show the part which is the same or corresponds.

[Embodiment 1]
FIG. 1 is a schematic block diagram showing an overall configuration of MRAM device 1 according to the embodiment of the present invention.

  Referring to FIG. 1, MRAM device 1 performs random access in response to external control signal CMD and address signal ADD, and executes input of write data DIN and output of read data DOUT.

  The MRAM device 1 includes a control circuit 5 that controls the entire operation of the MRAM device 1 in response to a control signal CMD, and a memory array 10 having a plurality of MTJ memory cells arranged in a matrix. The configuration of the memory array 10 will be described in detail later. A plurality of write word lines WWL and read word lines RWL are arranged corresponding to MTJ memory cell rows (hereinafter also simply referred to as “memory cell rows”). . A bit line BL is arranged corresponding to a column of MTJ memory cells (hereinafter also simply referred to as “memory cell column”).

  The MRAM device 1 further includes a row decoder 20, a column decoder 25, a word line driver 30, a word line current control circuit 40, and read / write control circuits 50 and 60.

  Row decoder 20 performs row selection in memory array 10 in accordance with row address RA indicated by address signal ADD. Column decoder 25 performs column selection in memory array 10 in accordance with column address CA indicated by address signal ADD. The word line driver 30 selectively activates the read word line RWL or the write word line WWL based on the row selection result of the row decoder 20. A memory cell (hereinafter also referred to as “selected memory cell”) designated as a data read or data write target is indicated by row address RA and column address CA.

  The word line current control circuit 40 is provided for supplying a data write current to the write word line WWL during data writing. Read / write control circuits 50 and 60 are arranged in a region in contact with memory array 10 in order to pass a data write current and a sense current (data read current) through bit line BL during data read and data write. Is a general term for circuit groups.

  FIG. 2 is a circuit diagram for illustrating in detail the configuration of memory array 10 and its peripheral circuits according to the first embodiment.

  Referring to FIG. 2, memory array 10 has MTJ memory cells MC arranged in n rows × m columns (n, m: natural numbers). Each configuration of the MTJ memory cell is the same as that shown in FIG. 14, and it functions as a tunnel magnetoresistive element TMR that functions as a magnetic memory unit whose electric resistance changes according to the level of stored data, and as an access gate. And an access transistor ATR.

  Read word lines RWL1 to RWLn and write word lines WWL1 to WWLn are provided corresponding to the first to nth memory cell rows, respectively. Corresponding to the first to mth memory cell columns, bit lines BL1, / BL1 to BLm, / BLm, respectively, constituting the bit line pairs BLP1 to BLPm are provided.

  The MTJ memory cell MC is connected to one of the bit lines BL and / BL for each row. For example, the MTJ memory cell belonging to the first memory cell column will be described. The MTJ memory cell in the first row is coupled to the bit line / BL1, and the MTJ memory cell in the second row is connected to the bit line BL1. Combined with. Similarly, each of the MTJ memory cells is connected to one of the bit line pairs / BL1 to / BLm in the odd-numbered row, and is connected to one of the other bit line pairs BL1 to BLm in the even-numbered row.

  Memory array 10 further includes a plurality of dummy memory cells DMC coupled to bit lines BL1, / BL1 to BLm, / BLm, respectively. The dummy memory cells DMC are arranged in 2 rows × m columns so as to correspond to one of the dummy read word lines DRWL1 and DRWL2. Dummy memory cells corresponding to dummy read word line DRWL1 are coupled to bit lines BL1, BL2-BLm, respectively. On the other hand, the remaining dummy memory cells corresponding to dummy read word line DRWL2 are coupled to bit lines / BL1, / BL2- / BLm, respectively.

  For example, the dummy memory cell DMC has a configuration in which the tunnel magnetoresistive element TMR is replaced with a dummy resistive element (not shown) in the configuration of the MTJ memory cell shown in FIG. The electric resistance Rd of the dummy resistance element is set between electric resistances R1 and R0 corresponding to the storage data levels “1” and “0” in the MTJ memory cell MC, that is, R1> Rd> R0.

  When odd-numbered rows are selected according to the row selection result and each of bit lines / BL1 to / BLm is coupled to MTJ memory cell MC, dummy read word line DRWL1 is activated and bit line BL1 is activated. Each of .about.BLm and dummy memory cell DMC are coupled. On the other hand, when an even row is selected according to the row selection result and each of the bit lines BL1 to BLm and the MTJ memory cell MC are coupled, the dummy read word line DRWL2 is activated and the bit line Each of lines / BL1- / BLm is coupled to dummy memory cell DMC.

  In the following, when the write word line, the read word line, the dummy read word line, the bit line and the bit line pair are collectively expressed, the symbols WWL, RWL, DRWL, BL (/ BL) and BLP are used. When a specific write word line, read word line, dummy read word line, bit line, and bit line pair are indicated, a subscript is added to these symbols, and RWL1, WWL1, DRWL1 , BL1 (/ BL1), and BLP1.

  Hereinafter, the high voltage state (power supply voltages Vcc1, Vcc2, Vcc3) and the low voltage state (ground voltage Vss) of the signal and signal line are also referred to as “H level” and “L level”, respectively.

  The word line current control circuit 40 couples each write word line WWL to the ground voltage Vss in a region opposite to the word line driver 30 across the memory array 10. Thus, data write current Ip in a certain direction can be supplied to the write word line selectively coupled to the power supply voltage by the word line driver.

  Write column selection lines WCSL1 to WCSLm and read column selection lines RCSL1 to RCSLm for performing column selection are provided corresponding to the first to mth memory cell columns, respectively.

  Column decoder 25 activates one of write column selection lines WCSL1 to WCSLm to a selected state (H level) at the time of data writing in accordance with the decoding result of column address CA, that is, the column selection result. At the time of data reading, column decoder 25 activates one of read column selection lines RCSL1 to RCSLm to a selected state (H level) according to the column selection result.

  Further, a write data bus pair WDBP for transmitting write data and a read data bus pair RDBP for transmitting read data are arranged independently. Write data bus pair WDBP includes mutually complementary write data buses WDB and / WDB, and read data bus pair RDBP includes mutually complementary read data buses RDB and / RDB.

  Read / write control circuit 50 includes read column select gates RCSG1 to RCSGm, read gates RG1 to RGm, and read drive select provided corresponding to data write circuit 51W, data read circuit 51R, and memory cell columns, respectively. Gates RCDG1 to RCDGm and write column selection gates WCSG1 to WCSGm are included.

  Each of read column select gates RCSG1 to RCSGm, each of read gates RG1 to RGm, each of read drive select gates RCDG1 to RCDGm, and each of write column select gates WCSG1 to WCSGm are arranged corresponding to the memory cell columns, respectively. Since each has the same configuration, the configuration of read column selection gate RCSG1, read gate RG1, read drive selection gate RCDG1, and write column selection gate WCSG1 provided corresponding to bit lines BL1, / BL1 will be representatively described. To do.

  Read drive select gate RCDG1 includes transistor switches electrically coupled between bit lines BL1 and / BL1 and power supply voltage Vcc2. These transistor switches are turned on / off according to the voltage of the read column selection line RCSL1. That is, when read column select line RCSL1 is activated to a selected state (H level), read drive select gate RCDG1 electrically couples bit lines BL1 and / BL1 to power supply voltage Vcc2.

  Read column select gate RCSG1 and read gate RG1 are coupled in series between read data buses RDB, / RDB and ground voltage Vss. Read column select gate RCSG1 includes a transistor switch electrically coupled between read data bus RDB and node N1a, and a transistor switch electrically coupled between read data bus / RDB and node N1b. Have. These transistor switches are turned on / off according to the voltage of the read column selection line RCSL1. That is, when read column select line RCSL1 is activated to a selected state (H level), read column select gate RCSG1 electrically couples read data buses RDB and / RDB to nodes N1a and N1b, respectively.

  Read gate RG1 has N-type MOS transistors Q11 and Q12 electrically coupled between nodes N1a and N1b and ground voltage Vss, respectively. Transistors Q11 and Q12 have their gates coupled to bit lines / BL1 and BL1, respectively. Therefore, the voltages of nodes N1a and N1b are driven to ground voltage Vss with the driving force corresponding to the voltages of bit lines / BL1 and BL1, respectively.

  Specifically, when the voltage of the bit line BL1 is higher than the voltage of the bit line / BL1, the node N1b is driven to the ground voltage Vss more strongly by the transistor Q12, so that the voltage of the node N1a is It becomes higher than the voltage. On the other hand, when the voltage of the bit line BL1 is lower than the voltage of the bit line / BL1, the voltage of the node N1b becomes higher than the voltage of the node N1a.

  Write column select gate WCSG1 includes a transistor switch electrically coupled between write data bus WDB and bit line B1, and a transistor electrically coupled between write data bus / WDB and bit line / BL1. And a switch. These transistor switches are turned on / off according to the voltage of the write column selection line WCSL1. That is, when write column select line WCSL1 is activated to a selected state (H level), write column select gate WCSG1 electrically couples write data buses WDB and / WDB to bit lines BL1 and / BL1, respectively. To do.

  In the following, read column selection lines RCSL1 to RCSLm, write column selection lines WCSL1 to WCSLm, read column selection gates RCSG1 to RCSGm, read gates RG1 to RGm, read drive selection gates RCDG1 to RCDGm, and write column selection gates WCSG1 to WCSG1 Each WCSGm is collectively referred to as a read column selection line RCSL, a write column selection line WCSL, a read column selection gate RCSG, a read gate RG, a read drive selection gate RCDG, and a write column selection gate WCSG.

  Read / write control circuit 60 includes short-circuit switch transistors 62-1 to 62-m provided corresponding to the memory cell columns, respectively. The short-circuit switch transistors 62-1 to 62-m are turned on / off in response to the write column selection lines WCSL1 to WCSLm, respectively. For example, short-circuit switch transistor 62-1 is provided corresponding to the first memory cell column, and one end of bit lines BL1 and / BL1 is responsive to activation (H level) of write column select line WCSL1. (The opposite side of the write column selection gate WCSG1) is electrically coupled.

  Similarly, the short-circuit switch transistors 62-2 to 62-m provided corresponding to the other memory cell columns are also bit-responsive in the corresponding memory cell columns in response to activation of the write column selection lines WCSL2 to WCSLm, respectively. The bit lines BL and / BL constituting the line pair BLP are electrically coupled.

  Read / write control circuit 60 further includes precharge transistors 64-1a, 64-1b to 64-ma provided between bit lines BL1, / BL1 to bit lines BLm, / BLm and ground voltage Vss, respectively. 64-mb. The precharge transistors 64-1a, 64-1b to 64-ma, 64-mb are turned on in response to activation of the bit line precharge signal BLPR, whereby the bit lines BL1, / BL1 to bit lines BLm, / BLm is precharged to the ground voltage Vss.

  In the following, the short-circuit switch transistors 62-1 to 62-m and the precharge transistors 64-1a, 64-1b to 64-ma, 64-mb are collectively referred to as the short-circuit switch transistor 62 and the precharge transistor 64, respectively. Also called.

  The bit line precharge signal BLPR generated by the control circuit 5 is activated to the H level in the active period of the MRAM device 1 at least in a predetermined period before executing data reading. On the other hand, during the data read operation and data write operation in the active period of MRAM device 1, bit line precharge signal BLPR is inactivated to L level and precharge transistor 64 is turned off.

Next, the configuration of the data read circuit and the data write circuit will be described.
FIG. 3 is a circuit diagram showing a configuration of data read circuit 51R.

  Referring to FIG. 3, data read circuit 51R receives power supply voltage Vcc1 and supplies current sources 161 and 162 for supplying a constant current to internal nodes Ns1 and Ns2, respectively, internal node Ns1 and read data bus RDB. N-type MOS transistor 163 electrically coupled between N-type MOS transistor 164 electrically coupled between internal node Ns2 and read data bus / RDB, and voltage between internal nodes Ns1 and Ns2 And an amplifier 165 that amplifies the level difference and outputs read data DOUT.

  Reference voltage Vrr is applied to the gates of N-type MOS transistors 163 and 164, respectively. Resistors 166 and 167 are provided for pulling down internal nodes Ns1 and Ns2 to ground voltage Vss. With such a configuration, data read circuit 51R can supply an equal current to each of read data buses RDB and / RDB during data read.

  At the time of data reading, read data buses RDB and / RDB are pulled down to ground voltage Vss by different driving forces by read gate RG corresponding to the selected memory cell column. Therefore, data stored in the selected memory cell can be read by amplifying the voltage difference between internal nodes Ns1 and Ns2 by data read circuit 51R.

FIG. 4 is a circuit diagram showing a configuration of data read circuit 52R according to another circuit configuration example.
Referring to FIG. 4, data read circuit 52R includes P-type MOS transistors 171 and 172 used as precharge transistors, N-type MOS transistors 173 and 174 used as switching transistors, cross-couple amplifier 175, and cross-couple amplifier. An N-type MOS transistor 180 used as an operating current supply switch and inverters 182 and 184 are included.

  P-type MOS transistors 171 and 172 are electrically coupled between power supply voltage Vcc1 and internal nodes Nr and / Nr, respectively. Precharge signal φpr which is activated to L level in a predetermined period before data reading is input to each gate of P-type MOS transistors 171 and 172.

N-type MOS transistors 173 and 174 are electrically coupled between internal nodes Nr and / Nr and read data buses RDB and / RDB, respectively. Each gate of MOS transistors 173 and 174 receives a trigger pulse φtr that is activated to L level for a predetermined period during data reading.

  Cross-coupled amplifier 175 has P-type MOS transistors 176 and 177 and N-type MOS transistors 178 and 179 which are cross-coupled. N-type MOS transistor 180 is electrically coupled between cross-coupled amplifier 175 and ground voltage Vss, and receives sense signal φs at its gate. Sense signal φs has an activation period (H level) at least overlapping with trigger pulse φtr at the time of data reading.

  Before data reading, nodes Nr and / Nr are precharged to power supply voltage Vcc1 in response to activation of precharge signal φpr. Data read operation is started in a state where nodes Nr and / Nr and read data buses RDB and / RDB are electrically coupled to each other. Further, at a predetermined timing after the start of the data read operation, in response to activation of trigger pulse φtr (L level), N-type MOS transistors 173 and 174 connect read data buses RDB and / RDB to internal nodes Nr and / r. Electrically separated from Nr.

  Cross-coupled amplifier 175 is supplied with an operating current from N-type MOS transistor 180 in response to activation of sense signal φs, and converts the voltage difference between internal nodes Nr and / Nr to the amplitude of power supply voltage Vcc1 to ground voltage Vss. Amplify with. That is, in the case where the voltage of read data bus RDB becomes higher than that of read data bus / RDB by the data read operation, internal nodes Nr and / Nr are set to power supply voltage Vcc1 and ground voltage Vss, respectively.

  Inverters 182 and 184 invert the voltage levels of internal nodes Nr and / Nr to generate read data / DOUT and DOUT, respectively. That is, the polarities of read data DOUT and / DOUT match the polarities of read data buses RDB and / RDB.

FIG. 5 is a circuit diagram showing a configuration of data write circuit 51W.
Referring to FIG. 5, data write circuit 51W includes a P-type MOS transistor 151 for supplying a constant current to internal node Nw0 and a P-type constituting a current mirror circuit for controlling a passing current of transistor 151. MOS transistor 152 and current source 153, and inverters 154, 155, and 156 that operate by receiving an operating current supply through internal node Nw0. Each of inverters 154, 155 and 156 operates by receiving supply of power supply voltage Vcc3 and ground voltage Vss.

  Inverter 154 inverts the voltage level of write data DIN and transmits it to write data bus WDB. Inverter 155 inverts the voltage level of write data DIN and transmits it to the input node of inverter 156. Inverter 156 inverts the output of inverter 155 and transmits it to write data bus / WDB. Therefore, data write circuit 51W sets the voltages of write data buses WDB and / WDB to one of power supply voltage Vcc3 and ground voltage Vss according to the voltage level of write data DIN.

  FIG. 6 is a timing chart for illustrating data read and data write operations in the MRAM device according to the first embodiment.

First, the data read operation will be described.
Before data reading, read data buses RDB and / RDB are precharged to power supply voltage Vcc1, and bit lines BL and / BL are precharged to ground voltage Vss.

  In data reading, each of bit lines BL and / BL corresponding to the selected memory cell is electrically coupled to power supply voltage Vcc2 by corresponding read drive selection gate RCDG.

  Furthermore, one of the read word lines RWL corresponding to the selected memory cell is activated to the selected state (H level) according to the row selection result. As a result, the selected memory cell is electrically coupled between one of bit lines BL and / BL and ground voltage Vss. In addition, one of dummy read word lines DRWL1 and DRWL2 is activated, and the other of bit lines BL and / BL, which is not coupled to MTJ memory cell MC, is coupled to dummy memory cell DMC.

  On the other hand, the write word line WWL and the write column selection line WCSL are inactivated to L level (ground voltage Vss). No current flows through write word line WWL and write data buses WDB, / WDB.

  Thus, at the time of data reading, each of bit lines BL and / BL is pulled down to ground voltage Vss via selected memory cell or dummy memory cell DMC acting as a resistor. Further, in the selected memory cell column, each of the corresponding bit lines BL and / BL is pulled up to the power supply voltage Vcc2 by the read drive selection gate RCDG. Therefore, the voltages of the bit lines BL and / BL are determined according to the balance between the pull-up force (to Vcc2) and the pull-down force (to Vss), in other words, the electric resistance of the selected memory cell or dummy memory cell that is a resistor. Is done.

  For example, when the storage data level of the selected memory cell is “1” (electrical resistance R1), one of the bit lines BL and / BL coupled to the memory cell has a bit coupled to the dummy memory cell DMC. A voltage change ΔV1 larger than the voltage change ΔVm occurring on the other of the lines BL and / BL occurs. The relative relationship between the voltages on bit lines BL and / BL constituting bit line pair BLP corresponding to the selected memory cell changes according to the level of the read storage data. In accordance with such a voltage difference between bit lines BL and / BL, the potentials of read data buses RDB and / RDB are driven by read gate RG.

  That is, when the voltage of the bit line BL is higher than the voltage of the bit line / BL, the read data bus / RDB is driven more strongly to the ground voltage Vss side than the read data bus RDB by the read gate RG. (Voltage change ΔVb1> ΔVbm in FIG. 6).

  The voltage difference between read data buses RDB and / RDB generated in this way can be amplified by data read circuit 51R or 52R to output H level read data DOUT. When data read circuit 52R is used, precharge signal φpr is deactivated to the H level during the data read operation. Further, after a predetermined time has elapsed from the start of the data read operation, sense signal φs is activated to H level, and trigger pulse φtr is activated to L level so as to have an activation period overlapping with sense signal φs. .

  On the contrary, when the selected memory cell holds “0” (electrical resistance R0), that is, when the voltage of the bit line / BL is higher than the voltage of the bit line BL, the read gate RG causes the read data bus RDB to However, it is driven to the ground voltage Vss side more strongly than the read data bus / RDB. Based on the voltage difference between read data buses RDB and / RDB generated in this way, L level read data DOUT can be output.

  As described above, the potential of the read data buses RDB and / RDB is driven via the read gate RG, so that the read data buses RDB and / RDB having a large parasitic capacitance are selected memory cells (or dummy memory cells). Further, it is possible to execute data reading by excluding it from the sense current path flowing through the bit line. As a result, the RC load on the sense current path passing through the selected memory cell and the dummy memory cell can be reduced, and a voltage change necessary for data reading can be quickly generated in the bit lines BL and / BL. As a result, data can be read at high speed, and access to the MRAM device can be speeded up.

  Further, in order to suppress the voltage applied to both ends of tunneling magneto-resistance element TMR in the MTJ memory cell, power supply voltage Vcc2 for pulling up bit lines BL and / BL during data reading is determined. In general, in consideration of the reliability of an insulating film which is a tunnel barrier of a tunnel magnetoresistive element, it is necessary to set the bias voltage to be about 400 mV or less. As a result, it is possible to increase the speed of data reading while ensuring the operational reliability of the MTJ memory cell.

  In addition, since the precharge voltage of bit lines BL and / BL is set to the ground voltage, in the non-selected column, the bit line BL and the bit line BL and the BL are connected via the access transistor turned on in response to the activation of the read word line RWL of the selected row. No discharge current is generated from / BL. As a result, it is possible to reduce power consumption due to charge / discharge accompanying precharge in the bit lines BL and / BL.

Next, the operation at the time of data writing will be described.
The write column selection line WCSL corresponding to the column selection result is activated to the selected state (H level), and the corresponding write column selection gate WCSG is turned on. In response, one end of each of bit lines BL and / BL in the selected column corresponding to the selected memory cell is coupled to write data buses WDB and / WDB, respectively.

  Further, at the time of data writing, corresponding short-circuit switch transistor 62 is turned on to short-circuit the other ends of bit lines BL and / BL (opposite side of write column selection gate WCSG) of the selected column.

  As already described, data write circuit 51W sets write data buses WDB and / WDB to either one of power supply voltage Vcc3 and ground voltage Vss. For example, when the data level of write data DIN is L level, data write current −Iw for writing L level data to write data bus WDB is supplied. Data write current -Iw is supplied to bit line BL of the selected column via write column select gate WCSG.

  The data write current −Iw flowing through the bit line BL of the selected column is turned back by the short circuit switch transistor 62. As a result, data write current + Iw in the opposite direction flows through the other bit line / BL. Data write current + Iw flowing through bit line / BL is transmitted to write data bus / WDB via write column select gate WCSG.

  Further, any one of write word lines WWL is activated to a selected state (H level: power supply voltage Vcc3) according to the row selection result, and data write current Ip flows. As a result, data writing is performed on the selected memory cell in which the data write current is supplied to both the corresponding write word line WWL and bit line BL (/ BL). The direction of the data write current ± Iw that flows through the bit lines BL and / BL in the selected column is inverted according to the data level of the write data DIN.

  At the time of data writing, read word line RWL is maintained in a non-selected state (L level). In data read circuit 52R, precharge signal φpr is activated to H level during data writing. On the other hand, sense signal φs is deactivated to L level, and trigger pulse φtr is deactivated to H level.

  Further, by activating bit line precharge signal BLPR to H level also during data writing, the voltages of bit lines BL and / BL during data writing correspond to the precharge voltage level during data reading. Set to ground voltage Vss.

  Similarly, read data buses RDB and / RDB are set to power supply voltage Vcc1 corresponding to the precharge voltage at the time of data reading. As described above, the voltage at the time of data writing in the bit lines BL and / BL corresponding to the non-selected columns and the read data buses RDB and / RDB is made to coincide with the precharge voltage provided for data reading. It is not necessary to perform a new precharge operation before reading, and the data reading operation can be speeded up.

  Next, the power supply voltage level of the data read and data write circuit system will be described. Vcc1, which is the operating power supply voltage for data read circuits 51R, 52R, and Vcc2, which is the pull-up voltage for bit lines BL, / BL, reduce the bit line amplitude to suppress the voltage applied to both ends of the tunnel magnetoresistive element. In order to increase the amplitude voltage of the data buses RDB and / RDB, Vcc1> Vcc2 is set. That is, Vcc3> Vcc1> Vcc2 is set.

  On the other hand, at the time of data writing, it is necessary to sufficiently magnetize tunneling magneto-resistance element TMR of the selected memory cell. Therefore, Vcc3 which is the operation power supply voltage of data write circuit 51W is set higher than power supply voltages Vcc1 and Vcc2 in order to supply a sufficient data write current via write data buses WDB and / WDB. The

  For example, an external power supply voltage supplied from the outside of the MRAM device is applied as it is to the power supply voltage Vcc3, and this external power supply voltage is dropped by a voltage drop circuit (not shown) to generate power supply voltages Vcc1 and Vcc2. By doing so, it is possible to efficiently supply the power supply voltage in accordance with the relationship of “Vcc3> Vcc1> Vcc2”.

[Modification of Embodiment 1]
FIG. 7 is a circuit diagram for explaining in detail a configuration according to a modification of the first embodiment of memory array 10 and its peripheral circuits.

  Referring to FIG. 7, in the configuration according to the modification of the first embodiment, data write circuit 52W is provided instead of data write circuit 51W, and the arrangement of read drive selection gates RCDG1 to RCDGm is omitted. This is different from the configuration according to the first embodiment.

FIG. 8 is a circuit diagram illustrating the configuration of data write circuit 52W.
Referring to FIG. 8, data write circuit 52W according to the modification of the first embodiment further includes a pull-up circuit 53 in addition to the configuration of data write circuit 51W for supplying a data write current.

  Pull-up circuit 53 has pull-up transistors 157 and 158 arranged between power supply voltage Vcc2 and write data buses WDB and / WDB, respectively. Pull-up transistors 157 and 158 are formed of, for example, P-type MOS transistors that receive at their gates a write control signal WE that is activated to H level during data writing and inactivated to L level during data reading. be able to. Since the configuration corresponding to data write circuit 51W is the same as that shown in FIG. 5, detailed description will not be repeated.

  At the time of data writing, pull-up transistors 157 and 158 are turned off, so that data write current ± Iw can be supplied to write data buses WDB and / WDB similarly to data write circuit 51W. On the other hand, at the time of data reading, supply of data write current ± Iw by the portion corresponding to data write circuit 51W is stopped, and write data buses WDB and / WDB are respectively turned on by pull-up transistors 157 and 158 turned on. Are pulled up to the power supply voltage Vcc2.

  FIG. 9 is a timing chart illustrating a data write operation and a data read operation according to the modification of the first embodiment.

  Referring to FIG. 9, in the configuration according to the modification of the first embodiment, the write column selection line WCSL corresponding to the selected column is activated to the H level even during data reading. As a result, write data buses WDB and / WDB pulled up to power supply voltage Vcc2 are electrically coupled to bit lines BL and / BL of the selected column, respectively.

  That is, in the configuration according to the modification of the first embodiment, the bit line BL and / BL of the selected column is pulled up by the data write system circuit (data write circuit 52W) according to the first embodiment. Different from the configuration. Detecting voltage changes occurring in bit lines BL, / BL pulled up to power supply voltage Vcc2 and read data buses RDB, / RDB driven to ground voltage Vss by read gate RG, and these voltage changes Since the data reading operation by is similar to that described with reference to FIG. 6, detailed description thereof will not be repeated.

  Since the operation at the time of data writing is similar to that of FIG. 6, detailed description will not be repeated.

  In the configuration according to the modification of the first embodiment, the arrangement of read drive selection gates RCDG1 to RCDGm can be omitted, and bit lines BL and / BL corresponding to the selected column can be efficiently pulled up. Note that write data buses WDB and / WDB can be pulled up to power supply voltage Vcc2 at times other than during data writing, so that the operating speed is not reduced at the start of data reading.

  The voltage levels of power supply voltages Vcc1, Vcc2, and Vcc3 may be set in the same manner as in the first embodiment.

[Embodiment 2]
In the second embodiment, the configuration of an MRAM device that exchanges multi-bit data in parallel with the outside will be described.

  FIG. 10 is a schematic block diagram illustrating a configuration according to the second embodiment of memory array 10 and its peripheral circuits.

  Referring to FIG. 10, the memory array according to the second embodiment has N (N: natural number) memory banks MB1 to MBN arranged along the column direction. Each of memory banks MB1 to MBN has a configuration similar to that of memory array 10 according to the first embodiment.

  Along the column direction, M (M: natural number data bus pairs DBP1 to DBPM) shared by memory banks MB1 to MBN are arranged. For example, data bus pair DBP1 includes complementary data buses DB1 and / DB1. In the following description, the data bus pairs DBP1 to DBPM are generically referred to as DBP, the data buses DB1 to DBM are generically referred to as data bus DB, and the data buses / DB1 to / DBM are generically referred to as data buses. Also called / DB.

  Read / write control circuits 50 and 60 have data read circuits RDV1 to RDVM and data write circuits WDV1 to WDVM provided corresponding to data bus pairs DBP1 to DBPM, respectively. Data read circuits RDV1 to RDVM operate in response to read control signals RE1 to REM, respectively. Similarly, data write circuits WDV1 to WDVM operate in response to write control signals WE1 to WEM, respectively.

  The configuration of data read circuits 51R and 52R described with reference to FIGS. 3 and 4 can be applied to each of data read circuits RDV1 to RDVM. That is, if data read circuits 51R and 52R are configured to detect and amplify the voltages of corresponding data buses DB and / DB instead of read data buses RDB and / RDB, similar data read can be executed.

  In particular, each of the memory banks MB1 to MBK is configured to execute data reading using the same read gate as in the first embodiment, so that data reading suitable for miniaturization without a sense current Is supply function is provided. Since circuit 52R can be applied, it is possible to reduce the chip area in a configuration in which a large number of data read circuits are arranged, and the data read speed and the operation reliability of the MTJ memory cell are ensured.

  Further, when the data read circuit 51R having the function of supplying the sense current Is is used, the selected memory cell is connected to the selected memory cell via the data bus DB (/ DB) and the bit line BL (/ BL) as in the conventional technique. Data can also be read by passing the sense current Is.

  Data write circuits 51W and 52W shown in FIGS. 5 and 8 can be applied to each of data write circuits WDV1 to WDVM. That is, if data write circuits 51W and 52W are configured to drive the voltages of corresponding data buses DB and / DB instead of write data buses WDB and / WDB, similar data writing can be executed.

  In particular, when each of the memory banks MB1 to MBK is configured to execute data reading using the same read gate as in the first embodiment, the chip area can be reduced by applying the data writing circuit 52W. Further efforts can be made.

  With such a configuration, data can be exchanged with the selected memory cell independently for each data bus pair DBP. Therefore, parallel data reading and data writing of a plurality of bits can be executed simultaneously using a plurality of data bus pairs DBP.

The data bus pair DBP is arranged for every k (k: natural number) memory cells.
FIG. 11 is a circuit diagram illustrating the arrangement of data bus pairs. Since data bus pairs DBP1 to DBPM are similarly arranged, the arrangement of data bus pair DBP1 is representatively shown in FIG.

  Referring to FIG. 11, column decoder 25 includes read column selection lines RCSL1 to RCSLk and write column selection lines WCSL1 to WCSL1 for performing column selection between k memory cell columns corresponding to the same data bus pair. Selectively activates WCSLk.

  A write column selection gate WCSG, a read column selection gate RCSG, a read gate RG and a read drive selection gate RDCG similar to those in the first embodiment are arranged corresponding to each of the first to kth memory cell columns. The The arrangement of the MTJ memory cell MC, the dummy memory cell DMC, the short-circuit switch transistor 62, and the precharge transistor 64 is also the same as that of the memory array shown in FIG.

  Read column select gate RCSG electrically couples data buses DB1 and / DB1 and corresponding bit lines BL and / BL in response to activation of corresponding read column select line RCSL. Similarly, write column select gate WCSG electrically couples corresponding bit lines BL and / BL to data buses DB1 and / DB1, respectively, according to the voltage of corresponding write column select line WCSL.

  With this configuration, one data bus pair DBP can be shared by k memory cell columns.

  Data buses DB1 and / DB1 are arranged along the same direction as bit lines BL and / BL. On the other hand, read column selection line RCSL and write column selection line WCSL are arranged along the direction intersecting bit lines BL and / BL (that is, the row direction). As a result, the wiring pitch arranged in the same direction as the bit lines BL and / BL can be avoided and the wiring pitch can be secured.

  Referring to FIG. 10 again, memory banks MB1-MBN are selected according to a bank address (not shown). In the selected memory bank, the read data DOUT and the write data DIN of the M ′ bit (M ′: a natural number equal to or less than M) are respectively transmitted to the outside by one data read command and one data write command. It is exchanged between.

  Therefore, at the time of data reading, data of maximum M bits can be read in parallel. As a result, it is possible to configure an MRAM device that is particularly suitable for a system LSI or the like mixed on the same chip as the logic.

  On the other hand, at the time of data writing, it is necessary to pass a relatively large data write current to the bit lines BL, / BL, so the number of bits of write data written in parallel (hereinafter referred to as “number of parallel write bits”). If a large number is taken, the data consumption current also increases in proportion to this. In particular, in a configuration in which multiple bits are read in parallel, if the number of read data bits read in parallel (hereinafter also referred to as “parallel read bit number”) is the same as the number of parallel write bits, the peak current value is It becomes excessive and the burden on the power supply system increases. As a result, malfunction may occur due to the influence of the power supply voltage bounce.

  Therefore, in the configuration according to the second embodiment, the number of parallel write bits is set smaller than the number of parallel read bits by write selection circuit 6 included in control circuit 5.

  For example, when data reading of M ′ bits is executed in parallel, the number of bits of data simultaneously written in parallel in memory array 10 is set to N ′ bits (N ′: a natural number smaller than M ′). The

  FIG. 12 is a timing chart for explaining the operation control of the data read circuit and the data write circuit by the control circuit 5.

  In FIG. 12, as an example, the number M of data bus pairs DBP and the number of data bits M ′ exchanged by one data read operation and data write operation are equal, and M = M ′ = 8. A case will be described representatively.

  Referring to FIG. 12A, at the time of data reading, when one data read command is started at time tr0, read control signals RE1-RE8 are simultaneously activated to generate 8 bits (M 'bit). ) Data is read out in parallel. When M = M ′ as described above, each data read circuit may be activated in response to a common read control signal RE.

  Referring to FIG. 12B, at the time of data writing, parallel write bit number N ′ is suppressed to be smaller than parallel read bit number M ′ in order to suppress an increase in peak current. For example, when one data write command is started, the write selection circuit 6 divides each of the write control signals WE1 to WEM by time tw0, tw1, tw2, and tw3, respectively. Is done.

  Data write circuits WDV1-WDVM are activated and deactivated in response to activation and deactivation of corresponding write control signal WE, respectively. In the activated data write circuit, supply of operating current to inverters 154 to 156 shown in FIG. 5 is executed, and data writing using corresponding data bus pair DBP is executed. On the other hand, in the deactivated data write circuit, supply of operating current to inverters 154 to 156 shown in FIG. 5 is stopped.

  In the example shown in FIG. 12B, data writing by 2 bits (N ′ bits) is executed in parallel. In other words, 8-bit (M′-bit) write data input in one data write command is divided into four, and parallel data writing is performed in units of 2 bits (N′-bit).

  As described above, the memory array 10 is configured to be able to read and write data of a plurality of bits, and the parallel write bit number N ′ is set smaller than the parallel read bit number M ′. By setting = 1 and serially accessing one bit at a time, the peak current during data writing can be effectively reduced. As a result, in the MRAM device, the data rate at the time of data reading can be improved, and the operation current can be improved by suppressing the peak current value at the time of data writing and reducing the burden on the power supply system. .

  In particular, one data write command for writing data of M ′ bits is configured by repeating parallel writing of N ′ bits (N ′: a natural number smaller than M ′) (M ′ / N ′) times. Thus, the word length (number of bits) of one data read command and the word length (number of bits) of one data write command can be made uniform.

[Modification of Embodiment 2]
FIG. 13 is a schematic block diagram showing a configuration according to a modification of the second embodiment of memory array 10 and its peripheral circuits.

  In the configuration according to the modification of the second embodiment, data bus pair DBP is divided into read data bus pair RDBP and write data bus pair WDBP. Furthermore, the number of read data bus pairs RDBP arranged in the entire memory array 10 is different from the number of write data bus pairs WDBP arranged.

  FIG. 13 shows a configuration in which M read data bus pairs RDBP1 to RDBPM and H (H: natural number of H <M) write data bus pairs WDBP1 to WDPH are arranged in the entire memory array 10. .

  Each of read data bus pairs RDBP1 to RDBPM is arranged for every k memory cell columns as in the configuration according to the second embodiment. On the other hand, each of the write data bus pairs WDBP1 to WDPH is arranged for every k ′ (k ′: natural number of k ′> k) memory cell columns.

  Data read circuits RDV1 to RDVM are arranged corresponding to read data bus pairs RDBP1 to RDBPM as in the second embodiment. Similarly, data write circuits WDV1 to WDVH are arranged similarly to the configuration of the second embodiment, corresponding to write data bus pairs WDBP1 to WDPH, respectively. Since the configuration of the other parts is the same as that of the second embodiment, detailed description will not be repeated.

  With such a configuration, the number of data write circuits WDV can be reduced in a configuration on the premise that the number of parallel write bits is smaller than the number of parallel read bits. As a result, the degree of freedom in layout is improved, and the chip area of the MRAM device can be reduced.

  Furthermore, if the ratio of the number of arrangement of write data bus pair WDBP and read data bus pair RDBP is set appropriately, it becomes unnecessary to perform activation selection control in the data write circuit and data read circuit. For example, the number of write data bus pairs WDBP is set equal to the number of parallel write bits (H = N ′), and the number of read data bus pairs RDBP is set equal to the number of parallel read bits (M = M ′). Thus, each data read circuit is activated in parallel based on a common read control signal RE at the time of data read, while each data write circuit is activated at a common write control signal WE at the time of data write. The same effect as that of the second embodiment can be obtained even if the configuration is activated in parallel in response to the above. Thereby, the operation control of each data writing circuit and each data reading circuit is simplified.

  Similarly to the second embodiment, one data write command for writing M ′ bits of data is written in parallel by N ′ bits (N ′: a natural number smaller than M ′) (M ′ / N ′) By repeating the configuration, the word length (number of bits) of one data read command and the word length (number of bits) of one data write command can be made uniform.

  In particular, as described above, with H = N ′ and M = M ′, the ratio (M / H) of the number of write data bus pair WDBP and read data bus pair RDBP is an integer. If each of the data write operations is configured to repeatedly execute (M / H) times of parallel data writing of H bits using a different memory bank in response to one data write command. The word length (number of bits) of one data read command and the word length (number of bits) of one data write command are made uniform without performing activation selection control in the write circuit and each data read circuit. be able to.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  5 control circuit, 6 write selection circuit, 10 memory array, 20 row decoder, 25 column decoder, 30 word line driver, 40 word line current control circuit, 50, 60 read / write control circuit, 51W, 52W, WDV1 WDVM data write circuit, 51R, 52R, RDV1 to RDVM data read circuit, 53 pull-up circuit, BL1, / BL1 to BLm, / BLm bit line, BLP1 to BLPm bit line pair, DB1, / DB1 to DBM, / DBM Data bus, DBP1-DBPM data bus pair, DMC dummy memory cell, DRWL1, DRWL2 dummy read word line, Ip, ± Iw Data write current, Is sense current, MB1-MBN memory bank, MC memory cell, RCDG1-RCDGm read Drive selection gate RCSL1 to RCSLm Read column selection line, RDB, / RDB, RDB1 to RDBM, / RDB1 to / RDBM Read data bus, RDBP, RDBP1 to RDBPM Read data bus pair, RE1 to REM read control signal, RG1 to RGm read gate, RWL1 to RWLn Read word line, TMR tunnel magnetoresistive element, Vcc1, Vcc2, Vcc3 power supply voltage, Vss ground voltage, WCSG1 to WCSGm write column selection gate, WDB, / WDB, WDB1 to WDBH, / WDB1 to / WDBH Write data bus , WDBP, WDPP1-WDBPH Write data bus pairs, WE1-WEM write control signals, WWL1-WWLn write word lines.

Claims (7)

A plurality of memory cells arranged in a matrix;
Each of the memory cells
A magnetic storage unit that is magnetized in a direction according to a level of stored data by a magnetic field generated by a data write current, and whose electric resistance changes according to the direction of the magnetization;
An access gate for selectively turning on at the time of data reading and causing a data read current to flow through the magnetic storage unit,
A plurality of bit lines arranged corresponding to the memory cell columns in order to transmit an electrical signal corresponding to the level of the stored data;
A plurality of read data lines each for transmitting read data to and from a selected memory cell;
A plurality of write data lines each for transmitting write data to and from a selected memory cell;
A control circuit for instructing parallel data reading of M bits (M: an integer of 2 or more) using at least a part of the plurality of read data lines at the time of data reading;
The control circuit instructs N-bit (N: natural number indicated by N <M) parallel data writing using a part of the plurality of write data lines at the time of data writing. Storage device.   2. The thin film magnetic memory device according to claim 1, wherein the plurality of read data lines and the plurality of write data lines are arranged in a direction along the plurality of bit lines. The plurality of read data lines and the plurality of write data lines are arranged in the same number.
Each of the read data lines and each of the write data lines is formed as the same wiring by using a data bus arranged for each predetermined section of the plurality of memory cells.
The thin film magnetic memory device includes:
A data read circuit provided for each of the data buses and selectively activated at the time of data read to execute data read according to the voltage of the data bus;
A data write circuit provided for each of the data buses and selectively activated at the time of data writing to supply the data write current to the corresponding data bus;
2. The thin film magnetic body according to claim 1, wherein said control circuit activates M data read circuits during said data read and selectively activates N data write circuits during said data write. Storage device. M data buses are arranged in total,
4. The control circuit according to claim 3, wherein the control circuit activates each data read circuit during the data read and selectively activates N of the M data write circuits during the data write. The thin film magnetic memory device described. Each of the plurality of read data lines is arranged for each of the K memory cell columns (K: an integer of 2 or more),
Each of the plurality of write data lines is arranged for each of the L memory cells (L: an integer represented by L> K),
2. The thin film magnetic memory device according to claim 1, wherein said control circuit activates M data read circuits during said data read and activates N data write circuits during said data write. The plurality of write data lines are arranged in total N,
The plurality of read data lines are arranged in total M,
6. The thin film magnetic memory device according to claim 5, wherein the control circuit activates each data read circuit during the data read and activates each data write circuit during the data write. The M bits are an integer multiple of the N bits;
2. The thin film magnetic memory device according to claim 1, wherein the control circuit repeatedly instructs the N-bit parallel data writing (M / N) times in response to one data write command.

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