JP2011165968A - Electronic component mounting structure and mounting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic component mounting structure and mounting method that can achieve an excellent continuity between a wiring board and the electronic component and is low-cost, highly reliable, and environmentally friendly in terms of the number of manufacturing steps and resource consumption. <P>SOLUTION: A bonding material 55 is composed of a conductive resin, and led out beyond a mounting region J of an LSI package 19 on a substrate 5 for connection to a substrate surface layer interconnection. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a mounting structure for an electronic component using a conductive resin, and a method for manufacturing an electronic component having this structure.

Conventionally, a build-up substrate has been used for mounting an area array BGA (Ball Grid Array) type semiconductor package. The build-up board is a wiring board having a multilayer structure formed by repeatedly performing wiring formation, insulating material formation, and via processing on a core base material serving as a base, and wiring of each layer is connected to each other through vias. It is. Here, a manufacturing method of the build-up substrate and a mounting method when mounting the BGA type semiconductor package on the build-up substrate will be described in detail with reference to FIGS.
First, the core base material 27 as shown in FIG. Specifically, two layers (front and back) or multiple layers are formed, and an IVH (Inner Via Hall) 3 is formed to electrically connect the layers. This IVH3 can be obtained by performing plating after opening the through hole 3a using a drill. And the board | substrate inner layer wiring 37 electrically connected via IVH3 is formed in the front and back of the core base material 27. As shown in FIG.
Next, as shown in FIG. 15B, after forming an insulating material 28 covering the substrate inner layer wiring 37 on the front and back surfaces of the core base material 27, as shown in FIG. A via (before plating) 2b is drilled at a desired position. Subsequently, as shown in FIG. 15D, after the surfaces of the insulating material 28 and the via 2b are roughened, a seed layer 29 for depositing plating is formed on the surface of the insulating material 28 and the entire inner surface of the via 2b. . The seed layer 29 is immersed in a catalyst such as Pd and then plated, or formed by sputtering.

Thereafter, as shown in FIG. 16A, a plating resist 30 is formed using a photolithography method or the like in addition to the plating pattern portion, and the seed layer 29 exposed from the opening 30a of the plating resist 30 is formed. The plating 24 is deposited (FIG. 16B). Thereafter, as shown in FIG. 16C, the plating resist 30 is removed. As shown in FIG. 16D, after the plating resist 30 is removed, etching is performed until the portion where the plating 24 is not formed, that is, until the seed layer 29 other than the pattern portion disappears. The portions where the plating 24 remains are formed as vias 2, substrate surface wirings 33, and electrode pads 36.
Finally, as shown in FIG. 17A, the build-up substrate 34 is completed by forming the solder resist 35 on the insulating material 28 with only the soldered portions (electrode pads 36) opened. To do. Note that the multilayered build-up substrate 34 can be obtained by repeating the steps from FIG. 15B to FIG. 16D a desired number of times.

  As a general mounting method of the electronic component on the completed build-up board 34, first, as shown in FIG. 17B, the position of the opening of the metal mask 32 is overlapped with the electrode pad 36 of the build-up board 34. At the same time, the solder paste 18 is printed by the squeegee 31. Then, as shown in FIG. 17 (c), the pins (external electrodes) 22 such as the BGA type LSI package 19 (electronic parts) and the electrode pads 36 are aligned and mounted, and then put into a reflow furnace and the solder paste 18 is placed. Is melted and solidified on the pins 22 of the LSI package 19.

FIG. 18 is a perspective view of the build-up substrate.
In this case, as shown in FIG. 18, in the mounting region J ′ of the LSI package 19 on the build-up substrate 34, a plurality of electrode pads 36 are arranged in a matrix direction corresponding to the pins 22 of the LSI package 19. In this case, in order to draw the wiring from the pin 22 (electrode pad 36) on the inner peripheral row side of the LSI package 19 to the outside, the wiring (for example, FIG. It is necessary to pass the code 33a). However, since the number of wirings that can be passed between the pins 22 is limited by the pin pitch and wiring width, the LSI package 19 with a relatively large number of pins, such as CSP (Chip Size Package), and a narrow pitch and a large number of pins 22 can be pulled out. Often difficult.
FIG. 19 is an enlarged cross-sectional view of a portion D of 17 (c). In order to avoid this, as shown in FIGS. 18 and 19, the pins 22 on the inner peripheral row side of the LSI package 19 are temporarily connected to the substrate inner layer wiring (for example, reference numeral 37 a in FIG. 18) of the build-up substrate 34 using the vias 2. To the outside of the LSI package 19 through the substrate inner layer wiring 37a.

JP 2005-71825 A

  The above-described conventional build-up substrate 34 is a method of building up a wiring layer (wirings 33, 37, etc.) after the core base material 27 is manufactured, so that the number of processes increases and the build-up insulating material 28 is used. Are relatively difficult to manufacture, the insulating material 28 is expensive, and a production line for build-up is necessary, which makes it expensive compared to a general printed circuit board using a through-hole. There was a problem.

  By the way, in recent years, a technique using a conductive resin in which a conductive metal filler is contained in a resin has been proposed as an alternative to the conventional wiring technique based on the photolithography method (see, for example, Patent Document 1). For example, when the LSI package 19 is connected by the conductive resin 38, the paste-like conductive resin 38 is first printed on the electrode pad 36 as shown in FIG. Then, after mounting the pins 22 of the LSI package 19 on the conductive resin 38, the conductive resin 38 is cured. Thereby, it is considered that the pins 22 and the electrode pads 36 of the LSI package 19 can be joined. In this case, the electrode pad 19a / pin 22 (Sn) / conductive resin 38 / electrode pad 36 / buildup substrate 34 of the LSI package 19 are stacked in this order along the thickness direction of the buildup substrate 34 in the mounting region J ′. It will be in the state.

  Here, as the metal filler 40 mixed in the conductive resin 38 described above, Ag is generally used. In this case, when a component (for example, the pin 22 of the LSI package 19) having a terminal electrode plated with solder or Sn-based between the electrode pads 19a and 36 made of a conductive metal material is joined by the conductive resin 38, the pin 22 is diffused in the metal filler 40 (Ag) of the conductive resin 38 to form a void 39 at the bonding interface between the pin 22 and the conductive resin 38, causing a problem of conduction failure. .

  Therefore, the present invention has been made in view of the above circumstances, is excellent in conductivity between the wiring board and the electronic component, is inexpensive and highly reliable, and is environmentally friendly from the viewpoint of the number of manufacturing steps and resource consumption. It is an object of the present invention to provide a gentle electronic component mounting structure and electronic component mounting method.

  In order to solve the above-described problem, the present invention provides a wiring board having a wiring on a surface layer and an inner layer, and the wirings between the layers are connected to each other through through-holes. The electronic component mounting structure is mounted on the wiring board, and the bonding material is made of a conductive resin, and the bonding material is drawn to the outside of the area facing the electronic component on the wiring board. It is connected.

According to the present invention, the bonding material has a structure that also serves as a bonding material in addition to a function as a pad for mounting the external electrode on the wiring board. Furthermore, since the bonding material is drawn to the outside of the region facing the electronic component, the metal material (in comparison with the case where the external electrode is connected using the conductive material between the electrode pads made of the conductive metal material ( The distance between the electrode pads and wirings of the electronic component is increased. Thereby, it can suppress that an external electrode (Sn) diffuses in the metal filler in conductive resin, and can obtain a highly reliable mounting structure.
In addition, the conductive resin is simple and can be formed with a relatively fine pattern with a small number of processes, and the equipment necessary for pattern formation is only a printing machine and a furnace for resin curing. Manufacturing cost can be reduced. In addition, because the number of processes is small, it is a fully additive method that supplies members only to the necessary places, and when the resin material is a thermosetting resin, it can be cured at a low temperature compared to lead-free solder, etc. A low environmental load can be realized.

It is sectional drawing which shows roughly the mounting structure of the electronic component in 1st Embodiment. It is a perspective view of the wiring board in a 1st embodiment. It is sectional drawing which shows roughly the junction part detail in 1st Embodiment. It is sectional drawing which shows roughly the other form of a junction detail. It is sectional drawing which shows the other form of a junction detail schematically. It is sectional drawing which shows schematically the other form of a junction detail. It is process drawing which shows the mounting method of the electronic component in 1st Embodiment. It is process drawing which shows the mounting method of the electronic component in 1st Embodiment. It is sectional drawing which shows roughly the mounting structure of the electronic component in the modification of 1st Embodiment. It is process drawing which shows the mounting method of the electronic component in the modification of 1st Embodiment. It is sectional drawing which shows roughly the mounting structure of the electronic component in 2nd Embodiment. It is process drawing which shows the mounting method of the electronic component in 2nd Embodiment. It is sectional drawing which shows roughly the mounting structure of the electronic component in the modification of 2nd Embodiment. It is process drawing which shows the mounting method of the electronic component in the modification of 2nd Embodiment. It is sectional drawing which shows schematically the manufacturing method of the buildup board | substrate used conventionally. It is sectional drawing which shows schematically the manufacturing method of the buildup board | substrate used conventionally. It is sectional drawing which shows schematically the manufacturing method of the buildup board | substrate used conventionally. It is the schematic which shows the BGA mounting part of the conventional buildup board in three dimensions. It is sectional drawing which shows the junction part detail of the mounting structure of the conventional electronic component. It is sectional drawing which shows the junction part detail of the mounting structure of the conventional electronic component.

Next, embodiments of the present invention will be described with reference to the drawings. In the following description, components having the same function may be denoted by the same reference numerals and description thereof may be omitted.
(First embodiment)
(Electronic component mounting structure)
The electronic component mounting structure according to the first embodiment of the present invention will be described. FIG. 1 is a schematic cross-sectional view showing a mounting structure of an electronic component in the first embodiment, and FIG. 2 is a perspective view of a substrate. In the following description, the electronic component mounting structure of the present invention will be described by taking as an example a semiconductor device in which a plurality of electronic components are mounted on a substrate.
As shown in FIGS. 1 and 2, the semiconductor device 50 of the present embodiment includes a through-hole substrate 5 (hereinafter referred to as a substrate 5) and a plurality of electronic components 51 mounted on the substrate 5. Yes.

  The substrate 5 is a multi-layer substrate in which wiring layers on which wiring patterns are formed and insulating layers are alternately stacked. The wiring pattern (in-substrate wiring 10) formed between the wiring layers and the uppermost layer of the substrate 5 And a substrate surface layer wiring 9 formed on the surface of the lowermost layer, a plurality of through holes 4 penetrating all layers of the substrate 5 in the thickness direction, and formed in each through hole 4. It mainly has through through holes 6 that electrically connect the substrate surface layer wirings 9. In addition, the board | substrate 5 (each insulating layer) will not be restrict | limited on a material, if glass epoxy, a polyimide, etc. can form wiring.

  In the uppermost layer and the lowermost layer of the substrate 5, a through-hole land 7 is formed around the through-through hole 6, and a substrate surface layer wiring 9 extends from the through-hole land 7 along the surface direction of the substrate 5. . The wiring patterns such as the substrate inner layer wiring 10, the substrate surface layer wiring 9, and the through through hole 6 are made of a conductive metal material such as Cu. Further, on the substrate 5, the through hole land 7, the base end side of the substrate surface wiring 9, the non-formation region of the substrate surface wiring 9 (that is, the front end side of the substrate surface wiring 9 and the mounting region of the electronic component 51 are excluded. The area) is covered with the solder resist 8.

  The electronic component 51 includes the LSI package 19, the passive component 20, and other components (for example, the connector 21). In this case, the passive component 20 and the connector 21 are mounted on the substrate electrode pad 11 formed at the tip of the substrate surface wiring 9 via the solder 17.

FIG. 3 is an enlarged view of part A of FIG.
As shown in FIGS. 1 to 3, the LSI package 19 is an area array BGA type semiconductor package, and a plurality of electrode pads 19a are exposed along the matrix direction on the lower surface, and on each electrode pad 19a. A spherical pin 22 made of solder or the like is formed. The LSI package 19 is mounted on the substrate 5 with a bonding material 55 made of a conductive resin material.

  The bonding material 55 includes a plurality of conductive resin pads 13 (hereinafter referred to as resin pads 13) formed on the substrate 5 corresponding to the pins 22 of the LSI package 19, and the tips of the resin pads 13 and the substrate surface layer wiring 9. Conductive resin wiring 12 (hereinafter referred to as “resin wiring 12”) is provided. The resin pad 13 and the resin wiring 12 are integrally formed of the same material.

The resin pad 13 is disposed on the substrate 5 in a region facing each pin 22 of the LSI package 19 and is formed so as to sandwich the pin 22 between the electrode pad 19 a of the LSI package 19. That is, the resin pads 13 are arranged along the matrix direction in the mounting region J of the LSI package 19 on the substrate 5 (the region facing (directly below) the planar view outline of the LSI package 19 on the substrate 5). The LSI package 19 is mounted on the substrate 5 by directly bonding the pad 13 and the pin 22.
The resin wiring 12 connects the resin pad 13 and the substrate surface wiring 9, the proximal end side is connected to the resin pad 13, and the distal end side is connected to the substrate surface wiring 9 outside the mounting area J of the LSI package 19. ing. In this case, among the plurality of resin pads 13, the resin wiring 12 drawn out from the resin pads 13 arranged on the inner circumferential row side of the mounting region J of the LSI package 19 passes between the resin pads 13 arranged outside. Thus, the LSI package 19 is drawn to the outside of the mounting area J. In other words, in the present embodiment, no electrode pad made of a conductive metal material corresponding to the pins 22 of the LSI package 19 in one-to-one correspondence is formed in the mounting region J of the LSI package 19 on the substrate 5.

  As described above, in the semiconductor device 50 according to the present embodiment, the electrode pad made of the conductive metal material is not disposed immediately below the pin 22 of the LSI package 19, and the resin formed integrally and integrally with the resin wiring 12. The pin 22 is joined by the pad 13. That is, the resin pad 13 has a structure that also serves as a bonding material in addition to a function as a pad for mounting the pins 22 on the substrate 5. Further, the resin wiring 12 is connected to the substrate surface wiring 9 formed on the substrate 5. Therefore, the semiconductor device 50 is stacked in the order of the electrode pad 19a / pin 22 (solder) / resin pad 13 / substrate 5 along the thickness direction of the substrate 5 from the LSI package 19 side.

The conductive resin used for the bonding material 55 is obtained by blending the conductive metal filler 14 in the resin 16. The resin 16 constituting the bonding material 55 of the present embodiment is not particularly limited as long as desired conductivity, printability, curing characteristics, reliability, and the like are obtained. For example, epoxy-based, polyester-based, phenol-based, Various resins such as urethane and acrylic can be used. A resin 16 in which these resin materials are mixed may be used, but it is preferable that at least a part of the resin contains an epoxy resin from the viewpoint of adhesive strength and the strength of the resin itself. Further, from the viewpoint of ensuring the conductivity of the bonding material 55, the ratio of the metal filler 14 in the resin 16 is preferably 80 wt% to 95 wt%. In addition to this, it is more preferable to disperse and blend about 1 wt% or less of carbon nanotubes in order to increase the conductive path in the resin 16 and improve the conductivity by improving the resin strength.
Furthermore, as will be described later, it is desirable that the conductive material is printed and applied by screen printing, and the thickness after printing is as large as possible. By these measures, it is possible to obtain the adhesion necessary for the substrate 5 and the pins 22 and the strength required for component joining while ensuring conductivity.

  Moreover, the metal filler 14 contained in the resin 16 can be, for example, a powder of Au, Ag, Cu, Ni or the like, or a powder in which Cu or Ni is coated with Au or Ag. Moreover, the shape is not limited and can be a flake shape, a spherical shape, or a combination thereof. In this case, by setting the diameter (major axis direction) of the metal filler 14 to about 0.1 to 5 μm, it is possible to easily form a relatively fine resin wiring 12 having a line width of 30 μm or less.

  In the conventional electronic component mounting structure described above, as shown in FIG. 20, when the conductive resin 38 is joined to a solder or Sn-based plating component, the electrode pad 19a of the LSI package 19 and the build-up substrate 34 The pin 22 (solder) and the conductive resin 38 are sandwiched between the electrode pads 36 (electrode pad 19a / pin 22 (solder) / conductive resin 38 / electrode pad 36 / build-up substrate 34). ). In this case, there is a problem that Sn contained in the pin 22 diffuses into the metal filler 14 to form a void 39 in a high temperature storage test or the like, resulting in deterioration of bonding strength and poor conduction.

In contrast, the inventor of the present application has found that the diffusion of Sn contained in the solder hardly proceeds unless sandwiched between metals in a state where Sn and Ag are in contact with each other.
That is, in this embodiment, the LSI package 19 is mounted on the substrate 5 by the resin pad 13 made of conductive resin, and is connected to the substrate surface wiring 9 by the resin wiring 12 outside the mounting area J of the LSI package 19. It was set as the structure.
According to this configuration, the metal material (the pins 22 of the LSI package 19 and the substrate surface layer wiring 9) is compared with the conventional case in which the electrode pads 36 made of a conductive metal material and the pins 22 are connected by the conductive resin 38. Since the distance between them is enlarged, it is possible to suppress the Sn contained in the pins 22 from diffusing into the metal filler 14 in the conductive resin. Thereby, since the joint strength and electrical conductivity between the pin 22 and the resin pad 13 can be maintained, a highly reliable mounting structure can be obtained. In other words, in the present embodiment, there is no electrode pad made of the same material as the electrode pad 19a in the mounting region J of the LSI package 19 on the substrate 5, and Sn and Ag cannot be sandwiched between the same metal materials. Therefore, the diffusion of Sn can be suppressed, and the reliability of the bonding material 55 using the conductive resin can be significantly increased.

  Further, as described above, in the conventional electronic component mounting structure, as shown in FIGS. 18 and 19, when wiring is drawn from the inner circumferential row side of the LSI package 19, the substrate surface layer wiring 9 a is provided between the electrode pads 36. There is a way to pass. However, since the number of wirings that can be passed between the pins 22 is limited by the pin pitch and wiring width, it is often difficult to pull out a package with a relatively large number of pins such as CSP and a large number of columns at a narrow pitch. When the build-up substrate 34 is used, the substrate surface layer wiring 9 having a line width of 75 μm or more is generally used from the viewpoint of cost and the like except for the package interposer and the like. In this case, for example, in a CSP with a pitch of 0.5 mm, it is the limit to pass one wiring between the pins 22, and the third and subsequent rows from the outermost periphery must be drawn out by the substrate inner layer wiring 10 a via the vias 2.

On the other hand, in the present embodiment, since the wiring pattern on the mounting region J of the LSI package is formed of conductive resin (resin wiring 12), a relatively fine wiring pattern can be formed. In this case, even if the pitch of the pins 22 (resin pads 13) is a fine pitch of about 0.5 mm, about 2 to 3 resin wirings 12 can be passed between the pins 22. If it is not a full-grid BGA, the resin wiring 12 is drawn out to the inner peripheral side of the LSI package 19, and the substrate inner layer wiring 10 or the substrate surface layer wiring 9 formed on the back surface of the substrate 5 through the through-hole 6. Just pull it out.
In this way, it is possible to draw out about 4 rows of resin wirings 12 from the outer periphery using the substrate 5 in which the wirings between the layers are connected only by the through-through holes 6 as shown in FIG. Therefore, the substrate cost can be greatly reduced as compared with the build-up substrate 34 (see FIG. 18).
Furthermore, as described above, in the semiconductor device 50 of this embodiment, the resin pad 13 and the pin 22 that are integrally formed of the same material as the resin wiring 12 are bonded together, and the resin pad 13 is also a bonding material. Since it also serves as a structure, there is an advantage that the mounting material cost such as solder paste and the mounting process cost can be reduced.

FIG. 4 is a cross-sectional view showing another form of details of the joint.
By the way, in the LSI package 19 described above, as shown in FIG. 4, the oxide film 23 may exist on the surface of the pin 22, thereby reducing the conductivity of the pin 22 and mounting the electronic component 51. In some cases, there is a problem of high resistance.
Accordingly, at least a part of the metal filler 15 in the resin 16 is formed in a polygonal shape having a plurality of apex portions 56 in a cross-sectional view, such as a polyhedron, a polygonal column, a polygonal pyramid, or a cone, and has a long side of 10 nm or more It is preferable to have a joining structure in which the apex portion 56 of the metal filler 15 penetrates the oxide film 23 of the pin 22 and enters the pin 22. As a result, stable electrical conduction that is not affected by the oxide film 23 is obtained.

FIG. 5 is a cross-sectional view showing another form of details of the joint.
As shown in FIG. 5, at least some of the metal fillers 58 of the metal filler 14 have protrusions 57 such as a polyhedron, a polygonal column, a polygonal pyramid, a cone, and an ellipsoid on the surface, and the metal filler 58. It is also preferable to adopt a mounting structure in which the protrusions 57 of the pin pierce the oxide film 23 of the pin 22 and enter the pin 22. Also in this case, stable electrical conduction that is not affected by the oxide film 23 as described above can be obtained.

  It should be noted that when the component is mounted, the pin amount is adjusted so that the distance between the pin 22 of the LSI package 19 and the substrate 5 is equal to or less than the diameter of the metal fillers 15 and 58 having the apex portion 56 and the protrusion portion 57. Metal fillers 15 and 58 are pierced into the surface of 22 and break through the oxide film 23 on the surface of the pin 22 to obtain a more stable electrical connection. This interval is not necessarily equal to or smaller than the diameter of the metal fillers 15 and 58 having the apex portions 56 and 57, but the smaller the distance, the higher the possibility that the metal fillers 15 and 58 break through the oxide film 23 of the pin 22.

FIG. 6 is a cross-sectional view showing another form of details of the joint.
Furthermore, as shown in FIG. 6, it is also preferable to provide a metal nanoparticle fired film (metal film) 25 having a thickness of 30 nm or less on at least a part of the portion of the pin 22 that contacts the resin pad 13. The metal nanoparticles used at this time are preferably noble metals such as Au and Ag, and a dispersing agent that can be fired at a temperature below the melting point of the pin 22 and that reacts with oxygen during curing such as dodecylamine is used. is necessary. As a result, when the metal nanoparticles are applied to the pin 22 and cured, the oxide film 23 of the pin 22 is reduced along with the removal of the dispersant, and after curing, the metal nanoparticle fired film 25 made of a noble metal becomes the pin 22. Since the surface is covered, reoxidation can be suppressed. Furthermore, when nano Ag is used, since it is the same metal as general Ag as the metal filler 14 of conductive resin, there is also an advantage that good electrical connection can be obtained. Although not shown, a material having an oxide film reducing effect, such as nano Ag, a dispersing agent, a flux, or the like may be included in the bonding material 55 (conductive resin) in advance. As a result, when the bonding material 55 is cured, the oxide film 23 of the pin 22 can be removed and good electrical connection can be obtained.

  In order to further increase the density of the resin wiring 12 in the semiconductor device 50 of the present embodiment, a conductive resin containing fine particles having a particle diameter of about 20 nm or less in at least a part of the metal filler 14 is used as a raw material. Is preferred. By containing such metal fine particles, not only can the printability of the conductive resin be improved and the pitch can be reduced, but also the conductivity can be improved by fusing fine particles together. Moreover, since the metal fine particles can be sintered at a relatively low temperature (about 150 to 230 ° C.) with a metal having a particle diameter of about 20 nm or less, the conductivity of the bonding material 55 is accompanied by the sintering of the metal fillers 14. The improvement can be achieved, and the metal nanoparticle fired film 25 can be fused and the conductivity of the bonding material 55 can be further improved. At this time, the bonding force of the mounted LSI package 19 is borne by the resin 16 in the conductive resin, but the metal forming the pins 22 of the LSI package 19 and the metal filler 14 in the conductive resin are directly fused or anchored. The connection may be made by the above, or may be combined with both of the bonding forces. The resin 16 and the nano-sized metal filler 14 are preferably formed by a material that can be cured and sintered below the melting point of the pin 22 and a heating process.

(Electronic component mounting method)
Next, a method for manufacturing the semiconductor device 50 described above will be described as a method for mounting an electronic component according to the present invention. 7 and 8 are cross-sectional views schematically showing an example of an electronic component mounting method in the present embodiment.
First, as shown in FIG. 7A, the substrate 5 on which the resin wiring 12 and the resin pad 13 can be formed is prepared on at least one surface (preparation process). The substrate 5 has a substrate surface layer wiring 9, electrode pads 11, a solder resist 8 and the like provided in advance on the surface. In this case, the substrate surface layer wiring 9 is not formed in the mounting region J of the LSI package 19. Further, in the mounting region J of the LSI package 19 on the substrate 5, an electrode pad made of a conductive metal material corresponding to the pins 22 of the LSI package 19 on a one-to-one basis is not formed.

  Next, as shown in FIG. 7B, a paste-like conductive resin is printed and applied in a desired shape on the substrate 5 to form a resin wiring (uncured) 12a and a resin pad (uncured) 13a. (Application process). The method of applying the conductive resin is not limited as long as a predetermined pattern can be formed, and the coating method is not limited. The predetermined pattern is formed on the surface of the substrate 5 by a screen printing method using a mask, a dispensing method, an inkjet method, or the like. It can apply | coat so that it may become.

  Next, as shown in FIG. 7C, the LSI package 19 is mounted on the substrate 5 with the uncured resin pad 13a and the pins 22 of the LSI package 19 aligned, and then the conductive resin is cured. (Mounting process) Thereby, the resin wiring (after curing) 12 and the resin pad (after curing) 13 can be obtained, and the electrical conductivity of both can be realized and the bonding of the pins 22 of the LSI package 19 can be realized at the same time.

  At this time, the set temperature of the heating furnace at the time of curing the conductive resin can be lower than that of lead-free solder, which contributes to energy saving and reduces the thermal load on the LSI package 19 and the substrate 5 and is highly reliable. Can be provided. In addition, the conductive resin is simple and can be formed with a relatively fine pattern with a small number of processes, and the equipment necessary for pattern formation is only a printing machine and a furnace for resin curing. Manufacturing cost can be reduced. In addition, the resin pad 13 and the resin wiring 12 are integrally formed of the same material, a complete additive method for supplying members only to necessary portions, and lead-free solder when the resin material is a thermosetting resin. Since it can be cured at a low temperature as compared with the above, it is possible to reduce the number of processes and the number of discarded members, and it is possible to provide environmentally conscious (low environmental load) products at low cost. Prior to the mounting process, the metal nanoparticle fired film 25 as shown in FIG. 6 may be provided on the surface of the pin 22.

  Subsequently, as shown in FIG. 8A, the solder paste 18 is supplied onto the electrode pads 11 formed on the surface of the substrate 5 in order to mount other electronic components 51 (passive components 20, connectors 21, etc.). (Solder paste supply process). The method for applying the solder paste 18 is not particularly limited, but it can be supplied by a printing method or a dispensing method using a metal mask. However, when the printing method using the metal mask is performed, the LSI package 19 is already mounted, and therefore it is necessary to provide a counterbore in the mounting area of the LSI package 19 in the metal mask.

Finally, as shown in FIG. 8B, the passive component 20 and the connector 21 are mounted on the solder paste 18, and the solder paste 18 is melted, solidified, and joined. Thereby, the semiconductor device 50 of this embodiment is completed.
At this time, when soldering in a reflow furnace, the pins 22 of the previously mounted LSI package 19 may also be melted at the same time, so that the metal filler 14 in the resin pad 13 is fused to the melted pins 22. May spread. Therefore, it is preferable to provide a temperature rise suppression member 26 on the LSI package 19 to prevent the temperature rise and melting of the pins 22 of the LSI package 19. The temperature rise suppression member 26 only needs to have a heat capacity that can suppress melting of the pins 22, and the material and shape are not particularly limited, but a metal block or a heat sink metal with fins is preferable. The temperature increase suppression member 26 may be removed after soldering, or may be left as it is and used as a heat dissipation member for the LSI package 19. As other soldering methods, there are a method of using a soldering iron and local heating using a hot nozzle so that the pins 22 of the LSI package 19 are not melted.

As described above, according to the electronic component mounting method of the present embodiment, it is possible to reduce the substrate cost, reduce the mounting process, etc., and to provide a highly reliable electronic device product that is inexpensive, has a low environmental load, and the like.
In addition, according to the present embodiment, there is an advantage that even if the form of the electronic component 51 (part mounting position, and further, the form of the mounted part, the pin pitch, etc.) is changed, the board 5 itself need not be revised. . That is, it is only necessary to change the screen mask for conductive resin printing or the drawing pattern data in accordance with the form of the electronic component 51, so that the semiconductor device 50 having a high degree of design freedom can be provided. Therefore, it is possible to easily cope with diversification of the electronic component 51.

(Modification)
FIG. 9 is a sectional view showing a modification of the semiconductor device according to the first embodiment.
In the first embodiment described above, the case where only the LSI package 19 is mounted on the bonding material 55 (resin pad 13) has been described. However, in the semiconductor device 100 shown in FIG. The electronic component 51 may also be mounted with a bonding material 155 using a conductive resin. In this case, the bonding material 155 is pulled out from the resin pad 113 connected to the electrode pads 20a and 21a of the passive component 20 and the connector 21 and from the resin pad 113 to the outside of the mounting regions K and L of the passive component 20 and the connector 21. The resin wiring 112 connected to the substrate surface wiring 9 is integrally formed. That is, in this modification, metal electrode pads corresponding to the electrode pads 20a and 21a are not formed in the mounting regions K and L of the passive components 20 and the connectors 21 on the substrate 5. .

FIG. 10 is a cross-sectional view schematically showing an example of the electronic component mounting method according to the modified example described above.
As shown in FIGS. 10A and 10B, when manufacturing the semiconductor device 100 of this modification, the substrate surface layer wiring 9 is formed outside the mounting regions J, K, and L of the electronic components 51 on the substrate 5. Has been. In the above-described coating process, the resin wiring (uncured) 112a and the resin pad (uncured) 113a are mounted not only on the mounting region J of the LSI package 19 but also on the mounting regions K and L of the passive component 20, the connector 21, and the like. Apply. Then, in the mounting process, the passive component 20 and the connector 21 are mounted on the substrate 5 in a state where the uncured resin pad 113a and the passive component 20 and the electrode pads 20a and 21a of the connector 21 are aligned. Cure the functional resin. As a result, the passive component 20 and the connector 21 are joined simultaneously with the LSI package 19. As described above, the semiconductor device 100 shown in FIG. 9 can be manufactured.
By adopting such a mounting method, it is not necessary to solder the passive component 20 and the connector 21 separately, the joining member and the mounting process can be reduced, and the effects of cost reduction and environmental load reduction can be obtained.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 11 is a schematic cross-sectional view showing the electronic component mounting structure (semiconductor device) of the second embodiment. In the following description, components similar to those in the first embodiment described above are denoted by the same reference numerals, and description thereof is omitted.
As shown in FIG. 11, the semiconductor device 200 according to the present embodiment includes an LSI package 19 mounted on the through hole land 7 in the substrate 5, the base end side of the substrate surface wiring 9, and the non-formation region of the substrate surface wiring 9. A solder resist 201 is formed so as to cover the region J, and the resin wiring 12 drawn from the substrate surface wiring 9 is formed so as to run on the solder resist 201. A resin pad 13 is formed at the tip of the resin wiring 12, and an LSI package 19 is mounted on the resin pad 13. In this case, in the mounting region J of the LSI package 19, the member configuration perpendicular to the substrate 5 is electrode pad 19 a / pin 22 (solder) / resin pad 13 / solder resist 201 / substrate 5.

Next, the electronic component mounting method (semiconductor device manufacturing method) of the second embodiment will be described. FIG. 12 is a process diagram illustrating the method of manufacturing the semiconductor device according to the second embodiment, and is a cross-sectional view of the semiconductor device.
As shown in FIG. 12A, first, a substrate 5 on which a solder resist 201 is formed is prepared. Thereafter, as in the first embodiment, as shown in FIG. 12B, a paste-like resin wiring (uncured) 12a and a resin electrode pad (uncured) 13a are printed on the solder resist 201, As shown in FIG. 12C, after mounting the LSI package 19, the uncured resin wiring (uncured) 12a and the resin electrode pad (uncured) 13a are cured to form the wiring and mount the LSI package 19. Conduct at the same time. The subsequent soldering method for the passive component 20 and the connector 21 is the same as in the first embodiment.

  According to the present embodiment, the same effect as that of the first embodiment can be obtained, and the substrate surface layer wiring 9 can be formed in the portion covered with the solder resist 201 on the substrate 5, so that the number of substantial wiring layers As a result, the degree of freedom in wiring is improved. Furthermore, compared with the surface of the base material of the board | substrate 5, the solder resist 201 has a smooth surface state and can improve the printability of the joining material 55. FIG. Further, since the surface of the solder resist 201 is smooth, it is possible to prevent the bonding material 55 from being infiltrated into the recesses that are likely to occur in the base material, and to reduce the amount of resin that contributes to the component bonding. By these effects, wiring with high wiring density and high reliability and a bonding material can be obtained.

(Modification)
Next, a modification of the second embodiment will be described. FIG. 13 is a cross-sectional view showing a modified semiconductor device.
FIG. 13 is a cross-sectional view schematically showing a semiconductor device according to a modification of the second embodiment. As shown in FIG. 13, the present modified example is that the solder resist 251 is also formed in the mounting regions K and L of the substrate 5 such as the passive component 20 and the connector 21. This is different from the modification of the embodiment. That is, the semiconductor device 250 of the present modification includes the through hole land 7 on the substrate 5, the base end side of the substrate surface wiring 9, the non-formation region of the substrate surface wiring 9, and the mounting region J of the LSI package 19, Solder resist 251 is formed in the mounting regions K and L of the passive component 20 and the connector 21. In the mounting regions K and L of the passive component 20 and the connector 21, a bonding material 255 on which the passive component 20 and the connector 21 are mounted is formed on the solder resist 251. In this case, the bonding material 255 is drawn out from the resin pads 213 connected to the electrode pads 20a and 21a of the passive component 20 and the connector 21 and from the resin pad 213 to the outside of the mounting regions K and L of the passive component 20 and the connector 21. The resin wiring 212 connected to the substrate surface wiring 9 is integrally formed.

FIG. 14 is a cross-sectional view schematically showing an example of an electronic component mounting method (semiconductor device manufacturing method) according to a modification. When manufacturing the semiconductor device 250 of this modification, it can be manufactured by a method substantially the same as the modification of the first embodiment described above. Specifically, as shown in FIG. 14A, first, a substrate 5 on which a solder resist 251 is formed is prepared. 14B, in the coating process, in addition to the mounting region J of the LSI package 19, the resin wiring (on the solder resist 251 in the mounting regions K and L such as the passive component 20 and the connector 21 is also provided. (Uncured) 212a and resin pad (uncured) 213a are applied. In the mounting process, the passive component 20 and the connector 21 are mounted on the substrate 5 in a state where the uncured resin pad 213a and the passive component 20 and the electrode pads 20a and 21a of the connector 21 are aligned. Cure the functional resin. As a result, the passive component 20 and the connector 21 are joined simultaneously with the LSI package 19. Thus, the semiconductor device 250 shown in FIG. 13 described above can be manufactured.
By adopting such a mounting method, it is not necessary to solder the passive component 20 and the connector 21 separately, the joining member and the mounting process can be reduced, and the effects of cost reduction and environmental load reduction can be obtained.

The technical scope of the present invention is not limited to the above-described embodiments, and includes those in which various modifications are made to the above-described embodiments without departing from the spirit of the present invention. In other words, the configuration described in the above-described embodiment is merely an example, and can be changed as appropriate.
For example, although the case where the electronic component 51 is mounted only on one side of the substrate 5 is described as an example in the above-described embodiment, the electronic component 51 may be mounted on both sides of the substrate 5 by the same method. Furthermore, the electronic component 51 mounted on the substrate 5 of the present embodiment is not limited to the LSI package 19, the passive component 20, and the connector 21 described above.

(Appendix 1) A plurality of the electronic components are mounted on the wiring board, and among the electronic components, the area array type electronic components are mounted on the bonding material, and the other electronic components are mounted on the wiring board. Mounting structure of electronic components mounted with solder.

(Additional remark 2) The said wiring board consists of glass epoxy, and the mounting structure of the electronic component by which the said resin wiring is printed on the said wiring board.

(Additional remark 3) The mounting structure of the electronic component in which Sn is contained in the said external electrode surface of the said electronic component.

(Additional remark 4) The mounting structure of the electronic component whose metal filler material contained in the said conductive resin coat | covers the surface of Au, Ag, Cu, Ni or Cu, Ni with Au or Ag.

(Additional remark 5) The mounting structure of the electronic component in which the carbon nanotube is contained in the said conductive resin.

(Supplementary note 6) An electronic device in which a plurality of electronic components having external electrodes are mounted on a wiring board having wirings on the surface layer and the inner layer, and the wirings between the layers are connected by through-holes via a bonding material A component mounting method, an application step of applying the bonding material made of a conductive resin so as to be connected to the wiring on the surface layer outside a region facing the electronic component on the wiring board; A first mounting step of mounting at least an area array type electronic component among the plurality of electronic components on the conductive resin, and the electrons other than the area array type electronic component among the plurality of electronic components. A second mounting step of mounting the component on the wiring board with solder.

(Supplementary Note 7) Prior to the mounting step, a metal film is formed by applying and firing metal particles having a diameter of 30 nm or less on at least a part of the surface of the external electrode of the electronic component to be mounted in the mounting step. A mounting method for an electronic component, comprising: a forming step, wherein, in the first mounting step, the electronic component is mounted in a state where the metal film and the conductive resin are in contact with each other.

(Additional remark 8) The mounting method of the electronic component which forms the said conductive resin by the screen printing method, the dispensing method, or the inkjet method in the said application | coating process.

5: Through-through-hole board (wiring board)
6: Through-hole 8, 201, 251: Solder resist 9: Substrate surface wiring (wiring)
10: Inner layer wiring (wiring)
11: Substrate electrode pad 12, 112, 212: Conductive resin wiring (resin wiring)
13, 113, 213: Resin pad (pad part)
14, 15, 58: Metal filler 56: Vertex portion (vertex)
57: Protrusion 17: Solder 18: Solder paste 19: LSI package (electronic component)
20: Passive components (other electronic components)
21: Connector (other electronic components)
22: Pin (external electrode)
23: Oxide film 25: Metal nanoparticle fired film (metal film)
55, 155, 255: bonding material

Claims (9)

An electronic component mounting structure in which an electronic component having an external electrode is mounted via a bonding material on a wiring board having wirings on a surface layer and an inner layer, and the wirings between the layers being connected by through-holes. And
The bonding material is made of a conductive resin,
The mounting structure of an electronic component, wherein the bonding material is drawn out to the outside of a region facing the electronic component on the wiring board and connected to the wiring. The bonding material includes a pad portion on which the external electrode is mounted;
A resin wiring connecting the pad portion and the wiring;
2. The electronic component mounting structure according to claim 1, wherein the pad portion and the resin wiring are integrally formed of the same material.   3. The electronic component mounting structure according to claim 1, wherein a solder resist is formed between the wiring board and the bonding material.   4. The metal film obtained by firing metal particles having a diameter of 30 nm or less is formed on at least a part of the surface of the external electrode. 5. Electronic component mounting structure. Among the metal fillers contained in the conductive resin, at least some of the metal fillers are formed in a polygonal shape having a plurality of vertices in cross-sectional view, and the long sides are formed to be 10 nm or more,
The electronic component mounting structure according to any one of claims 1 to 4, wherein the apex penetrates into the external electrode. Among the metal fillers contained in the conductive resin, at least some of the metal fillers are formed with protrusions that protrude from the surface,
The electronic component mounting structure according to claim 1, wherein the protruding portion penetrates into the external electrode. An electronic component mounting method in which an electronic component having an external electrode is mounted via a bonding material on a wiring board having wiring on a surface layer and an inner layer, and the wirings between the layers being connected by through-through holes. And
An application step of applying the bonding material made of conductive resin on the wiring board;
A mounting step of mounting the electronic component on the conductive resin;
In the application step, the bonding material is applied so as to be connected to the wiring on the surface layer outside the region facing the electronic component on the wiring board. Among the metal fillers contained in the conductive resin, at least some of the metal fillers are formed in a polygonal shape having a plurality of vertices in cross-sectional view, and the long sides are formed to be 10 nm or more,
The electronic component mounting method according to claim 7, wherein, in the mounting step, the electronic component is mounted while being pressed toward the wiring board, and the apex is allowed to enter the external electrode. Among the metal fillers contained in the conductive resin, at least some of the metal fillers are formed with protrusions that protrude from the surface,
9. The mounting step is characterized in that at least the area array type electronic component is mounted while being pressed toward the wiring board, and the protrusion is inserted into the external electrode. The electronic component mounting method described.

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