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JP2011029492A - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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Publication number
JP2011029492A
JP2011029492A JP2009175322A JP2009175322A JP2011029492A JP 2011029492 A JP2011029492 A JP 2011029492A JP 2009175322 A JP2009175322 A JP 2009175322A JP 2009175322 A JP2009175322 A JP 2009175322A JP 2011029492 A JP2011029492 A JP 2011029492A
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semiconductor element
power semiconductor
wire
semiconductor device
die pad
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Japanese (ja)
Inventor
Yuji Kawashima
裕史 川島
Kenichi Hayashi
建一 林
Shinya Nakagawa
信也 中川
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2009175322A priority Critical patent/JP2011029492A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a power semiconductor device that is compact and is high in reliability, and can be easily manufactured. <P>SOLUTION: The power semiconductor device 100 includes: a power semiconductor element 50 mounted on a first die pad part 21a formed at a first lead 21 and having a gate electrode formed on a surface; a first control semiconductor element 30 mounted on a second die pad part 22a formed at a second lead 22 and having a plurality of die pads formed on a surface; and a second control semiconductor element 40 mounted within the surface area of the first control semiconductor element 30 via an insulating material 74 and having a plurality of die pads formed on a surface, wherein the first power semiconductor element 50 and second control semiconductor element 40 are electrically and directly connected to each other by a metal wire 94. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

この発明は、電力用半導体装置に関し、特に小型化が可能な電力用半導体装置に関するものである。   The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device that can be miniaturized.

近年、半導体装置の小型化が進むにつれて、実装密度を高めるために半導体素子を積層した半導体装置が次々に登場している。
例えば、特許文献１には、半導体素子を積層した半導体装置として、長方形からなる２つの半導体素子を長辺が互いに直交するように積層し、互いに他方の半導体素子の両端をオーバーハングさせたものが記載されている。この半導体装置では、ワイヤボンド時に上記オーバーハング部を治具で支えるため、一定量以上のオーバーハング量が必要とされている。 In recent years, as the size of semiconductor devices has been reduced, semiconductor devices in which semiconductor elements are stacked have appeared one after another in order to increase the mounting density.
For example, Patent Document 1 discloses a semiconductor device in which semiconductor elements are stacked, in which two rectangular semiconductor elements are stacked so that long sides are orthogonal to each other, and both ends of the other semiconductor element are overhanged. Are listed. In this semiconductor device, an overhang amount of a certain amount or more is required to support the overhang portion with a jig during wire bonding.

特許第３４６８２０６号公報Japanese Patent No. 3468206

しかしながら、特許文献１に記載の半導体装置においては、積層した半導体素子にオーバーハング部が存在するため、積層した半導体素子と並置して第３の半導体素子やリード等を設ける場合、オーバーハング部の外側でなければ第３の半導体またはリード等をワイヤボンドで接続することができず、半導体装置を小型化することが難しいという問題があった。また、オーバーハング部を設ける必要があるため、長辺の長さを小さくできないという制約があり、モジュールの小型化に対して不向きであるという問題もある。   However, in the semiconductor device described in Patent Document 1, since the overhang portion exists in the stacked semiconductor elements, when the third semiconductor element, the lead, or the like is provided in parallel with the stacked semiconductor elements, If it is not outside, the third semiconductor or the lead cannot be connected by wire bonding, and there is a problem that it is difficult to downsize the semiconductor device. Further, since it is necessary to provide an overhang portion, there is a restriction that the length of the long side cannot be reduced, and there is a problem that it is not suitable for downsizing of the module.

さらに、特許文献１に記載の半導体装置では、ワイヤボンド時にオーバーハング部を支えとして使用しているが、リードフレームの傾き、積層する半導体素子の傾きおよび回転や、ダイボンディング装置のダイボンディング位置精度、ワイヤボンディング装置の支え治具の位置精度等を考慮すると、半導体装置の製造が極めて難しいという問題もあった。   Furthermore, in the semiconductor device described in Patent Document 1, the overhang portion is used as a support at the time of wire bonding, but the inclination of the lead frame, the inclination and rotation of the semiconductor elements to be stacked, and the die bonding position accuracy of the die bonding apparatus. Considering the positional accuracy of the support jig of the wire bonding apparatus, there is a problem that it is extremely difficult to manufacture the semiconductor device.

この発明は、上記のような問題を解決するためになされたもので、小型で信頼性が高く、容易に製造できる電力用半導体装置を提供するものである。   The present invention has been made to solve the above-described problems, and provides a power semiconductor device that is small in size, highly reliable, and easily manufactured.

この発明における電力用半導体装置は、モールド樹脂から複数のリードが突出した電力用半導体装置であって、第１のダイパッド部が形成された第１のリードと、前記第１のリードと並置して設けられ、第２のダイパッド部が形成された第２のリードと、前記第１のダイパッド部の第１面に載置され、表面にゲート電極が形成された電力用半導体素子と、前記第２のダイパッド部の第１面に載置され、表面に複数のワイヤパッドが形成された第１の制御用半導体素子と、前記第１の制御用半導体素子の表面積内に絶縁性材料を介して載置され、表面に複数のワイヤパッドが形成された第２の制御用半導体素子と、前記電力用半導体素子と前記第２の制御用半導体素子とを電気的に直接接続する金属線とを備えたものである。   The power semiconductor device according to the present invention is a power semiconductor device in which a plurality of leads protrude from a mold resin, and is arranged in parallel with the first lead on which the first die pad portion is formed and the first lead. A second lead provided with a second die pad portion; a power semiconductor element mounted on a first surface of the first die pad portion and having a gate electrode formed on the surface; and the second lead A first control semiconductor element placed on the first surface of the die pad portion and having a plurality of wire pads formed on the surface, and an insulating material placed within the surface area of the first control semiconductor element. And a second control semiconductor element having a plurality of wire pads formed on a surface thereof, and a metal wire that electrically connects the power semiconductor element and the second control semiconductor element directly. Is.

この発明によれば、積層された２つの制御用半導体素子と電力用半導体素子とを近接して設置することができるので、小型で製造の容易な電力用半導体素子を得ることができる。   According to the present invention, two stacked control semiconductor elements and power semiconductor elements can be installed close to each other, so that a power semiconductor element that is small and easily manufactured can be obtained.

この発明の実施の形態１における電力用半導体装置を示す平面図、正面図、背面図および側面図である。1 is a plan view, a front view, a rear view, and a side view showing a power semiconductor device according to a first embodiment of the present invention. 図１のＩ−Ｉ線における断面図である。It is sectional drawing in the II line | wire of FIG. この発明の実施の形態１における電力用半導体装置の要部を拡大して示す平面図である。It is a top view which expands and shows the principal part of the semiconductor device for electric power in Embodiment 1 of this invention. この発明の実施の形態１における電力用半導体装置の要部を拡大して示す平面図である。It is a top view which expands and shows the principal part of the semiconductor device for electric power in Embodiment 1 of this invention. 従来の電力用半導体装置を示す平面図である。It is a top view which shows the conventional semiconductor device for electric power. この発明の実施の形態１における電力用半導体装置の要部を、従来の電力用半導体装置と比較して示す平面図である。It is a top view which shows the principal part of the power semiconductor device in Embodiment 1 of this invention compared with the conventional power semiconductor device. この発明の実施の形態２における電力用半導体装置を示す平面図、正面図、背面図および側面図である。It is the top view, front view, back view, and side view which show the semiconductor device for electric power in Embodiment 2 of this invention. 図７のＩ−Ｉ線における断面図である。It is sectional drawing in the II line | wire of FIG. この発明の実施の形態２における電力用半導体装置の要部を拡大して示す平面図である。It is a top view which expands and shows the principal part of the semiconductor device for electric power in Embodiment 2 of this invention. この発明の実施の形態２における電力用半導体装置の要部を拡大して示す平面図である。It is a top view which expands and shows the principal part of the semiconductor device for electric power in Embodiment 2 of this invention. この発明の実施の形態２における電力用半導体装置の要部を、実施の形態１における電力用半導体装置と比較して示す平面図である。It is a top view which shows the principal part of the power semiconductor device in Embodiment 2 of this invention compared with the power semiconductor device in Embodiment 1. FIG. この発明の実施の形態２における電力用半導体装置の要部を拡大して示す平面図である。It is a top view which expands and shows the principal part of the semiconductor device for electric power in Embodiment 2 of this invention.

実施の形態１．
図１（ａ）〜（ｄ）は、それぞれこの発明の実施の形態１における電力用半導体装置を示す平面図、正面図、背面図および側面図であり、図２は図１のＩ−Ｉ線における断面図である。図３および図４は、この発明の実施の形態１における電力用半導体装置の要部を拡大して示す平面図である。また、図５は従来の電力用半導体装置を示す平面図であり、図６はこの発明の実施の形態１における電力用半導体装置の要部を、従来の電力用半導体装置と比較して示す平面図である。 Embodiment 1 FIG.
1A to 1D are a plan view, a front view, a rear view, and a side view, respectively, showing a power semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a II line in FIG. FIG. 3 and 4 are enlarged plan views showing main portions of the power semiconductor device according to the first embodiment of the present invention. 5 is a plan view showing a conventional power semiconductor device, and FIG. 6 is a plan view showing the main part of the power semiconductor device according to the first embodiment of the present invention in comparison with the conventional power semiconductor device. FIG.

まず、図１ないし図６を参照して、実施の形態１における電力用半導体装置の構成について説明する。   First, the configuration of the power semiconductor device according to the first embodiment will be described with reference to FIGS.

図１および図２に示す電力用半導体装置１００は、モールド樹脂１０の両側面から複数のリード２０が突出するように配置されたトランスファーモールド型のＤＩＰ（Ｄｕａｌ Ｉｎｌｉｎｅ Ｐａｃｋａｇｅ）で構成されており、半導体素子として、第１の制御用半導体素子であるマイコン３０、第２の制御用半導体素子であるＩＣ４０、電力用半導体素子であるＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）５０、および還流ダイオードであるＦｗＤｉ（Ｆｌｙｗｈｅｅｌ Ｄｉｏｄｅ）６０とを有している。   A power semiconductor device 100 shown in FIG. 1 and FIG. 2 includes a transfer mold type DIP (Dual Inline Package) in which a plurality of leads 20 protrude from both side surfaces of a mold resin 10. As elements, the microcomputer 30 as the first control semiconductor element, the IC 40 as the second control semiconductor element, the IGBT (Insulated Gate Bipolar Transistor) 50 as the power semiconductor element, and the FwDi (Flywheel Diode) as the free wheel diode. ) 60.

複数のリード２０のうち、第１のリード２１には第１のダイパッド部２１ａが形成されており、第１のダイパッド部２１ａの第１面にはＩＧＢＴ５０とＦｗＤｉ６０とが載置されている。ＩＧＢＴ５０の裏面と第１のダイパッド部２１ａの第１面は、例えばＰｂフリーはんだ７１で接合される。また、ＦｗＤｉ６０の裏面と第１のダイパッド部２１ａの第１面も、Ｐｂフリーはんだ７１と同じ組成のＰｂフリーはんだ７２で接合される。なお、ＩＧＢＴ５０、ＦｗＤｉ６０と第１のダイパッド部２１ａとの接合は、Ｐｂフリーはんだ７１，７２に限られるものではなく、Ａｇペーストなどの導電性接着剤など導電性に優れる材料であればよいが、樹脂モールド時の耐熱性を考慮すると、耐熱性が１８０℃以上であって、ある程度以上の接着力を有するものが好ましい。また、環境に配慮すると、Ｐｂを含むはんだではない方が好ましい。   Among the plurality of leads 20, the first lead 21 is formed with a first die pad portion 21 a, and the IGBT 50 and FwDi 60 are placed on the first surface of the first die pad portion 21 a. The back surface of the IGBT 50 and the first surface of the first die pad portion 21 a are joined by, for example, Pb-free solder 71. Further, the back surface of the FwDi 60 and the first surface of the first die pad portion 21 a are also joined by the Pb-free solder 72 having the same composition as the Pb-free solder 71. In addition, joining of IGBT50, FwDi60, and the 1st die pad part 21a is not restricted to Pb free solder 71,72, What is necessary is just a material excellent in electroconductivity, such as conductive adhesives, such as Ag paste, Considering the heat resistance at the time of resin molding, it is preferable that the heat resistance is 180 ° C. or higher and has a certain degree of adhesive strength. In consideration of the environment, it is preferable that the solder is not Pb-containing solder.

また、第２のリード２２には第２のダイパッド部２２ａが形成されており、この第２のダイパッド部２２ａの第１面にはマイコン３０が載置されている。マイコン３０の裏面と第２のダイパッド部２２ａの第１面は、例えば、接着剤７３を用いて固着される。また、マイコン３０の表面上にはＩＣ４０が載置されており、マイコン３０の表面とＩＣ４０の裏面は、例えば、ＤＡＦ（Ｄｉｅ Ａｔｔａｃｈ Ｆｉｌｍ）などの絶縁性接着シート７４を介して固着される。マイコン３０とＩＣ４０とを固着する部材は、絶縁性材料であればＤＡＦでなくてもよいが、フロー性が大きい材料では固着時のフローによるはみ出しでマイコン３０の表面上に形成されたワイヤパッドが汚染されてしまい、ワイヤボンド性が低下するという問題が発生する可能性があるため、固着時のフロー性が小さいシート状のものが好ましい。   A second die pad portion 22a is formed on the second lead 22, and a microcomputer 30 is placed on the first surface of the second die pad portion 22a. The back surface of the microcomputer 30 and the first surface of the second die pad portion 22a are fixed using, for example, an adhesive 73. The IC 40 is placed on the surface of the microcomputer 30, and the front surface of the microcomputer 30 and the back surface of the IC 40 are fixed via an insulating adhesive sheet 74 such as DAF (Die Attach Film). The member that fixes the microcomputer 30 and the IC 40 may not be a DAF as long as it is an insulating material. However, in the case of a material having a high flow property, a wire pad formed on the surface of the microcomputer 30 due to the protrusion at the time of fixing is used. Since it may become contaminated and the problem that wire bondability falls may generate | occur | produce, the sheet-like thing with the small flow property at the time of fixation is preferable.

なお、ＩＣ４０はマイコン３０よりも表面積が小さい形状であり、マイコン３０の表面積内、すなわちマイコン３０に対してオーバーハング部が生じないにようにマイコン３０の表面上に積層されている。また、マイコン３０の四辺に沿ってに形成された複数のワイヤパッドと干渉しない位置に配置されている。   The IC 40 has a smaller surface area than the microcomputer 30 and is laminated on the surface of the microcomputer 30 so that an overhang portion does not occur in the surface area of the microcomputer 30, that is, with respect to the microcomputer 30. Moreover, it arrange | positions in the position which does not interfere with the several wire pad formed along the four sides of the microcomputer 30. FIG.

そして、第１のダイパッド部２１ａの第１面と対向する第２面は、放熱板であるヒートシンク８０の表面と接合されている。ヒートシンク８０は、ＡｌやＣｕ等の熱伝導率の高い材料で形成されており、ヒートシンク８０の裏面は、モールド樹脂１０から露出するように配置されている。ヒートシンク８０の表面と第１のダイパッド部２１ａの第２面とは、放熱性の高い絶縁材料７５を介して固着されている。   And the 2nd surface facing the 1st surface of the 1st die pad part 21a is joined with the surface of the heat sink 80 which is a heat sink. The heat sink 80 is formed of a material having high thermal conductivity such as Al or Cu, and the rear surface of the heat sink 80 is disposed so as to be exposed from the mold resin 10. The surface of the heat sink 80 and the second surface of the first die pad portion 21a are fixed with an insulating material 75 having high heat dissipation.

一般的にマイコン３０は熱に弱いため、マイコン３０がＩＧＢＴ５０の発熱による悪影響を防ぐために、第２のダイパッド部２２ａの第１面と対向する第２面は第１のダイパッド部２１ａの第１面よりもヒートシンク８０から離れた側に配置させ、第２のダイパッド部２２ａの第２面がモールド樹脂１０によって覆われるよう設ける。このように第２のダイパッド部２２ａを配置することにより、マイコン３０がＩＧＢＴ５０の発熱による影響を受けないようにできる。   Since the microcomputer 30 is generally sensitive to heat, the second surface facing the first surface of the second die pad portion 22a is the first surface of the first die pad portion 21a in order to prevent the microcomputer 30 from adversely affecting the heat generated by the IGBT 50. The second surface of the second die pad portion 22 a is provided so as to be covered with the mold resin 10. By arranging the second die pad portion 22 a in this way, the microcomputer 30 can be prevented from being affected by the heat generated by the IGBT 50.

また、マイコン３０と第２のリード２２、マイコン３０とＩＣ４０、ＩＣ４０と第２のリード２２、ＩＣ４０とＩＧＢＴ５０、ＩＧＢＴ５０とＦｗＤｉ６０、ＦｗＤｉ６０と第１のリード２１は、それぞれ金属線であるワイヤ９１〜９６によって電気的に接続されている。ワイヤ９１〜９６は、例えば、Ａｕを主成分とするＡｕワイヤで形成されている。   The microcomputer 30 and the second lead 22, the microcomputer 30 and the IC 40, the IC 40 and the second lead 22, the IC 40 and the IGBT 50, the IGBT 50 and the FwDi 60, and the FwDi 60 and the first lead 21 are wires 91 to 96 which are metal wires, respectively. Are electrically connected. The wires 91 to 96 are formed of, for example, an Au wire containing Au as a main component.

次に、図３および図４を参照して、第１のダイパッド部２１ａおよび第２のダイパッド部２２ａ周辺の構成について詳しく説明する。   Next, with reference to FIG. 3 and FIG. 4, the configuration around the first die pad portion 21a and the second die pad portion 22a will be described in detail.

図３に示すように、マイコン３０の表面およびＩＣ４０の表面には、それぞれ４辺に沿って複数のワイヤパッド３１，４１が設けられている。また、ＩＧＢＴ５０の表面にはゲート電極５１が設けられている。そして、図４に示すように、マイコン３０のワイヤパッド３１は、リード２０に設けられたワイヤ接続部２０ａとワイヤ９１によって電気的に接続されている。また、ＩＣ４０のワイヤパッド４１は、マイコン３０のワイヤパッド３１およびリード２０に設けられたワイヤ接続部２０ａとワイヤ９２，９３によってそれぞれ電気的に接続されている。さらに、ＩＧＢＴ５０のゲート電極５１は、ＩＣ４０のワイヤパッド４１の１つとワイヤ９４によって直接ワイヤ接続されている。   As shown in FIG. 3, a plurality of wire pads 31 and 41 are provided along the four sides on the surface of the microcomputer 30 and the surface of the IC 40, respectively. A gate electrode 51 is provided on the surface of the IGBT 50. As shown in FIG. 4, the wire pad 31 of the microcomputer 30 is electrically connected to the wire connecting portion 20 a provided on the lead 20 by a wire 91. The wire pad 41 of the IC 40 is electrically connected to the wire pad 31 of the microcomputer 30 and the wire connecting portion 20a provided on the lead 20 by wires 92 and 93, respectively. Further, the gate electrode 51 of the IGBT 50 is directly connected to one of the wire pads 41 of the IC 40 by a wire 94.

このように、電力用半導体装置１００のＩＣ４０をマイコン３０からはみ出さないようにマイコン３０の表面積内に設置するとともに、ＩＧＢＴ５０のゲート電極５１とＩＣ４０のワイヤパッド４１とをワイヤ９４で直接接続することにより、電力半導体装置を従来のものに比べて大幅に小型化することができる。   As described above, the IC 40 of the power semiconductor device 100 is installed within the surface area of the microcomputer 30 so as not to protrude from the microcomputer 30, and the gate electrode 51 of the IGBT 50 and the wire pad 41 of the IC 40 are directly connected by the wire 94. As a result, the power semiconductor device can be significantly reduced in size as compared with the conventional one.

すなわち、従来技術のように、互いにオーバーハングするように半導体素子を積層した場合、図５に示すように、ＩＧＢＴ５０とＩＣ４０のオーバーハング部と重なる領域Ａにはワイヤボンドをすることができないため、ＩＧＢＴ５０とＩＣ４０との距離を広げる必要があったが、本実施の形態ではマイコン３０上に積層したＩＣ４０はオーバーハング部が存在しないため、ＩＧＢＴ５０をＩＣ４０を半導体素子の近傍に配置することができる。   That is, when the semiconductor elements are stacked so as to overhang each other as in the prior art, as shown in FIG. 5, the region A overlapping the overhang portion of the IGBT 50 and the IC 40 cannot be wire-bonded. Although it is necessary to increase the distance between the IGBT 50 and the IC 40, in the present embodiment, the IC 40 stacked on the microcomputer 30 does not have an overhang portion. Therefore, the IGBT 50 can be disposed in the vicinity of the semiconductor element.

また、従来の半導体素子は、図６（ｂ）に示すように、中継端子２４を介してＩＣ４０とＩＧＢＴ５０とを接続することが一般的であるが、本実施の形態においては、ワイヤ９４によってＩＣ４０とＩＧＢＴ５０とを直接接続しているので、図６（ａ）に示すように中継端子を省略することができ、その結果、中継端子２４の幅および中継端子２４とＩＧＢＴ５０との間隔を加えた長さΔｅだけ電力用半導体素子１００を小型化することができる。   In addition, as shown in FIG. 6B, the conventional semiconductor element generally connects the IC 40 and the IGBT 50 via the relay terminal 24. In the present embodiment, the IC 40 is connected by the wire 94. 6 and the IGBT 50 are directly connected, the relay terminal can be omitted as shown in FIG. 6A. As a result, the length obtained by adding the width of the relay terminal 24 and the interval between the relay terminal 24 and the IGBT 50 The power semiconductor element 100 can be reduced in size by Δe.

次に、実施の形態１における電力用半導体装置１００の製造方法について説明する。   Next, a method for manufacturing power semiconductor device 100 in the first embodiment will be described.

まず、チップウェハをダイシングする前のプロセスにおいて、ＩＣ４０の裏面と絶縁性接着シートであるＤＡＦ７４を熱圧着させて両者を一体にする。ＤＡＦ７４を接着した状態でウェハをダイシングしてＩＣ４０とする。そして、第２のリード２２に形成された第２のダイパッド部２２ａの第１面にマイコン３０を導電性接着剤でダイボンディングして取り付ける。ＩＣ４０はマイコン３０の表面上にＤＡＦ７４を介して熱圧着する。ＩＧＢＴ５０は、第１のリード２１に形成された第１のダイパッド部２１ａの第１面上にＰｂフリーはんだでダイボンディングして取り付けられる。   First, in the process before dicing the chip wafer, the back surface of the IC 40 and the DAF 74 that is an insulating adhesive sheet are thermocompression bonded to integrate them. The wafer is diced with the DAF 74 adhered to make an IC 40. Then, the microcomputer 30 is attached to the first surface of the second die pad portion 22a formed on the second lead 22 by die bonding with a conductive adhesive. The IC 40 is thermocompression bonded on the surface of the microcomputer 30 via the DAF 74. The IGBT 50 is attached to the first surface of the first die pad portion 21a formed on the first lead 21 by die bonding using Pb-free solder.

そして、マイコン３０のワイヤパッド３１とリード２０のワイヤ接続部２０ａとをワイヤ９１を用いてワイヤボンドにより電気的に接続し、ＩＣ４０のワイヤパッド４１とマイコン３０のワイヤパッド３１とを、ワイヤ９２を用いてワイヤボンドにより電気的に接続し、ＩＣ４０のワイヤパッド４１とワイヤ接続部２３ａとを、ワイヤ９３を用いてワイヤボンドにより接続し、ＩＧＢＴ５０のゲート電極５１とＩＣ４０とをワイヤ９４を用いてワイヤボンドに電気的に接続する。   Then, the wire pad 31 of the microcomputer 30 and the wire connection portion 20a of the lead 20 are electrically connected by wire bonding using the wire 91, and the wire pad 41 of the IC 40 and the wire pad 31 of the microcomputer 30 are connected to the wire 92. The wire pad 41 of the IC 40 and the wire connecting portion 23a are connected by wire bonding using the wire 93, and the gate electrode 51 of the IGBT 50 and the IC 40 are connected using the wire 94. Electrical connection to the bond.

次いで、第２のダイパッド６の第２面に、ヒートシンク８０を接着剤７５を介して取り付ける。さらにこれら部材を保護するために、モールド樹脂１０を用いてトランスファーモールドする。   Next, a heat sink 80 is attached to the second surface of the second die pad 6 with an adhesive 75. Further, in order to protect these members, transfer molding is performed using a mold resin 10.

その後、モールド樹脂１０から露出したリード２０の余分な部分、例えばタイバなどをタイバカット工程で切断し、ディッピング技術やめっき技術等によりはんだコーティングし、最後にリードフォーミングを行うことにより、本実施の形態の電力用半導体装置１００を得ることができる。   Thereafter, an excess portion of the lead 20 exposed from the mold resin 10, such as a tie bar, is cut by a tie bar cutting process, solder-coated by a dipping technique or a plating technique, and finally lead forming is performed. The power semiconductor device 100 can be obtained.

以上、本実施の形態によれば、第１の制御用半導体素子であるマイコン３０の表面積内にオーバーハング部が生じないように第２の制御用半導体素子であるＩＣ４０を配置するとともに、電力用半導体素子であるＩＧＢＴ５０と第２の制御用半導体素子であるＩＣ４０とをワイヤによって直接電気的に接続したので、小型且つ容易に製造できる電力用半導体装置を得ることができる。   As described above, according to the present embodiment, the IC 40 as the second control semiconductor element is disposed so as not to cause an overhang portion in the surface area of the microcomputer 30 as the first control semiconductor element, and the power Since the IGBT 50, which is a semiconductor element, and the IC 40, which is a second control semiconductor element, are directly and electrically connected by wires, a power semiconductor device that can be manufactured in a small size and easily can be obtained.

実施の形態２．
図７（ａ）〜（ｄ）は、それぞれこの発明の実施の形態２における電力用半導体装置を示す平面図、正面図、背面図および側面図であり、図８は図７のＩ−Ｉ線における断面図である。また、図９ないし図１２は、この発明の実施の形態２における電力用半導体装置の要部を拡大して示す平面図である。 Embodiment 2. FIG.
FIGS. 7A to 7D are a plan view, a front view, a rear view, and a side view, respectively, showing a power semiconductor device according to the second embodiment of the present invention, and FIG. 8 is a II line in FIG. FIG. 9 to 12 are enlarged plan views showing the main part of the power semiconductor device according to the second embodiment of the present invention.

実施の形態１における電力用半導体装置１００では、一部のワイヤ９１はマイコン３０から、ＩＧＢＴ５０側に位置するマイコン３０の辺３０ａをまたがって第１のダイパッド部２１ａと第２のダイパッド部２２ａとの間に設けられたリード２３のワイヤ接続部２３ａに接続されており、また一部のワイヤ９２はＩＣ４０から、ＩＧＢＴ５０側に位置するＩＣ４０の辺４０ａをまたがってマイコン３０に接続されている。したがって、上記のワイヤボンド接続ではマイコン３０とＩＧＢＴ５０間に一定の距離をとってリード２３のワイヤ接続部２３ａを配置しなければならない。さらにＩＣ４０からＩＧＢＴ５０に直接接続されるワイヤ９４はワイヤ接続部２３ａをまたがるためワイヤボンドのスパンが長くなってしまう。また、ワイヤ９４のループ高さが不十分であった場合や、ワイヤ９１のループ高さが高すぎた場合などに不具合を生じさせる可能性があるので、ワイヤループ高さのコントロールを正確にしないといけないという製造の管理面でやや難しい点があった。
そこでさらなる小型化、高信頼化のために改良したものが図７および図８に示す電力用半導体装置２００である。 In the power semiconductor device 100 according to the first embodiment, a part of the wires 91 extends from the microcomputer 30 across the side 30a of the microcomputer 30 located on the IGBT 50 side, between the first die pad portion 21a and the second die pad portion 22a. A part of the wires 92 is connected to the microcomputer 30 across the side 40 a of the IC 40 located on the IGBT 50 side from the IC 40. Therefore, in the wire bond connection described above, the wire connection portion 23a of the lead 23 must be disposed at a certain distance between the microcomputer 30 and the IGBT 50. Further, since the wire 94 directly connected from the IC 40 to the IGBT 50 extends over the wire connecting portion 23a, the wire bond span becomes long. Moreover, since the malfunction may be caused when the loop height of the wire 94 is insufficient or when the loop height of the wire 91 is too high, the wire loop height is not accurately controlled. There was a slightly difficult point in the management of manufacturing that it should not be done.
Accordingly, a power semiconductor device 200 shown in FIGS. 7 and 8 is improved for further miniaturization and higher reliability.

図９に示すように、電力用半導体装置２００は、マイコン３０のワイヤパッド３１がＩＣ４０とＩＧＢＴ５０との間を除いて設けられており、マイコン３０の表面に積層されたＩＣ４０は、ワイヤパッド３１が設置されていないマイコン３０のＩＧＢＴ５０側の辺３０ａ側に寄せて配置されている。すなわち、ＩＣ４０の中心ａがマイコン３０の中心ｂよりもＩＧＢＴ５０側に寄せられた位置になるようにＩＣ４０が配置されている。このとき、ＩＣ４０はマイコン３０の表面上からはみ出さないようにマイコン３０の表面積内に配置する。これはＩＣ４０のワイヤボンドが不安定になるためである。なお、ＩＣ４０の長辺はマイコン３０の長辺もしくは短辺と概ね平行に積層されていることが望ましい。   As shown in FIG. 9, in the power semiconductor device 200, the wire pad 31 of the microcomputer 30 is provided except between the IC 40 and the IGBT 50, and the IC 40 stacked on the surface of the microcomputer 30 has the wire pad 31. The microcomputer 30 which is not installed is arranged close to the side 30a on the IGBT 50 side. That is, the IC 40 is arranged so that the center a of the IC 40 is located closer to the IGBT 50 than the center b of the microcomputer 30. At this time, the IC 40 is disposed within the surface area of the microcomputer 30 so as not to protrude from the surface of the microcomputer 30. This is because the wire bond of the IC 40 becomes unstable. It is desirable that the long side of the IC 40 is laminated substantially in parallel with the long side or the short side of the microcomputer 30.

さらに、図１０に示すように、ＩＣ４０の四辺のうちＩＧＢＴ５０に近い辺４０ａが、マイコン３０の四辺のうちＩＧＢＴ５０側に近い辺３０ａ上に位置すること、すなわち、上記辺３０ａと辺４０ａがＩＣ４０の表面と平行な投影面上で重なるように配置することが望ましい。このように構成することにより、ＩＣ４０をＩＧＢＴ５０側に寄せた距離の長さだけワイヤ９４が短くなるため、信頼性をさらに向上させることができる。   Further, as shown in FIG. 10, the side 40 a close to the IGBT 50 among the four sides of the IC 40 is located on the side 30 a close to the IGBT 50 side among the four sides of the microcomputer 30, that is, the side 30 a and the side 40 a are the IC 40. It is desirable to arrange so as to overlap on a projection plane parallel to the surface. By configuring in this manner, the wire 94 is shortened by the length of the distance where the IC 40 is brought closer to the IGBT 50, so that the reliability can be further improved.

このように、マイコン３０の四辺のうちＩＧＢＴ５０側の辺に沿ってワイヤパッド３１を配置しないように構成することによって、ワイヤ９１はマイコン３０の辺３０ａをまたがらずにマイコン３０からワイヤ接続部２０ａに接続される。さらにワイヤ９２はＩＣ４０の辺４０ａをまたがらずにＩＣ４０からマイコン３０のワイヤパッド３１に接続される。したがって、マイコン３０とＩＧＢＴ５０の間にワイヤ接続部２３ａを設ける必要が無くなり、その結果、図１１に示すように、第１および第２のダイパッド部２１ａ，２２ａが、第１のダイパッド部２１ａに平行な投影面上で互いに隣接するように構成することができ、ＩＣ３の寄せ幅分とマイコン３０とＩＧＢＴ５０の間にあるワイヤ接続部２３ａの幅を足した長さΔｄだけ、マイコン３０とＩＧＢＴ５０との距離を小さくすることが可能となる。   As described above, by configuring the wire pad 31 so as not to be arranged along the IGBT 50 side of the four sides of the microcomputer 30, the wire 91 does not straddle the side 30 a of the microcomputer 30 and is connected from the microcomputer 30 to the wire connection portion 20 a. Connected to. Further, the wire 92 is connected from the IC 40 to the wire pad 31 of the microcomputer 30 without straddling the side 40a of the IC 40. Therefore, it is not necessary to provide the wire connection portion 23a between the microcomputer 30 and the IGBT 50. As a result, as shown in FIG. 11, the first and second die pad portions 21a and 22a are parallel to the first die pad portion 21a. Can be configured so as to be adjacent to each other on the projection plane, and the microcomputer 30 and the IGBT 50 are equal to each other by a length Δd obtained by adding the width of the IC 3 and the width of the wire connection portion 23a between the microcomputer 30 and the IGBT 50. The distance can be reduced.

また、ＩＣ４０からＩＧＢＴ５０に接続するワイヤ９４は、ＩＣ４０からマイコン３０に接続するワイヤ９２に干渉することなくワイヤボンドできるため、ワイヤボンド不良が減少し、さらに高信頼性を確保できる。   Further, since the wire 94 connected from the IC 40 to the IGBT 50 can be wire bonded without interfering with the wire 92 connected from the IC 40 to the microcomputer 30, wire bond defects are reduced, and high reliability can be secured.

ここで、ＩＧＢＴ５０とＩＣ４０を接続するワイヤ９４はワイヤボンド時に二点間の距離が長くなるため他のワイヤ９１，９２，９３よりも直径が大きいことが望ましい。これによりワイヤ９４は剛性が増すため、トランスファーモールド時のモールド樹脂の流れによる変形を防げる。また、モールド完了までに懸念される振動等による変形を防ぐことができる。これにより、さらに信頼性の高い製品を得ることができる。   Here, it is desirable that the wire 94 connecting the IGBT 50 and the IC 40 has a larger diameter than the other wires 91, 92, 93 because the distance between the two points becomes longer at the time of wire bonding. As a result, the rigidity of the wire 94 is increased, so that deformation due to the flow of the molding resin during transfer molding can be prevented. In addition, it is possible to prevent deformation due to vibration or the like which is a concern until completion of the molding. Thereby, a product with higher reliability can be obtained.

以上、本実施の形態によれば、ＩＣ４０の中心ａをマイコン３０の中心ｂよりもＩＧＢＴ５０側に配置するとともに、第１および第２のダイパッド部２１ａ，２２ａが、第１のダイパッド部２１ａに平行な投影面上で互いに隣接するように構成することで、電力用半導体装置の幅を従来よりも縮小することができ、電力用半導体装置の小型化が可能となる。さらにＩＣ４０とＩＧＢＴ５０とを電気的に接続するワイヤを短くできるので、ワイヤボンド不良を減らし、高い信頼性も確保できる。   As described above, according to the present embodiment, the center a of the IC 40 is arranged closer to the IGBT 50 than the center b of the microcomputer 30, and the first and second die pad portions 21a and 22a are parallel to the first die pad portion 21a. By configuring the projection surfaces so as to be adjacent to each other on the projection surface, the width of the power semiconductor device can be reduced as compared with the conventional case, and the power semiconductor device can be downsized. Furthermore, since the wire for electrically connecting the IC 40 and the IGBT 50 can be shortened, wire bond defects can be reduced and high reliability can be ensured.

なお、実施の形態１および２において、電力用半導体装置１００，２００に用いる電力用半導体素子はＩＧＢＴではなくＭＯＳＦＥＴでもよい。また、Ａｕを主成分とするＡｕワイヤ９１〜９６はＡｌまたはＣｕあるいはこれらを主成分とする合金からなるワイヤでもよい。   In the first and second embodiments, the power semiconductor element used for power semiconductor devices 100 and 200 may be a MOSFET instead of an IGBT. Further, the Au wires 91 to 96 mainly composed of Au may be wires made of Al, Cu, or an alloy mainly composed of these.

また、図１２のように、ＩＣ４０の中心ａがマイコンの中心ｂよりもＩＧＢＴ５０側にあれば、マイコン３０上でＩＣ４０の配置を自由に変えてもよい。   In addition, as shown in FIG. 12, if the center a of the IC 40 is closer to the IGBT 50 than the center b of the microcomputer, the arrangement of the IC 40 may be freely changed on the microcomputer 30.

１０ モールド樹脂、 ２０ リード、 ２１ 第１のリード、 ２１ａ 第１のダイパッド部、 ２２ 第２のリード、 ２２ａ 第２のダイパッド部、 ３０ マイコン（第１の制御用半導体素子）、 ３１ ワイヤパッド、 ４０ ＩＣ（第２の制御用半導体素子）、 ４１ ワイヤパッド、 ５０ ＩＧＢＴ（電力用半導体素子）、 ５１ ゲート電極、 ７４，７５ 絶縁性材料、 ８０ ヒートシンク（放熱板）、 ９１〜９６ ワイヤ（金属線）、 １００，２００ 電力用半導体装置。   DESCRIPTION OF SYMBOLS 10 Mold resin, 20 lead | read | reed, 21 1st lead | read | reed, 21a 1st die pad part, 22 2nd lead | read | reed, 22a 2nd die pad part, 30 Microcomputer (1st control semiconductor element), 31 Wire pad, 40 IC (second control semiconductor element), 41 wire pad, 50 IGBT (power semiconductor element), 51 gate electrode, 74, 75 insulating material, 80 heat sink (heat sink), 91-96 wire (metal wire) 100, 200 Power semiconductor device.

Claims (7)

モールド樹脂から複数のリードが突出した電力用半導体装置であって、
第１のダイパッド部が形成された第１のリードと、
前記第１のリードと並置して設けられ、第２のダイパッド部が形成された第２のリードと、
前記第１のダイパッド部の第１面に載置され、表面にゲート電極が形成された電力用半導体素子と、
前記第２のダイパッド部の第１面に載置され、表面に複数のワイヤパッドが形成された第１の制御用半導体素子と、
前記第１の制御用半導体素子の表面積内に絶縁性材料を介して載置され、表面に複数のワイヤパッドが形成された第２の制御用半導体素子と、
前記電力用半導体素子と前記第２の制御用半導体素子とを電気的に直接接続する金属線と
を備えた電力用半導体装置。 A power semiconductor device in which a plurality of leads protrudes from a mold resin,
A first lead on which a first die pad portion is formed;
A second lead provided in parallel with the first lead and having a second die pad portion formed thereon;
A power semiconductor element mounted on the first surface of the first die pad portion and having a gate electrode formed on the surface;
A first control semiconductor element mounted on the first surface of the second die pad portion and having a plurality of wire pads formed on the surface;
A second control semiconductor element mounted on the surface of the first control semiconductor element via an insulating material and having a plurality of wire pads formed on the surface;
A power semiconductor device comprising: a metal wire that electrically connects the power semiconductor element and the second control semiconductor element directly. 前記第２の制御用半導体素子は、その中心が前記第１の制御用半導体素子の中心に対して、前記電力用半導体素子側にあることを特徴とする請求項１に記載の電力用半導体装置。   2. The power semiconductor device according to claim 1, wherein the center of the second control semiconductor element is on the power semiconductor element side with respect to the center of the first control semiconductor element. . 前記第１の制御用半導体素子のワイヤパッドは、前記電力用半導体素子と前記第２の制御用半導体素子との間を除いて設けたことを特徴とする請求項１または請求項２に記載の電力用半導体装置。   The wire pad of said 1st control semiconductor element was provided except between the said power semiconductor element and said 2nd control semiconductor element, The Claim 1 or Claim 2 characterized by the above-mentioned. Power semiconductor device. 前記第１および第２のダイパッド部は、前記第１のダイパッド部に平行な投影面上で互いに隣接することを特徴とする請求項１ないし請求項３のいずれか１項に記載の電力用半導体装置。   4. The power semiconductor according to claim 1, wherein the first and second die pad portions are adjacent to each other on a projection plane parallel to the first die pad portion. 5. apparatus. 前記金属線は、前記第１の制御用半導体素子と前記リードとを電気的に接続する金属線、前記第１の制御用半導体素子と前記第２の制御用半導体素子とを電気的に接続する金属線、および前記第２の制御用半導体素子と前記リードと電気的に接続する金属線のいずれよりも直径が大きいことを特徴とする請求項１ないし請求項４のいずれか１項に記載の電力用半導体装置。   The metal line electrically connects the first control semiconductor element and the lead, and electrically connects the first control semiconductor element and the second control semiconductor element. 5. The diameter according to claim 1, wherein the diameter is larger than any of the metal wire and the metal wire electrically connected to the second control semiconductor element and the lead. Power semiconductor device. 裏面が前記モールド樹脂から露出するように設けられた放熱板をさらに備え、
前記第１のダイパッド部の第１面と対向する第２面が絶縁性材料を介して前記放熱板の表面と接するように設けられ、
前記第２のダイパッド部の第１面と対向する第２面が前記モールド樹脂に覆われるように設けられたことを特徴とする請求項１ないし請求項５のいずれか１項に記載の電力用半導体装置。 A heat sink provided so that the back surface is exposed from the mold resin;
A second surface facing the first surface of the first die pad portion is provided so as to be in contact with the surface of the heat sink via an insulating material;
6. The electric power according to claim 1, wherein a second surface facing the first surface of the second die pad portion is provided so as to be covered with the mold resin. 6. Semiconductor device. 前記第２の制御用半導体素子の四辺のうち、前記電力用半導体素子側の辺が、前記第１の制御用半導体素子の四辺のうち前記電力用半導体素子側の辺上に位置することを特徴とする請求項２ないし請求項６のいずれか１項に記載の電力用半導体装置。   Of the four sides of the second control semiconductor element, the side on the power semiconductor element side is located on the side on the power semiconductor element side of the four sides of the first control semiconductor element. The power semiconductor device according to any one of claims 2 to 6.
JP2009175322A 2009-07-28 2009-07-28 Power semiconductor device Pending JP2011029492A (en)

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