JP2010192815A - Image sensor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve productivity of an image sensor by preventing the spread of the area where a fault current is output in the periphery even when defective pixels exist caused by short circuit and the like. <P>SOLUTION: An image sensor includes a plurality of pixels 1 including a first photoconductor type element 6 and a second photoconductor type element 8, an output electrode 12B connected with the first photoconductor type element 6 and the second photoconductor type element 8, a common electrode 12C connected with the first photoconductor type element 6 that is included in each plurality of pixels 1, and rectifier elements 7A and 7B that are provided between the output electrode 12B and the common electrode 12C to prevent a current flowing in the opposite direction during operation. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an image sensor.

As an image sensor in which a large number of pixels are arranged, there is an infrared image sensor in which each pixel is configured by, for example, a quantum well type infrared photo detector (QWIP).
For example, as shown in FIG. 9, there is an infrared image sensor in which each pixel is configured by two-wavelength QWIP having an element structure having sensitivity in two wavelength regions.

  Here, the two-wavelength QWIP is a lower contact layer, a lower multi quantum well (MQW) layer having sensitivity to one wavelength region, an intermediate contact layer, and an upper portion having sensitivity to another wavelength region. The MQW layer and the upper contact layer are sequentially stacked. The lower MQW layer is referred to as a first sensor element (QWIP element), and the upper MQW layer is also referred to as a second sensor element (QWIP element).

Then, an electrode is attached so as to be in contact with each of these three contact layers, a readout circuit is connected to these three electrodes, and a photocurrent signal (output current) from the upper MQW layer or the lower MQW layer is individually read out. It is like that.
In this case, three bump electrodes are formed on the surface of each pixel, and a bias voltage is applied to the upper MQW layer and the lower MQW layer via the bump electrode and the intermediate contact layer connected to the intermediate contact layer. Then, the first switch is turned on, the second switch is turned off, and the photocurrent signal from the lower MQW layer is read out via the bump electrode connected to the lower contact layer. Further, the first switch is turned off and the second switch is turned on so that the photocurrent signal from the upper MQW layer is read out via the bump electrode connected to the upper contact layer.

Japanese Patent No. 3942296

By the way, in the infrared image sensor as described above, it is desired to increase the number of pixels so that a higher definition image can be acquired.
For this reason, it is conceivable to reduce the area of each pixel in order to increase the number of pixels.
However, as shown in FIG. 9, if there are three bump electrodes on the surface of each pixel for connection to the readout circuit, it is difficult to reduce the size of each pixel.

Therefore, as shown in FIG. 10, the lower contact layer is a common contact layer that connects all the pixels arranged in large numbers, and this is used as one bump electrode provided outside the region where the large number of pixels are provided. It is possible to connect. Thereby, it is only necessary to form two bump electrodes on the surface of each pixel.
In this case, a bias voltage is supplied through the bump electrode connected to the lower contact layer and the bump electrode connected to the upper contact layer, and a photocurrent signal is taken out through the bump electrode connected to the intermediate contact layer. Like that.

For this reason, the bump electrode connected to the lower contact layer is connected to the bias power source via the first switch, and the bump electrode connected to the upper contact layer is connected to the bias power source via the second switch. Then, the first switch and the second switch are alternately turned on, and a bias voltage is alternately applied to the upper MQW layer and the lower MQW layer.
Further, the bump electrode connected to the intermediate contact layer is connected to the readout circuit via the third switch.

  Then, the first switch is turned on, the second switch is turned off, the lower contact layer and the bias power source are connected, the bump electrode provided outside the pixel formation region, and the lower contact layer common to all pixels A bias voltage is applied to the lower MQW layer of all the pixels through. In this state, the third switch is turned on to take out a photocurrent signal from the lower MQW layer through the bump electrode connected to the intermediate contact layer.

  On the other hand, the first switch is turned off, the second switch is turned on, the upper contact layer and the bias power source are connected, and the bump electrode connected to the upper contact layer and the upper contact layer are connected to each pixel. A bias voltage is applied to the upper MQW layer. In this state, the third switch is turned on to take out a photocurrent signal from the upper MQW layer through the bump electrode connected to the intermediate contact layer.

By the way, since such an infrared image sensor uses a common lower contact layer for all pixels, if there is a defective pixel (such as a short circuit), an abnormal current flows not only in the defective pixel but also in an adjacent pixel. As a result, it has been found that there are cases where the signal cannot be read normally.
That is, only the output current of the second sensor element is operated by operating the second sensor element (upper MQW layer) positioned above without operating the first sensor element (lower MQW layer) positioned below each pixel. As shown in FIG. 11, the first switch common to all the pixels is turned off, and the second switch provided for each pixel is turned on.

  As shown on the left side in FIG. 11, in a normal region that does not include a defective pixel, in each pixel, the upper contact layer side connected to the bias power supply has a negative potential, and the intermediate contact layer side connected to the readout circuit has a positive potential. Become potential. A bias voltage is applied to the second sensor element due to the potential difference between the two, and a photocurrent signal (signal current) generated in the second sensor element can be read as an output current.

In this case, the first sensor element is connected to the lower contact layer common to all the pixels, but the first switch is turned off and is disconnected from the bias power source (here, a negative potential). For this reason, the first sensor elements of adjacent pixels are maintained at substantially the same potential, and no current flows through the first sensor elements.
Accordingly, only the photocurrent signal generated by the second sensor element connected to the bias power source is output as an output current to the readout circuit, and an image image (image information) by the photocurrent signal generated by the second sensor element. Can be obtained.

On the other hand, as shown on the right side in FIG. 11, in a region including a defective pixel in which a defect such as a short circuit exists in a part of the second sensor element, the potential difference between both ends of the second sensor element of the defective pixel is almost zero. (No voltage drop occurs due to signal current). As a result, in this defective pixel, the intermediate contact layer side also has a negative potential.
On the other hand, in a normal pixel adjacent to the defective pixel, the intermediate contact layer side has a positive potential. For this reason, a potential difference is generated between the first sensor elements of adjacent pixels, and a current flows from the first sensor element included in the normal pixel to the first sensor element included in the defective pixel.

As a result, an extra current other than the output current of the second sensor element flows in a normal pixel adjacent to the defective pixel. For this reason, an abnormal output current is output to the readout circuit as an output current of the second sensor element not only in a defective pixel having a short circuit but also in a normal pixel adjacent thereto.
In addition, as described above, when a current flows from the first sensor element included in the normal pixel to the first sensor element included in the defective pixel, the region that has decreased to the negative potential spreads around the defective pixel. It will be. For this reason, a region where an abnormal output current is output to the readout circuit as the output current of the second sensor element also extends to the periphery. As described above, the presence of one defective pixel causes an abnormality in the output current of a wide range of pixels. In this regard, if a defective pixel is isolated, it can be dealt with by a replacement process with an adjacent pixel. However, if an abnormality occurs in a wide range, correction cannot be performed by such a process.

In particular, if the pixels are miniaturized, the upper MQW layer is processed and wiring is formed in a narrow region, so that defects such as a short circuit are likely to occur, and it is difficult to improve the productivity of the image sensor.
Therefore, even if there is a defective pixel that causes a short circuit or the like, it is desired to improve the productivity of the image sensor by preventing the area around which the abnormal output current is output from expanding.

  For this reason, the image sensor includes a plurality of pixels including a first photoconductor element and a second photoconductor element, an output electrode connected to the first photoconductor element and the second photoconductor element, Provided between the common electrode connected to the first photoconductive element included in each of the plurality of pixels, the output electrode, and the common electrode, and prevents a current flowing in the direction opposite to the direction of the current flowing during operation. It is a requirement to provide a rectifying element to perform.

  The image sensor includes a sensor element array and a signal processing circuit connected to the sensor element array, and the sensor element array includes a plurality of pixels including a first photoconductor element and a second photoconductor element; An output electrode connected to the first photoconductor element and the second photoconductor element, a common electrode connected to the first photoconductor element included in each of the plurality of pixels, and an output electrode and a common electrode And a rectifying element that is provided between them and prevents a current that flows in a direction opposite to the direction of the current that flows during operation.

  Therefore, according to the present image sensor, even if there is a defective pixel that has caused a short circuit or the like, it is possible to prevent an area where an abnormal output current is output from expanding around the defective pixel. There is an advantage that the performance can be improved.

It is a schematic diagram which shows the structure of the image sensor concerning this embodiment. It is a figure for demonstrating the effect | action and effect by the image sensor concerning this embodiment. It is a figure which shows the structure of the circuit contained in the signal processing circuit array of the image sensor concerning this embodiment. It is a figure which shows the structure of the circuit contained in the signal processing circuit array of the image sensor concerning this embodiment. It is a time chart for demonstrating operation | movement of the image sensor concerning this embodiment. It is a typical sectional view showing the semiconductor lamination structure of the sensor element array of the image sensor concerning this embodiment. (A)-(I) are typical sectional drawings for demonstrating the manufacturing method of the sensor element array of the image sensor concerning this embodiment. It is typical sectional drawing which shows the modification of the semiconductor laminated structure of the sensor element array of the image sensor concerning this embodiment. It is a schematic diagram which shows the structure of the conventional infrared image sensor. It is a schematic diagram which shows the structure of the image sensor proposed in the creation process of the image sensor concerning this embodiment. It is a figure for demonstrating the subject of an image sensor.

Hereinafter, the image sensor according to the present embodiment will be described with reference to FIGS.
This image sensor is an image sensor (two-dimensional array sensor) in which a plurality of pixels including a photodetection element that generates a photocurrent signal according to incident light (incident light amount) is two-dimensionally arranged. This is a multi-wavelength image sensor having an element structure having sensitivity in a plurality of wavelength regions in a pixel.

In particular, this image sensor is an infrared image sensor in which each pixel is configured by a quantum well infrared photodetector (QWIP).
As shown in FIG. 1, this infrared image sensor includes an array sensor including a sensor element array 2 including a plurality of pixels 1 and a signal processing circuit array (signal processing circuit) 3 connected to each of the plurality of pixels 1. (Imaging device). The sensor element array 2 and the signal processing circuit array 3 are connected via conductive metal bump electrodes (here, In bump electrodes) 4A to 4C. The sensor element array 2 is also referred to as an infrared focal plane array (IRFPA) or a QWIP focal plane array (QWIP-FPA).

Hereinafter, a two-wavelength IRFPA in which a plurality of pixels including a two-wavelength QWIP having an element structure having sensitivity in two wavelength regions as a light detection element (sensor element) is two-dimensionally arranged will be described as an example.
As shown in FIG. 1, the two-wavelength IRFPA includes a lower contact layer 5, a lower multi quantum well (MQW) layer 6 having sensitivity to one wavelength region, an intermediate contact layer 7, and other wavelengths. The semiconductor device includes a semiconductor multilayer structure in which an upper MQW layer 8 and an upper contact layer 9 having a sensitivity to a region are sequentially stacked.

In other words, this two-wavelength IRFPA has a plurality of pixels 1 in which a lower MQW layer 6, an intermediate contact layer 7, an upper MQW layer 8, and an upper contact layer 9 are sequentially stacked on a lower contact layer 5 common to all pixels. It has a formed structure. The upper MQW layer 8 and the lower MQW layer 6 are light absorbing portions, and these have different absorption regions.
Here, the optical response wavelength of the lower MQW layer 6 or the upper MQW layer 8 depends on the energy difference between the quantum levels. Therefore, depending on the thickness of the well layer constituting the lower MQW layer or the upper MQW layer and the energy height of the barrier layer (which varies depending on the material and composition of the barrier layer), the optical response wavelength [one wavelength region (absorption region) ) Or other wavelength region (absorption region)].

Here, the upper MQW layer 8 and the lower MQW layer 6 are set so that the photoresponse peak wavelengths of 5 μm and 8.5 μm can be obtained as standard by the quantum well structure, respectively.
Note that the MQW layers 6 and 8 can be regarded as resistors whose resistance values change according to incident light (infrared rays in this case), and are also referred to as photoconductor elements. The MQW layers 6 and 8 are also called infrared photodetectors. A structure in which the MQW layers 6 and 8 are sandwiched between the contact layers 5, 7, and 9 is also referred to as a QWIP or a QWIP element. Further, the lower MQW layer 6 is also referred to as a first sensor element (first photoconductor element), and the upper MQW layer 8 is also referred to as a second sensor element (second photoconductor element). The lower contact layer 5 is also referred to as a common contact layer because it is connected to all of the lower MQW layers 6 included in each of the plurality of pixels 1. Further, the lower contact layer 5 extends to the outside (outer periphery) of the pixel formation region where the plurality of pixels 1 are provided, and supplies a bias voltage to the lower MQW layer 6 of each pixel 1 as will be described later. It also functions as a wiring for the purpose, so it is also called a common wiring.

  In particular, in the present embodiment, the intermediate contact layer 7 includes the lower contact layer 7A in contact with the lower MQW layer 6, the upper contact layer 7C in contact with the upper MQW layer 8, and the lower contact layer 7A and the upper contact layer 7C. Between the lower contact layer 7A and the upper contact layer 7C and a semiconductor layer 7B having a different conductivity type (reverse conductivity type). That is, the semiconductor layer 7B is connected to the upper MQW layer 8 via the upper contact layer 7C, and is connected to the lower MQW layer 6 via the lower contact layer 7A.

The contact layer sandwiching the lower MQW layer 6, that is, the lower contact layer 7A included in the lower contact layer 5 and the intermediate contact layer 7 is also referred to as a first contact layer. The contact layer sandwiching the upper MQW layer 8, that is, the upper contact layer 7C included in the upper contact layer 9 and the intermediate contact layer 7 is also referred to as a second contact layer.
Specifically, in this embodiment, an i-GaAs layer 11, an n-type GaAs lower contact layer 5, an AlGaAs / GaAs lower MQW layer 6, a GaAs intermediate contact layer 7 (an n-type GaAs lower contact) are formed on a GaAs substrate 10. The layer 7A, the p-type GaAs layer 7B, the n-type GaAs upper contact layer 7C), the AlGaAs / InGaAs upper MQW layer 8, and the n-type GaAs upper contact layer 9 are sequentially stacked.

  The AlGaAs / GaAs lower MQW layer 6 has a structure in which a number of quantum wells composed of an AlGaAs barrier layer 6A and a GaAs well layer 6B are repeated (see FIGS. 6 and 8). Similarly, the AlGaAs / InGaAs upper MQW layer 8 has a structure in which a large number of quantum wells composed of an AlGaAs barrier layer 8A and an InGaAs well layer 8B are repeated (see FIGS. 6 and 8).

As described above, in this embodiment, each of the two MQW layers 6 and 8 is sandwiched between the n-type contact layers 5, 7 A, 7 C, and 9, and the n-type contact layer 7 A provided between the two MQW layers 6 and 8. , 7C, a p-type semiconductor layer 7B having a conductivity type opposite to that of the contact layers 7A, 7C is provided.
In addition, ohmic electrodes 12A, 12B, and 12C are attached to the upper contact layer 9, the intermediate contact layer 7, and the lower contact layer 5, respectively. The signal processing circuit array 3 is connected to these three ohmic electrodes 12A, 12B, and 12C via wirings 13A, 13B, and 13C and bump electrodes 4A, 4B, and 4C. As a result, a bias voltage is applied to the upper MQW layer 8 or the lower MQW layer 6 by electrons photoexcited from the ground level to the excited level by light absorption in the quantum well of the upper MQW layer 8 or the lower MQW layer 6. To take out the quantum well and generate a photocurrent. The readout circuit 14 (see FIG. 4) included in the signal processing circuit array 3 individually reads out photocurrent signals (output currents) from the upper MQW layer 8 or the lower MQW layer 6.

In particular, in this embodiment, two bump electrodes 4A and 4B are provided on the surface of each pixel 1, and one bump electrode 4C is provided outside the pixel formation region. In this manner, the number of bump electrodes on the surface of each pixel 1 is reduced to reduce the size of each pixel 1.
Then, one bump electrode 4A formed on the surface of each pixel 1 and the ohmic electrode 12A formed on the upper contact layer 9 are connected by a wiring 13A. Further, the other bump electrode 4B formed on the surface of each pixel 1 and the ohmic electrode 12B formed on the semiconductor layer 7B included in the intermediate contact layer 7 are connected by a wiring 13B. Further, one bump electrode 4A provided outside the pixel formation region and an ohmic electrode 12C formed on the lower contact layer 5 common to all the pixels 1 are connected by a wiring 13C.

  One bump electrode 4C provided outside the pixel formation region is connected to the first switch 15 in the bias voltage supply circuit 16 (see FIG. 3) included in the signal processing circuit array 3. That is, by switching the first switch 15, the bias voltage supplied from the bias voltage supply circuit 16 is supplied to the lower MQW layer 6 via the ohmic electrode 12 </ b> C and the lower contact layer 5. Here, since the first switch 15 is connected to the lower contact layer 5 as a common wiring, the bias voltage is supplied to the lower MQW layer 6 included in all the pixels 1 by switching the first switch 15. To be performed. For this reason, since the ohmic electrode 12C connected to the lower contact layer 5 is used to supply a bias voltage, it is also referred to as a bias electrode (bias supply electrode; lower MQW drive electrode). The ohmic electrode 12C connected to the lower contact layer 5 is also referred to as a common electrode because it is used to supply a bias voltage to all of the lower MQW layers 6 included in each of the plurality of pixels 1.

  One bump electrode 4A formed on the surface of each pixel 1 is connected to a second switch 17 in a bias voltage supply circuit 16 (see FIG. 3) included in the signal processing circuit array 3. That is, by switching the second switch 17, the bias voltage supplied from the bias voltage supply circuit 16 is supplied to the upper MQW layer 8 through the ohmic electrode 12 A and the upper contact layer 9. For this reason, since the ohmic electrode 12A connected to the upper contact layer 9 is used to supply a bias voltage, it is also referred to as a bias electrode (bias supply electrode; upper MQW drive electrode).

  Further, the other bump electrode 4B formed on the surface of each pixel 1 is included in the signal processing circuit array 3 and provided for each pixel in order to input a photocurrent signal to the readout circuit 14 (see FIG. 4). Connected to the third switch 18 in the input circuit 19 (see FIG. 3). That is, by switching the third switch 18, the photocurrent signal flowing through the upper MQW layer 8 or the lower MQW layer 6 is output as an output current via the ohmic electrode 12B connected to the semiconductor layer 7B included in the intermediate contact layer 7. Thus, the signal is output to the input circuit 19 included in the signal processing circuit array 3. Therefore, the ohmic electrode 12B formed on the semiconductor layer 7B included in the intermediate contact layer 7 is used to output a photocurrent signal flowing in the upper MQW layer 8 or the lower MQW layer 6 as an output current. Also referred to as an electrode (signal extraction electrode). The third switch 18 is also referred to as an output switch because it is used to output a photocurrent signal flowing through the upper MQW layer 8 or the lower MQW layer 6 as an output current. The third switch 18 is also referred to as an input gate because it is used to input a photocurrent signal to the input circuit 19.

The semiconductor layer 7B is connected to the upper MQW layer 8 via the upper contact layer 7C, and is connected to the lower MQW layer 6 via the lower contact layer 7A. Therefore, the semiconductor layer 7B is formed on the semiconductor layer 7B. The ohmic electrode 12B thus formed is connected to the upper MQW layer 8 and the lower MQW layer 6.
By the way, in this embodiment, as described above, the intermediate contact layer 7 has a structure in which the lower contact layer 7A, the upper contact layer 7C, and the semiconductor layer 7B having different conductivity types are stacked. The output electrode 12B is attached to the semiconductor layer 7B.

  Thus, since the lower contact layer 7A and the semiconductor layer 7B included in the intermediate contact layer 7 have different conductivity types, a current in the direction opposite to the direction of current flowing during operation flows through these layers 7A and 7B. A rectifying element (pn junction diode) 20 (see FIG. 2) is constructed. That is, the rectifying element 20 is provided between the output electrode 12B and the common electrode 12C so as to prevent a current flowing in the direction opposite to the direction of the current flowing during operation.

Therefore, as described below, even if there is a defective pixel that causes a short circuit or the like, it is possible to prevent an area in which an abnormal output current is output from expanding.
Hereinafter, as shown in FIG. 2, the second sensor element (upper MQW layer) 8 is operated without operating the first sensor element (lower MQW layer) 6 of each pixel 1. In the case of reading only the output current, a case where the first switch 15 common to all the pixels 1 is turned off and the second switch 17 provided for each pixel is turned on will be described as an example.

  As shown on the left side in FIG. 2, in a normal region that does not include a defective pixel, one side of the second sensor element 8 connected to the bias source (−V) via the second switch 17 in each pixel 1. (Upper contact layer 9 side) becomes a negative potential, and the other side (intermediate contact layer 7 side) of the second sensor element 8 connected to the third switch 18 in the input circuit 19 of the signal processing circuit array 3 is a positive potential. become. A bias voltage is applied to the second sensor element 8 due to the potential difference between the two, and a photocurrent signal (signal current) generated in the second sensor element 8 can be read as an output current.

  Here, in the present embodiment, a pn junction diode 21 constituted by the upper contact layer 7C and the semiconductor layer 7B included in the intermediate contact layer 7 is connected to the second sensor element 8 in series. The forward bias state is such that a positive potential is applied to the p side (p-type semiconductor layer 7B side) of the pn junction diode 21 and a negative potential is applied to the n-side (n-type upper contact layer 7C side). For this reason, the output current of the second sensor element 8 flows as it is.

In this case, the first sensor element 6 is connected to the lower contact layer 5 common to all the pixels 1, but the first switch 15 is turned off, and what is a bias source (here, negative potential; −V)? Is disconnected. For this reason, the first sensor elements 6 of the adjacent pixels 1 are maintained at substantially the same potential, and no current flows through the first sensor elements 6.
Therefore, only the photocurrent signal generated by the second sensor element 8 connected to the bias source (−V) is output as the output current to the readout circuit 14 via the third switch 18, and the second sensor element. The image information by the photocurrent signal generated in 8 can be read.

On the other hand, as shown on the right side in FIG. 2, in the region including defective pixels in which a defect such as a short circuit exists in a part of the second sensor element 8, the intermediate contact layer side becomes a negative potential. That is, in the region including the defective pixel, the n-type upper contact layer and the p-type semiconductor layer that are in contact with the second sensor element of the defective pixel have a negative potential.
On the other hand, in the normal pixel 1 adjacent to the defective pixel, the other side of the second sensor element 8 connected to the third switch 18 in the input circuit 19 of the signal processing circuit array 3 (the intermediate contact layer 7 side; FIG. 2) The middle and lower sides are positive. That is, the n-type lower contact layer 7A and the p-type semiconductor layer 7B included in the intermediate contact layer 7 in contact with the first sensor element 6 are at a positive potential.

For this reason, a potential difference occurs between the first sensor elements 6 of adjacent pixels. That is, a potential difference is generated between the p-type semiconductor layer 7B of the defective pixel and the n-type lower contact layer of the normal pixel 1 adjacent to the defective pixel.
However, in the present embodiment, a pn junction diode 20 is connected in series to the first sensor element 6 of the defective pixel 1, and on the p side (p type semiconductor layer 7B side) of the pn junction diode 20. A negative potential is in a reverse bias state in which a positive potential is applied to the n side (n-type lower contact layer 7A side). For this reason, the current flowing between the first sensor elements 6 of the adjacent pixels 1 is cut off by the pn junction diode 20 in the reverse bias state, and the most potential difference is applied to the diode portion. There is almost no potential difference between the first sensor elements 6 of the pixel 1.

As a result, the current flowing between the first sensor elements 6 of the adjacent pixels 1, that is, the current flowing from the first sensor element 6 included in the normal pixel 1 to the first sensor element 6 included in the defective pixel 1 is greatly suppressed. Will be.
As a result, even if there is a defective pixel 1 that has caused a short circuit or the like, it is possible to prevent an area in which an abnormal output current is output from expanding.

  In addition, when a defect such as a short circuit exists in a part of the first sensor element 6 and the output current of the first sensor element 6 is read, the second switch 17 provided for each pixel is turned off, Since adjacent pixels are not connected, there is no problem that an abnormal current flows as described above. Further, since a metal wiring or the like is usually provided on the top of the pixel 1, defects such as a short circuit often occur in the second sensor element 8 provided on the top of the pixel 1.

By the way, as shown in FIG. 1, this infrared image sensor connects the two-wavelength IRFPA 2 configured as described above and the signal processing circuit array 3 configured by a CMOS circuit via bump electrodes 4A to 4C. It has a structure.
Here, as shown in FIGS. 3 and 4, the signal processing circuit array 3 includes a first switch (first transistor) 15, a second switch (second transistor) 17, an input circuit 19, and each input circuit. The readout circuit 14 sequentially reads out the 19 outputs to the outside. In addition, the one pixel unit 22 provided for every pixel is comprised as what contains the 2nd switch 17 and the input circuit 19. FIG.

Among these, the first switch 15 is a switch for turning on / off a bias voltage (here, a negative bias voltage) supplied to the lower contact layer 5 common to all the pixels 1 as shown in FIG.
The second switch 17 is a switch for turning on / off a bias voltage (here, a negative bias voltage) supplied to the upper contact layer 9 of each pixel 1.

The first switch 15 and the second switch 17 are connected to a common bias source (negative bias source). A bias voltage supply circuit 16 is configured to include the first switch 15 and the second switch 17.
The input circuit 19 is provided for each pixel in order to convert the output current from the sensor elements 6 and 8 of each pixel 1 into a voltage and output the voltage. The input circuit 19 includes an input gate (third switch) 18 and an integration capacitor element (capacitor). And a reset switch (reset transistor) 25 connected to the reset power supply 24.

The two sensor elements 6 and 8 are connected to the input side of the input circuit 19 via the bump electrode 4B. On the other hand, the output terminal of the input circuit 19 is connected to the gate terminal of the source follower transistor 26 of the readout circuit 14 described later.
In the input circuit 19 configured as described above, an output voltage corresponding to the amount of current flowing through the sensor elements 6 and 8 when infrared rays are incident is output from the output terminal.

  As shown in FIG. 4, the readout circuit 14 includes a plurality of source follower transistors 26 that operate according to the output of the input circuit 19 included in one pixel unit 22, a plurality of row selection transistors 27, and a plurality of row lines 28. A plurality of column lines (output lines) 29, a plurality of column selection transistors 30, a readout line (output line) 31, a load transistor 32, a vertical scanning shift register 33, and a horizontal scanning shift register 34. .

Here, the gate terminal of each source follower transistor 26 is connected to each of the plurality of input circuits 19. Further, the drain terminal of each source follower transistor 26 is connected to the power supply line 35 and is supplied with a power supply voltage.
Each row selection transistor 27 is connected to each of the source terminals of the plurality of source follower transistors 26. Each row line 28 is connected to the gate terminal of the row selection transistor 27 in each row.

  Each column line 29 is connected to a source follower transistor 26 via a row selection transistor 27. That is, each column line 29 is connected to the source follower transistor 26 of each column via the row selection transistor 27. Each column selection transistor 30 is connected to each of a plurality of column lines 29. Further, the readout line 31 is connected to all the column selection transistors 30.

  The vertical scanning shift register 33 is connected to all the row lines 28, sequentially drives each row line 28, and performs conduction / non-conduction control of the row selection transistor 27 connected to each row line 28. Yes. The horizontal scanning shift register 34 is connected to all the column selection transistors 30 and sequentially drives each column selection transistor 30 to control conduction / non-conduction of each column selection transistor 30.

One of the read lines 31 is connected to the output terminal (Vout), and the other is connected to the ground potential (GND) via the load transistor 32.
When the row line 28 is selected by the vertical scanning shift register 33, the row selection transistor 27 connected to the selected row line 28 is turned on (on state). When the row selection transistor 27 becomes conductive, output signals from the sensor elements 6 and 8 included in each pixel 1 are output to the column line 29 via the input circuit 19, the source follower transistor 26 and the row selection transistor 27. The

  On the other hand, when the column selection transistor 30 is selected by the horizontal scanning shift register 34, the selected column selection transistor 30 is turned on (on state). When the column selection transistor 30 becomes conductive, the output signal output to each column line 29 as described above is output to the readout line 31 via the column selection transistor 30. The output signal output to the readout line 31 is output to the output terminal.

In particular, in the present embodiment, as shown in FIGS. 3 and 4, the first sensor element (lower MQW layer) 6 and the second sensor element ( The upper MQW layer) 8 is alternately connected to the bias power source, and the first sensor element 6 and the second sensor element 8 are operated alternately.
When either the first sensor element 6 or the second sensor element 8 is operating and the input gate 18 is turned on for a necessary period (integration time), the first sensor element 6 or the second sensor element 8 The photocurrent signal flows into the integrating capacitor 23, and the voltage generated by the accumulated charges is output to the readout circuit 1 as an output signal voltage.

After completion of the integration time, the input gate 18 is turned off to determine the output voltage from each pixel 1, and this is read out in time series using the shift registers 33 and 34.
A specific operation will be described below with reference to the timing chart of FIG. The following operations are executed based on commands from the controller.
First, the first switch 15 is turned on, the second switch 17 is turned off, and a bias voltage is supplied to the lower MQW layer (first sensor element) 6.

Next, the reset transistor 25 is turned on to perform a reset operation. Thereby, the integrating capacitive element 23 is connected to the reset power supply 24, and the capacitive voltage is set to the reset value.
Next, the input gate 18 is turned on, and the integration capacitor element 23 is discharged.
Then, after the elapse of a predetermined period (integration time), the input gate 18 is turned off. Thereby, the voltage at the end of the integration capacitor element determined by the electrons flowing into the integration capacitor element 23 during the discharge period (integration time) becomes the output voltage value of each pixel 1.

Such an operation is performed in all the pixels 1 arranged two-dimensionally.
Next, the start signals of the shift registers 33 and 34 are input, and the scanning read operation of the output voltage value of each pixel 1 is executed.
The vertical scanning shift register 33 selects the first row, and the horizontal scanning shift register 34 sequentially selects the column lines 29 to execute scanning for one row. By selecting the last column line 29, the vertical scanning shift register 33 advances one count, the next row line 28 is selected, and the horizontal scanning shift register 34 sequentially selects the column line 29. This is repeated and the output voltage values of all the pixels 1 are read out. Note that both the vertical scanning shift register 33 and the horizontal scanning shift register 34 are stopped when the selection of the last row line 29 and the last column line 29 is completed.

Thereafter, the on / off state of the first switch 15 and the second switch 17 is reversed, the first switch 15 is turned off, the second switch 17 is turned on, and the bias voltage is applied to the upper MQW layer (second sensor element) 8. Supply.
Next, a reset operation is performed again, and after setting the capacitance voltage of the integration capacitance element 23 to a reset value, the input gate 18 is turned on, and an integration operation is performed by the photocurrent signal flowing in the upper MQW layer 8. The output voltage value of the pixel 1 is determined.

That is, as in the case described above, the input gate 18 is turned on and the integrating capacitor element 23 is discharged. Then, after the integration time has elapsed, the input gate 18 is turned off. Thereby, the voltage at the end of the integration capacitor element determined by the electrons flowing into the integration capacitor element 23 during the discharge period (integration time) becomes the output voltage value of each pixel 1.
Thereafter, in the same manner as described above, the horizontal scanning shift register 34 and the vertical scanning shift register 33 are operated, and the scanning read operation of the output voltage values of all the pixels 1 is executed.

By repeating such an operation by switching the first switch 15 and the second switch 17 at a frame rate of 60 Hz, for example, infrared images of two different wavelength ranges, for example, an infrared image image of 5 μm and an infrared image image of 8.5 μm. Images can be acquired with a 30 Hz period.
Hereinafter, a specific configuration example of the infrared image sensor (two-wavelength image sensor) and a manufacturing method thereof will be described with reference to FIGS.

  First, as shown in FIG. 6, a semiconductor laminated structure constituting the infrared image sensor has an i-GaAs layer 11, an n-GaAs lower contact layer 5, and a first MQW layer 6 (i) on a GaAs (100) substrate 10. -AlGaAs barrier layer 6A / n-GaAs well layer 6B), intermediate contact layer 7 (n-GaAs lower contact layer 7A, p-GaAs layer 7B, n-GaAs upper contact layer 7C), second MQW layer 8 (i- The AlGaAs barrier layer 8A / n-InGaAs well layer 8B) and the n-GaAs upper contact layer 9 are sequentially stacked.

Next, the manufacturing method of the semiconductor laminated structure which comprises this infrared image sensor is demonstrated, referring FIG.
First, an i-GaAs layer 11 and an n-GaAs layer 5 as a lower contact layer are grown on a GaAs (100) substrate 10, and a first MQW layer 6 is formed thereon.
Here, the i-GaAs layer 11 has a thickness of 1000 mm. The n-GaAs lower contact layer 5 has a thickness of 9000 mm and an n-type impurity (Si) concentration of 1 × 10 ¹⁸ cm ⁻³ . Furthermore, the first MQW layer 6 has a structure in which the barrier layer is an i-AlGaAs layer 6A, the well layer is an n-GaAs layer 6B, and these layers are alternately stacked 20 times. Here, the i-AlGaAs barrier layer 6A has an Al composition of 0.25 and a thickness of 400 mm. The n-GaAs well layer 6B has an n-type impurity (Si) concentration of 4 × 10 ¹⁷ cm ⁻³ and a thickness of 50 mm.

Next, on the first MQW layer 6, as an intermediate contact layer 7, an n-GaAs layer (lower contact layer) 7A, a p-GaAs layer (reverse conductivity type semiconductor layer) 7B, and an n-GaAs layer (upper contact layer) 7C is laminated in order.
Here, the n-GaAs lower contact layer 7A has a thickness of 4000 mm and an n-type impurity (Si) concentration of 1 × 10 ¹⁸ cm ⁻³ . The p-GaAs layer 7B has a thickness of 5000 mm and a p-type impurity (Be) concentration of 5 × 10 ¹⁷ cm ⁻³ . The n-GaAs upper contact layer 7C has a thickness of 4000 mm and an n-type impurity (Si) concentration of 1 × 10 ¹⁸ cm ⁻³ .

Next, the second MQW layer 8 is formed on the n-GaAs upper contact layer 7C.
Here, the second MQW layer 8 has a structure in which the barrier layer is an i-AlGaAs layer 8A, the well layer is an n-InGaAs layer 8B, and these layers are alternately stacked 20 times. Here, the i-AlGaAs barrier layer 8A has an Al composition of 0.35 and a thickness of 300 mm. Further, n-InGaAs well layer 8B is an In composition and 0.3, n-type impurity (Si) concentration of 5 × ¹⁰ 18 ^{cm -3,} and the thickness and 25 Å.

Thereafter, an n-GaAs layer 9 as an upper contact layer is grown on the second MQW layer 8.
Here, the n-GaAs upper contact layer 9 has a thickness of 10,000 mm and an n-type impurity (Si) concentration of 1 × 10 ¹⁸ cm ⁻³ .
For example, MBE (Molecular Beam Epitaxy) method or MOVPE (Metal Organic Chemical Vapor Deposition) method may be used for crystal growth of each semiconductor layer.

In this way, a semiconductor laminated structure (wafer) constituting the infrared image sensor is produced.
Next, a method for manufacturing the sensor element array 2 constituting the infrared image sensor using the wafer thus manufactured will be described with reference to FIG.
First, as shown in FIG. 7A, a diffraction grating structure (unevenness) 50 is formed on the wafer surface in order to produce an optical coupler necessary for QWIP. This is produced by processing the uppermost n-GaAs upper contact layer 9 by using, for example, dry etching and adding a predetermined step.

Next, as shown in FIG. 7B, each pixel is included in the intermediate contact layer 7 in order to form an ohmic electrode 12B in contact with the p-GaAs layer 7B included in the intermediate contact layer 7 of each pixel 1. A contact hole 36 extending to the p-GaAs layer 7B is formed.
That is, for example, by dry etching, the n-GaAs upper contact layer 9, the second MQW layer 8 (AlGaAs / InGaAs layer), and the intermediate contact layer 7 that are included in the outermost surface to the depth reaching the p-GaAs layer 7B. The contact hole 36 extending to the p-GaAs layer 7B is formed by sequentially processing the −GaAs upper contact layer 7C.

Next, as shown in FIG. 7C, in order to form an ohmic electrode 12C in contact with the n-GaAs lower contact layer 5 common to all the pixels 1 at the outer periphery of the pixel formation region, the n-GaAs lower contact is formed. A contact hole 37 extending to the layer 5 is formed.
That is, for example, by dry etching, the outermost n-GaAs upper contact layer 9, the second MQW layer 8 (AlGaAs / InGaAs layer), and the intermediate contact layer 7 (n -A contact hole extending to the n-GaAs lower contact layer 5 by sequentially processing the GaAs upper contact layer 7C, the p-GaAs layer 7B, the n-GaAs lower contact layer 7A), and the first MQW layer 6 (AlGaAs / InGaAs layer). 37 is formed.

Next, as shown in FIG. 7D, a SiON film 38 (protective film; insulating film) is formed so as to cover the entire surface.
Next, the SiON film 38 in the region for forming the ohmic electrodes 12A, 12B, 12C in contact with the n-GaAs upper contact layer 9, the p-GaAs layer 7B and the n-GaAs lower contact layer 5 included in the intermediate contact layer 7, respectively. Is removed by dry etching, for example.

Thereafter, for example, an AuGe / Au electrode is lifted off as the ohmic electrodes 12A, 12B, 12C in contact with the n-GaAs upper contact layer 9, the p-GaAs layer 7B included in the intermediate contact layer 7, and the n-GaAs lower contact layer 5, respectively. Form by law.
Next, as shown in FIG. 7E, after the SiON film 38 on the diffraction grating structure 50 formed on the outermost surface of the wafer is removed by, for example, dry etching, the TiW / Au is formed on the diffraction grating structure 50. A mirror electrode 39 is formed by, for example, a lift-off method.

Next, as shown in FIG. 7F, a SiON film 39 is formed so as to cover the entire surface, and wiring 13A for connecting the ohmic electrodes 12A, 12B, 12C and the In bump electrodes 4A, 4B, 4C. , 13B, 13C are removed from the regions where the ohmic electrodes 12A, 12B, 12C are in contact with each other by, for example, dry etching.
Then, as shown in FIG. 7G, wirings 13A, 13B, and 13C are formed so as to extend from the respective ohmic electrodes 12A, 12B, and 12C to the surface of the SiON film 39. Here, after Ti / Pt is sputter-deposited on the entire surface, a pattern is formed so that the regions for forming the wirings 13A, 13B, and 13C remain, and unnecessary Ti / Pt is removed by using, for example, ion milling. / Pt wirings 13A, 13B, and 13C are formed.

Next, as shown in FIG. 7H, separation grooves 40 for separating the plurality of pixels 1 are formed.
Here, after the SiON films 39 and 38 in the region where the isolation groove 40 is to be formed are removed by, for example, dry etching, each semiconductor layer 9, 8 is deepened to reach the n-GaAs lower contact layer 5 by using, for example, dry etching. , 7 and 6 are sequentially processed to form an isolation groove 40 extending to the n-GaAs lower contact layer 5.

After that, as shown in FIG. 7I, an SiON film 41 is again formed so as to cover the entire surface, and then In bump electrodes 4A, 4B, 4C necessary for connection with the signal processing circuit array 3 are formed. Form.
Here, the SiON film 41 in the region where the In bump electrodes 4A, 4B, and 4C are formed is removed by dry etching, for example, and the In bumps are connected to the wirings 13A, 13B, and 13C formed as described above. The electrodes 4A, 4B, 4C are formed by, for example, a lift-off method.

In this way, the sensor element array 2 constituting the infrared image sensor is manufactured.
Then, by connecting the sensor element array 2 manufactured in this way and the signal processing circuit array 3 constituted by a CMOS circuit via In bump electrodes 4A, 4B, 4C, the infrared image sensor is It is manufactured (see FIG. 1).
In addition, the manufacturing method of the semiconductor laminated structure (wafer) and the sensor element array 2 which comprise this infrared image sensor is not restricted to the above-mentioned structure and manufacturing method.

For example, as shown in FIG. 8, for example, an i-GaAs layer (surface insulating layer) is further formed on the uppermost n-GaAs upper contact layer 9 as shown in FIG. 45 and 46 may be provided.
Further, for example, as shown in FIG. 8, the layer structure of the semiconductor laminated structure constituting the infrared image sensor described above is included in the layer structure in order to achieve good depth control when processed by dry etching. Etching stopper layers 42, 43, and 44 for selective dry etching may be provided.

  Specifically, a semiconductor laminated structure constituting the infrared image sensor is formed on a GaAs (100) substrate 10 with an i-GaAs layer 11, an n-GaAs lower contact layer 5, an n-InGaP etching stopper layer 42, an n- GaAs layer 47, first MQW layer 6 (i-AlGaAs barrier layer 6A / n-GaAs well layer 6B), intermediate contact layer 7 (n-GaAs lower contact layer 7A, p-GaAs layer 7B, n-InGaP etching stopper layer) 43, n-GaAs upper contact layer 7C), second MQW layer 8 (i-AlGaAs barrier layer 8A / n-InGaAs well layer 8B), n-GaAs upper contact layer 9, i-GaAs insulating layer 45, i-AlGaAs etching A structure in which the stopper layer 44 and the i-GaAs insulating layer 46 are sequentially laminated may be employed.

Here, the n-InGaP etching stopper layer 42 has a thickness of 100 mm and an n-type impurity (Si) concentration of 1 × 10 ¹⁸ cm ⁻³ . The n-InGaP etching stopper layer 42 is an etching stopper layer for selective dry etching of GaAs / AlGaAs / InGaAs.
The n-GaAs layer 47 has a thickness of 500 mm and an n-type impurity (Si) concentration of 1 × 10 ¹⁸ cm ⁻³ .

The n-InGaP etching stopper layer 43 has a thickness of 100 mm and an n-type impurity (Si) concentration of 1 × 10 ¹⁸ cm ⁻³ . The n-InGaP etching stopper layer 43 is an etching stopper layer for selective dry etching of GaAs / AlGaAs / InGaAs.
The lower i-GaAs insulating layer 45 has a thickness of 2000 mm.

The i-AlGaAs etching stopper layer 44 has an Al composition of 0.3 and a thickness of 50 mm. The i-AlGaAs etching stopper layer 44 is an etching stopper layer for GaAs selective dry etching.
The upper i-GaAs insulating layer 46 has a thickness of 6500 mm.
As described above, by providing the i-GaAs insulating layers 45 and 46 on the outermost surface side, it is possible to improve the insulation between the wirings when the metal wirings are provided close to the wafer surface (element surface). Usually, the insulating property is ensured only by the SiON film, but the insulating property can be further improved by providing the insulating i-GaAs layers 45 and 46 below the insulating film. Thereby, it is possible to prevent a short circuit from occurring in the upper part of the pixel where the metal wiring is formed.

  Further, by providing the etching stopper layers 42 and 43 as described above, only the semiconductor layer to be removed by dry etching in the step of forming the diffraction grating structure 50 and the step of forming the contact holes 36 and 37 described above. The dry etching can be advanced to a predetermined depth by using the selective dry etching in which the etching stopper layers 42 and 43 are not etched.

Here, when it is set as the above layer structure, it is necessary to change each process in the manufacturing method of the above-mentioned embodiment as follows.
First, in the step of forming the diffraction grating structure 50 of the above-described manufacturing method [see FIG. 7A], first, using the i-AlGaAs etching stopper layer 44 as a stopper, the diffraction grating structure 50 as in the above-described manufacturing method. Are formed by selective dry etching.

  Further, in the step of forming the contact holes 36 and 37 in the manufacturing method described above [see FIGS. 7B and 7C], contact holes extending to the n-GaAs upper contact layer 9 are further formed. That is, since the i-GaAs insulating layers 46 and 45 exist on the outermost surface side of the semiconductor multilayer structure, the n-GaAs upper contact is formed for each pixel in order to form the ohmic electrode 12A in contact with the n-GaAs upper contact layer 9. It is necessary to form a contact hole extending to the layer 9.

  In this case, first, using the i-AlGaAs etching stopper layer 44 as a stopper, the i-GaAs insulating layer 46 on the outermost surface in a region where a contact hole extending to the n-GaAs upper contact layer 9 is formed is removed by selective dry etching. Next, the i-AlGaAs etching stopper layer 44 and the underlying i-GaAs insulating layer 45 are removed by wet etching using, for example, sulfuric acid + phosphoric acid + hydrogen peroxide solution as an etchant. In this way, a contact hole extending to the n-GaAs upper contact layer 9 is formed for each pixel.

  In the step of forming the contact hole 36 extending to the semiconductor layer (p-GaAs layer) 7B included in the intermediate contact layer 7 of the above manufacturing method [see FIG. 7B], the n-InGaP etching stopper layer 43 is formed. As a stopper, each semiconductor layer (GaAs layer / AlGaAs layer / InGaAs layer) in a region where the contact hole 36 extending to the semiconductor layer (p-GaAs layer) 7B included in the intermediate contact layer 7 is formed is removed by selective dry etching. Then, the n-InGaP etching stopper layer 43 is removed by wet etching using, for example, HCl. In this manner, a contact hole extending to the semiconductor layer (p-GaAs layer) 7B included in the intermediate contact layer 7 is formed for each pixel.

  In the step of forming the contact hole 37 extending to the lower contact layer 5 in the above-described manufacturing method [see FIG. 7C], first, the n-InGaP etching stopper layer 43 is used as a stopper to extend to the lower contact layer 5. Each semiconductor layer (GaAs layer / AlGaAs layer / InGaAs layer) in the region where the contact hole 37 is to be formed is removed by selective dry etching. Next, the n-InGaP etching stopper layer 43 is removed by wet etching using, for example, HCl. Next, using the n-InGaP etching stopper layer 42 as a stopper, each semiconductor layer (GaAs layer / AlGaAs layer / InGaAs layer) in the region where the contact hole 37 extending to the lower contact layer 5 is formed is removed by selective dry etching. Then, the n-InGaP etching stopper layer 42 is removed by wet etching using, for example, HCl. In this way, a contact hole 37 extending to the lower contact layer 5 is formed.

  Therefore, according to the image sensor according to the present embodiment, even if there is a defective pixel that has caused a short circuit or the like, it is possible to prevent an area where an abnormal output current is output from expanding around the defective pixel. There is an advantage that the productivity of the image sensor can be improved. That is, it is possible to suppress the deterioration of the output image obtained from the image sensor, and it is possible to improve the productivity of the image sensor that can obtain an output image with good uniformity.

  In particular, when a multi-wavelength image sensor in which a plurality of pixels 1 in which a plurality of sensor elements are stacked so as to receive light in different wavelength ranges is prepared, if the pixel 1 is further miniaturized, each pixel 1 The upper part is processed, and wiring is formed in a narrow area. For this reason, a defect such as a short circuit is likely to occur, and as a result, a region where an abnormal output current is output around the defective pixel tends to expand. Even in such a case, there is an advantage that the area where the abnormal output current is output around the defective pixel can be prevented from expanding, and the productivity of the image sensor can be improved. For example, even if there are several short-circuit defects in the sensor element array 2, it is possible to prevent this from affecting a wide area of the imaging screen.

Since such an effect is obtained, by using the image sensor according to the present embodiment, a night vision imaging system for night monitoring and a remote sensing system for heat source detection can be constructed with high productivity.
In the above-described embodiment, the lower contact layer 7A and the semiconductor layer 7B included in the intermediate contact layer 7 have different conductivity types, so that these layers have a direction opposite to the direction of current flowing during operation. Although the rectifying element 20 that prevents the current from flowing is configured, the present invention is not limited to this.

  For example, instead of the reverse conductivity type semiconductor layer 7B, a semiconductor layer made of a material (composition) having a narrower forbidden band than the lower contact layer 7A included in the intermediate contact layer 7 may be used. In this case, the conductivity types of the lower contact layer and the semiconductor layer included in the intermediate contact layer may be the same or different. That is, as the semiconductor layer included in the intermediate contact layer, a material having the same conductivity type as the lower contact layer included in the intermediate contact layer and having a narrower forbidden band than the lower contact layer included in the intermediate contact layer A semiconductor layer made of (composition) may be used. In addition, as a semiconductor layer included in the intermediate contact layer, a material having a conductivity type different from that of the lower contact layer included in the intermediate contact layer and having a narrower forbidden band than the lower contact layer included in the intermediate contact layer ( You may use the semiconductor layer which consists of a composition.

As described above, in the above-described embodiment, instead of using the pn junction or using the pn junction as a mechanism for providing rectification by the bias polarity applied to the intermediate contact layer, the forbidden band is used. Heterojunctions made of semiconductor materials having different widths can also be used, and in this case, similar actions and effects can be obtained.
Specifically, instead of the p-GaAs layer 7B sandwiched between the n-GaAs lower contact layer 7A and the n-GaAs upper contact layer 7C included in the intermediate contact layer 7 of the above-described embodiment, GaAs is used. It is conceivable to use an n-InGaAs layer (In = 0.3) having a narrow band gap Eg.

  Further, instead of the n-GaAs lower contact layer 7A and the n-GaAs upper contact layer 7C included in the intermediate contact layer 7 of the above-described embodiment, an n-AlGaAs (Al = 0.2) lower contact layer and n It is also conceivable to use an AlGaAs (Al = 0.2) upper contact layer and use an n-GaAs layer instead of the p-GaAs layer 7B included in the intermediate contact layer 7 of the above-described embodiment.

In the above-described embodiment, the n-type contact layers are used as the contact layers 5, 7A, 7C, and 9 sandwiching the upper MQW layer 8 and the lower MQW layer 6. However, the present invention is not limited to this. A contact layer may be used. That is, the upper MQW layer and the lower MQW layer may be sandwiched between contact layers of one type of conductivity type.
In the above-described embodiment, the lower contact layer 5 is used as a common wiring by connecting all the pixels by the lower contact layer 5 and extending to the outer periphery of the pixel formation region. However, the present invention is not limited to this. . For example, a lower contact layer may be provided for each pixel, and the lower contact layers of all the pixels may be connected by metal wiring that extends to the outer periphery of the pixel formation region.

In the above-described embodiment, the two sensor elements 6 and 8 are used as one pixel, and a plurality of pixels 1 are arranged to form a two-wavelength image sensor. However, the present invention is not limited to this. The multi-wavelength image sensor may be configured by using one sensor element as a pixel and arranging a plurality of pixels.
Further, the materials and compositions of the MQW layers 6 and 8 and the contact layers 5, 7, and 9 in the above embodiment are not limited to those in the above embodiment. For example, the MQW layer and the contact layer may be made of GaAs, InAs, AlAs, InP, GaP, AlP, or a mixed crystal thereof.

  In the above-described embodiment, the case where a quantum well infrared detector (QWIP) is used as a sensor element has been described as an example. However, the present invention is not limited to this. For example, another photoconductor type element may be used as the sensor element. In addition, for example, the light absorbing portion may be a quantum dot layer instead of a quantum well layer, or a bulk semiconductor layer having a forbidden band width that matches a light receiving wavelength.

In the above-described embodiment, the signal processing circuit array 3 is configured to include the bias voltage supply circuit. However, the present invention is not limited to this. For example, the signal processing circuit array 3 is separate from the signal processing circuit array (that is, the infrared array). A bias voltage supply circuit may be provided separately from the sensor and connected to the signal processing circuit array.
Note that the present invention is not limited to the configurations described in the above-described embodiments and modifications, and various modifications can be made without departing from the spirit of the present invention.

1 pixel 2 sensor element array 3 signal processing circuit array 4A, 4B, 4C bump electrode 5 n-type GaAs lower contact layer 6 AlGaAs / GaAs lower MQW layer 7 intermediate contact layer 7A n-type GaAs lower contact layer 7B semiconductor layer (p-type) GaAs layer)
7C n-type GaAs upper contact layer 8 AlGaAs / InGaAs upper MQW layer 8A AlGaAs barrier layer 8B InGaAs well layer 9 n-type GaAs upper contact layer 10 GaAs substrate 11 i-GaAs layer 12A, 12B, 12C ohmic electrode 13A, 13B, 13C wiring 14 readout circuit 15 first switch 16 bias voltage supply circuit 17 second switch 18 third switch (input gate)
19 Input circuit 20 Rectifier (pn junction diode)
21 pn junction diode 22 One pixel unit 23 Integration capacitance element (capacitor)
24 Reset power supply 25 Reset switch (Reset transistor)
26 Source follower transistor 27 Row select transistor 28 Row line 29 Column line 30 Column select transistor 31 Read line 32 Load transistor 33 Vertical scan shift register 34 Horizontal scan shift register 35 Power supply line 36, 37 Contact hole 38, 41 SiON film 39 Mirror electrode 40 Separation groove 42, 43 n-InGaP etching stopper layer 44 i-AlGaAs etching stopper layer 45, 46 i-GaAs layer (surface insulating layer)
47 n-GaAs layer 50 diffraction grating structure

Claims (6)

A plurality of pixels including a first photoconductor-type element and a second photoconductor-type element;
An output electrode connected to the first photoconductor element and the second photoconductor element;
A common electrode connected to a first photoconductive element included in each of the plurality of pixels;
An image sensor comprising: a rectifying element that is provided between the output electrode and the common electrode and prevents a current flowing in a direction opposite to a direction of a current flowing during operation. A first contact layer sandwiching the first photoconductor element;
A second contact layer sandwiching the second photoconductor element;
A semiconductor layer provided between one of the first contact layers and one of the second contact layers, directly connected to the output electrode, and having a conductivity type different from that of the one first contact layer;
The image sensor according to claim 1, wherein the rectifying element includes the one first contact layer and the semiconductor layer. A first contact layer sandwiching the first photoconductor element;
A second contact layer sandwiching the second photoconductor element;
A semiconductor layer provided between one of the first contact layers and one of the second contact layers, connected to the output electrode, and made of a material having a forbidden band narrower than the one first contact layer; With
The image sensor according to claim 1, wherein the rectifying element includes the one first contact layer and the semiconductor layer. A bias electrode connected to the other of the second contact layers;
A first switch for supplying a bias voltage to the common electrode;
A second switch for supplying a bias voltage to the bias electrode;
The image sensor according to claim 2, further comprising a third switch connected to the output electrode. The other of the first contact layers is a common contact layer connected to the first photoconductive element included in each of the plurality of pixels;
5. The device according to claim 2, wherein the common electrode is connected to the first photoconductive element included in each of the plurality of pixels via the common contact layer. 6. The image sensor described in 1. A sensor element array;
A signal processing circuit connected to the sensor element array,
The sensor element array is
A plurality of pixels including a first photoconductor-type element and a second photoconductor-type element;
An output electrode connected to the first photoconductor element and the second photoconductor element;
A common electrode connected to a first photoconductive element included in each of the plurality of pixels;
An image sensor comprising: a rectifying element that is provided between the output electrode and the common electrode and prevents a current flowing in a direction opposite to a direction of a current flowing during operation.

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