JP2010161158A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the chip size of a semiconductor chip having an area bump structure by laying out an I/O cell with optimality in the semiconductor chip. <P>SOLUTION: The I/O cell 3 has a signal voltage converting circuit 6, a logic part 7, a prebuffer part 8, a resistance 30 of an ESD protection part, a transistor 28 of an output buffer part, a resistance 31 of the ESD protection part, a diode 32 of the ESD protection part, a diode 33 having a pad connection opening 3a interposed, a transistor 29 of the output buffer part, and a core buffer part 5, laid out linearly from an edge side to the center side of the semiconductor chip. The pad connection opening 3a can be laid out closer to the center of the semiconductor chip than to the center part of the I/O cell 3 and a pad closest to the edge side of the semiconductor chip can be laid out without protruding from a region of the I/O cell 3 by arranging the prebuffer part 8 closer to the semiconductor chip edge side than to the center part of the I/O cell 3. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technique for reducing the chip area of a semiconductor chip, and more particularly to a technique effective in improving the layout efficiency of an I / O (Input / Output) cell in a semiconductor integrated circuit device having an area bump structure.

  In recent years, with the miniaturization of semiconductor elements, high performance and high integration of semiconductor integrated circuit devices have been advanced. Due to higher performance, the number of pins required for a semiconductor chip tends to increase, but the increase in chip size area tends to be suppressed for higher integration and higher profitability.

  As a result, it is becoming difficult to cope with the increase in the number of pins with the technology of arranging pads around the semiconductor chip, and the pads are arranged in a grid shape or a staggered pattern on the outer periphery of the semiconductor chip and inside thereof, Techniques for forming bumps on these pads, so-called area bumps, have been developed.

  In a semiconductor integrated circuit device, a plurality of I / O cells connected to the pads described above are arranged in a straight line along a side portion of a semiconductor chip. The I / O cell includes, for example, an N-channel MOS (Metal Oxide Semiconductor) transistor and a P-channel MOS transistor that constitute an output buffer, two diodes for ESD (ElectroStatic Discharge) protection, a pre-buffer that drives the output buffer, and an output The logic unit controls the signal input to the buffer and the level shifter converts the voltage level.

  In general, the I / O cell is laid out in the order of, for example, an N channel MOS transistor, two diodes, a P channel MOS transistor, a prebuffer, a logic unit, and a level shifter from the end to the center of the semiconductor chip. A pad connection port is formed between the two diodes, and the pad connection port and the pad are connected via a wiring pattern.

  Also, regarding this type of I / O cell and pad arrangement technique, for example, the long side of the I / O cell is made parallel to the first side of the semiconductor integrated circuit device, and the short side of the I / O cell is The semiconductor integrated circuit device is arranged so as to be parallel to the second side of the semiconductor integrated circuit device orthogonal to the first side, and the chip core can be reduced and the number of pins can be increased without changing the internal core transistor region. It is known (for example, refer to Patent Document 1).

JP 2003-318263 A

  However, the present inventors have found that the area bump technology in the semiconductor integrated circuit device as described above has the following problems.

  In the area bump, the pads arranged on the outermost peripheral portion of the semiconductor chip are arranged inside the semiconductor chip with respect to the pad connection port serving as the connection port with the pad described above, and In some cases, the layout is made on the outer peripheral side.

  When placing inside the semiconductor chip from the pad connection port, place the wiring pattern that connects the pad and the pad connection port located further inside than the pad arranged at the outermost periphery on the outermost periphery. If the number of pads increases, it becomes difficult to wire this wiring pattern.

  In recent years, with the increase in the number of pumps in a semiconductor integrated circuit device, it has become necessary to reduce the width of I / O cells, which tends to make wiring of wiring patterns more difficult.

  In addition, when the pads arranged on the outermost peripheral part of the semiconductor chip are laid out on the outer peripheral side of the semiconductor chip from the pad connection port, the wiring pattern that connects the pad arranged on the inner side and the pad connection port is arranged on the outermost peripheral side. Since there is no need to wire between pads arranged in the section, the wiring layout itself is easy.

  However, considering the prevention of contact between the blade and the bump in dicing the semiconductor wafer and the error at the time of bump formation, the pad arranged on the outermost peripheral portion is a certain distance from the edge of the semiconductor chip (for example, about 100 μm or more). Therefore, there is a problem that a useless area is generated between the end of the semiconductor chip and the pad, resulting in an increase in chip size.

  An object of the present invention is to provide a technique for reducing the chip size by applying an optimized I / O cell layout to an area bump semiconductor chip.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention includes a semiconductor chip, and the semiconductor chip is arranged along a side of the semiconductor chip, and a plurality of I / O pads arranged along the side of the semiconductor chip. A plurality of I / O units connected to the pad, the I / O unit converting a voltage of an input signal and an output signal, a pad connection port serving as a connection unit with an arbitrary I / O pad A signal voltage conversion circuit, a first transistor, and a second transistor, and an output buffer unit that outputs an output signal based on a drive control signal, and a pre-drive that outputs the drive signal and drives the output buffer unit. A buffer unit, an output buffer unit, and a logic unit for controlling an input signal. The first transistor and the second transistor are arranged from the center side of the semiconductor chip to the side of the semiconductor chip across the pad connection port. Each of the transistors is laid out, and a prebuffer unit, a logic unit, and a signal voltage conversion circuit are arbitrarily laid out on the side of the semiconductor chip with respect to the second transistor.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  In the present invention, the I / O portion is laid out on the side of the semiconductor chip with respect to the second transistor, and the logic portion is laid out on the side of the semiconductor chip with respect to the prebuffer portion. The signal voltage conversion circuit is laid out on the side of the semiconductor chip with respect to the logic portion.

  Further, according to the present invention, the I / O section is laid out on the side of the semiconductor chip with respect to the second transistor, and the signal voltage conversion is performed on the side of the semiconductor chip with respect to the prebuffer section. The circuit is laid out, and the logic part is laid out on the side of the semiconductor chip with respect to the signal voltage conversion circuit.

  Further, according to the present invention, the I / O portion has a signal voltage conversion circuit laid out on the side of the semiconductor chip with respect to the second transistor, and the logic on the side of the semiconductor chip with respect to the signal voltage conversion circuit. The part is laid out, and the pre-buffer part is laid out on the side of the semiconductor chip from the logic part.

  Further, according to the present invention, the I / O unit includes first and second diodes for ESD protection, and the first diode is laid out between the pad connection port and the first transistor. The second diode is laid out between the pad connection port and the second transistor.

  Further, according to the present invention, the I / O unit includes an output buffer unit and a core buffer unit that prevents a delay of a signal that controls the input signal, and the core buffer unit is formed on the semiconductor chip more than the first transistor. It is laid out on the center side.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) The chip size of the semiconductor chip can be reduced.

  (2) According to the above (1), the semiconductor integrated circuit device can be reduced in size and cost.

It is explanatory drawing which shows the example of an arrangement | sequence of the pad in the semiconductor chip provided in the semiconductor integrated circuit device by Embodiment 1 of this invention. FIG. 2 is an explanatory diagram in which a partial region of a pad and an I / O cell in the semiconductor chip of FIG. FIG. 3 is a circuit diagram showing an example of a circuit configuration in the I / O cell of FIG. 2. FIG. 3 is an explanatory diagram showing an example of a layout in the I / O cell of FIG. 2 and a circumferential power supply line formed thereabove. FIG. 3 is an explanatory diagram showing a connection example between the I / O cell of FIG. 2 and a pad closest to a side portion of the semiconductor chip. It is explanatory drawing which shows the other example of the connection of the I / O cell by Embodiment 1 of this invention, and the pad nearest to the side part of a semiconductor chip. It is explanatory drawing which shows the layout example of the general I / O cell which this inventor examined. It is explanatory drawing which shows the example of a connection of the I / O cell of FIG. 7, and a pad. It is explanatory drawing which shows the example of an arrangement | sequence of the pad in the semiconductor chip provided in the semiconductor integrated circuit device by other embodiment of this invention. FIG. 10 is an explanatory diagram enlarging a partial region of a pad and an I / O cell in the semiconductor chip of FIG. 9. It is explanatory drawing which shows the example of a layout of the I / O cell by Embodiment 2 of this invention. FIG. 12 is an explanatory diagram illustrating another example of the layout in the I / O cell of FIG. 11.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is an explanatory diagram showing an example of the arrangement of pads in a semiconductor chip provided in the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 2 is a diagram illustrating pads and I / O cells in the semiconductor chip of FIG. FIG. 3 is a circuit diagram showing an example of a circuit configuration of the I / O cell of FIG. 2, and FIG. 4 is an I / O cell of FIG. 2 and a circuit formed thereabove. FIG. 5 is an explanatory diagram showing an example of the layout in the power supply line, FIG. 5 is an explanatory diagram showing an example of connection between the I / O cell of FIG. 2 and the pad closest to the side of the semiconductor chip, and FIG. 6 is an embodiment of the present invention. FIG. 7 is an explanatory diagram showing another example of connection between the I / O cell according to mode 1 and the pad closest to the side of the semiconductor chip, and FIG. 7 is a layout example of a general I / O cell examined by the present inventor; FIG. 8 shows an example of connection between the I / O cell and the pad of FIG. It is an explanatory diagram.

  In the first embodiment, a plurality of pads 2 are formed on the surface of a semiconductor chip 1 provided in a semiconductor integrated circuit device, as shown in FIG. These pads 2 are arranged in a grid pattern on the outer periphery of the semiconductor chip 1 and on the inner side of each rectangular region. Each pad 2 has a bump formed on the pad 2 to form a semiconductor integrated circuit device having an area bump structure.

  FIG. 2 is an explanatory diagram showing an enlargement of a partial region (region indicated by a dotted line in FIG. 1) between the pad 2 and the I / O cell 3 serving as the I / O portion in the semiconductor chip 1 of FIG.

  Further, as shown in FIG. 2, I / O regions 1a are provided on the four sides of the semiconductor chip 1, respectively. In this I / O area 1a, a plurality of I / O cells 3 which are interfaces with the outside are provided in a straight line.

  The I / O cell 3 has a rectangular shape, and is linearly arranged so that one short side is parallel to any one side of the semiconductor chip 1. In the I / O cell 3, a pad connection port 3 a is formed above the center portion, that is, at the center side of the semiconductor chip 1 from the center portion of the I / O cell 3. The pad connection port 3 a is connected via an arbitrary pad 2 and a wiring pattern 4 formed on the semiconductor chip 1.

  Furthermore, of the pads 2 arranged in a grid, the pad 2 closest to the side of the semiconductor chip 1 is laid out outside the pad connection port 3a (outer peripheral side of the semiconductor chip 1). The remaining pads 2 arranged inside the pads 2 closest to the side of 1 are laid out inside the pad connection port 3a (center side of the semiconductor chip 1).

  FIG. 3 is a circuit diagram showing an example of the circuit configuration of the I / O cell 3.

  The I / O cell 3 includes a core buffer unit 5, a signal voltage conversion circuit 6, a logic unit 7, a prebuffer unit 8, an output buffer unit 9, and ESD protection units 10 and 11, as shown in the figure. The core buffer unit 5 prevents delay of the output buffer unit 9 and a signal for controlling the input signal.

  The signal voltage conversion circuit 6 converts the voltages of the input signal and the output signal. The logic unit 7 is a logic circuit that controls the output buffer unit 9 and an input signal.

  The pre-buffer unit 8 drives the output buffer unit 9. The output buffer unit 9 outputs an output signal based on the control signal of the pre-buffer unit 8. The ESD protection units 10 and 11 are ESD protection circuits in the I / O cell 3.

  The core buffer unit 5 includes buffers 12 to 15, and the signal voltage conversion circuit 6 includes level shifters 16 to 19. The logic unit 7 includes AND circuits 20 and 21, an OR circuit 22, and an inverter 23. The prebuffer unit 8 includes transistors 24-27. Transistors 24 and 26 are P-channel MOS transistors, and transistors 25 and 27 are N-channel MOS transistors.

  The output buffer unit 9 includes a P-channel MOS transistor 28 as a second transistor and an N-channel MOS transistor 29 as a first transistor. The ESD protection unit 10 includes resistors 30 and 31, and the ESD protection unit 11 includes diodes 32 and 33.

  The power supply voltage VCCQ is connected to the cathode of the diode 32 serving as the second diode, and the cathode of the diode 33 serving as the first diode is connected to the anode of the diode 32. A reference potential VSSQ is connected to the anode of the diode 33.

  Further, the pad 2 is connected to the connection portion between the diode 32 and the diode 33 via the pad connection port 3 a and the wiring pattern 4. A connection portion between the diode 32 and the diode 33 is connected to one connection portion of the resistors 30 and 31 and one connection portion of the transistor 29. A reference potential VSSQ is connected to the other connection portion of the transistor 29.

  The power supply voltage VCCQ is connected to one connection portion of the transistor 28, and the other connection portion of the resistor 31 is connected to the other connection portion of the transistor 28. The transistor 24 and the transistor 25 have an inverter configuration connected in series between the power supply voltage VCCQ and the reference potential VSSQ. The gate of the transistor 28 is connected to a connection portion between the transistor 24 and the transistor 25 which is an output portion of the inverter.

  Similarly, the transistor 26 and the transistor 27 have an inverter configuration connected in series between the power supply voltage VCCQ and the reference potential VSSQ. A gate of the transistor 29 is connected to a connection portion between the transistor 26 and the transistor 27 which is an output portion of the inverter.

  The output parts of the AND circuit 21 are connected to the gates of the transistors 24 and 25 that are the input parts of the inverter, respectively, and the OR circuits 22 are connected to the gates of the transistors 26 and 27 that are also the input parts of the inverter. Each output part is connected.

  Further, one input part of the AND circuit 20 is connected to the other connection part of the resistor 30, and the output part of the level shifter 17 is connected to the other input part of the AND circuit 20. . The output unit of the AND circuit 20 is connected to the input unit of the level shifter 16.

  The output part of the level shifter 18 is connected to one input part of the logical product circuit 21 and one input part of the logical sum circuit 22. The other connection part of the OR circuit 22 is connected to the output part of the level shifter 19 and the input part of the inverter 23. The other input part of the AND circuit 21 is connected to the output part of the inverter 23.

  Here, the level shifter 16 converts the amplitude of the power supply voltage VCCQ−reference potential VSSQ into the amplitude of the power supply voltage VDD−reference potential VSS, and the level shifters 17 to 19 convert the amplitude of the power supply voltage VDD−reference potential VSS to the power supply voltage. VCCQ—converted to the amplitude of the reference potential VSSQ.

  The power supply voltage VCCQ is, for example, about 3.3V, about 2.8V, about 2.5V, about 1.8V, or about 1.2V, and the power supply voltage VDD is, for example, The voltage level is about 1.1V.

  The level shifter 16 includes a buffer 34 that operates with an amplitude of power supply voltage VCCQ−reference potential VSSQ and a buffer 35 that operates with an amplitude of power supply voltage VDD−reference potential VSS. The output unit of the AND circuit 20 is connected to the input unit of the buffer 34. The input unit of the buffer 35 is connected to the output unit of the buffer 34, and the input unit of the buffer 12 is connected to the output unit of the buffer 35.

  A signal output from the output unit of the buffer 12 becomes an input signal input via the pad 2 and is input to the core region of the semiconductor chip 1 as the signal CIN.

  The level shifter 19 includes a latch circuit including transistors 36 to 39 and an inverter 40. Transistors 36 and 38 are P-channel MOS, and transistors 37 and 39 are N-channel MOS.

  The transistors 36 and 37 are connected in series between the power supply voltage VCCQ and the reference potential VSS. Similarly, the transistors 38 and 39 are also connected in series between the power supply voltage VCCQ and the reference potential VSS.

  The gate of the transistor 38 is connected to the connection portion between the transistor 36 and the transistor 37, and the gate of the transistor 36 is connected to the connection portion between the transistor 38 and the transistor 39.

  A connection portion between the transistor 36 and the transistor 37 is an output portion of the level shifter 19, and the other input portion of the OR circuit 22 and the input portion of the inverter 23 are connected to each other.

  The output section of the buffer 15 is connected to the gate of the transistor 39 which is an input section of the level shifter 19 and the input section of the inverter 40. Further, the gate of the transistor 37 is connected to the output part of the inverter 40. Here, the configuration of the level shifters 17 to 18 is the same as that of the level shifter 19.

  In addition, the input portion of the buffer 15 is connected so that an output control signal OE serving as a control signal of an output signal output from the core region of the semiconductor chip 1 is input. An input permission signal IE serving as a control signal for the signal CIN is connected to the input portion of the buffer 13 so as to be input from the core region.

  The input unit of the level shifter 17 is connected to the output unit of the buffer 13. The input portion of the buffer 14 is connected so that the output signal I output from the core region is input, and the input portion of the level shifter 18 is connected to the output portion of the buffer 14. Here, the core buffer unit 5 is a logic that operates with the amplitude of the power supply voltage VDD−the reference potential VSS.

  FIG. 4 is an explanatory diagram showing an example of the layout of the I / O cell 3 and the peripheral power supply line formed thereabove. In FIG. 4, the lower side is the chip end side of the semiconductor chip 1, and the upper side is the center side of the semiconductor chip 1.

  In the I / O cell 3, a signal voltage conversion circuit 6 is laid out in the lower part of FIG. A logic part 7 is laid out above the signal voltage conversion circuit 6, and a pre-buffer part 8 is laid out above the logic part 7.

  A resistor 30 of the ESD protection unit 10 is laid out above the prebuffer unit 8, and a transistor 28 in the output buffer unit 9 is laid out above the resistor 30.

  The resistor 31 of the ESD protection unit 10 is laid out above the transistor 28, and the diode 32 of the ESD protection unit 11 is laid out above the resistor 31. The resistor 30 may be laid out at a position other than between the pre-buffer unit 8 and the transistor 28. For example, the resistor 30 may be disposed between the diode 32 and the logic unit 7.

  A diode 33 is laid out above the diode 32 with the pad connection port 3a interposed therebetween. The transistor 29 in the output buffer unit 9 is laid out above the diode 33, and the core buffer unit 5 is laid out above the transistor 29.

  Further, the peripheral power supply line is provided with a peripheral power supply line 43 for supplying the power supply voltage VDD below the FIG. 4, and above the peripheral power supply line 43 is a peripheral reference potential line 44 for supplying the reference potential VSS. Wired.

  A circular reference potential line 45 that supplies a reference potential VSSQ is wired above the circular reference potential line 44, and a circular power supply line 46 that supplies a power supply voltage VCCQ is wired above the circular reference potential line 45. Has been.

  A circular reference potential line 47 that supplies a reference potential VSSQ is wired above the circular power supply line 46, and a circular reference potential line 48 that supplies a reference potential VSS is provided above the circular reference potential line 47. Is wired. A circular power supply line 49 for supplying the power supply voltage VDD is wired above the circular reference potential line 48.

  As described above, the pre-buffer unit 8 is disposed below the pad connection port 3a (on the end side of the semiconductor chip 1), so that the pad connection port 3a is located above the central portion of the I / O cell 3 (semiconductor). It can be laid out on the center side of the chip 1.

  FIG. 5 is an explanatory diagram showing an example of connection between the I / O cell 3 and the pad 2 closest to the side portion of the semiconductor chip 1.

  In this case, the pad 2 is laid out below the pad connection port 3 a (on the side of the semiconductor chip 1) and connected to the pad connection port 3 a via the wiring pattern 4. The pad 2 closest to the side of the semiconductor chip 1 is arranged at a predetermined distance (for example, about 100 μm) from the chip end due to restrictions such as prevention of contact between the blade and the bump when dicing the semiconductor wafer. Although the I / O cell 3 can be arranged in the region from the chip end to the position where the pad 2 is laid out (indicated by A in the figure), the layout area can be reduced. It becomes.

  6 shows the pad 2 closest to the side of the I / O cell 3 and the semiconductor chip 1 when the length in the width direction of the I / O cell 3 is longer than that of the I / O cell 3 shown in FIG. It is explanatory drawing which shows the example of a connection.

  In this case as well, the pad 2 is laid out below the pad connection port 3a (on the side of the semiconductor chip 1) and connected to the pad connection port 3a via the wiring pattern 4. Since the I / O cell 3 can be disposed in the region from the end to the position where the pad 2 is laid out (indicated by A in the figure), the layout area can be reduced.

  FIG. 7 is an explanatory diagram showing a layout example of a general I / O cell 100 examined by the present inventors.

  In the I / O cell 100, an N-channel MOS transistor 101 constituting an output buffer unit is laid out on the side of the semiconductor chip, and diodes 102 and 103 of an ESD protection circuit are laid out above the transistor 101, respectively. ing.

  Above the diode 103, an N-channel MOS transistor 104 constituting an output buffer unit is laid out. Above the transistor 104, a pre-buffer unit 105 is laid out.

  A logic unit 106 is located above the prebuffer unit 105, and a signal voltage conversion circuit 107 is laid out above the logic unit 106. A pad connection port 108 is provided so as to sandwich the diode 102 and the diode 103.

  FIG. 8 is an explanatory diagram showing a connection example between the I / O cell 100 and the pad 109 of FIG.

  The pad connection port 108 and the pad 109 of the I / O cell 100 are connected via a wiring pattern 111 formed on the semiconductor chip 110.

  As shown in FIG. 7, the I / O cell 100 has the pad connection port 108 at the center of the I / O cell 100 because the pre-buffer unit 105 is laid out in the vicinity of the center of the I / O cell 100. In other words, it is laid out below (side of the semiconductor chip).

  Therefore, if the pad 109 closest to the side of the semiconductor chip is arranged away from the chip end to a preset distance, the pad 109 is laid out on the chip end side with respect to the I / O cell 100. A dead space in which elements are not laid out in the semiconductor chip 110 (a region having a distance indicated by B in the drawing) is generated, layout efficiency is lowered, and the semiconductor chip 110 is enlarged.

  Thereby, according to the first embodiment, the layout in the I / O cell 3 can effectively use the region where the pad 2 closest to the side of the semiconductor chip 1 is laid out. Can be reduced in size.

  In the first embodiment, the example in which the pads 2 are arranged in a grid pattern for each arbitrary rectangular region on the back surface of the semiconductor chip 1 has been described. For example, as shown in FIG. The pads 2 may be arranged in a grid pattern in a frame-like region along the four peripheral parts.

  Further, FIG. 10 shows a wiring example when the pad 2 in the pad arrangement in the region indicated by the dotted line in FIG. 9 and the pad connection port 3 a of the I / O cell 3 are connected by the wiring pattern 4.

  This also makes it possible to effectively use the area where the pads 2 closest to the side of the semiconductor chip 1 are laid out, and the size of the semiconductor chip 1 can be reduced.

(Embodiment 2)
FIG. 11 is an explanatory diagram showing an example layout of the I / O cell according to the second embodiment of the present invention, and FIG. 12 is an explanatory diagram showing another example of the layout in the I / O cell of FIG.

  In the first embodiment (FIG. 4), the layout of the I / O cell 3 is such that the signal voltage conversion circuit 6, the logic unit 7, and the prebuffer are arranged from the chip end side of the semiconductor chip 1 to the center side of the semiconductor chip 1. Although an example of the layout in the order of the unit 8 has been described, the order of layout of the signal voltage conversion circuit 6, the logic unit 7, and the prebuffer unit 8 may be other than that shown in FIG.

  FIG. 11 is an explanatory diagram illustrating another layout example of the signal voltage conversion circuit 6, the logic unit 7, and the prebuffer unit 8 in the I / O cell 3.

  In this case, as shown in the figure, the I / O cell 3 has a logic portion 7 laid out on the chip end side (lower side in FIG. 11) of the semiconductor chip 1, and a signal voltage conversion above the logic portion 7. Circuit 6 is laid out.

  A prebuffer unit 8 is laid out above the signal voltage conversion circuit 6, and a resistor 30 of the ESD protection unit 10 is laid out above the prebuffer unit 8. A transistor 28 in the output buffer unit 9 is laid out above the resistor 30, and a resistor 31 of the ESD protection unit 10 is laid out above the transistor 28, and above the resistor 31. The diode 32 of the ESD protection unit 11 is laid out.

  The layout of the diode 33, the transistor 29 in the output buffer unit 9, and the core buffer unit 5 is the same as that in FIG. 4, and the pad connection port 3a is also connected to the diode 32 and the diode 33 as in FIG. It is provided in between.

  FIG. 12 is an explanatory diagram showing another example of the layout in the I / O cell 3.

  In FIG. 12, the prebuffer unit 8 is laid out on the chip end side (lower side in FIG. 12) of the semiconductor chip 1, and the logic unit 7 is laid out above the prebuffer unit 8. A signal voltage conversion circuit 6 is laid out above the logic unit 7, a resistor 30 is laid out above the signal voltage conversion circuit 6, and a transistor 28 in the output buffer unit 9 is arranged above the signal voltage conversion circuit 6. Is laid out.

  A resistor 31 is laid out above the transistor 28, and a diode 32 is laid out above the resistor 31. Also in FIG. 12, the layout of the diode 33, the transistor 29 in the output buffer unit 9, and the core buffer unit 5 is the same as in FIG. 4, and the pad connection port 3a is the same as in FIG. It is provided between.

  Thereby, also in the second embodiment, it is possible to effectively utilize the region where the pad 2 closest to the side portion of the semiconductor chip 1 is laid out, and the size of the semiconductor chip 1 can be reduced.

  The invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Not too long.

  The present invention is suitable for a chip area reduction technique in a semiconductor chip having an area bump structure.

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 1a I / O area | region 2 Pad 3 I / O cell 3a Pad connection port 4 Wiring pattern 5 Core buffer part 6 Signal voltage conversion circuit 7 Logic part 8 Prebuffer part 9 Output buffer part 10 ESD protection part 11 ESD protection part 12 buffer 13 buffer 14 buffer 15 buffer 16 level shifter 17 level shifter 18 level shifter 19 level shifter 20 AND circuit 21 AND circuit 22 OR circuit 23 inverter 24 transistor 25 transistor 26 transistor 27 transistor 28 transistor 29 transistor 30 resistor 31 resistor 32 diode 33 diode 34 buffer 35 buffer 36 transistor 37 transistor 38 transistor 39 transistor 40 inverter 43 circuit power line 44 circuit reference potential line 45 circuit group Potential line 46 Circular power supply line 47 Circular reference potential line 48 Circular reference potential line 49 Circular power supply line 100 I / O cell 101 Transistor 102 Diode 103 Diode 104 Transistor 105 Prebuffer unit 106 Logic unit 107 Signal voltage conversion circuit 108 Pad connection port 109 Pad 110 Semiconductor chip 111 Wiring pattern

Claims (6)

With a semiconductor chip,
The semiconductor chip is
A plurality of I / O pads arranged in an array along the side of the semiconductor chip;
A plurality of I / O units disposed along the side of the semiconductor chip and connected to any of the I / O pads;
The I / O unit is
A pad connection port to be connected to any I / O pad;
A signal voltage conversion circuit for converting the voltage of the input signal and the output signal;
An output buffer unit configured by a first transistor and a second transistor and outputting an output signal based on a drive control signal;
A pre-buffer unit that outputs a drive signal and drives the output buffer unit;
The output buffer unit, and a logic unit for controlling the input signal,
The first transistor and the second transistor are laid out from the center side of the semiconductor chip to the side of the semiconductor chip across the pad connection port,
The semiconductor integrated circuit device, wherein the prebuffer unit, the logic unit, and the signal voltage conversion circuit are arbitrarily laid out on the side of the semiconductor chip with respect to the second transistor. The semiconductor integrated circuit device according to claim 1.
The I / O unit is
The pre-buffer unit is laid out on the side of the semiconductor chip from the second transistor,
The logic part is laid out on the side of the semiconductor chip from the prebuffer part,
The semiconductor integrated circuit device, wherein the signal voltage conversion circuit is laid out on the side of the semiconductor chip with respect to the logic unit. The semiconductor integrated circuit device according to claim 1.
The I / O unit is
The pre-buffer unit is laid out on the side of the semiconductor chip from the second transistor,
The signal voltage conversion circuit is laid out on the side of the semiconductor chip from the prebuffer unit,
A semiconductor integrated circuit device, wherein the logic section is laid out on a side of the semiconductor chip with respect to the signal voltage conversion circuit. The semiconductor integrated circuit device according to claim 1.
The I / O unit is
The signal voltage conversion circuit is laid out on the side of the semiconductor chip from the second transistor,
The logic part is laid out on the side of the semiconductor chip from the signal voltage conversion circuit,
The semiconductor integrated circuit device, wherein the prebuffer unit is laid out on the side of the semiconductor chip with respect to the logic unit. The semiconductor integrated circuit device according to any one of claims 1 to 4,
The I / O unit is
Comprising first and second diodes for ESD protection;
The first diode is
Laid out between the pad connection port and the first transistor;
The second diode is
A semiconductor integrated circuit device laid out between the pad connection port and the second transistor. In the semiconductor integrated circuit device according to claim 1,
The I / O unit is
The output buffer unit, and a core buffer unit for preventing delay of a signal for controlling an input signal,
The core buffer unit is
The semiconductor integrated circuit device is laid out closer to the center of the semiconductor chip than the first transistor.

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