JP2010021347A - Multilayer chip type semiconductor device and method of manufacturing the same - Google Patents

Abstract

[Objective] To provide a multilayer chip type semiconductor device which does not damage the surface of a semiconductor chip even by packaging using a filler-added resin, and a method for manufacturing the same.
[Structure] At least one adhesive that is provided for each combination of a plurality of semiconductor chips stacked in a plurality of stages and an upper semiconductor chip and a lower semiconductor chip facing each other among the plurality of semiconductor chips. A semiconductor device comprising a layer and one filler-added resin region that seals all of the plurality of semiconductor chips, and sandwiched between both adhesive surfaces of the upper and lower semiconductor chips and the adhesive It further includes a filler-free resin region formed along at least a portion of the layer.
[Selection] Figure 2

Description

  The present invention relates to a multilayer chip type semiconductor device in which a plurality of semiconductor chips are stacked in a single package and a method for manufacturing the same.

  Conventionally, in a multilayer chip type semiconductor device, there has been a problem that a filler contained in a molding resin for packaging is pushed into an end portion of an adhesive layer to which the chip is bonded, thereby damaging the semiconductor chip. In order to maintain the fastness and heat release performance of the packaged semiconductor device, a filler-added resin obtained by adding a particulate filler such as silica to an epoxy resin is usually used as the molding resin.

  Referring to the cross-sectional view shown on the right side of FIG. 1, a cross-section of a conventional semiconductor device in which three chips are stacked is shown. Here, the chip 1 and the chip 3 are laminated via a DB film 2 as an adhesive. At this time, the DB film 2 is diced, that is, cut in accordance with the size of the side portion of the chip 1. However, after the cutting, the phenomenon that the DB film 2 contracts laterally from the side surface of the chip 1 to create a gap is avoided. I can't. In such a state, when the semiconductor device is filled with the pressurized filler-added resin 10 and packaged, a part of the filler 10 ′ included in the filler-added resin 10 is pushed into the gap of the DB film 2. It will be. Then, as schematically shown in a region A in the drawing, the edge of the filler 10 ′ is pressed so as to bite into the surface of the semiconductor chip 3 during solidification shrinkage after filling, and scratches the surface of the chip 3. A phenomenon occurs (see the picture shown on the left side of FIG. 1).

In order to solve such a problem, Patent Document 1 discloses that the filler is pushed into the end portion of the adhesive layer by making the size of the filler contained in the molding resin larger than the thickness of the adhesive layer between the chips. The semiconductor chip can be prevented from being damaged.
JP 2006-54359 A

  However, with the above-described technology, it is difficult to manage the uniform particle diameter of the filler in the molding resin, and in fact, the edge of the small-diameter filler or the large-diameter filler may enter the gap between the chips. The semiconductor chip was still damaged.

  An object of the present invention is to provide a multilayer chip type semiconductor device that does not damage the surface of the semiconductor chip even by packaging using a filler-added resin, and a method for manufacturing the same.

  A multilayer chip type semiconductor device according to the present invention is provided for each combination of a plurality of semiconductor chips stacked in a plurality of stages and an upper semiconductor chip and a lower semiconductor chip that are opposed to each other. A semiconductor device comprising at least one adhesive layer to be bonded and one filler-added resin region for sealing all of the plurality of semiconductor chips, wherein both bonding surfaces of the upper semiconductor chip and the lower semiconductor chip It further includes a filler-free resin region sandwiched between and formed along at least a part of the periphery of the adhesive layer.

  A manufacturing method according to the present invention is a manufacturing method for manufacturing a semiconductor device including a plurality of semiconductor chips, and an adhesive layer is provided for each combination of an upper semiconductor chip and a lower semiconductor chip among the plurality of semiconductor chips. And laminating the plurality of semiconductor chips in a plurality of stages, and sandwiching between both adhesion surfaces of the upper and lower semiconductor chips and at least a part of the periphery of the adhesive layer A filling step of filling the gap region formed along the filler with additive-free resin, and a molding step of molding by sealing all of the plurality of semiconductor chips filled with the filler-free resin with filler-added resin It is characterized by including these.

  According to the multilayer chip type semiconductor device and the method for manufacturing the same according to the present invention, the surface of the semiconductor chip is not damaged even by packaging using a filler-added resin.

Embodiments of the present invention will be described in detail with reference to the accompanying drawings.
<First embodiment>
FIG. 2 shows a cross section of a multilayer chip type semiconductor device according to the present invention, which is a first embodiment. The semiconductor device in the present embodiment is a semiconductor device including an upper semiconductor chip 1 and a lower semiconductor chip 3 that are stacked in two stages as an example of multi-stage stacking. Each of the upper semiconductor chip 1 and the lower semiconductor chip 3 is a semiconductor chip in which a desired semiconductor element has already been formed in advance before such lamination, and the upper surface has, for example, a rectangular flat plate shape. Both the back surface of the semiconductor chip 1 and the surface of the semiconductor chip 3 are bonded as an adhesive surface via the adhesive layer 2, and both the back surface of the semiconductor chip 3 and the surface of the lead frame 5 are bonded as adhesive surfaces via the adhesive layer 4. Are joined. The upper semiconductor chip 1 and the lower semiconductor chip 3 are also electrically connected to each other through lead wires 11 and bonding wires 8 and 9 extending from the outside to the side of the semiconductor device.

  The lead frame 5 is a thin frame that fulfills the internal wiring of the upper semiconductor chip 1 and the lower semiconductor chip 3 and also functions as a die pad for mounting and fixing them. The lead frame 11 is a frame that performs an outer lead function that is connected to terminals on the upper semiconductor chip 1 and the lower semiconductor chip 3 to serve as external terminals.

  The adhesive layer 2 has substantially the same size as that of the upper semiconductor chip 1, but due to the contraction at the time of cutting, the gap region 16 is slightly smaller than the size of the upper semiconductor chip 1 and the rectangular region of the upper semiconductor chip 1 is formed. It is formed along the periphery. As a material for the adhesive layers 2 and 4, for example, a film type material having a relatively low elasticity made of an imide resin may be used.

  A filler-free resin region 7 is formed in the gap region 16. The filler-free resin region 7 is bonded to the surface of the lower semiconductor chip 3 and the end surface (cut surface) of the adhesive layer 2 by filling the gap region 16 with the filler-free resin. Further, the filler-free resin region 7 may extend beyond the back surface of the upper semiconductor chip 1 to its side depending on the filling amount. The shape of the filler-free resin region 7 after filling is sandwiched between the upper and lower bonding surfaces of the upper semiconductor chip 1 and the lower semiconductor chip 3 and is formed annularly along the periphery of the adhesive layer 2. Further, as shown in FIG. 2, the cross-sectional shape forms a skirt shape outward from the rectangular periphery of the upper semiconductor chip 1.

  The entire semiconductor device is formed into a shape including a filler-added resin region 10 by filling the entire semiconductor device with a filler-added resin except for a lead frame 11 that is partially exposed for external connection. To be shaped. Examples of the material used for the filler-added resin region 10 include, for example, an epoxy resin as a main component and containing, for example, about 80 to 90% by weight of filler that is silica particles. The diameter and shape of the filler particles in this embodiment can be selected based only on the robustness and heat dissipation characteristics of the entire semiconductor device.

  FIG. 3 shows a manufacturing method in the packaging process of the multilayer chip type semiconductor device shown in FIG. As a premise, each of the plurality of semiconductor chips is manufactured in advance in a separate process. In addition, some wafer coating may be applied to each of the plurality of semiconductor chips.

  In step S1, a plurality of semiconductor chips are stacked with an adhesive layer interposed therebetween (stacking step). As the adhesive layer, for example, a double-sided adhesive film having elasticity and adhesiveness in which a pressure-sensitive adhesive is applied to both sides of a film such as polyimide can be used. When the adhesive layer is realized by a film material, the film material is bonded to the upper semiconductor chip and then diced, that is, cut into an appropriate size together with the upper semiconductor chip.

  Next, in step S2, wire bonding is performed by performing a reflow process for electrically connecting the lead frame and the plurality of semiconductor chips with an appropriate wire material such as an aluminum wire or a gold wire (wire bonding step). . A wire bonding process may be implemented after the filling process which inject | pours the filler additive-free resin of step 3 mentioned later. The reason why the wire bonding step is performed before the filling step is that bonding becomes impossible when the filler-free resin adheres to the pad portion. Therefore, when the phenomenon of the resin without additive added to the upper semiconductor chip is not expected, the wire bonding process to the upper semiconductor chip can be performed after the filling process.

  Next, in step S3, the gap region is filled by injecting filler-free resin into the peripheral portion of the upper semiconductor chip (filling step). After the injection, the injected filler-free resin is cured by performing a heat treatment at an appropriate temperature and time according to the curing characteristics of the filler-free resin.

  Next, in step S4, all of the plurality of semiconductor chips subjected to filler-free resin injection and wire bonding are packaged by resin molding that is sealed with filler-added resin (molding process). The resin molding method can be performed by a normal packaging method in which a filler-added resin before curing is put into a mold in which a semiconductor device is installed.

  FIG. 4 shows a specific example of the method of injecting the filler-free resin in the filling step shown in FIG. A plurality of injection conduits 20 are vertically extended downward from the upper part of the semiconductor device, and the discharge ports are arranged so as to come near the sides of the upper semiconductor chip 1. The filler-free resin 21 is injected into the periphery of the upper semiconductor chip 1 through the injection conduit 20. The injected filler-free resin 21 is cured by an appropriate heat treatment. As the filler-free resin 21, for example, a chip coating agent, for example, a resin such as JCR (junction coating resin) -6134 can be used.

  Actually, in an experiment using JCR-6134, if there are about one or two injection conduits 20 per side surface of the upper semiconductor chip 1, the surface activation effect sufficiently spreads the entire periphery of the upper semiconductor chip 1. The result of completely filling the gap region 21 is obtained. The material used as the filler-free resin 21 is not limited to this JCR-6134, and has a property capable of filling the gap region 16 and does not adversely affect other semiconductor members and has sufficient heat resistance. A variety of materials can be used.

  In addition, as the shape and arrangement of the plurality of injection conduits 20, depending on the viscosity characteristics of the filler-free resin 21 to be used, for example, it extends obliquely downward from the top toward the end of the upper semiconductor chip 1. Alternatively, various shapes and arrangements such as extending in the lateral direction from the side portions may be used.

  Moreover, instead of the form in which the filler-free resin 21 is injected at discrete locations as described above, the filler-free resin is continuously added by revolving or reciprocating the injection conduit 20 along the periphery of the upper semiconductor chip. You may make it inject | pour. In addition, by using the injection conduit 20 having a plurality of discharge ports and simultaneously injecting into a plurality of locations, the time required for injection may be shortened and the efficiency of the manufacturing process may be improved.

  In the first embodiment described above, by applying the present invention, the filler is prevented from entering the gap region formed at the end of the adhesive layer, and the semiconductor chip can be prevented from being damaged. Further, not only the type of molding resin constituting the package is not limited, but also management of the filler in the molding resin is not necessary, so that the cost is excellent.

  5A and 5B are each a modification of the first embodiment and show a plane of a multilayer chip type semiconductor device according to the present invention. These two modifications show a form in which, as a result of dicing, the edges of the upper semiconductor chip and the lower semiconductor chip are aligned, and there are places where the surface of the lower semiconductor chip does not come out, that is, there are no gap areas. Yes.

  Referring to FIG. 5A, there is shown a case where the upper semiconductor chip 1 and the lower semiconductor chip 3 are stacked with the same size being slightly shifted from each other. In this case, the filler-free resin region 7 does not need to be formed in an annular shape along the periphery of the upper semiconductor chip 1, and only needs to be injected into the gap region 16 on one side of the upper semiconductor chip 1.

Referring to FIG. 5B, the lengths of the vertical sides of the upper semiconductor chip 1 and the lower semiconductor chip 3 are the same, and the length of the horizontal side of the upper semiconductor chip 1 is larger than that of the lower semiconductor chip 3. The short case is shown. In this case, the filler-free resin region 7 does not need to be formed in an annular shape along the periphery of the upper semiconductor chip 1, but only injected into the gap regions 16 on the two vertical sides at both ends of the upper semiconductor chip 1. Good.
<Second embodiment>
In the experimental results according to the first example, there was an inconvenient phenomenon that the filler-free resin spreads too much at the time of injection and covers the conductor bonding portion for wire bonding. In the second embodiment, a mode for avoiding such inconvenience will be described.

  FIG. 6 is a second embodiment, and shows a cross section of a multilayer chip type semiconductor device according to the present invention. The semiconductor device in the present embodiment is a semiconductor device including two upper semiconductor chips 1 and a lower semiconductor chip 3 as a stacked example, as in the first embodiment. Each of the upper semiconductor chip 1 and the lower semiconductor chip 3 is a semiconductor chip in which a semiconductor element having a desired function is already formed in advance before stacking, and the upper surface has, for example, a rectangular flat plate shape. Both the back surface of the upper semiconductor chip 1 and the surface of the lower semiconductor chip 3 are bonded as adhesive surfaces via the adhesive layer 2, and both the rear surface of the lower semiconductor chip 3 and the surface of the lead frame 5 are bonded as adhesive surfaces. It is joined via the agent layer 4. The upper semiconductor chip 1 and the lower semiconductor chip 3 are also electrically connected to each other through lead wires 11 and bonding wires 8 and 9 extending from the outside to the side of the semiconductor device.

  The filler-free resin region 7 is sandwiched between the upper and lower bonding surfaces of the upper semiconductor chip 1 and the lower semiconductor chip 3 in the same manner as in the first embodiment, and along the periphery of the adhesive layer 2. It is formed in an annular shape. In the second embodiment, however, the cross-sectional shape of the filler-free resin region 7 is a skirt shape outward from the rectangular periphery of the upper semiconductor chip 1, but the farthest end is the wafer coat 12. The shape is blocked by

  The wafer coat 12 is provided in a cross-sectional shape at a position surrounding the filler-free resin region 7 in an annular shape on the upper surface of the lower semiconductor chip 3. The wafer coat 12 also has a cross-sectional shape that opens a region for wire bonding on the upper surface of the lower semiconductor chip 3. As the material of the wafer coat 12, for example, a normal coating material such as polyimide can be used.

  FIG. 7 is a plan view of the multilayer chip type semiconductor device shown in FIG. Here, the wafer coat 12 is provided on the surface of the lower semiconductor chip 3 so as to surround the periphery of the gap region 16. The shape of the wafer coat 12 is patterned on the lower semiconductor chip 3 so as to surround the filler-free resin in an annular shape. Also in the second embodiment, as in the case of the first embodiment, the filler-free resin is injected into the gap region 16 formed at the end of the adhesive layer 2. Thereby, the filler contained in the filler-added resin which is a molding resin is prevented from entering the gap region 16.

  Further, in the second embodiment, the resin that flows out when the filler-added resin is injected is blocked by the edge of the wafer coat 12, and a bonding pad portion or a lead frame portion below the lower semiconductor chip 3 is necessary. There is no flow in the part without. The wafer coat 12 needs to be provided when the lower semiconductor chip is manufactured. The shape of the wafer coat 12 provided on the lower semiconductor chip is patterned into a shape surrounding the filler-free resin in an annular shape on the lower semiconductor chip 3, exposing a portion corresponding to the size of the upper semiconductor chip, and wire A region for bonding is exposed. This exposure pattern can be implemented using a photolithography technique using a normal resist pattern.

  As a modification of the second embodiment, there may be a form in which the edges of the upper semiconductor chip and the lower semiconductor chip are aligned and the surface of the lower semiconductor chip does not come out (see FIGS. 5A and 5B). In this case, the shape of the wafer coat 12 is patterned so as to be adjacent to a gap region that will be formed by the surface of the lower semiconductor chip coming out. For example, the filler-added resin flows to unnecessary portions such as a bonding pad portion and a lead frame portion below the lower semiconductor chip so as to form a weir along one vertical side of the upper semiconductor chip. If it is patterned into a shape that does not occur, it will be sufficient.

  In the second embodiment described above, the filler is prevented from entering the gap region formed at the end of the adhesive layer to prevent the semiconductor chip from being damaged, and the filler-free resin region is required. Only retained. This minimizes the amount of filler-free resin used, and causes troubles in wire strength by flowing to the bonding pad area, and troubles such as reflow strength reduction by flowing in the lead frame area under the chip. Do not do. Further, the type of molding resin constituting the package is not limited, and management of the filler in the molding resin is not necessary, so that the cost is excellent.

  In the first and second embodiments described above, an example of a two-layer chip package in which quadrangular chips are stacked in two stages is shown. However, in the application of the present invention, the number of stacked layers, chip shape, size, and There is no restriction on the type of chip. For example, the present invention is effective for a multilayer chip type semiconductor device in which a spacer chip is provided in a part of a plurality of chips.

It is sectional drawing of the conventional multilayer chip type semiconductor device packaged by the molding resin. 1 is a cross-sectional view of a multilayer chip type semiconductor device according to a first embodiment of the present invention. 3 is a flowchart showing a manufacturing method in the packaging process of the multilayer chip type semiconductor device shown in FIG. It is sectional drawing which shows the specific example of the injection | pouring method of the filler additive-free resin in the filling process shown by FIG. It is a top view which shows the modification of a 1st Example. It is a top view which shows the other modification of a 1st Example. FIG. 3 is a cross-sectional view of a multilayer chip type semiconductor device according to the present invention, which is a second embodiment. FIG. 7 is a plan view of the multilayer chip type semiconductor device shown in FIG. 6.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Upper semiconductor chip 3 Lower semiconductor chip 2, 4 Adhesive layer 5, 11 Lead frame 7 Filler-free resin area 8, 9 Bonding wire 10 Filler-added resin area 12 Wafer coat 16 Crevice area 20 Injection conduit 21 Filler-free resin 21

Claims (8)

A plurality of semiconductor chips stacked in a plurality of stages, and at least one adhesive layer provided for each combination of the upper semiconductor chip and the lower semiconductor chip facing each other among the plurality of semiconductor chips, A filler-added resin region for sealing all of the plurality of semiconductor chips, and a semiconductor device comprising:
A semiconductor device further comprising a filler-free resin region sandwiched between both bonding surfaces of the upper semiconductor chip and the lower semiconductor chip and formed along at least a part of the periphery of the adhesive layer .   The semiconductor device according to claim 1, wherein the filler-free resin region is formed in an annular shape along a peripheral edge of the adhesive layer.   3. The semiconductor device according to claim 1, further comprising a wafer coat region adjacent to the filler-free resin region on the lower semiconductor chip.   The semiconductor device according to claim 1, further comprising a wafer coat region that annularly surrounds the filler-free resin region on the lower semiconductor chip. A manufacturing method for manufacturing a semiconductor device including a plurality of semiconductor chips,
A lamination step of laminating the plurality of semiconductor chips in a plurality of stages by bonding both via an adhesive layer for each combination of the upper semiconductor chip and the lower semiconductor chip among the plurality of semiconductor chips;
A filling step of filling a gap region formed between at least one part of the periphery of the adhesive layer and sandwiched between both adhesive surfaces of the upper semiconductor chip and the lower semiconductor chip with a filler-free resin;
A molding step of molding by sealing all of the plurality of semiconductor chips filled with the filler-free resin with filler-added resin,
The manufacturing method characterized by including.   The manufacturing method according to claim 5, wherein in the filling step, a filler-free resin is filled in a gap region formed in an annular shape along a peripheral edge of the adhesive layer.   7. The manufacturing method according to claim 5, further comprising a forming step of forming a wafer coat region in advance so as to be adjacent to the gap region on the lower semiconductor chip prior to the stacking step. The manufacturing method according to claim 5, further comprising a forming step of forming in advance a wafer coat region that annularly surrounds the gap region on the lower semiconductor chip prior to the stacking step.

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