JP2009200546A - Solid-state image pickup apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image pickup apparatus capable of suppressing the occurrence of noise caused by crosstalk from column AD circuit to horizontal transfer bus lines 55 while suppressing an increase in a layout area even in a configuration in which the horizontal transfer bus lines 55 cross over the column AD circuits 51. <P>SOLUTION: The solid-state image pickup apparatus has a configuration in which the horizontal transfer bus lines 55 having a plurality of horizontal transfer lines each for transmitting digital signals to be outputted from the plurality of column AD circuits 51A, 51B are arranged so as to cross over the column AD circuits 51A, 51B arranged in parallel and converting pixel signals obtained from pixels into digital signals. The solid-state image pickup apparatus is composed of the first column AD circuits 51A and the second column AD circuits 51B in which signal phases of a portions where the horizontal transfer bus lines 55 cross one another reverted from each other, wherein the first column AD circuits 51A and the second column AD circuits 51B are alternately arranged per predetermined number. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device including a plurality of analog-digital conversion circuits arranged in parallel to convert pixel signals obtained from pixels according to incident light amounts into digital signals.

  A solid-state imaging device including a conversion unit that converts charges generated according to the amount of incident light into a pixel signal, such as a CCD (Charge Coupled Device) type solid-state imaging device or a CMOS (Complementary Metal Oxide Semiconductor) type solid-state imaging. The device is used in various fields.

  Here, FIG. 9 shows a configuration of a conventional solid-state imaging device 100. The solid-state imaging device 100 is a solid-state imaging device including a plurality of analog-digital conversion circuits arranged in parallel to convert pixel signals obtained from pixels into digital signals according to the amount of incident light (Patent Document 1). reference).

  As shown in FIG. 9, the solid-state imaging device 100 includes a pixel unit 110 in which a plurality of pixels 101 are arranged in rows and columns in a matrix, a vertical scanning circuit 120 that controls row scanning of the pixel unit 110, and the like. A horizontal scanning circuit 130 that controls column scanning of the pixel unit 110, an SCU (Sensor Control Unit) 140 that controls the vertical scanning circuit 120, the horizontal scanning circuit 130, and the like, and a pixel signal obtained from the pixel 101 A column processing unit 150 having a plurality of column analog-digital conversion circuits 151 (hereinafter referred to as “column AD circuits 151”) arranged in parallel to convert to digital signals, and each column AD of the column processing unit 150 A digital-analog conversion circuit (hereinafter referred to as “DAC”) which is a reference signal generation unit that supplies a reference signal for conversion into a digital signal to the circuit 151. 160, a sense amplifier unit (SA unit) 170 that amplifies the output signal of each column AD circuit 151 of the column processing unit 150, an output unit 180 that converts the output of the sense amplifier unit 170 into video data, It has.

  Each pixel 101 is connected to a row control line 102 controlled by the vertical scanning circuit 120 and a vertical signal line 103 that transmits a pixel signal to the column processing unit 150.

  The column AD circuit 151 compares, for each row control line 102, an analog pixel signal obtained from the pixel 101 via the vertical signal line 103 and a reference signal generated by the DAC 160, and the comparison circuit 152. Has a count unit 153 that counts the time until the comparison processing is completed and holds this count value, and has an n-bit AD conversion function.

The output side of each column AD circuit 151 is connected to a horizontal transfer bus line 155. The horizontal transfer bus line 155 has a horizontal transfer line having an n-bit width and is connected to the output unit 180 via n sense amplifiers of the sense amplifier unit 170. Video data output from the output unit 180 is output from the output terminal 190 to the outside of the solid-state imaging device 100.
JP 2005-323331 A

  However, in the above-described conventional solid-state imaging device 100, generally, due to layout restrictions, as shown in FIG. 9, the horizontal transfer bus line 155 intersects the column AD circuit 151 (for example, When each component and wiring of the solid-state imaging device 100 are arranged on the multilayer substrate, the horizontal transfer bus line 155 crosses the column AD circuit 151 in a layer different from the layer where the column AD circuit 151 is formed. In such a case, parasitic capacitance is generated between the horizontal transfer bus line 155 and the wiring in the column AD circuit 151.

  Therefore, the signal in the column AD circuit 151 adversely affects the operation of each sense amplifier of the sense amplifier unit 170 via the horizontal transfer bus line 155, and finally an error occurs in the output from the sense amplifier unit 170. There is a risk that.

  As conventional measures against such a problem, (a) the parasitic capacitance between the horizontal transfer bus line 155 and the wiring in the column AD circuit 151 is reduced by a layout method, and (b) each sense amplifier of the sense amplifier unit 170 is reduced. Countermeasures such as making it differential and improving the endurance against noise were taken.

  By taking these measures (a) and (b), it is possible to obtain a certain effect. However, the countermeasure (a) only reduces the adverse effects of noise quantitatively, and it is difficult to estimate the quantitative noise reduction effect at the layout stage. Accordingly, although the error generation amount itself of the sense amplifier unit 170 can be reduced, there are many cases where it cannot be solved sufficiently, and the design period may increase due to feedback correction to the layout. In the countermeasure (b), power consumption is increased by differentiating a sense amplifier, which is normally a single-ended configuration, and the layout area of the sense amplifier unit 170 is increased.

  The present invention has been made in view of the above circumstances, and even when the horizontal transfer bus line intersects the column AD circuit, the horizontal transfer bus line is controlled from the column AD circuit while suppressing an increase in layout area. An object of the present invention is to provide a solid-state imaging device capable of reducing the generation of noise due to crosstalk.

  According to the first aspect of the present invention, a plurality of pixels that convert incident light amounts into pixel signals are arranged, and a plurality of pixels arranged in parallel to convert pixel signals obtained from the pixels into digital signals according to the incident light amounts. Analog-to-digital conversion circuits and a plurality of transfer lines for transmitting digital signals output from the plurality of analog-to-digital conversion circuits, and the transfer lines cross over the plurality of analog-to-digital conversion circuits. In the solid-state imaging device arranged in a manner, the plurality of analog-digital conversion circuits include a first analog-digital conversion circuit and a second analog-digital conversion circuit in which signal phases of portions where the transfer lines intersect with each other are inverted. The first analog-digital conversion circuit and the second analog-digital conversion circuit are alternately arranged for each predetermined number. .

  According to a second aspect of the present invention, in the first aspect of the invention, the analog-digital conversion circuit includes a comparison circuit that compares the pixel signal with a reference signal for conversion into the digital signal. A counter unit having a plurality of counter circuits connected in series, performing a count process in parallel with the comparison process by the comparison circuit, and holding a count value at the time when the comparison by the comparison circuit is completed; And the transfer line is arranged so as to cross the counter circuit of the counter unit.

  According to a third aspect of the present invention, in the second aspect of the present invention, each counter circuit constituting the counter unit is provided with a phase inverting circuit that inverts and outputs the phase of the count output unit, When each of the first analog-digital conversion circuit and the second analog-digital conversion circuit inverts and outputs the phase of the count output unit by the phase inversion circuit of each counter circuit, the other counter The phase inverting circuit of the circuit outputs the signal without inverting the phase of the count output unit, and the transfer line is arranged so as to cross the wiring connecting the count output unit of the counter circuit and the phase inverting circuit. It is characterized by being.

  According to the present invention, even if the horizontal transfer bus line crosses the column AD circuit, noise due to crosstalk from the column AD circuit to the horizontal transfer bus line is suppressed while suppressing an increase in layout area. Can be reduced.

  In a solid-state imaging device according to an embodiment of the present invention, a plurality of pixels that convert incident light amounts into pixel signals are arranged in rows and columns, and pixel signals obtained from pixels in each pixel column in accordance with the incident light amounts are converted into n-bit digital signals. A plurality of analog-digital conversion circuits arranged in parallel to each other to convert signals, and a plurality of horizontal transfer lines for transmitting digital signals output from these analog-digital conversion circuits. This is a solid-state imaging device in which horizontal transfer lines are arranged to cross over a plurality of analog-digital conversion circuits.

  Each pixel has a light receiving element that outputs an electric charge corresponding to the amount of incident light as a pixel signal that is an analog signal, an in-pixel amplifier that controls the output of the pixel signal from the light receiving element to the vertical signal line, and the like. Controlled by a vertical scanning circuit or the like. The output side of each analog-digital conversion circuit is connected to a plurality of horizontal transfer lines of the horizontal transfer bus line. Each horizontal transfer line of the horizontal transfer bus line is connected to a sense amplifier, and video data is output from the output unit via these sense amplifiers.

  Here, since the analog-digital conversion circuit (for example, wiring in the circuit) intersects the horizontal transfer line, parasitic capacitance is generated between the wiring in the analog-digital conversion circuit and the horizontal transfer line. To do. Therefore, there is a possibility that a signal passing through the wiring in the analog-digital conversion circuit has an influence (crosstalk) on the horizontal transfer line. In particular, due to layout restrictions, the analog-to-digital conversion circuit has the same layout, and the horizontal transfer lines often cross over the same part in the analog-to-digital conversion circuit. That is, the horizontal transfer line often crosses over a plurality of analog-digital conversion circuits.

  Therefore, in the solid-state imaging device according to the present embodiment, the first analog-digital conversion circuit and the second analog-digital conversion in which the signal phases of the portions where the horizontal transfer lines intersect with each other are inverted. It consists of a circuit.

  Accordingly, a parasitic capacitance is generated between the horizontal transfer line and a plurality of analog-digital conversion circuits, and the signal in the first analog-digital conversion circuit crosstalks. -The signal in the digital conversion circuit will also cross-talk.

  As a result, the signal crosstalked by the first analog-digital conversion circuit cancels out the signal crosstalked by the second analog-digital conversion circuit, and noise generated in the horizontal transfer line can be reduced.

  By the way, for example, when the analog-digital conversion circuit is divided into a first analog-digital conversion circuit group and a second analog-digital conversion circuit group on the left and right, it is close to the sense amplifier due to the wiring resistance of the horizontal transfer line. The influence from the analog-digital conversion circuit becomes large, and the effect of cancellation becomes worse.

  Therefore, in the solid-state imaging device according to the present embodiment, the first analog-digital conversion circuit and the second analog-digital conversion circuit are alternately arranged as a set every predetermined number. By doing so, it is possible to further improve the effect of canceling out the crosstalk from the first analog-digital conversion circuit and the crosstalk from the second analog-digital conversion circuit. Noise generated in the line can be further reduced. In particular, a larger noise reduction effect can be obtained by alternately arranging the first analog-digital conversion circuit and the second analog-digital conversion circuit one by one.

  In the solid-state imaging device according to the present embodiment, the analog-digital conversion circuit includes a comparison circuit that compares a reference signal for conversion into a digital signal and a pixel signal, and a plurality of counter circuits connected in series. And a counter unit that performs count processing in parallel with the comparison processing by the comparison circuit and holds the count value at the time when the comparison by the comparison circuit is completed, and the horizontal transfer line is a counter circuit of the counter unit It is arranged to cross over.

  As described above, due to layout restrictions, the analog-to-digital conversion circuits have the same layout, and the horizontal transfer lines often cross over the same portion in the analog-to-digital conversion circuit. Therefore, if the counter circuits of the analog-digital conversion circuit perform the counting operation at the same time, the count signals simultaneously crosstalk from these counter circuits to the horizontal transfer line, and the influence on the horizontal transfer line becomes large.

  However, in the solid-state imaging device according to the present embodiment, the signal phases of the portions where the horizontal transfer lines intersect with each other are inverted, so noise generated in the horizontal transfer lines can be reduced. That is, the signal of the counter circuit of the analog-digital conversion circuit is made to have a different signal phase between the first analog-digital conversion circuit and the second analog-digital conversion circuit, thereby canceling the crosstalk signal. I meet.

  In addition, in order to read the reset component, in one mode of the up-count operation and the down-count operation, the count process is performed in parallel with the comparison process by the comparison circuit, and the comparison by the comparison circuit is completed. Holds the count value, and then performs the count process in parallel with the comparison process by the comparison circuit in the other mode for reading the signal component, and holds the count value when the comparison by the comparison circuit is completed. Thus, a CDS (Correlated Double Sampling) processing function and an AD conversion function are realized, and details will be described later.

  Here, the counter unit can count in both the up-counting operation and the down-counting mode, and each counter circuit constituting the counter unit inverts the phase of the count output unit and outputs it. A phase inversion circuit is provided.

  When the phase of the count output unit is inverted and output by the phase inversion circuit of each counter circuit of the first analog-digital conversion circuit and the second analog-digital conversion circuit, the other counters The output is performed without inverting the phase of the count output unit by the phase inverting circuit of the circuit.

  As described above, by providing the phase inverting circuit in each counter circuit, the output from each counter circuit is output in the same count operation in the first analog-digital conversion circuit and the second analog-digital conversion circuit. The first analog-digital conversion circuit and the second analog-digital conversion circuit can also be used when the horizontal transfer lines are arranged so as to cross over the wiring connecting the count output unit of the counter circuit and the phase inversion circuit. Signals that crosstalk to the horizontal transfer line have opposite phases, and noise due to cancellation can be reduced.

  Hereinafter, an example of a specific configuration and operation of the solid-state imaging device according to the present embodiment will be described with reference to the drawings. 1 is an overall configuration diagram of a solid-state imaging device according to the present embodiment, FIG. 2 is a diagram illustrating a specific configuration of a counter circuit in a counter unit, FIG. 3 is a diagram illustrating an example of a layout of a conventional column AD circuit, and FIG. It is a figure which shows the example of the layout of the column AD circuit in this embodiment.

  As shown in FIG. 1, the solid-state imaging device 1 according to the present embodiment includes a pixel unit 10 in which a plurality of pixels 11 that convert incident light amounts into pixel signals are arranged in rows and columns in a matrix, and rows of pixel units 10. A vertical scanning circuit 20 that controls scanning, a horizontal scanning circuit 30 that controls column scanning of the pixel unit 10, and an SCU (Sensor Control Unit) that controls the vertical scanning circuit 20 and the horizontal scanning circuit 30. 40 and a plurality of column analog-digital conversion circuits 51 (hereinafter referred to as “column AD circuits 51”) arranged in parallel to convert pixel signals obtained from the pixels 11 of each pixel column into digital signals. And a digital-analog conversion circuit 6 that is a reference signal generation unit that supplies a reference signal for conversion to a digital signal to each column AD circuit 51 of the column processing unit 50. 0 (hereinafter referred to as “DAC60”), a bias (Bias) circuit 61 that supplies a bias to each circuit, a PLL circuit 62 that supplies a clock signal xCK for counting to the column AD circuit 51, and the column AD circuit 51 Is provided with a sense amplifier (SA) unit 70 for amplifying the output of the video signal and an output unit 80 for converting the output of the sense amplifier unit 70 into video data.

  In reality, the pixel unit 10 has tens to thousands of pixels 11 arranged in each row and each column. The pixel 11 is typically composed of a light receiving element as a charge generation unit and an in-pixel amplifier having an amplifying semiconductor element (for example, a transistor).

  As the intra-pixel amplifier, for example, a floating diffusion amplifier configuration is used. As an example, with respect to the charge generation unit, a read selection transistor that is an example of a charge readout unit (transfer gate unit / read gate unit), a reset transistor that is an example of a reset gate unit, a vertical selection transistor, and a floating diffusion As a CMOS sensor having a source follower-amplifying transistor, which is an example of a detection element for detecting a change in potential, a sensor composed of four general-purpose transistors can be used.

  Further, the pixels 11 are respectively connected to the vertical scanning circuit 20 via the row control line 12 for row selection, and to the column processing unit 50 provided with the column AD circuit 51 for each vertical column via the vertical signal line 13. Connected. Here, the row control line 12 indicates all the wiring that enters the pixel 11 from the vertical scanning circuit 20.

  The vertical scanning circuit 20 selects a row of the pixel unit 10 and supplies a necessary pulse to the row. For example, although not shown, a vertical decoder that defines a readout row in the vertical direction (selects a row of the pixel unit 10), and a row control line for the pixel 11 on the readout address (in the row direction) defined by the vertical decoder. 12 and a vertical drive circuit for driving by supplying pulses. Note that the row control line 12 includes one that transmits various pulse signals (for example, a reset pulse, a transfer pulse, a DRN control pulse, etc.) for driving the pixels 11.

  The horizontal scanning circuit 30 sequentially selects the column AD circuits 51 of the column processing unit 50 in synchronization with the clock, and guides the signals to the horizontal transfer lines 56 (56_1, 56_2,...) Of the horizontal transfer bus line 55. Is. For example, although not shown, a horizontal decoder that defines a read column in the horizontal direction (selects each column AD circuit 51 in the column processing unit 50) and a column processing unit according to a read address defined by the horizontal decoder A horizontal drive circuit for guiding each of the 50 signals to the horizontal transfer line 56 of the horizontal transfer bus line 55. For example, if the number of bits n (n is a positive integer) handled by the column AD circuit 51 is 10 (= n), for example, 10 horizontal transfer lines 56 are arranged corresponding to the number of bits. .

  Although not shown, the SCU 40 includes a functional block that supplies a clock necessary for the operation of each unit, a pulse signal of a predetermined timing, an address signal, and the like. For example, the SCU 40 sends a vertical address signal to the vertical scanning circuit 20 and a horizontal address signal. Are output to the horizontal scanning circuit 30, and the decoders of the vertical scanning circuit 20 and the horizontal scanning circuit 30 receive it and select a corresponding row or column.

  Here, the pixel signal output from the pixel 11 is supplied to the column AD circuit 51 of the column processing unit 50 via the vertical signal line 13 for each vertical column.

  The column AD circuit 51 includes a comparison circuit 52 that compares the voltage of the reference signal generated by the DAC 60 and an analog pixel signal obtained from the pixel 11 via the vertical signal line 13 for each row control line 12, a latch, and a plurality of signals. Counter circuits (B0, B1,...) Are connected in series, and the count process is performed in parallel with the comparison process by the comparison circuit 52, and the time until the comparison circuit 52 completes the comparison process is determined. The counter unit 53 is configured to count and hold the count value, and has an n-bit AD conversion function.

  The count value held by each column AD circuit 51 is supplied to the sense amplifier unit 70 via the horizontal transfer bus line 55. The sense amplifier unit 70 has a sense amplifier connected to each horizontal transfer line 56, and amplifies a signal output from the latch in each counter circuit of the column AD circuit 51 to each horizontal transfer line 56. The signal amplified by the sense amplifier unit 70 is output as video data from the output unit 80 via the output terminal 90.

  Here, a specific operation of the column AD circuit 51 will be described with reference to FIG. The column AD circuit 51 is a circuit that realizes a CDS (Correlated Double Sampling) processing function and an AD conversion function for each pixel column of the pixel unit 10.

  The DAC 60 generates a step-like sawtooth wave (ramp waveform) in synchronization with the count clock signal xCK, and AD converts the generated sawtooth wave to each column AD circuit 51 of the column processing unit 50. Is supplied as a reference signal.

  One input terminal of the comparison circuit 52 is input with a stepped reference signal generated by the ADC 60 in common with the input terminal of the other comparison circuit 52, and each of the other input terminals has a vertical line in the corresponding vertical column. The signal lines 13 are connected, and pixel signal voltages from the pixel unit 10 are individually input. The output signal of the comparison circuit 52 is supplied to the counter unit 53.

  The counter unit 53 uses a common up / down counter (U / D CNT) regardless of the count mode, and switches between the down count operation and the up count operation (specifically, alternately) by the control of the SCU 40. It is comprised so that it can perform.

  The counter unit 53 starts a count operation by a down-count operation or an up-count operation in synchronization with the ramp waveform voltage emitted from the DAC 60, and when the counter unit 53 is notified of the inverted information from the output of the comparison circuit 52, the counter unit 53 counts. The operation is stopped, and the AD conversion is completed by latching (holding / storing) the count value at that time as pixel data.

  Thereafter, the counter unit 53 stores the pixel data stored and held on the horizontal transfer bus line 55 on the horizontal transfer bus line 55 based on a shift operation by a horizontal selection signal input from the horizontal scanning circuit 30 via the control line at a predetermined timing. Output to the transfer line 56.

  Here, the pixel signal output from the vertical signal line 13 has a signal component Vsig appearing after the reset component ΔV including the noise of the pixel signal as a reference component as a time series. The reset level in the signal voltage is detected by the comparison circuit 52 and the count operation is performed. Thereby, the reset component ΔV of the pixel 11 can be read out. Thereafter, in the second reading, in addition to the reset component ΔV, the signal component Vsig corresponding to the incident light amount for each pixel 11 is read, and the same operation as the first reading is performed. Thereby, the signal component Vsig of the pixel 11 can be read out.

  Then, the counting operation in the counter unit 53 is, for example, a down-counting operation at the first reading, and an up-counting operation at the second reading, so that the subtraction represented by the equation (1) is automatically performed in the counter unit 53. The count value corresponding to the subtraction result is held in the counter unit 53.

  Here, Expression (1) can be transformed into Expression (2), and as a result, the count value held in the counter unit 53 corresponds to the signal component Vsig.

  That is, as described above, there are 2 count operations (P phase: reset component ΔV read operation) at the time of the first read and up count operations (D phase: signal component Vsig read operation) at the time of the second read. The reset component ΔV including the variation for each pixel 11 and the offset component for each column AD circuit 51 can be removed by the subtraction process in the counter unit 53 by the read-out and count processing, and the incidence for each pixel 11 can be removed. Only the signal component Vsig corresponding to the amount of light can be extracted with a simple configuration. At this time, there is an advantage that reset noise can also be removed.

  Therefore, the column AD circuit 51 of the present embodiment operates not only as a digital conversion unit that converts an analog pixel signal into digital pixel data but also as a CDS (Correlated Double Sampling) processing function unit. It will be.

  Here, the counter unit 53 of the column AD circuit 51 of the present embodiment is composed of a plurality of counter circuits B0, B1,. FIG. 2 is a diagram showing a specific configuration of the counter circuit in the counter unit 53. Here, for ease of explanation, the AD conversion of the column AD circuit 51 is 5 bits, and five counter circuits B0, B1, B2, B3, B4 are connected in series to form a 5-bit counter. Explain that it is. In the following, any counter circuit among the counter circuits B0, B1, B2, B3, and B4 may be expressed as a counter circuit B. Further, each of the switches SW1 to SW8 in FIG. 2 is short-circuited when an H-level signal is input, and is not short-circuited when an L-level signal is input.

  As shown in FIG. 2, the counter circuit B is a binary counter circuit, and includes a counter 57, a phase inversion circuit 58, and a latch (Latch) 59. The counter circuit B is controlled by the horizontal scanning circuit 30, the SCU 40, or the like.

  The counter 57 changes the state of the signal (carry bit signal) output from the count output unit NodeA at the falling timing of the input signal CIN. That is, the carry bit signal output from the count output unit NodeA is changed from the L level to the H level or from the H level to the L level at the falling timing of the input signal CIN.

  Further, when the control pulse signal XRL (XRL_A, XRL_B) is input, the counter 57 resets the output from NodeA to the L level and clears the counter value. When the control pulse signal RH (RH_A, RH_B) is input, the output from the count output unit NodeA is reset to H level, and the counter value is cleared.

  Further, the counter 57 holds the count when the hold signal HOLD is input. In other words, the hold signal HOLD becomes an enable signal for holding the count value in order to prevent a malfunction of the count which is a concern when switching between the up-count operation and the down-count operation.

  The phase inversion circuit 58 is a circuit that inverts and outputs the phase of the count output unit NodeA, and also has a function of switching between an up count operation and a down count operation. The phase inverting circuit 58 is controlled by the control signal UDSL (UDSL_A, UDSL_B) output from the horizontal scanning circuit 30. When the control signal UDSL is at the L level, a signal obtained by inverting the voltage of the count output unit NodeA is output. Output from COUT. The control signal UDSL is controlled so that the P-phase is a down-count operation and the D-phase is an up-count operation.

  The latch 59 is a circuit that latches and holds the output of the phase inverting circuit 58, that is, the output of the counter circuit B. The count value held in the latch 59 is output to one horizontal transfer line 56 of the horizontal transfer bus line 55.

  In the counter circuit B configured as described above, horizontal transfer bus lines 55 may cross each other as shown in FIG. 2 due to layout restrictions. When the horizontal transfer bus line 55 crosses the counter circuit B in this way, a parasitic capacitance is generated between the wiring in the counter circuit B and the horizontal transfer line 56 of the horizontal transfer bus line 55. Therefore, there is a possibility that a signal passing through the wiring in the counter circuit B has an influence (crosstalk) on the horizontal transfer line.

  Here, the horizontal transfer bus line 55 intersects with the wiring between the count output unit NodeA of the counter 57 and the phase inversion circuit 58 (for example, each component and wiring of the solid-state imaging device 1 are disposed on the multilayer substrate. The horizontal transfer bus line 55 is arranged in a layer different from the layer in which the wiring between the count output unit NodeA of the counter 57 and the phase inverting circuit 58 is formed so as to cross the wiring. In this case, due to layout restrictions, as shown in FIG. 3, the column AD circuits 51 are arranged in parallel in the same layout, and the horizontal transfer bus lines 55 are the same in each column AD circuit 51. Often crossed over parts.

  In the solid-state imaging device 1 according to the present embodiment, all the column AD circuits 51 are collectively counted (P-phase and D-phase), and therefore, from these counter circuits B to the horizontal transfer line 56 of the horizontal transfer bus line 55. At the same time, the count signal causes crosstalk, and there is a possibility that large noise is generated in the horizontal transfer line 56. When large noise occurs in the horizontal transfer line 56 in this way, the operation of each sense amplifier of the sense amplifier unit 70 is adversely affected via the horizontal transfer bus line 55, and finally the output from the sense amplifier unit 70 is affected. An error may occur.

  Therefore, in the solid-state imaging device 1 according to the present embodiment, a plurality of column AD circuits 51 are connected to signals at portions where horizontal transfer lines intersect (here, wiring between the count output unit NodeA of the counter 57 and the phase inversion circuit 58). The first column AD circuit 51A and the second column AD circuit 51B are mutually inverted in phase.

  The first column AD circuit 51A and the second column AD circuit 51B are alternately arranged for each constant in the row direction. By doing so, it is possible to further improve the effect of canceling the crosstalk from the first column AD circuit 51A and the second column AD circuit 51B, and thereby noise generated in the horizontal transfer line 56. Can be further reduced. For example, if the column AD circuit 51 is divided into two groups, a first column AD circuit 51A and a second column AD circuit 51B, left and right, the horizontal transfer is performed. This is because the influence of the analog-to-digital conversion circuit close to the sense amplifier is increased due to the wiring resistance of the line, and the effect of cancellation is deteriorated.

  In the example shown in FIG. 4, the first column AD circuit 51A and the second column AD circuit 51B are alternately arranged as a set of four units (UNIT_A, UNIT_B) in the row direction. Note that if the first column AD circuit 51A and the second column AD circuit 51B are alternately arranged one by one, a greater noise reduction effect can be obtained.

  As described above, the operation of each counter circuit B of the solid-state imaging device 1 in the present embodiment in which the first column AD circuit 51A and the second column AD circuit 51B are alternately arranged in a predetermined number in the row direction. This will be described with reference to the drawings. 5 and 6 are diagrams for explaining the operation of the counter circuit B of the first column AD circuit 51A in the solid-state imaging device 1 of the present embodiment, and FIGS. 7 and 8 are solid-state imaging devices of the present embodiment. 6 is a diagram for explaining the operation of the counter circuit B of the second column AD circuit 51B in FIG.

  First, the operation of the counter circuits B0 to B4 of the first column AD circuit 51A will be described. Note that NodeA [0] to NodeA [4] shown in FIG. 5 are the carry bit signals and control pulse signals XRL_A and RH_A output from the count output unit NodeA of the counter 57 of each counter circuit B0 to B4. The control pulse signals XRL and RH and the control signal UDSL_A input to the column AD circuit 51A are control signals UDSL input to the first column AD circuit 51A. Further, COUT [0] to COUT [4] shown in FIG. 6 are output signals of the counter circuits B0 to B4.

  As shown in FIG. 5, first, when a control pulse signal XRL_A (L level pulse) is input to each of the counter circuits B0 to B4, each counter 57 outputs a signal from NodeA [0] to NodeA [4]. The output is reset to L level and the counter value is cleared.

  Next, the clock signal xCK is input to the counter circuit B0, and the carry bit signal output from the count output unit NodeA [0] in the counter circuit B0 is between the L level and the H level at the falling timing of the clock signal xCK. It changes with. The voltage of the carry bit signal output from the count output unit NodeA [0] in the counter circuit B0 is input to the phase inversion circuit 58 in the counter circuit B0.

  Here, since the control signal UDSL of H level is input to each of the counter circuits B0 to B4, the phase of the carry bit signal output from the count output unit NodeA [0] is inverted, as shown in FIG. As described above, the output signal COUT [0] is output from the phase inverting circuit 58 in the counter circuit B0.

  The counter circuit B0 changes the count value at every falling timing of the count clock signal xCK. When the count value of the counter circuit B0 changes, the change of the count value (COUT [0]) is input as CIN of the counter circuit B1, and the counter circuit B1 performs counting. Similarly, the counter circuit B2 is based on the output (COUT [1]) of the counter circuit B1, the counter circuit B3 is based on the output (COUT [2]) of the counter circuit B2, and the counter circuit B4 is countered with the counter circuit B3 (COUT The counter value is changed based on the output of [3]). This first count is a P-phase count, and is performed by a down-count operation as shown in FIG.

  Thereafter, when the comparison in the comparison circuit 52 is completed, the counter circuits B0 to B4 of the first column AD circuit 51A end the count and store the count value in the latch 59.

  Next, a second count is performed. This second count is a D-phase count and is performed by an up-count operation.

  Since each of the counter circuits B0 to B4 is in the down count operation, the control signal UDSL_A is changed from the H level to the L level in order to switch to the up count operation. Thus, the L level control signal UDSL is input to the phase inverting circuit 58, and the phase of the carry bit signal output from the count output unit NodeA is not inverted, and the output signal COUT is output from the phase inverting circuit 58 in the counter circuit B0. Output as [0].

  Thereafter, similarly, at each falling timing of the clock signal xCK, the counter circuit B0 sequentially changes the count value (COUT [0]) in the same manner as the P-phase count, and as shown in FIG. The counter values (COUT [0] to COUT [4]) of the circuits B0 to B4 are changed. This second count is a D-phase count and is performed by an up-count operation.

  Thereafter, when the comparison in the comparison circuit 52 is completed, the counter circuits B0 to B4 of the first column AD circuit 51A end the count and store the count value in the latch 59. As a result, the count value obtained by subtracting the first count value from the second count value is stored in the latch 59 of the counter circuits B0 to B4.

  On the other hand, the counter circuits B0 to B4 of the second column AD circuit 51B also output from the counter circuits B0 to B4 (COUT [0] to COUT [4]) as shown in FIG. This is similar to the circuit 51A (see FIG. 6). 7 and 8, the control pulse signals XRL_B and RH_B are input to the second column AD circuit 51B, and the control pulse signals XRL and RH and the control signal UDSL_B are input to the second column AD circuit 51B. Control signal UDSL.

  However, the count output sections NodeA [0] to NodeA [4] of each counter circuit B in the second column AD circuit 51B are the count output sections NodeA [0] to NodeA of the counter circuit B of the first column AD circuit 51A. The voltage is inverted with respect to [4].

  As a result, the first column AD circuit 51A and the second column AD circuit 51B transmit the wiring between the count output units NodeA [0] to NodeA [4] of the counter 57 and the phase inversion circuit 58. The phase of the carry bit signal is inverted.

  That is, in the second column AD circuit 51B, not the control pulse signal XRL_A (L level pulse) but the control pulse signal RH_B (L level pulse) is input to each counter circuit B0 to B4, and each counter 57 , The carry bit signals output from the count output units NodeA [0] to NodeA [4] are reset to H level to clear the counter value. As a result, the state of each counter 57 of the second column AD circuit 51B is inverted with respect to the state of each counter 57 of the first column AD circuit 51A, so that the first column AD circuit 51A and the second column AD circuit 51A The column AD circuit 51B is a signal (inverted phase signal) obtained by inverting the phases of carry bit signals output from the output units NodeA [0] to NodeA [4].

  Then, the control signal UDSL_B obtained by inverting the level of the control signal UDSL_A input to each counter circuit B of the first column AD circuit 51A is input to each counter circuit B of the second column AD circuit 51B, whereby the second As shown in FIG. 8, the output (COUT [0] to COUT [4]) from the counter circuit B of the column AD circuit 51B is output from the counter circuit B of the first column AD circuit 51A (COUT [0]). ] To COUT [4]).

  As described above, in the solid-state imaging device 1 according to the present embodiment, the column AD circuit is compared with the conventional one by simple wiring processing and control in which different control pulse signals XRL and RH and the control signal UDSL are input and the column AD circuit is controlled. The carry bit of the portion intersecting with the horizontal transfer line 56 (in this case, the wiring between the count output unit NodeA of the counter 57 and the phase inversion circuit 58) without changing the configuration of FIG. The first column AD circuit 51A and the second column AD circuit 51B can be configured in which the phases of the signals are inverted (that is, have opposite phases).

  Therefore, even if the horizontal transfer bus line 55 intersects the column AD circuit 51, noise due to crosstalk from the column AD circuit 51 to the horizontal transfer bus line 55 is suppressed while suppressing an increase in layout area. Can be reduced

1 is an overall configuration diagram of a solid-state imaging device according to an embodiment of the present invention. It is a figure which shows the specific structure of the counter circuit in the counter part shown in FIG. It is a figure which shows the example of the layout of the conventional column AD circuit. It is a figure which shows the example of the layout of the column AD circuit in this embodiment. It is a figure for demonstrating operation | movement of the counter circuit of a 1st column AD circuit. It is a figure for demonstrating operation | movement of the counter circuit of a 1st column AD circuit. It is a figure for demonstrating operation | movement of the counter circuit of a 2nd column AD circuit. It is a figure for demonstrating operation | movement of the counter circuit of a 2nd column AD circuit. It is a figure which shows the structure of the conventional solid-state imaging device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 11 Pixel 12 Row control line 13 Vertical signal line 20 Vertical scanning circuit 30 Horizontal scanning circuit 40 Sense amplifier (SA) part 50 Column processing part 51 Column AD circuit (analog-digital conversion circuit)
52 Comparison Circuit 53 Counter 54 Latch 55 Horizontal Transfer Bus Line 56 Horizontal Transfer Line 57 Counter 58 Phase Inversion Circuit 59 Latch 60 Digital-Analog Conversion Circuit (DAC)
61 Bias circuit 62 PLL circuit 70 Sense amplifier (SA) section 80 Output section 90 Output terminal

Claims (3)

A plurality of pixels that convert incident light amounts into pixel signals, a plurality of analog-digital conversion circuits arranged in parallel to convert pixel signals obtained from the pixels into digital signals according to the incident light amounts, and A solid-state imaging device having a plurality of transfer lines that transmit digital signals output from a plurality of analog-digital conversion circuits, and wherein the transfer lines are arranged to cross over the plurality of analog-digital conversion circuits,
The plurality of analog-to-digital conversion circuits include a first analog-to-digital conversion circuit and a second analog-to-digital conversion circuit in which signal phases of portions where the transfer lines intersect with each other are inverted, and the first analog-to-digital conversion circuit A solid-state image pickup device, wherein a predetermined number of digital conversion circuits and second analog-digital conversion circuits are alternately arranged. The analog-digital conversion circuit includes:
A comparison circuit that compares the pixel signal with a reference signal for conversion to the digital signal;
A counter unit having a plurality of counter circuits connected in series, performing a count process in parallel with the comparison process by the comparison circuit, and holding a count value at the time when the comparison by the comparison circuit is completed; Have
The solid-state imaging device according to claim 1, wherein the transfer line is arranged so as to intersect with a counter circuit of the counter unit. Each counter circuit constituting the counter unit is provided with a phase inverting circuit for inverting and outputting the phase of the count output unit, and the first analog-digital conversion circuit and the second analog-digital conversion circuit are provided. When the phase of the count output unit is inverted by the phase inversion circuit of each counter circuit, the phase output unit of the other counter circuit outputs the phase without inverting the phase of the count output unit,
The solid-state imaging device according to claim 2, wherein the transfer line is arranged so as to intersect on a wiring connecting the count output unit of the counter circuit and the phase inversion circuit.

Images