JP2009283799A - Nonvolatile semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a NAND-type nonvolatile semiconductor memory device capable of making a minimum area of memory cells smaller, as well as, attaining higher integration, higher density, and larger capacity. <P>SOLUTION: The nonvolatile semiconductor memory device includes: layered structures L, in which insulating layers and semiconductor layers are alternately stacked, in a first direction which is vertical to the surface of a semiconductor substrate 10 and configured in a ridge-like manner, with each having a pair of side surfaces opposing each other; charge accumulation layers CS, each being in contact with both the pair of side surfaces of the laminate structure L and formed so as to have a given width in a second direction which is parallel to the surface of the semiconductor substrate 10 in the side surfaces; and first conductive layers CG1, each being in contact with the surface of the charge accumulation layer CS and formed so as to cover the stacked structure L and the charge accumulation layer CS. Source drain regions A2 are formed on both side portions, in the second direction of the first conductor layer CG1 of the semiconductor layer. The source drain region A2, the charge accumulation layer CS, and the first conductor layer CG1 constitute a pair of memory cells with respect to one semiconductor layer on the pair of the side surfaces of the layered structure L. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a NAND-type nonvolatile semiconductor memory device and a manufacturing method thereof.

  An example of a nonvolatile semiconductor memory device is a flash memory that can be electrically written and erased. For flash memory, for example, high density and high integration are relatively easy, NAND flash memory suitable for data storage, and random access processing is relatively fast, suitable for program code storage, etc. There is a NOR type flash memory.

  Here, the NAND flash memory has a relatively high writing speed as compared with other nonvolatile memories such as a NOR flash memory, and as described above, high density and high integration are relatively easy. Therefore, it is suitable for large capacity. In recent years, due to an increase in data capacity handled on a computer and the like, NAND flash memories are also required to have a larger capacity, that is, higher integration and higher density.

Conventionally, the increase in the capacity of the NAND flash memory has been realized mainly by reducing the area of the memory cell with respect to the semiconductor substrate plane by the development of the microfabrication technology. For this reason, the minimum area of the memory cell is 2F × 2F = 4F ² as shown in FIG. In recent years, since the fine processing technology is approaching the limit, a technology capable of realizing high integration and high density without using the fine processing technology is desired.

  As a technique for achieving high integration and high density of memory cells, for example, a charge holding portion and a conductor layer (gate terminal) of a memory cell are formed on a side surface portion of a trench between the memory cells, and a bottom surface portion of the trench. There has been proposed a NAND flash memory in which a source region (drain region) is formed and a drain region (source region) is formed in a region in contact with the upper portion of the trench (see, for example, Patent Document 1).

Here, FIG. 11 partially shows the configuration of the memory cell array in the NAND flash memory 100 described in Patent Document 1. As shown in FIG. 11, the NAND flash memory 100 has a memory cell charge holding portion 102 at the side surface portion of the trench, a source region (drain region) 104 at the bottom surface portion of the trench, and a drain at a region in contact with the upper portion of the trench. Regions (source regions) 103 are respectively formed. FIG. 11B shows a cross section perpendicular to the surface of the semiconductor substrate 110 taken along the line EE ′ of FIG. As shown in FIG. 11, in Patent Document 1, two memory cells are formed in a range of 2F × 2F, so that the minimum area of the memory cell is substantially 2F × 2F ÷ 2 = 2F ^2. . Compared with the area 4F ² of the conventional memory cell, when the same process is used, it is possible to achieve about twice as high integration and high density.

JP 2008-4915 A

As described above, for example, when the same process is used, the area of the memory cell described in Patent Document 1 is 2F ² , which is about twice as high as the conventional memory cell area 4F ² . In addition, the density can be increased. However, the data capacity handled on the computer continues to increase, and further increase in capacity, that is, further higher integration and higher density is demanded in the NAND flash memory.

  The present invention has been made in view of the above problems, and an object of the present invention is to make the minimum area of a memory cell smaller and to achieve higher integration, higher density, and higher capacity. A nonvolatile semiconductor memory device is provided.

  In order to achieve the above object, a non-volatile semiconductor memory device according to the present invention includes an insulating layer and a semiconductor layer disposed on a surface of the semiconductor substrate such that the insulating layer is disposed on the bottom and top of the semiconductor substrate. A stacked structure section alternately stacked along a first vertical direction; a charge storage layer having a charge holding function; and a first conductor layer constituting a gate terminal. A pair of side surfaces facing each other is configured in a bowl shape, and the charge storage layer is in contact with both of the pair of side surfaces of the stacked structure portion, and in a second direction parallel to the semiconductor substrate surface in the side surfaces The first conductor layer is in contact with the surface of the charge storage layer and covers the stacked structure portion and the charge storage layer, and the semiconductor layer is formed of the first conductive layer. The side surface is not covered with one conductor layer The first conductivity of the semiconductor layer in which the side surface is covered with the first conductor layer at least on both side portions in the second direction of the first conductor layer in the inner region from the side surface of the semiconductor layer. A source / drain region of a second conductivity type different from the type is formed, and one semiconductor is formed on the pair of side surfaces of the stacked structure portion by the source / drain region, the charge storage layer, and the first conductor layer. A first feature is that a pair of memory cells are formed for each layer.

  In the nonvolatile semiconductor memory device according to the present invention having the above characteristics, the stacked structure portion includes two or more semiconductor layers, and a plurality of pairs of the memory cells are configured in the first direction. This is the second feature.

  In the nonvolatile semiconductor memory device according to the present invention having any one of the above features, the plurality of stacked structure portions are arranged such that each of the adjacent stacked structure portions has one side surface facing each other. A third feature is that a plurality of pairs of the memory cells are configured in the third direction, each including a stacked structure group arranged in a third direction orthogonal to the direction and the second direction.

  In the nonvolatile semiconductor memory device according to the first or second feature of the present invention, the charge storage layer and the first conductor layer are separated from each other in the second direction with respect to one stacked structure portion. A fourth feature is that a plurality of pairs of the formed memory cells are formed in the second direction.

  In the nonvolatile semiconductor memory device according to the first or second feature of the present invention, a plurality of the stacked structure portions are arranged such that each of the adjacent stacked structure portions is opposed to each other on one side surface. A stacked structure group disposed in a first direction and a third direction orthogonal to the second direction, wherein the charge storage layer and the first conductor layer are provided in the plurality of stacked structure portions constituting the stacked structure group; A fifth feature is that a plurality of pairs of memory cells are formed in the second direction and the third direction, and a plurality of pairs are formed in the second direction.

  In the nonvolatile semiconductor memory device according to the fourth or fifth feature of the present invention, the second conductor is formed so as to be in contact with both of the side surfaces of the stacked structure portion and to have a certain width in the second direction. A second layer of the second conductor layer in the inner region of the semiconductor layer, the side surface of which is not covered with the first conductor layer or the second conductor layer. The source / drain regions of the second conductivity type are formed on both side portions of the second conductive layer, and the source / drain regions on both side portions in the second direction of the second conductive layer, and the second conductive layer, A sixth feature is that a pair of selection transistors is formed for one semiconductor layer on the pair of side surfaces of the stacked structure portion.

  In the nonvolatile semiconductor memory device according to the present invention having the above characteristics, a plurality of the second conductor layers are separately formed in the second direction with respect to one or a plurality of the stacked structure portions, and the pair of selections A plurality of transistors are configured in the second direction, and each of the selection transistors is classified into a selection transistor group set according to a side surface of the stacked structure portion and according to the semiconductor transmission, and the same selection transistor group Are connected in series by connecting the source / drain regions adjacent to each other in the second direction, and each of the memory cells is set for each side of the stacked structure and for each semiconductor layer. Each of the memory cells constituting the same memory cell unit is adjacent to the source / drain region in the second direction. The memory cell unit and the selection transistor group formed in the same semiconductor layer on the same side surface are connected in series by connecting the source / drain regions adjacent to each other in the second direction. This is the seventh feature.

  In the nonvolatile semiconductor memory device according to the present invention having the above characteristics, the stacked structure group includes a plurality of the stacked structure portions having the same number of the semiconductor layers, and the select transistor groups respectively include the stacked structure portions. When the number of the semiconductor layers is N, a pair of N + 2 selection transistors for selecting one of the side surfaces of the stacked structure portion on which the memory cell unit to be selected is formed is selected. A plurality of first selection control lines and N second selection control lines configured for each of the semiconductor layers to select the semiconductor layer in which the memory cell unit to be selected is formed; In the selection transistor group formed in the structure portion, an end portion that is not connected to the memory cell unit by the source / drain region is connected to a common bit line, and the selection transistor Among the selection transistors constituting the group, the first selection control line corresponding to the gate terminals of two selection transistors and the second selection control line corresponding to the gate terminals of N selection transistors are respectively provided. The connection is an eighth feature.

  In the nonvolatile semiconductor memory device according to the present invention having the above characteristics, each of the selection transistors includes a first selection transistor configured of either a normally-off type or a normally-on type, and the first selection transistor. The memory cell formed on one of the second selection transistors different in type from the transistor and formed on the side surface of the stacked structure portion to be selected among the selection transistors connected to the first selection control line The selection transistor connected to a unit is configured by the first selection transistor, the other selection transistor is configured by the second selection transistor, and among the selection transistors connected to the second selection control line, The selection transistor connected to the memory cell unit formed in the semiconductor layer is the first selection transistor. Consists of static, and ninth feature of that other of said selection transistor is formed by the second selection transistor.

  In the nonvolatile semiconductor memory device according to the present invention having any one of the above characteristics, the stacked structure portion includes the insulating layer made of an oxide film, the semiconductor layer made of a polycrystalline silicon film, and the charge storage layer The oxide film and the nitride film are the first unit laminated film, and the first laminated film composed of one or more first unit laminated films, or the oxide film, the nitride film, and the oxide film are the second unit laminated film, A tenth feature is that it is configured by one of the second stacked films including one or a plurality of second unit stacked films.

  In order to achieve the above object, a method for manufacturing a nonvolatile semiconductor memory device according to the present invention is a method for manufacturing a nonvolatile semiconductor memory device according to the present invention having any one of the above-described features, wherein the insulating layer constitutes the insulating layer. An insulating material deposition step for depositing a material; and a semiconductor material deposition step for depositing a semiconductor material constituting the semiconductor layer, wherein the insulating material deposition step is performed first and last. A step of alternately performing the process and the semiconductor material deposition step a predetermined number of times to form a laminated film, and a first mask for forming the laminated film in a bowl shape is formed on the laminated film, Etching the laminated film to form the laminated structure portion, and a dielectric material deposition process for depositing a dielectric material constituting the charge storage layer on at least the side surface of the laminated structure portion A conductor material deposition step of depositing a conductor material constituting the first conductor layer so as to be in contact with at least the surface of the dielectric material and cover the stacked structure portion and the dielectric material; and the dielectric A second mask for processing the body material and the conductor material so as to have a certain width in the second direction, and processing the dielectric material and the conductor material to form the charge storage layer and the A charge storage layer / conductor layer forming step of forming a first conductor layer, and at least the first conductor layer of the semiconductor layer in which the side surface is not covered with the first conductor layer in the second direction. A source / drain region forming step is performed in which impurities are ion-implanted into both side portions at a predetermined implantation angle to form the source / drain region.

  According to the non-volatile semiconductor memory device of the present invention having the above characteristics, a charge storage having a stacked structure part in which insulating layers and semiconductor layers are alternately stored and having a certain width in the second direction on both side surfaces of the stacked structure part A source / drain region is formed on both side portions of the first conductor layer in the second direction, and the source / drain region, the charge storage layer, and the first layer are formed. Since a pair of memory cells is constituted by the conductor layer, the gate terminal, the source terminal and the drain terminal of the same memory cell are arranged on the same plane, and a simple process and a special process are required. Therefore, higher integration and higher density than those of the nonvolatile semiconductor memory device described in Patent Document 1 can be achieved.

Furthermore, according to the nonvolatile semiconductor memory device of the present invention having the above characteristics, the stacked structure portion is configured by alternately stacking insulating layers and semiconductor layers in a first direction perpendicular to the surface of the semiconductor substrate. Only by increasing the number of semiconductor layers to be stacked, high integration and high density can be easily achieved. Specifically, when the minimum processing dimension is F and the number of semiconductor layers is N, the minimum area of the memory cell is 2F × 2F ÷ (2 × N) = 2F ² / N. That is, every time the number N of semiconductor layers is increased, the minimum area of the memory cell is reduced, so that the capacity can be increased relatively easily and the cost can be reduced without depending on the microfabrication technique. Become.

In particular, according to the nonvolatile semiconductor memory device having the second feature, since it has a configuration including two or more semiconductor layers, four or more memory cells are formed in a range of 2F × 2F. The minimum area is substantially 2F × 2F ÷ 4 = F ² or less, and the minimum area of the memory cell is substantially 2F ² , which is higher than that of the nonvolatile semiconductor device described in Patent Document 1 above. In addition, the density can be increased.

  According to the nonvolatile semiconductor memory device of the fourth or fifth aspect of the present invention device, a plurality of charge storage layers and first conductor layers are separated in the second direction with respect to one stacked structure portion. Since a plurality of pairs of memory cells are formed in the second direction, a NAND type memory cell array can be configured with a simple configuration.

  According to the nonvolatile semiconductor memory device according to the sixth aspect of the present invention, the selection transistor is formed in the stacked structure portion. Therefore, the selection transistor can be highly integrated and highly integrated like the memory cell. Densification can be achieved. Further, in a NAND type memory cell array, a column having memory cells to be processed can be easily selected.

  Embodiments of a nonvolatile semiconductor memory device and a method for manufacturing the same according to the present invention (hereinafter, abbreviated as “the device of the present invention” and “the method of the present invention” where appropriate) will be described below with reference to the drawings.

<First Embodiment>
The apparatus of the present invention and the method of the present invention will be described with reference to FIGS.

  First, the configuration of the device 1 of the present invention will be described with reference to FIGS. Here, FIG. 1 (a) shows a schematic partial configuration example of the device 1 of the present invention, and FIG. 1 (b) shows YZ parallel to the Y direction and the Z direction including CC ′ in FIG. 1 (a). A cross-sectional view in plan is shown. FIG. 2 is an equivalent circuit diagram showing a schematic configuration example of the memory cell array of the device 1 of the present invention. FIG. 3 shows a partial schematic configuration of the side when the device 1 of the present invention is viewed from the Z direction. 1 to 9 do not necessarily have the same dimensional ratio as that of an actual apparatus for the sake of explanation.

  Hereinafter, the present embodiment will be described assuming that the device 1 of the present invention is a NAND flash memory.

  As shown in FIG. 1, the device 1 of the present invention has an insulating layer and a semiconductor layer perpendicular to the surface of the semiconductor substrate 10 such that the insulating layer is disposed on the lowermost and uppermost portions on the semiconductor substrate 10. It is configured to include a stacked structure portion L that is alternately stacked along (corresponding to the first direction), a charge storage layer CS having a charge holding function, and a first conductor layer CG1 that forms a gate terminal. ing. In the device 1 of the present invention, the laminated structure portion L is configured in a bowl shape with a pair of side surfaces opposed to each other, and the charge storage layer CS is in contact with both of the pair of side surfaces of the laminated structure portion L. In the Y direction (corresponding to the second direction) parallel to the surface of the semiconductor substrate 10, the first conductor layer CG 1 is in contact with the surface of the charge storage layer CS, and the stacked structure portion L The semiconductor layer is formed so as to cover the charge storage layer CS, and the semiconductor layer is not covered with the first conductor layer CG1 and the side surface of the semiconductor layer is at least in the Y direction of the first conductor layer CG1 in the inner region. A source / drain region A2 of a second conductivity type different from the first conductivity type of the semiconductor layer whose side surface is covered with the first conductor layer CG1 is formed on both side portions, and the source / drain region A2, the charge storage layer CS, By the first conductor layer CG1, the laminated structure portion L The side surfaces of the pair for one semiconductor layer, a pair of memory cells is configured.

  More specifically, as shown in FIG. 1, the stacked structure portion L is formed of an oxide film along the X direction (corresponding to the first direction) perpendicular to the surface of the semiconductor substrate 10 in this embodiment. It comprises three insulating layers LI1, LI2, and LI3 and two P-type semiconductor layers LS1 and LS2 made of a polycrystalline silicon film, and two pairs of memory cells each in the X direction. It is configured. In the present embodiment, for the sake of explanation, a case where the stacked structure portion L includes two semiconductor layers LS1 and LS2 and two pairs of memory cells are configured in the X direction will be described. The number of semiconductor layers is appropriately set according to the application and process of the device 1 of the present invention, and the number of insulating layers is set to be one more than the number of semiconductor layers.

  In addition, in the present embodiment, the laminated structure portion L is formed in a rectangular parallelepiped shape (a bowl shape) extending in the Y direction, and two surfaces perpendicular to the Z direction constitute a pair of opposite side surfaces. A memory cell is formed on the side surface. In the present embodiment, the case where the laminated structure portion L is formed in a rectangular parallelepiped shape will be described. For example, a surface perpendicular to the Y direction is a bottom surface, and a surface perpendicular to the Y direction is a trapezoidal columnar shape. Other shapes, such as forming, may be used.

  As shown in FIG. 1B, each of the semiconductor layers LS1 and LS2 of the stacked structure portion L is a semiconductor layer whose side surface is covered with a first conductive layer CG1 described later via a charge storage layer CS described later. A channel region A1 is formed in the inner region from the side surfaces of LS1 and LS2. Further, as shown in FIG. 1B, the semiconductor layers LS1 and LS2 are located on both sides of the channel region A1 and from the side surfaces of the semiconductor layers LS1 and LS2 whose side surfaces are not covered with the first conductor layer CG1. An N-type source / drain region A2 is formed in the region.

  Furthermore, as shown in FIG. 1, the inventive device 1 of the present embodiment includes a plurality of stacked structure portions L formed of two semiconductor layers LS <b> 1 and LS <b> 2. The laminated structure group arrange | positioned in a Z direction is provided so that the side surfaces may mutually oppose. Thereby, in the stacked structure portion L of the present embodiment, a plurality of pairs of memory cells, which will be described later, are configured in the Z direction. Here, in the present embodiment, a case will be described in which memory cells formed in one stacked structure portion L form one memory cell block, as shown in FIG. The configuration of the memory cell block is not limited to this. For example, the memory cells formed in the plurality of stacked structure portions L may form one memory cell block, or one stacked structure. A configuration may be adopted in which a plurality of memory cell blocks are set in the part L.

  In this embodiment, the charge storage layer CS is composed of an ONO film CS ′ (corresponding to a second stacked film formed of one second unit stacked film) made of an oxide film, a nitride film, and an oxide film. In the present embodiment, since the charge storage layer CS is formed by the ONO film CS ′ having a MONOS structure that traps charges in the trap order in which the charges are scattered in the film, the charges cannot freely move in the charge storage layer CS. As a result, the memory cells adjacent in the X direction and the Z direction are electrically insulated. For this reason, as shown in FIG. 1, it is not necessary to insulate the charge storage layer CS between the memory cells, and the charge storage layer CS can be easily formed.

  As shown in FIG. 1, in this embodiment, the charge storage layer CS has a width of the minimum processing dimension F in the Y direction, and is separated in the Y direction over a plurality of stacked structure portions L constituting the stacked structure group. A plurality are formed. In the present embodiment, as shown in FIG. 2, 16 charge storage layers CS are separately formed in the Y direction for one stacked structure portion L.

  As shown in FIG. 1, in the present embodiment, the first conductor layer CG1 is formed so as to be in contact with the surface of the charge storage layer CS and cover the entire top surface of the charge storage layer CS. Function as. Like the charge storage layer CS, the first conductor layer CG1 of the device 1 of the present invention has a width of the minimum processing dimension F in the Y direction and extends over the plurality of stacked structure portions L constituting the stacked structure group. A plurality are formed separately in the direction. In the present embodiment, as in the charge storage layer CS, the 16 first conductor layers CG1 are formed separately in the Y direction.

  As described above, by forming the stacked structure portion L, the charge storage layer CS, and the first conductor layer CG1, a pair of memory cells in one semiconductor layer of the stacked structure portion L are arranged in the Y direction. There are 16 sets. In addition, since two stacked structure portions L1 and L2 are provided, two pairs of memory cells are configured in the Z direction.

<Selection transistor>
As shown in FIGS. 1 and 2, the inventive device 1 of the present embodiment is configured such that the stacked structure portions L <b> 1 and L <b> 2 further include a plurality of a pair of selection transistors on a pair of side surfaces.

  More specifically, the stacked structure portions L1 and L2 of the present embodiment include a second conductor layer CG2 formed so as to be in contact with both side surfaces and have a certain width in the Y direction. Here, the width in the Y direction of the second conductor layer CG2 is the minimum processing dimension F as in the first conductor layer CG1. Further, a plurality of second conductor layers CG2 of the present embodiment are formed separately in the Y direction with respect to the two stacked structure portions L1 and L2. Note that the configuration of the selection transistor of the present embodiment is the same as the configuration of the memory cell described above, and includes a charge storage layer CS on the semiconductor substrate 10 side of the second conductor layer CG2.

  As shown in FIG. 1B, each of the semiconductor layers LS1 and LS2 of the stacked structure portions L1 and L2 has a channel in an internal region of the semiconductor layers LS1 and LS2 whose side surfaces are covered with the second conductor layer CG2. A region A1 is formed, and in the inner regions of the semiconductor layers LS1 and LS2 whose side surfaces are not covered by the first conductor layer CG1 or the second conductor layer CG2, both sides in the Y direction of the second conductor layer CG2 are formed. N-type source / drain regions A2 are formed. Then, the source / drain region A2 on both sides in the Y direction of the second conductor layer CG2 and the second conductor layer CG2 form a pair of side surfaces of the stacked structure portions L1 and L2 with respect to one semiconductor layer. A pair of selection transistors is configured.

<Circuit configuration>
Subsequently, the connection configuration of the memory cell and the select transistor of the device 1 of the present invention will be described with reference to FIGS. In the present embodiment, for the sake of simplicity, a case where two laminated structures L are formed will be described.

  As described above, the device 1 of the present invention selects a plurality of memory cells, a selection transistor for selecting a memory cell to be processed, and a memory cell to be processed as shown in FIGS. The control line is configured.

  As described above, the inventive device 1 of the present embodiment includes two stacked structure portions L1 and L2 as shown in FIG. 2, and one memory cell is formed in one stacked structure portion L. Configure the block. As shown in FIG. 1, the device 1 of the present invention is classified into memory cell units U in which each of the memory cells is set according to the side surface of the stacked structure portion L and according to the semiconductor layers LS1 and LS2, and the same memory cell unit U Are connected in series by connecting the source / drain regions A2 adjacent to each other in the Y direction.

  Here, in the present embodiment, as described above, since one stacked structure portion L includes two semiconductor layers LS1 and LS2, four memory cell units U11 to U14 are provided for each stacked structure portion L. Is set. The semiconductor layer LS1 is set so that memory cell units U11 and U14 (not shown) are paired, and the semiconductor layer LS2 is set so that memory cell units U12 and U13 (not shown) are paired. Has been. The memory cell units U11 and U12 and the memory cell units U13 and U14 are electrically insulated by the insulator layer LI2, and the memory cell units U12 and U13 are electrically insulated by the insulator layer LI3. Is electrically insulated. In the present embodiment, as described above, the stacked structure portion L includes 16 pairs of memory cells in the Y direction, and one memory cell unit U includes 16 memory cells CT0k to CT15k ( k = 1 to the number of memory cell units 4). Further, the gate terminals (first conductor layer CG1) of the memory cells CT0k to CT15k are respectively connected to the corresponding word lines WL0 to WL15.

  In the device 1 of the present invention, as shown in FIG. 1, each of the selection transistors is classified into a selection transistor group set according to the side surface of the stacked structure portion L and according to the semiconductor transmission, and the selection transistor constituting the same selection transistor group Are connected in series by connecting the source / drain regions A2 adjacent to each other in the Y direction. The selection transistor group includes N + 2 selection transistors, where N is the number of semiconductor layers in each stacked structure portion L. Here, in this embodiment, since the number of semiconductor layers is two, the number of selection transistors constituting each selection transistor group is 2 + 2 = 4.

  Furthermore, the device 1 of the present invention includes a pair of first selection control lines for selecting one of the side surfaces of the stacked structure portion L on which the memory cell unit U to be selected is formed, and a memory cell unit U to be selected. In order to select the formed semiconductor layer, N second selection control lines configured separately for the semiconductor layers LS1 and LS2 are provided.

  As shown in FIGS. 1 and 2, the device 1 of the present invention has a memory cell unit U and a select transistor group formed in the same semiconductor layer on the same side surface, and connects the source / drain regions A2 adjacent to each other in the Y direction. They are connected in series. Further, the selection transistor group formed in the same stacked structure portion L has a selection transistor that constitutes the selection transistor group in which the end portion not connected to the memory cell unit U by the source / drain region A2 is connected to the common bit line. Of the two selection transistors, the second selection control line SGj (j = 3) corresponding to the first selection control line SGi (i = 1, 2) corresponding to the gate terminal of the two selection transistors. To N + 2).

  More specifically, the gate terminals of the select transistors ST11 to ST14 for selecting the side surface on which the memory cell unit U11 and the memory cell unit U12 of the stacked structure portion L1 shown in FIG. The gate terminals of the selection transistors ST21 to ST24 that are connected to SG1 and select other side surfaces are connected to the first selection control line SG2. In addition, the gate terminals of the selection transistors ST31 to ST34 for selecting the memory cells formed in the semiconductor layer LS2 are connected to the second selection control line SG3, so that the memory cells formed in the semiconductor layer LS1 are selected. The gate terminals of the selection transistors ST41 to ST44 are connected to the second selection control line SG4, respectively.

  In FIG. 2, selection transistors ST11, ST12, ST23, ST24, ST32, ST33, ST41, ST44 indicated by broken-line circles are normally on transistors, and other selection transistors ST01-04, ST13, ST14. , ST21, ST22, ST31, ST34, ST42, ST43 are normally-off transistors. In FIG. 2, the configuration of the memory cell block MB2 is the same as the configuration of the memory cell block MB1. Note that the selection transistor indicated by a broken-line circle may be a normally-off transistor, and the other selection transistors may be normally-on transistors.

  Note that the normally-on type selection transistor is turned on regardless of whether the voltage of the selection control line connected to the gate terminal (the gate voltage of the selection transistor) is in a selected state or a non-selected state. A normally-off type select transistor is turned on when the voltage of the selection control line connected to the gate terminal is in the selected state, and is selected when the voltage of the selection control line connected to the gate terminal is not selected. It will be in an off state.

  With this configuration, the memory cell unit U including the memory cell to be processed can be selected by appropriately selecting the first selection control lines SG1 and SG2 and the second selection control lines SG3 and SG4. By appropriately selecting the word lines WL0 to WL15, the selected memory cell to be processed in the memory cell unit U selected by the first selection control lines SG1 and SG2 and the second selection control lines SG3 and SG4 is appropriately selected. You can choose.

  Specifically, for example, when selecting the memory cell unit U11, by selecting the first selection control line SG2 and the second selection control line SG3, the selection transistors ST21 and ST31 which are normally-off transistors are turned on. Put it in a state. The selection transistor ST11, which is a normally-on type transistor, is turned on when the first selection control line SG1 is not selected, and the selection transistor ST41 is turned on when the second selection control line SG4 is not selected. The memory cell unit U12 is not selected because the selection transistor ST42, the memory cell unit U13, the selection transistors ST13 and ST43, and the memory cell unit U14, the selection transistor ST14, are off. Thereby, only the memory cell unit U11 can be selected.

  Similarly, when selecting the memory cell unit U12, the first control line SG2 and the second control line SG4 are selected. When selecting the memory cell unit U13, the first control line SG1 and the second control line SG4 are stored in the memory. When selecting the cell unit U14, the first control line SG1 and the second control line SG3 are selected.

  Further, in the present embodiment, as shown in FIG. 2, each of the stacked structure portions L1 and L2 includes a select transistor ST0k (1 to 4) set for each stacked structure portion L, and the memory cell. The source / drain region A2 not connected to the selection transistor group of the unit U0k and the source / drain region A2 of the selection transistor ST0k adjacent in the Y direction are connected and connected in series. The source / drain region A2 of the selection transistor ST0k that is not connected to the memory cell unit U0k is connected to a common source line SL in the memory cell array.

<Production method>
Next, the method of the present invention will be described with reference to FIGS. 4 to 7 partially show a cross section perpendicular to the surface of the semiconductor substrate 10 of the device 1 of the present invention in each step of the method of the present invention. More specifically, FIG. 4 (a), FIG. 5 (a), FIG. 6 (a) and FIG. 7 (a) show a vertical cross section including AA ′ shown in FIG. 5 (b), FIG. 6 (b), and FIG. 7 (b) are vertical cross sections including BB ′ shown in FIG. 1, and FIG. 4 (c), FIG. 5 (c), FIG. ) And FIG. 7C are vertical cross sections including CC ′ shown in FIG. 1, and FIGS. 4D, 5D, 6D, and 7D are FIGS. The vertical cross sections including DD ′ shown in FIG.

  In the method of the present invention, first, a laminated film forming step for forming the laminated film L ′ is performed. Specifically, the laminated film forming step includes an insulating material deposition step for depositing an insulating material constituting the insulating layers LI1, LI2, and LI3, and a semiconductor material deposition step for depositing a semiconductor material constituting the semiconductor layers LS1 and LS2. The insulating material deposition step and the semiconductor material deposition step are alternately performed a predetermined number of times so that the insulating material deposition step is performed first and last.

  Specifically, here, the laminated film L ′ is formed by executing three insulating material deposition steps and two semiconductor material deposition steps. In each insulating material deposition step, for example, oxide films LI1 ', LI2', and LI3 'having a film thickness of 10 nm to 50 nm are formed by a CVD method (Chemical VA por Deposition). The film thicknesses of the oxide films LI1 ′, LI2 ′, LI3 ′ (insulating layers LI1, LI2, LI3) depend on the process, transistor characteristics, etc., between the semiconductor substrate 10 and the semiconductor layer LS1, and between the semiconductor layers LS1 and LS1. It is set so that the semiconductor layer LS2 and the semiconductor layer LS2 and the charge storage layer CS are well insulated from each other.

In each semiconductor material deposition step, for example, a polycrystalline silicon film having a film thickness of 10 nm to 100 nm is formed on the oxide film LIh ′ (h = 1, 2) formed in the insulating material deposition step performed immediately before by the CVD method. LSh ′ (h = 1, 2) is formed. It should be noted that the polycrystalline silicon films LS1 ′ and LS2 ′ (semiconductor layers LS1 and LS2) are formed so that desired transistor characteristics can be obtained in consideration of the film thickness being the channel width of the memory cell and the select transistor. Set to. Further, the semiconductor material deposition step may be configured to epitaxially grow silicon to form the polycrystalline silicon film LSh ′. Subsequently, after the formation of the polycrystalline silicon film LSh ′, a P-type impurity such as boron is ion-implanted into the entire surface of the polycrystalline silicon film LSh ′. Here, the dose amount of the P-type impurity is adjusted to be about 1 × 10 ¹⁶ cm ³ to about 1 × 10 ¹⁹ cm ³ .

  Subsequently, as shown in FIG. 4, a first mask R1 for forming the laminated film L ′ in a bowl shape is formed on the laminated film L ′, and the laminated film L ′ is etched as shown in FIG. Then, a laminated structure portion forming step for forming the laminated structure portion L is executed. In the present embodiment, the selection transistor forming step for making the selection transistor a normally-on type or a normally-off type is executed together with the stacked structure portion forming step.

  Specifically, first, a nitride film having a film thickness of about 50 nm is formed on the entire surface of the laminated film L ′, the nitride film is patterned by photolithography, and a first mask forming process for forming the first mask R1 is performed. . Subsequently, the insulating film LI3 'and the polycrystalline silicon film LS2' in the stacked film L 'are etched using the first mask R1 formed of a nitride film.

  Subsequently, as shown in FIG. 2, select transistors ST32 and ST33 connected to the second selection control line SG3 for selecting a memory cell formed in the upper semiconductor layer LS2 of the stacked structure portion L1 are normally on. A first process is performed for the purpose.

  More specifically, a region corresponding to the side surface of the stacked structure portion L1 where the selection transistors ST32 and ST33 are formed by photolithography, that is, the side surface of the polycrystalline silicon film LS2 ′ constituting the stacked structure portion L1 is selected. A photoresist having an opening for implanting ions of N-type impurities is formed on both side surface portions (first partial regions) where the transistors ST32 and ST33 are formed. Then, an N-type impurity such as phosphorus is ion-implanted obliquely from above into the first partial region of the polycrystalline silicon film LS2 'constituting the stacked structure portion L1, and the photoresist is removed. As a result, the select transistors ST32 and ST33 are normally on.

  Subsequently, the second process for making the select transistors ST42 and ST43 connected to the second selection control line SG4 for selecting the memory cells formed in the lower semiconductor layer LS1 of the stacked structure portion L1 be normally off type I do.

  In more detail, by photolithography, P on both side surface portions (second partial regions) where the select transistors ST42 and ST43 are formed on both side surfaces of the polycrystalline silicon film LS2 ′ constituting the stacked structure portion L1. A photoresist having an opening for ion implantation of type impurities is formed. Then, a P-type impurity such as boron is ion-implanted from obliquely above into the second partial region of the polycrystalline silicon film LS2 'constituting the stacked structure portion L1, and the photoresist is removed. As a result, the select transistors ST42 and ST43 are normally off. In the present embodiment, since the N-type impurity is ion-implanted into the second partial region in the third process described later, the influence of the N-type impurity can be offset. The implantation amount of the P-type impurity is set to the extent.

  Subsequently, using the first mask R1 formed by the first mask formation process, the insulating film LI2 ′, the polycrystalline silicon film LS1 ′, and the insulating film LI1 ′ in the stacked film L ′ are etched, and the first mask R1 (nitriding) The membrane) is removed with phosphoric acid. Thereby, as shown in FIG. 5, the laminated structure part L is formed.

  Subsequently, as shown in FIG. 2, selection transistors ST11 and ST12 connected to the first selection control line SG1 for selecting the side surface of the stacked structure portion L1, and ST41 connected to the second selection control line SG4 are connected. A third process is performed to obtain a normally-on type.

  More specifically, regions corresponding to the side surfaces of the stacked structure portion L1 where the select transistors ST11 to ST14 and ST41 to ST44 are formed by photolithography, that is, the polycrystalline silicon films LS1 ′ and LS2 constituting the stacked structure portion L1. A photoresist having an opening for ion implantation of N-type impurities is formed on both side surface portions (third partial regions) where the select transistors ST11 to ST14 and ST41 to ST44 are formed. Then, N-type impurities such as phosphorus are ion-implanted from the upper side on the side where the select transistors ST11, ST12, ST41, and ST42 are formed on the side surface perpendicular to the Z direction of the stacked structure portion L1, and the photoresist is removed. To do. As a result, the N-type impurity is ion-implanted only to the side surface where the selection transistors ST11, ST12, ST41, and ST42 are formed, and the selection transistors ST11, ST12, and ST41 are normally on. As described above, the selection transistor ST42 adjusts the implantation amount of the P-type impurity to such an extent that the influence of the N-type impurity ion-implanted in the third processing can be offset in the second processing. Therefore, it is maintained in a normally-off type.

  Subsequently, as shown in FIG. 2, selection transistors ST23 and ST24 connected to the first selection control line SG2 for selecting the side surface of the stacked structure portion L1, and ST44 connected to the second selection control line SG4 are added. A fourth process is performed to obtain a normally-on type. By performing the fourth process of the selection transistor forming step, all the selection transistors ST11 to 14, ST21 to 24, ST31 to 34, and ST41 to 44 of the stacked structure portion L1 are made to have a desired normally-on type or normally. Can be set to off-type.

  More specifically, regions corresponding to the side surfaces of the stacked structure portion L1 where the select transistors ST11 to ST14 and ST41 to ST44 are formed by photolithography, that is, the polycrystalline silicon films LS1 ′ and LS2 constituting the stacked structure portion L1. A photoresist having an opening for ion-implanting N-type impurities is formed on both side surface portions (fourth partial regions) where the select transistors ST21 to ST24 and ST41 to ST44 are formed. Then, N-type impurities such as phosphorus are ion-implanted from the upper side on the side where the select transistors ST23, ST24, ST43, and ST44 are formed on the side surface perpendicular to the Z direction of the stacked structure portion L1, and the photoresist is removed. To do. As a result, the N-type impurity is ion-implanted only into the side surface on which the select transistors ST23, ST24, ST43, and ST44 are formed, and the select transistors ST23, ST24, and ST44 are normally on. As described above, the selection transistor ST43 adjusts the implantation amount of the P-type impurity in the second process so that the influence of the N-type impurity ion-implanted in the fourth process can be offset. Therefore, it is maintained in a normally-off type.

  Subsequently, as shown in FIG. 6, a dielectric material deposition step is performed in which a dielectric material constituting the charge storage layer CS is deposited at least on the side surface of the multilayer structure portion L1. Note that the charge storage layer CS of the present embodiment is composed of the ONO film CS ′, and the ONO film CS ′ is formed on the entire surface of both side surfaces of both of the two laminated structures L1 and L2.

  Further, as shown in FIG. 6, the conductor material constituting the first conductor layer CG1 so as to be in contact with at least the surface of the dielectric material (ONO film CS ′) and cover the laminated structure portion L and the ONO film CS ′. Conductor material deposition step of depositing CG ′ is performed. Here, in the present embodiment, the same conductor material CG ′ is used to form the second conductor layer CG2 constituting the gate terminal of the selection transistor, and the entire surface of the two stacked structure portions L1 and L2 is formed. A conductive material CG ′ is deposited on the entire surface of the charge storage layer CS formed in (1) to form a polycrystalline silicon film CG ′.

  Subsequently, the dielectric material and the conductor material CG ′ are processed by using a second mask (not shown) for processing the dielectric material and the conductor material CG ′ so as to have a certain width in the Y direction. Then, a charge storage layer / conductor layer forming step for forming the charge storage layer CS and the first conductor layer CG1 is executed. Specifically, the second mask is made of a nitride film, and the first conductor layer CG1 and the charge storage layer CS constituting the gate terminal of the memory cell and the second conductor constituting the gate terminal of the selection transistor. A pattern capable of forming both of the layers CG2 is provided. The first conductor layer CG1, the charge storage layer CS, and the second conductor layer CG2 are formed by photolithography by etching the dielectric material and the conductor material CG ′ using the second mask, and the second mask. Are removed with phosphoric acid.

  Subsequently, as shown in FIG. 7, at least a portion of the semiconductor layers LS1 and LS2 whose side surfaces are not covered with the first conductor layer CG1 and at both sides in the Y direction of the first conductor layer CG1 are N-type at a predetermined implantation angle. A source / drain region forming step of forming the source / drain region A2 is performed by ion implantation of the impurity. In the present embodiment, the source / drain region A2 is further formed by ion-implanting N-type impurities at the same implantation angle as that of the first conductor layer CG1 on both sides in the Y direction of the second conductor layer CG2.

In the memory cell manufactured by the method of the present invention of this embodiment, two pairs of memory cells can be formed in an area of 2F × 2F as shown in FIG. Therefore, the minimum area of the memory cell of the device of the present invention is substantially 2F × 2F ÷ (2 × 2) = F ² , and the minimum area 2F ² of the memory cell in the NAND flash memory described in Patent Document 1 Compared to the above, double integration and high density can be achieved.

Note that, in the method of the present invention and the device 1 of the present invention, the number of semiconductor layers in the stacked structure portion L can be increased depending on the restrictions of the process and the like. When the number of semiconductor layers is N, the minimum area of the memory cell is substantially 2F × 2F ÷ (2 × N) = 2F ² / N, and high integration and high density can be achieved.

<Another embodiment>
<1> In the first embodiment, the case where the semiconductor layers LS1 and LS2 have the P-type conductivity and the source / drain region A2 has the N-type conductivity has been described. However, the semiconductor layers LS1 and LS2 have the N-type conductivity type. The conductivity type of the source / drain region A2 may be P-type.

  <2> In the first embodiment, the case where the device 1 of the present invention includes the two laminated structures L1 and L2 has been described. However, the present invention is not limited to this. The number of the laminated structure portions L is appropriately set according to the use and process of the device 1 of the present invention.

  In the first embodiment, the case where the number of the semiconductor layers constituting the stacked structure portion L is the same in all the stacked structure portions L has been described. However, the present invention is not limited to this. It is also possible to adopt a configuration including the laminated structure portion L.

  <3> In the first embodiment, the laminated structure portion L is configured to include the two semiconductor layers LS1 and LS2, and the selection transistor group includes four selection transistors. However, it is not limited to this. The number of the semiconductor layers of the stacked structure portion L is appropriately set according to the application and process of the device 1 of the present invention, and the number of select transistors constituting the select transistor group is the number of the semiconductor layers forming the stacked structure portion L Set according to the number of layers. For example, as shown in FIG. 9 or FIG. 10, when the stacked structure portion L is configured to include four semiconductor layers, the selection transistor group may be configured to include six selection transistors. good.

  In the first embodiment, the case where the number of semiconductor layers of the stacked structure portion L is N is described as including two first selection control lines and N second selection control lines. There is no limit to this. The configuration of the selection control line is set according to the configuration and arrangement of the selection transistor.

  <4> In the first embodiment, the case where the memory cell unit U is composed of 16 memory cells has been described. However, the present invention is not limited to this. The number of memory cells in the memory cell unit U is appropriately set according to the application, process, etc. of the device 1 of the present invention.

  In the first embodiment, the case where the number of memory cells constituting the memory cell unit U is the same in all the stacked structure portions L has been described. However, the present invention is not limited to this. It is also possible to adopt a configuration including the laminated structure portion L.

  <5> In the first embodiment, the charge storage layer CS is configured by an ONO film CS ′ (second stacked film formed of one second unit stacked film) including an oxide film, a nitride film, and an oxide film. However, the present invention is not limited to this. For example, it may be a second laminated film constituted by a plurality of second unit laminated films, or an oxide film and a nitride film are used as the first unit laminated film, and constituted by one or a plurality of first unit laminated films. You may be comprised with the 1st laminated film.

The perspective view which shows the schematic partial structural example of the non-volatile semiconductor memory device which concerns on this invention Equivalent circuit diagram showing a schematic connection configuration example of a memory cell and a select transistor of a nonvolatile semiconductor memory device according to the present invention 1 is a partial side view showing a schematic partial configuration example of a nonvolatile semiconductor memory device according to the present invention. The fragmentary sectional view which shows the schematic partial structure example of the non-volatile semiconductor memory device in each process of the manufacturing method of the non-volatile semiconductor memory device concerning this invention The fragmentary sectional view which shows the schematic partial structure example of the non-volatile semiconductor memory device in each process of the manufacturing method of the non-volatile semiconductor memory device concerning this invention The fragmentary sectional view which shows the schematic partial structure example of the non-volatile semiconductor memory device in each process of the manufacturing method of the non-volatile semiconductor memory device concerning this invention The fragmentary sectional view which shows the schematic partial structure example of the non-volatile semiconductor memory device in each process of the manufacturing method of the non-volatile semiconductor memory device concerning this invention The fragmentary sectional view which shows the schematic partial structure example of the non-volatile semiconductor memory device in another embodiment of the manufacturing method of the non-volatile semiconductor memory device which concerns on this invention FIG. 7 is an equivalent circuit diagram showing a connection configuration example of selected memory cells in another embodiment of the nonvolatile semiconductor memory device according to the present invention. FIG. 7 is an equivalent circuit diagram showing a connection configuration example of selected memory cells in another embodiment of the nonvolatile semiconductor memory device according to the present invention. The perspective view which shows the schematic example of a partial structure of the non-volatile semiconductor memory device which concerns on a prior art

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Nonvolatile semiconductor memory device 10 according to the present invention Semiconductor substrate A1 Channel region A2 Source / drain region CG1 First conductor layer (control gate)
CG2 Second conductor layer (control gate)
CG 'Conductor material (polycrystalline silicon film)
CS charge storage layer CS ′ ONO film CT memory cell L stacked structure portion L1 stacked structure portion L2 stacked structure portion L ′ stacked film LI1 insulating layer LS1 semiconductor layer LI2 insulating layer LS2 semiconductor layer LI3 insulating layer LI1 ′ oxide film LS1 ′ polycrystal Silicon film LI2 ′ oxide film LS2 ′ polycrystalline silicon film LI3 ′ oxide film SL source line SG0 selection control line SG1 selection control line SG2 selection control line SG3 selection control line SG4 selection control line ST selection transistor U memory cell unit WL word line 100 Nonvolatile semiconductor memory device 101 according to prior art Insulating film 102 Charge holding portion (floating gate)
103 Source / drain region 104 Source / drain region

Claims (11)

A stacked structure part in which the insulating layer and the semiconductor layer are alternately stacked along a first direction perpendicular to the surface of the semiconductor substrate, such that the insulating layer is disposed on the lowermost part and the uppermost part on the semiconductor substrate; A charge storage layer having a charge holding function, and a first conductor layer constituting a gate terminal,
The laminated structure portion is configured in a bowl shape with a pair of side surfaces facing each other,
The charge storage layer is formed to be in contact with both of the pair of side surfaces of the stacked structure portion and to have a certain width in a second direction parallel to the surface of the semiconductor substrate in the side surface;
The first conductor layer is in contact with the surface of the charge storage layer and is formed so as to cover the stacked structure portion and the charge storage layer;
The semiconductor layer has at least both sides of the first conductor layer in the second direction in an inner region from the side surface of the semiconductor layer that is not covered with the first conductor layer. A source / drain region of a second conductivity type different from the first conductivity type of the semiconductor layer, wherein the side surface is covered with one conductor layer;
A pair of memory cells for one semiconductor layer is formed on the pair of side surfaces of the stacked structure portion by the source / drain region, the charge storage layer, and the first conductor layer. A non-volatile semiconductor memory device.   2. The nonvolatile semiconductor device according to claim 1, wherein the stacked structure portion includes two or more semiconductor layers, and the pair of memory cells includes a plurality of pairs in the first direction. Storage device. A laminated structure in which a plurality of the laminated structure portions are arranged in a third direction orthogonal to the first direction and the second direction so that each of the adjacent laminated structure portions has one side surface facing each other. With groups,
3. The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of sets of the pair of memory cells are configured in the third direction. A plurality of the charge storage layer and the first conductor layer are formed separately in the second direction with respect to one stacked structure portion;
3. The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of sets of the pair of memory cells are configured in the second direction. A laminated structure in which a plurality of the laminated structure portions are arranged in a third direction orthogonal to the first direction and the second direction so that each of the adjacent laminated structure portions has one side surface facing each other. With groups,
A plurality of the charge storage layers and the first conductor layers are formed separately in the second direction over the plurality of stacked structure portions constituting the stacked structure group,
3. The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of sets of the pair of memory cells are configured in the second direction and the third direction. 4. The second conductor layer formed so as to be in contact with both of the side surfaces of the multilayer structure portion and to have a certain width in the second direction,
The semiconductor layer is formed on both side portions of the second conductor layer in the second direction in the inner region of the semiconductor layer, the side surfaces of which are not covered with the first conductor layer or the second conductor layer. The source / drain region of the second conductivity type is formed;
The source / drain regions on both side portions of the second conductor layer in the second direction, and the second conductor layer, on one pair of the side surfaces of the stacked structure portion, with respect to one semiconductor layer, 6. The nonvolatile semiconductor memory device according to claim 4, wherein a pair of selection transistors is configured. A plurality of the second conductor layers are formed separately in the second direction with respect to one or a plurality of the stacked structure portions;
A plurality of sets of the pair of selection transistors in the second direction;
Each of the selection transistors is classified into a selection transistor group set for each side surface of the stacked structure portion and for each semiconductor layer, and each of the selection transistors constituting the same selection transistor group is arranged in the second direction. The adjacent source / drain regions are connected in series and connected in series,
Each of the memory cells is classified into a memory cell unit set for each side surface of the stacked structure portion and for each semiconductor layer, and each of the memory cells constituting the same memory cell unit is arranged in the second direction. The adjacent source / drain regions are connected in series and connected in series,
The memory cell unit and the selection transistor group formed in the same semiconductor layer on the same side surface are connected in series by connecting the source / drain regions adjacent to each other in the second direction. Item 7. The nonvolatile semiconductor memory device according to Item 6. The stacked structure group includes a plurality of the stacked structure portions having the same number of semiconductor layers,
The selection transistor group is composed of N + 2 selection transistors, where N is the number of the semiconductor layers in each of the stacked structure portions,
A pair of first selection control lines for selecting one of the side surfaces of the stacked structure portion on which the memory cell unit to be selected is formed;
N second selection control lines configured for each semiconductor layer to select the semiconductor layer in which the memory cell unit to be selected is formed, and
The selection transistor group formed in the same stacked structure portion is configured such that an end portion which is not connected to the memory cell unit by the source / drain region is connected to a common bit line, and constitutes the selection transistor group. Of the transistors, the gate terminals of two selection transistors are connected to the corresponding first selection control line, and the gate terminals of N selection transistors are connected to the corresponding second selection control line. The nonvolatile semiconductor memory device according to claim 7, wherein: Each of the selection transistors is a first selection transistor configured to be either a normally-off type or a normally-on type, and one of a second selection transistor of a type different from the first selection transistor. Consisting of
Among the selection transistors connected to the first selection control line, the selection transistor connected to the memory cell unit formed on the side surface of the stacked structure portion to be selected is configured by the first selection transistor, and the other The selection transistor is composed of the second selection transistor,
Among the selection transistors connected to the second selection control line, the selection transistor connected to the memory cell unit formed in the semiconductor layer to be selected is configured by the first selection transistor, and the other selection transistors 9. The nonvolatile semiconductor memory device according to claim 8, wherein a transistor is configured by the second selection transistor. In the stacked structure portion, the insulating layer is composed of an oxide film, the semiconductor layer is composed of a polycrystalline silicon film,
In the charge storage layer, an oxide film and a nitride film are used as a first unit laminated film, and a first laminated film including one or a plurality of first unit laminated films, or an oxide film, a nitride film, and an oxide film are formed as a second layer. The non-volatile device according to any one of claims 1 to 9, wherein the non-volatile layer is configured as one unit laminated film and one of a second laminated film constituted by one or a plurality of second unit laminated films. Semiconductor memory device. A method for manufacturing a nonvolatile semiconductor memory device according to claim 1,
An insulating material deposition step for depositing an insulating material constituting the insulating layer; and a semiconductor material deposition step for depositing a semiconductor material constituting the semiconductor layer, wherein the insulating material deposition step is executed first and last. As described above, the insulating material deposition step and the semiconductor material deposition step are alternately performed a predetermined number of times to form a laminated film forming step,
Forming a first mask for forming the laminated film in a bowl shape on the laminated film, etching the laminated film to form the laminated structure part; and
A dielectric material deposition step of depositing a dielectric material constituting the charge storage layer on at least the side surface of the multilayer structure; and
A conductor material deposition step of depositing a conductor material constituting the first conductor layer so as to be in contact with at least the surface of the dielectric material and cover the stacked structure portion and the dielectric material;
Using the second mask for processing the dielectric material and the conductive material so as to have a certain width in the second direction, the charge storage layer is processed by processing the dielectric material and the conductive material. And a charge storage layer / conductor layer forming step for forming the first conductor layer,
Impurities are ion-implanted at a predetermined implantation angle into at least both sides of the first conductor layer in the second direction of the semiconductor layer, the side surfaces of which are not covered with the first conductor layer, and the source drain And a step of forming a source / drain region for forming the region.

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