JP2009135417A - Method for manufacturing substrate for mounting semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a substrate for mounting a semiconductor element, by which a base material and a plating layer do not separate or the like during assembly steps and can extremely easily separated or the like after the completion of assembly. <P>SOLUTION: The method for manufacturing a substrate for mounting a semiconductor element includes: a step for forming a predetermined resist pattern by affixing resist to both the faces of the base material composed of a metallic thin film and using the resist formed on one of the faces as a masking for plating; a step for performing etching of a predetermined position on the base material which is exposed from the resist pattern; a step for forming a plating layer composed of at least three layers including lower, middle and upper layers on the etched base material; a step for separating the resist affixed to both faces of the base material; and a step for performing etching of the middle plating layer to make the middle plating layer narrower than the upper and lower plating layers. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a substrate for mounting a semiconductor element, and more specifically, in a method for manufacturing a substrate for mounting a semiconductor element in which a multilayer plating layer is formed on a base made of a thin metal plate. The present invention relates to a method for manufacturing a substrate for mounting a semiconductor element, which is excellent in adhesion between a material and a plating layer, and after the assembly is completed, the substrate and the plating layer can be peeled off very easily.

  As semiconductor devices have become smaller and thinner, the number of semiconductor devices having a connection portion (terminal portion) with the outside on the back surface of the sealing resin has increased. In such a semiconductor device, it is common to use a lead frame formed in a predetermined pattern by performing etching processing or press processing on a copper-based alloy or iron / nickel alloy for a pad portion and a terminal portion. . However, for such a lead frame, a metallic thin plate having a thickness of 0.125 to 0.20 mm is mainly used, which is one of the factors that hinder the thinning of the semiconductor device.

  Therefore, in recent years, a substrate for mounting a semiconductor element in which a plating layer having a thickness of 0.1 mm or less is formed on the surface of a base material made of a metal thin plate instead of the lead frame, and the plating layer is used as a pad portion or a terminal portion. Products that have been developed and that assemble semiconductor devices using the semiconductor element mounting substrate are on the market. As an example of a semiconductor mounting substrate for forming a pad portion or a terminal portion on a base material by this plating layer, a base material made of a metal material that can be etched in advance is selected, and a gold plating layer and a nickel plating layer are formed on the base material. A semiconductor element mounting substrate having a pad portion and a terminal portion formed of a gold plating layer is obtained, the semiconductor element is mounted on the pad portion, and the semiconductor element and the terminal portion are connected by wire bonding, and resin sealing is performed. A method of removing only the base material by etching after an assembly process such as the above has been proposed (for example, see Patent Document 1).

  Also, many proposals have been made for a semiconductor element mounting substrate having a connecting portion formed by plating on the back surface of the sealing resin by removing the metal thin plate as a base material from the resin sealing body. ing. However, in such a substrate for mounting semiconductor measures, the peelability between the metal thin plate as the base material and the generated plating layer is poor. For example, when a copper-based alloy is used as the base material, it may be easy depending on the mechanical means. Therefore, after the resin sealing, it is necessary to perform an etching process as a means for removing the copper-based alloy, which is a metal thin plate, which complicates the manufacturing process and is not economical. In addition, there is a problem that the formed pad portion and terminal portion remain on the side of the metal thin plate that has been peeled off and removed, and in order to improve this peelability, the surface of the metal thin plate is preliminarily subjected to blast treatment. There has also been proposed a method of performing a plating process after providing (see, for example, Patent Document 2). However, the surface treatment of providing unevenness on the metallic thin plate causes a new problem that the substrate is warped, and the problem that the manufacturing process becomes more complicated due to the addition of the surface treatment step and the peeling treatment step remains. It had been.

On the other hand, when stainless steel is used as the metal thin plate as the base material and the stainless steel thin plate is peeled off after resin sealing, the plating layer forming the terminal portion generally has poor adhesion to the stainless steel. In addition, there is a problem that the sealing resin wraps between the stainless steel thin plate and the plating layer, and after the resin sealing, the plating layer that becomes the pad portion and the terminal portion adheres to the sealing resin. However, it is important to prevent the floating state or peeling from the sealing resin, but as a means to improve the adhesion between the sealing resin and the plating layer, the periphery of the upper end of the plating layer is bowl-shaped. (See, for example, Patent Document 3). However, according to this method, since the plating layer is formed by overhanging more than the height of the resist, it is not easy to control the length for projecting in a bowl shape, and there is a possibility that it is connected to the adjacent terminal portion. As other means for improving the adhesion between the sealing resin and the generated plating layer, a semiconductor device using a substrate having a cross-sectional shape of the terminal portion and a manufacturing method thereof are disclosed (for example, see Patent Document 4). ) More specifically, by forming a conductive part in a predetermined pattern on both surfaces of the metal foil, and pasting it on the base material via an adhesive layer, the metal foil is etched using the conductive part as an etching mask, This is a method of manufacturing a semiconductor element mounting substrate having a cross-sectional shape of an E-shape, but a new manufacturing process is added. As a result, the manufacturing process becomes complicated, and there remains a problem in terms of cost. .
JP 59-208756 A Japanese Patent Laid-Open No. 10-50885 JP 2003-174121 A JP 2004-253694 A

  Thus, in the above-mentioned semiconductor element mounting substrate obtained by using a metal thin plate as a base material and removing it by peeling off the metal thin plate after resin sealing, the plating layer is a metal thin plate during the assembly process. In addition, it is necessary that the sealing resin is in close contact between the metal thin plate and the plating layer, and after the metal thin plate is peeled off, the metal thin plate is peeled off. Therefore, it is important to prevent the plating layer that becomes the pad portion and the terminal portion from remaining, and the state where the plating layer is in close contact with the sealing resin and is not lifted or peeled off. That is, the metal thin plate and the plating layer are in close contact until the assembly process is completed, and when the metal thin plate is peeled off, the metal thin plate and the plating layer are required to have a contradictory function. However, the present invention is a method for manufacturing a substrate for mounting a semiconductor element used in a method for peeling off a base material, and aims to solve the above-mentioned problems together. The adhesion between the base material and the plating layer is maintained without the separation of the material and the plating layer, and the sealing resin does not wrap around between the base material and the plating layer. For semiconductor device mounting, which peels off very easily and does not leave a plating layer on the removed substrate side, and does not come into close contact with the sealing resin and does not float or peel off from the sealing resin Providing a method for manufacturing a substrate A.

  The method for manufacturing a semiconductor element mounting substrate according to the present invention for solving the above-described problem is to apply a resist on both surfaces of a base material made of a thin metal plate, and use the resist on one surface as a mask for plating. A step of forming a predetermined resist pattern, a step of etching a predetermined position on the base material exposed from the resist pattern, a lower side, an intermediate side and an upper side on the base material subjected to the etching processing It comprises a step of forming a plating layer comprising three or more layers, a step of peeling off the resist stuck on both surfaces of the base material, and a step of etching the intermediate plating layer to make it narrower than the upper and lower plating layers. The manufacturing method of the substrate for mounting a semiconductor element having the characteristic constituent requirements is as a gist.

  In the method for manufacturing a substrate for mounting a semiconductor element according to the present invention, it is preferable that the metal thin plate is stainless steel having a plate thickness of 0.05 to 0.5 mm.

  Furthermore, in the method for manufacturing a semiconductor element mounting substrate according to the present invention, the etching process performed at a predetermined position on the base material is within a range of a depth of 3 to 10 μm. is there.

  The method for manufacturing a substrate for mounting a semiconductor element according to the present invention also includes first forming a gold plating layer using a strong acid bath instead of the etching process performed at a predetermined position on the base material. It is a feature.

  In the method for manufacturing a substrate for mounting a semiconductor element according to the present invention, the intermediate plating layer is further etched in a range of 2 to 10 μm on one side from the side surface to the central side, and the plating layer having a lower area is provided. In addition, it is characterized by being narrowed compared to the respective areas of the upper plating layer.

  In the method for manufacturing a semiconductor element mounting substrate according to the present invention, the lower plating layer is gold and / or nickel plating, the intermediate plating layer is copper and / or nickel plating, the upper plating layer is nickel, It is characterized by being gold, silver, palladium and alloy plating thereof.

  Furthermore, in the method for manufacturing a semiconductor element mounting substrate according to the present invention, the upper plating layer is formed to have a thickness of 5 μm or more.

  In addition, the intermediate plating layer includes a plating layer that is not etched from the side surface toward the center, and thus has a convex portion in the intermediate plating layer that is narrower than the upper and lower plating layers.

  When the semiconductor device is assembled using the semiconductor element mounting substrate manufactured by the manufacturing method of the present invention, the plating layer generated on the substrate has an upper plating layer having a thickness of 5 μm or more and an intermediate layer. Since the plating layer is formed narrower than the upper and lower plating layers, the sealing resin and the plating layer exhibit excellent adhesion, and after the substrate is peeled off, the plating layer floats from the sealing resin. Plating does not occur, and the plating layer initially formed on the base material is a gold plating layer using a strong acid bath instead of a commonly used weak acid to neutral bath. As a result, the adhesion to the substrate was improved, and the sealing resin did not wrap around between the base material and the plating layer. In addition, the etching process is performed at a depth of 3 to 10 μm at a predetermined position on the base material, and the plating layer is formed on the portion, thereby preventing the sealing resin from flowing between the base material and the plating layer. It is further preventing. As described above, the substrate for mounting a semiconductor element obtained by the method of the present invention has excellent adhesion between the generated plating layer and the sealing resin, although the manufacturing method is a simple process. The plating layer that becomes the pad portion and the terminal portion does not remain on the side of the base material that has been peeled off after the peeling, and exhibits an extremely excellent effect as a semiconductor element mounting substrate.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings and embodiments. However, the present invention is not limited thereto, and can be freely modified within the scope of the gist of the present invention.
FIG. 1 is a semiconductor element mounting substrate obtained by an embodiment according to the present invention, in which (a) is a cross-sectional view of an essential part showing a state in which three plating layers are formed on the substrate. Is a main part sectional view showing a state in which five plating layers are formed, (c) is a main part sectional view in a state in which seven plating layers are formed, and the intermediate plating layer is composed of a plurality of plating layers having convex portions. It is.
2A and 2B show a state in which a plurality of sets of plating layers are formed on the substrate, wherein FIG. 2A is a plan view of an essential part thereof, and FIG. 2B is a partially enlarged plan view of FIG.
FIG. 3 is a cross-sectional view for explaining the means for forming three plating layers on the substrate in the method for manufacturing a semiconductor element mounting substrate according to the present invention. FIG. 3A shows a pattern formed from a resist. The state, (b) is the state where the substrate is etched, (c) is the state where the three plating layers are applied on the substrate, (d) is the state where the resist pattern is peeled off, (e) is the intermediate state It is principal part sectional drawing which respectively shows the state which etched the plating layer of.
FIG. 4 shows the state of the substrate after resin sealing in the method for manufacturing a semiconductor element mounting substrate according to the present invention. (A) is the substrate obtained in Example 1, and (b) is Example 2 in the same manner. It is a principal part expanded sectional view which shows the board | substrate obtained by these.
FIG. 5 is a schematic cross-sectional view for explaining the plating layer of the present invention in the method for manufacturing a semiconductor element mounting substrate according to the present invention, (a) is a schematic cross-sectional view of a five-layer structure of three types of plating layers, ) Is a schematic cross-sectional view of a seven-layer structure with three types of plating layers.

  A preferred embodiment of a method for producing a substrate for mounting a semiconductor element according to the present invention will be described in the order of steps. As a substrate made of a thin metal plate, a plate thickness is 0.05 to 0.5 mm, preferably 0.1. A plate material made of ~ 0.3 mm stainless steel (SUS430) is used as a base material, a resist made of a photosensitive dry film is pasted on both surfaces of the base material, and then the resist on one side is used as a plating mask. To produce a predetermined pattern on the substrate. After that, 3-10 μm etching is performed on the plating area portion of the base material using an iron solution. If this etching process is shallower than 3 μm, the sealing resin may wrap around between the base material and the plating layer. In the case of etching processing deeper than 10 μm, after peeling off the base material, a plating layer that becomes a pad part or a terminal part may remain on the base material side, so that the etching processing is performed at a depth of 3 to 10 μm. It is desirable.

  The etched base material is first subjected to a general weakly acidic to neutral bath gold plating, followed by nickel plating, and then copper plating, nickel plating, and gold plating in that order. 5 layers of the lower plating layer consisting of gold plating and nickel plating, the intermediate plating layer consisting of copper plating, and the upper plating layer consisting of nickel plating and gold plating. Seven or more plating layers are formed in which the plating layer or the intermediate plating layer is formed by sequentially performing copper plating and nickel plating.

  Next, the resist previously stuck on both surfaces of the base material is peeled off, and only a portion of the copper plating layer that is an intermediate plating layer is subjected to etching processing on one side of 2 to 10 μm, whereby the plating layer of the schematic cross section shown in FIG. Is formed. If this side etching process is shallower than 2 μm, the adhesion to the resin will be insufficient, and conversely if it is deeper than 10 μm, the upper plating layer will be partially lowered and the shape may be damaged. Therefore, it is desirable that the etching process is performed within a range of 2 to 10 μm on one side. In addition, it is necessary to make the upper plating layer 5 μm or more in thickness by etching the intermediate plating layer as described above.

  Further, in the substrate for mounting a semiconductor element according to the present invention, the base material surface side in the lower plating layer is a part that connects the semiconductor device to a mother board or the like, and therefore must be a solderable plating. On the other hand, since the uppermost layer of the upper plating layer is a portion to be wire-bonded, it is a necessary condition that the plating is capable of wire bonding. In order to satisfy the above conditions, the plating layer on the substrate according to the present invention is composed of the lower plating layer in gold plating or palladium plating, the intermediate plating layer in copper plating or nickel plating, and the upper side in order from the base material side. These plating layers can be palladium plating or gold plating, and the lower, middle and upper layers are formed of a single or a plurality of plating layers.

A stainless steel plate (SUS430) having a thickness of 0.2 mm is used as a metal thin plate to be the base material 11, and after degreasing and acid cleaning treatment, a photosensitive dry film resist 12 having a thickness of 0.025mm is formed. After affixing on both surfaces of the base material 11 with a laminating roll, a glass mask for a plating mask is placed on the dry film resist 12 on one surface of the base material 11, and further exposed to ultraviolet light from above. Then, development processing was performed, and a predetermined pattern with the dry film resist 12 was produced.
The pattern at this time is prepared by arranging 16 3 mm square pad portions 41 and 16 0.5 mm square terminal portions 42 around it as a plating area 40 for forming a plating layer as shown in FIG. Such a product was prepared by arranging a plurality of sets so that 6 × 6 pieces were formed in the vicinity of the center of a substrate having a width of 40 mm.

  Next, after pre-plating the plating area 40 on the base material, gold plating is applied in a strong acid bath having a pH of 0.1 to 1.0, and nickel plating is applied thereon from about 10 μm. Then, copper plating is applied to about 10 μm thereon, nickel plating is further applied to about 5 μm thereon, and gold plating is applied to about 0.1 μm with a weakly acidic to neutral bath thereon, so that the thickness is gradually reduced from the substrate side. Lower plating layer 21 consisting of a gold plating layer and a 10 μm nickel plating layer, intermediate plating layer 22 consisting of a 10 μm copper plating layer, and an upper plating layer consisting of a 5 μm nickel plating layer and a 0.1 μm gold plating layer The plating layer 23 substantially formed three plating layers on the substrate (not counted because the gold plating layer was thin).

  Next, after the dry film resist 12 previously stuck on both surfaces of the substrate 11 is peeled off, washed with water and dried, the copper plating layer, which is an intermediate plating layer with an iron solution, is centered from the side surface. An etching process of about 7 μm on one side was performed. Through the series of processing steps, the plating layer 21 below the gold plating layer 31 and the nickel plating layer 32, the intermediate plating layer 22 of the copper plating layer 33, the nickel plating layer 34, and the gold plating are formed on the substrate as described above. FIG. 1B shows a cross-sectional view of the main part of FIG. 1B, in which a plating layer to be the upper plating layer 23 of the layer 35 is formed, and the copper plating layer 33 as the intermediate plating layer 22 is narrower by about 7 μm on one side than the upper and lower plating layers. An element mounting substrate was obtained.

  Using the obtained semiconductor element mounting substrate according to this example, the semiconductor element 51 was mounted on the pad portion 54 using a die bonding paste, and the electrode of the semiconductor element 51 and the terminal portion 52 were wire-bonded 53, As shown in FIG. 4A, resin sealing is performed using the sealing resin 55 so that the three sets are sealed together (see the semiconductor element mounting substrate 50 after resin sealing), and after the resin is cured. As a result of peeling the stainless steel as the base material 11 from the resin-sealed portion and observing the peeled stainless steel side in detail, there is no portion where the plating layer remains, and the resin-sealed portion is also sealed. On the gold plating side that was in contact with the stainless steel at the part, the trace of the sealing resin 55 wraps around, and the plating layer does not float or peel off from the sealing resin 55 and is held tightly confirmed.

  As in Example 1, using the base material 11 having a predetermined pattern formed on the surface of the base material with a dry film resist, the plating area portion 40 of the base material 11 is first etched to a depth of about 7 μm with an iron solution. Then, a semiconductor element mounting substrate was obtained by substantially the same means as in Example 1 except that the etched portion 13 was formed in the portion. Using the obtained semiconductor element mounting substrate, the semiconductor element 51 is mounted on the pad portion 54 using a die bonding paste, and the electrode of the semiconductor element 51 and the terminal portion 52 are wire-bonded, and then shown in FIG. In this way, resin sealing was performed so that the three sets were sealed together (see the semiconductor element mounting substrate 50 after resin sealing), and the stainless steel as the base material 11 was resin sealed after the resin was cured. I peeled it off the part. As a result of observing the surface of the peeled stainless steel side in detail, there is no portion where the plating layer remains, and on the gold plating side that was in contact with the stainless steel in the resin-sealed portion, It was confirmed that the sealing resin was kept tightly without any traces of the enclosing resin and the plating layer not floating or peeling off from the resin.

  Using the base material 11 in which the predetermined pattern made of the same dry film resist was prepared by replacing the stainless steel of Example 1 with a copper alloy, the depth 7 μm was first applied to the plating area portion 40 of the base material 11 by an iron solution. After etching to a certain extent and pre-plating, about 3 μm of gold plating is applied in a neutral bath, about 6 μm of nickel plating is applied thereon, and further about 6 μm of silver plating is applied thereon. A total of about 15 μm plating layer is formed on the substrate, and then the dry film resist remaining on the surface of the base material is peeled off. Then, the nickel plating layer is subjected to etching processing by selective etching to have a thickness of about 5 μm. A semiconductor element mounting substrate was obtained. Using the obtained semiconductor element mounting substrate, resin sealing was carried out in the same manner as in Example 1, and after the resin was cured, a copper alloy as the base material 11 was subjected to a dissolution treatment with an etching solution to form a plating layer. The resin containing was left. In the gold plating part that was in contact with the copper alloy in the plating layer on the resin side, there was no trace of the sealing resin wrapping, and there was no appearance of the plating layer floating or peeling from the resin, in a tight state It was confirmed that it was retained.

  Using the base material 11 with a predetermined pattern made of the same dry film resist as in Example 1, the plating area portion 40 of the base material 11 was first subjected to pre-plating treatment, and then pH 0.1 to 1.. Apply a gold plating of about 0.1 μm in a strong acidic bath of 0, apply a nickel plating of about 5 μm on top of it, apply a copper plating of about 5 μm on it, further apply a nickel plating of about 5 μm thereon, and further thereon Copper plating is applied at about 5 μm, nickel plating is further applied at about 5 μm, and then gold plating is applied at about 0.1 μm with a weakly acidic to neutral bath. The layer 31, the lower plating layer 21 of the nickel plating layer 32, and the intermediate plating layer 22 are a copper plating layer 33a, a nickel plating layer 33b, and a copper plating layer 33a. Kkiso 34, to obtain a semiconductor device mounting board comprising an upper plating layer 23 of the gold plating layer 35.

  Next, the dry film resist was peeled off, and an etching process with a depth of about 6 μm was applied to the copper plating layer with an alkali etchant to obtain a cross-sectional view of the main part of FIG. Using the obtained semiconductor element mounting substrate, resin sealing was performed in the same manner as in Example 1, and after the resin was cured, the stainless steel as the base material 11 was peeled off from the resin-sealed portion. As a result of observing the peeled stainless steel side, there is no portion where the plating layer remains, and the gold plating layer side that is in contact with the stainless steel in the resin-sealed portion has no sealing resin. There was no trace of wraparound, and no appearance of the plating layer floating or peeling from the resin was confirmed, confirming that it was held in a tight state. Moreover, after soldering by reflow, when the adhesion strength between the sealing resin and the plated metal terminal was measured by a destructive test, a higher strength than in Examples 1, 2, and 3 was obtained.

On the other hand, if the intermediate plating layer is further multi-layered, the process becomes complicated and each plating layer becomes thin so that the productivity is not lowered, and the sealing resin does not easily flow into the etched portion and is retained. Therefore, it is considered that the number of layers in this embodiment is suitable at most.
In this way, when the total thickness of the plating layer to be formed is increased, there are a method of increasing the thickness of the intermediate plating layer and a method of increasing the thickness of the upper and lower plating layers. By including a plating layer that is not applied, the effect of being held by the sealing resin can be improved by utilizing the convex shape in the upper and lower plating layers and the intermediate plating layer.

  In the method for manufacturing a semiconductor element mounting substrate of the present invention, as the plating layer of three or more layers formed on the base material, for example, gold plating, copper plating, Gold plating (or gold alloy plating), or gold plating, palladium plating, nickel plating, palladium plating, gold plating (or gold alloy plating), or gold plating, palladium plating, nickel plating, gold plating, silver plating (or silver alloy) Plating), or gold plating, palladium plating, nickel plating, palladium plating (or palladium alloy plating), and the like.

  The substrate for mounting a semiconductor element obtained by the method of the present invention is excellent in adhesion between the generated plating layer and the sealing resin, even though the manufacturing method is a simple process, and after peeling the substrate. Since the plating layer that becomes the pad portion and the terminal portion does not remain on the peeled base material side, and has an excellent effect as a semiconductor element mounting substrate, it can be widely used in the industrial field. Be expected.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a semiconductor element mounting substrate obtained by an embodiment according to the present invention, in which (a) is a cross-sectional view of an essential part showing a state in which three plating layers are applied on the substrate; The principal part sectional drawing which shows the state in which the plating layer of this was formed, (c) is a principal part sectional drawing of the state which consists of several plating layers in which the middle plating layer is a 7-layer plating layer and has a convex part. The state which formed several sets of plating layers with the resist pattern on the board | substrate is shown, (a) is the principal part top view, (b) is the partially expanded plan view of (a). In the method for manufacturing a substrate for mounting a semiconductor element according to the present invention, a sectional view for explaining a means for forming a three-layered plating layer on a substrate for each process, (a) is a state in which a pattern is formed from a resist; b) is a state in which the base material is etched, (c) is a state in which three plating layers are applied on the base material, (d) is a state in which the resist pattern is peeled off, and (e) is an intermediate plating layer. It is principal part sectional drawing which shows the state which performed the etching process, respectively. The state of the board | substrate after resin sealing in the manufacturing method of the board | substrate for semiconductor element mounting based on this invention is shown, (a) is a board | substrate obtained by Example 1, (b) is according to Example 2, 3 similarly. It is a principal part expanded sectional view using the obtained board | substrate. BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic cross section explaining the plating layer of this invention in the manufacturing method of the board | substrate for semiconductor element mounting based on this invention, (a) is a schematic cross section of 5 layer structure by three types of plating layers, (b) is three types It is sectional drawing of the 7-layer structure by the plating layer of.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Base material 12 Dry film resist 13 Etching part 21 Lower plating layer 22 Middle plating layer 23 Upper plating layer 31, 35 Gold plating layer 32, 33b, 34 Nickel plating layer 33a Copper plating layer 40 Plating area 41 Pad part 42 Terminal part 50 Semiconductor element mounting substrate 51 after resin sealing Semiconductor element 52 Terminal part 53 Wire bonding 54 Pad part 55 Sealing resin

Claims (8)

  A step of forming a predetermined resist pattern by applying a resist to both surfaces of a base material made of a thin metal plate and using the resist on one side as a mask for plating, on the base material exposed from the resist pattern A step of etching at a predetermined position, a step of forming a plating layer consisting of three or more layers of the lower side, the middle and the upper side on the etched base material, the affixed on both sides of the base material A method for producing a substrate for mounting a semiconductor element, comprising: a step of stripping a resist; and a step of etching the intermediate plating layer to make the intermediate plating layer narrower than the upper and lower plating layers.   2. The method of manufacturing a semiconductor element mounting substrate according to claim 1, wherein the metal thin plate is stainless steel having a thickness of 0.05 to 0.5 mm.   3. The method for manufacturing a semiconductor element mounting substrate according to claim 1, wherein the etching process performed at a predetermined position on the substrate is within a range of a depth of 3 to 10 μm.   3. A semiconductor element mounting substrate according to claim 1 or 2, wherein a gold plating layer is formed using a strongly acidic bath instead of the etching process applied to a predetermined position on the substrate. Method.   Etching is performed on the intermediate plating layer in a range of 2 to 10 μm on one side from the side surface to the center direction, and the area is narrowed compared to the areas of the lower plating layer and the upper plating layer. The method for manufacturing a substrate for mounting a semiconductor element according to claim 1, wherein:   The lower plating layer is gold and / or nickel plating, the intermediate plating layer is copper and / or nickel plating, and the upper plating layer is nickel, gold, silver, palladium and alloy plating thereof. The manufacturing method of the board | substrate for semiconductor element mounting of any one of Claims 1 thru | or 5.   The method of manufacturing a substrate for mounting a semiconductor element according to claim 1, wherein the upper plating layer has a thickness of 5 μm or more.   The intermediate plating layer includes a plating layer that is not etched from the side surface toward the center, and has a convex portion in the intermediate plating layer that is narrower than the upper and lower plating layers. 8. A method for producing a semiconductor element mounting substrate according to claim 7.

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