JP2009105335A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP2009105335A JP2009105335A JP2007277999A JP2007277999A JP2009105335A JP 2009105335 A JP2009105335 A JP 2009105335A JP 2007277999 A JP2007277999 A JP 2007277999A JP 2007277999 A JP2007277999 A JP 2007277999A JP 2009105335 A JP2009105335 A JP 2009105335A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor device
- semiconductor
- semiconductor chip
- resin portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 251
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229920005989 resin Polymers 0.000 claims abstract description 71
- 239000011347 resin Substances 0.000 claims abstract description 71
- 238000007789 sealing Methods 0.000 claims abstract description 5
- 239000000853 adhesive Substances 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 description 18
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 230000008646 thermal stress Effects 0.000 description 8
- 239000010408 film Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 230000007257 malfunction Effects 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 229910003271 Ni-Fe Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
【解決手段】本発明は、半導体チップ10と、半導体チップ10と電気的に接続された接続端子30と、半導体チップ10の回路12が形成された面と反対の面である下面が露出するように、半導体チップ10と接続端子30とを封止する樹脂部40と、半導体チップ10上に設けられ、上面が樹脂部40から露出し、熱膨張係数が樹脂部40より小さい第1チップ20と、を具備する半導体装置である。
【選択図】図3
Description
12 回路
20 第1チップ
22 回路
24 第2チップ
30 リード
32 ボンディングワイヤ
34 金属バンプ
40 樹脂部
50 接着剤
52 金属バンプ
54 接着剤
Claims (10)
- 半導体チップと、
前記半導体チップと電気的に接続された接続端子と、
前記半導体チップの回路が形成された面と反対の面である下面が露出するように、前記半導体チップと前記接続端子とを封止する樹脂部と、
前記半導体チップ上に設けられ、上面が前記樹脂部から露出し、熱膨張係数が前記樹脂部より小さい第1チップと、を具備することを特徴とする半導体装置。 - 前記接続端子の上面と下面とが前記樹脂部から露出していることを特徴とする請求項1記載の半導体装置。
- 前記第1チップは、前記半導体チップを構成する材料と同じ材料からなることを特徴とする請求項1または2記載の半導体装置。
- 前記第1チップの下面には、前記半導体チップと電気的に接続された回路が形成されていることを特徴とする請求項3記載の半導体装置。
- 前記半導体チップと前記第1チップとの間に、前記半導体チップと前記接続端子とを接続するボンディングワイヤを封止する接着剤を具備することを特徴とする請求項1から4のいずれか一項5記載の半導体装置。
- 半導体チップと、
前記半導体チップと電気的に接続された接続端子と、
前記半導体チップの上面に設けられた第1チップと、
前記半導体チップの下面に設けられた第2チップと、
前記第1チップの上面が露出し、前記第2チップの下面が露出するように、前記半導体チップと前記接続端子とを封止する樹脂部と、を具備し、
前記第1チップおよび前記第2チップの熱膨張係数は前記樹脂部より小さいことを特徴とする半導体装置。 - 前記接続端子の上面と下面とが前記樹脂部から露出していることを特徴とする請求項6記載の半導体装置。
- 前記第1チップは、前記半導体チップを構成する材料と同じ材料からなることを特徴とする請求項6または7記載の半導体装置。
- 請求項2または7記載の半導体装置である第1半導体装置および第2半導体装置を具備し、
前記第1半導体装置の接続端子の下面と前記第2半導体装置の接続端子上面とが接続するように、前記第1半導体装置と前記第2半導体装置とが積層された積層半導体装置。 - 前記半導体チップと接続端子とを電気的に接続する工程と、
前記半導体チップの回路が形成された面である上面と第1チップとを接着する工程と、
前記半導体チップの下面と、前記第1チップの上面とが露出するように、前記半導体チップ、前記第1チップおよび前記接続端子を封止する前記第1チップより熱膨張係数の大きな樹脂部を形成する工程と、を有することを特徴とする半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007277999A JP5553960B2 (ja) | 2007-10-25 | 2007-10-25 | 半導体装置及びその製造方法 |
US12/258,131 US20090115070A1 (en) | 2007-09-20 | 2008-10-24 | Semiconductor device and method for manufacturing thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007277999A JP5553960B2 (ja) | 2007-10-25 | 2007-10-25 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009105335A true JP2009105335A (ja) | 2009-05-14 |
JP5553960B2 JP5553960B2 (ja) | 2014-07-23 |
Family
ID=40706712
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007277999A Expired - Fee Related JP5553960B2 (ja) | 2007-09-20 | 2007-10-25 | 半導体装置及びその製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5553960B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011210913A (ja) * | 2010-03-30 | 2011-10-20 | Fujitsu Ltd | 半導体装置及びその製造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004031650A (ja) * | 2002-06-26 | 2004-01-29 | Sony Corp | リードレスパッケージおよび半導体装置 |
JP2005167292A (ja) * | 2005-03-14 | 2005-06-23 | Matsushita Electric Ind Co Ltd | リードフレームおよびその製造方法ならびに樹脂封止型半導体装置およびその製造方法 |
JP2005252295A (ja) * | 2005-04-14 | 2005-09-15 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2007165836A (ja) * | 2005-11-18 | 2007-06-28 | Shinko Electric Ind Co Ltd | 半導体装置 |
-
2007
- 2007-10-25 JP JP2007277999A patent/JP5553960B2/ja not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004031650A (ja) * | 2002-06-26 | 2004-01-29 | Sony Corp | リードレスパッケージおよび半導体装置 |
JP2005167292A (ja) * | 2005-03-14 | 2005-06-23 | Matsushita Electric Ind Co Ltd | リードフレームおよびその製造方法ならびに樹脂封止型半導体装置およびその製造方法 |
JP2005252295A (ja) * | 2005-04-14 | 2005-09-15 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2007165836A (ja) * | 2005-11-18 | 2007-06-28 | Shinko Electric Ind Co Ltd | 半導体装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011210913A (ja) * | 2010-03-30 | 2011-10-20 | Fujitsu Ltd | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP5553960B2 (ja) | 2014-07-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6650006B2 (en) | Semiconductor package with stacked chips | |
JP5227501B2 (ja) | スタックダイパッケージ及びそれを製造する方法 | |
US9385072B2 (en) | Method of manufacturing semiconductor device and semiconductor device | |
US8716861B2 (en) | Semiconductor package having electrical connecting structures and fabrication method thereof | |
JP2005183923A (ja) | 半導体装置およびその製造方法 | |
JP2008166527A (ja) | 半導体装置およびその製造方法 | |
US20100140786A1 (en) | Semiconductor power module package having external bonding area | |
KR100825784B1 (ko) | 휨 및 와이어 단선을 억제하는 반도체 패키지 및 그제조방법 | |
JP5921297B2 (ja) | 積層型半導体装置、プリント回路板及び積層型半導体装置の製造方法 | |
US20100123243A1 (en) | Flip-chip chip-scale package structure | |
JP4319229B2 (ja) | 半導体装置 | |
US20090115070A1 (en) | Semiconductor device and method for manufacturing thereof | |
JP4307362B2 (ja) | 半導体装置、リードフレーム及びリードフレームの製造方法 | |
KR100666919B1 (ko) | 반도체 패키지용 접착 시트, 이를 포함하는 반도체 소자,이를 포함하는 멀티 스택 패키지, 반도체 소자의 제조 방법및 멀티 스택 패키지의 제조 방법 | |
JP5553960B2 (ja) | 半導体装置及びその製造方法 | |
JP4207791B2 (ja) | 半導体装置 | |
JP2005327967A (ja) | 半導体装置 | |
JP2005311099A (ja) | 半導体装置及びその製造方法 | |
KR100437821B1 (ko) | 반도체 패키지 및 그 제조방법 | |
JP2006032773A (ja) | 半導体装置 | |
JP2001358286A (ja) | 半導体装置 | |
KR20100002868A (ko) | 반도체 패키지 | |
KR100308393B1 (ko) | 반도체패키지및그제조방법 | |
KR101040311B1 (ko) | 반도체 패키지 및 그 형성 방법 | |
KR19980022527A (ko) | 클립 리드를 갖는 칩 스케일 패키지 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20100327 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20100616 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20101021 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20111021 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20111101 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120126 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20120829 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20121023 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20130122 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20130125 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20130222 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20130227 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20130322 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20130327 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130422 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140109 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140319 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20140507 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20140528 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5553960 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |