JP2009038330A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device capable of improving gate withstand voltage decline defect in the semiconductor device provided with a top gate type structure. <P>SOLUTION: The manufacturing method of the top gate type semiconductor device has a step of forming a level difference by etching the surface of an initial insulating film 2 so as to be lower than the surface of an n type semiconductor crystal layer 16 by the thickness of 50% to 100% of the thickness of a gate insulating film 9 on the boundary surface of the surface of the initial insulating film 2 and the surface of the (n) type semiconductor crystal layer 16 between a step of forming a function region including a (p) type base region 13 and an n++ type emitter region 14 in the (n) type semiconductor crystal layer 16 clamped by the initial insulating film 2 and formed so as to be separated from a semiconductor substrate 1 by a substrate insulating film and a step of forming a MOS gate having a gate electrode 10 formed through the gate insulating film 9 on the surface of the (p) type base region 13. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a power semiconductor device used for a power conversion device or the like.

With respect to an IGBT which is a kind of power semiconductor device according to the present invention, the performance has been improved by many improvements so far. Here, the performance of the IGBT is a switching device that keeps a voltage and shuts off a current when it is off, and can flow a current with a voltage drop as small as possible, that is, a small on voltage when it is on, and has low power loss. It is the performance as.
The characteristics of the IGBT according to the present invention will be briefly described below. There is a so-called trade-off relationship between the maximum voltage that the IGBT can hold, that is, the magnitude of the withstand voltage and the voltage drop (ON voltage) at the time of ON, and the higher withstand voltage IGBT requires a thicker high resistance layer. The on-voltage increases. In addition, it is well known that there is a trade-off relationship between the on-voltage and the turn-off loss that the higher the residual carrier immediately after the off, the lower the on-voltage, but the higher the switching loss (especially the turn-off loss). Yes. It is generally considered difficult to improve both characteristics having such a trade-off relationship. The best strategy is to design the device structure so that trade-off optimization is achieved.
In order to achieve the optimum trade-off relationship, the carrier concentration on the anode side in the drift layer is lowered and the carrier concentration on the cathode side is raised, so that the ratio of the carrier concentration on the anode side to the cathode side is about 1: 5. It is known that this should be done. Furthermore, the average carrier concentration in the drift layer may be increased by keeping the carrier lifetime in the drift layer as large as possible.

As a method for reducing the carrier concentration on the anode side, the total impurity amount in the anode layer (collector layer) is actually reduced. On the other hand, the effect of increasing the carrier concentration on the cathode side is well known as the IE effect.
Further, a top gate type IGBT that can significantly improve the above-described on-voltage-turn-off loss trade-off by making the surface cathode side a novel high carrier injection structure has already been disclosed in the patent literature (Patent Literature). 1, Patent Document 2, Patent Document 3). Hereinafter, the manufacturing method of the IGBT having the top gate structure is related to the present invention and will be described in detail with reference to the drawings. Hereinafter, all of FIGS. 6 to 9 to be referred to are cross-sectional views of unit cells arranged in the order of the manufacturing process in order to show the manufacturing method of the IGBT. For the sake of brevity, only the figure numbers are shown for those drawings.
As shown in FIG. 6A, an initial oxide film 102 having a thickness of 0.7 μm is formed on the entire surface of the n ⁻ -type Si semiconductor substrate 101 by thermal oxidation or CVD growth. Next, the initial oxide film (stopper oxide film) 102 is selectively dry-etched so as to form a parallel stripe-like planar pattern, thereby forming a first opening 103 having a width of 20 μm between the parallel stripes of the initial oxide film 102. (FIG. 6B). The width in the substrate surface direction of the initial oxide film 102 having a parallel stripe-like planar pattern is preferably about 3 μm. Subsequently, as shown in FIG. 6C, a substrate oxide film 104 is formed on the entire surface to a thickness of 0.1 μm by thermal oxidation or CVD, and then a striped initial pattern is formed at the center of the substrate oxide film 104 by photolithography. A second opening 105 parallel to the oxide film 102 and having a width of 1 μm is formed.

Thereafter, an n-type epitaxial growth layer 106 is grown using the surface of the silicon substrate 101 exposed through the second opening 105 as a seed layer. If the growth surface exceeds the thickness of the substrate oxide film 104 after the growth of the n-type epitaxial growth layer 106 starts at the second opening 105, the growth proceeds in the lateral direction on the substrate oxide film 104. After that, the growth is stopped when the thickness of the initial oxide film 102 at the end is overcome and the entire surface of the first opening 103 is covered by the thickness of the initial oxide film 102 or more (FIG. 6C).
Next, polishing is performed using the initial oxide film 102 as an oxide film stopper until the surface of the n-type epitaxial growth layer 106 has a flat cross-sectional shape whose height is substantially equal to the surface of the initial oxide film 102 as shown in FIG. . The thickness of the n-type epitaxial growth layer 106 after polishing becomes about 0.6 μm to 0.7 μm.
Next, as shown in FIGS. 7E and 7F, a buffer oxide film 107a having a thickness of 30 nm is formed on the surface of the polished n-type epitaxial growth layer 106, and then the photoresist 30 is masked by photolithography. After the p channel region 109 is formed by boron ion implantation and heat treatment, the p ⁺ body region 112 and the n ⁺⁺ emitter region 113 are formed as shown in FIGS. 8 (g), (h) and (i). Then, each region is formed by ion implantation of boron and arsenic and post-heat treatment at 1000 ° C. using each photoresist 30 as a mask. A region remaining as the original n-type epitaxial growth layer 106 is defined as an n ⁺ buffer region 106a. A layer in which the n ⁺ buffer region 106a, the p channel region 109, the p ⁺ body region 112, the n ⁺⁺ emitter region 113, and the like are formed on the n type epitaxial growth layer 106 may be hereinafter referred to as a cathode film 120.

Next, after removing the buffer oxide film 107a and cleaning the surface of the cathode film 120, as shown in FIG. 9 (j), gate oxidation is performed on the cathode film 120 by thermal oxidation or CVD. A film 107b is formed on the entire surface with a thickness of 80 nm. Further, a polysilicon layer serving as a gate electrode is formed on the entire surface by CVD with a thickness of about 500 nm. After doping the polysilicon layer with a high concentration of phosphorus to form a low resistance layer, the polysilicon layer is formed by photolithography. A part thereof is removed to form a conductive polysilicon gate electrode 108 having a predetermined shape.
At this time, in the above-described process of forming the p ⁺ body region 112 and the n ⁺⁺ emitter region 113, the p ⁺ body region 112 exceeds the n ⁺⁺ emitter region 113 from the lower side in the plane direction, and immediately below the gate oxide film 107b. When the n-channel is formed on the p-channel region 109, the channel generation is adversely affected and the gate threshold voltage rises. Therefore, the p ⁺ body under the n ⁺⁺ emitter region 113 is generated. It is necessary to recede the region 112 by a predetermined width in a direction away from the p-channel region 109 where the channel is generated.
Thereafter, as shown in FIG. 9K, a PSG (phosphosilicate glass) film having a thickness of about 1 μm is formed on the entire surface to form an interlayer insulating film 114. Subsequently, a contact opening 116 for contact between the n ⁺⁺ emitter region 113 and the emitter electrode 115 is formed in the interlayer insulating film 114, an aluminum electrode (emitter electrode) 115 is formed, and an anode on the back surface of the substrate (not shown) is formed. By forming an anode electrode on the side, a conventional IGBT having a top gate structure is completed. According to this top gate type IGBT, the trade-off between the ON voltage and the turn-off loss can be greatly improved.
JP 2007-43028 A JP 2006-237553 A US Patent Application Publication No. 2006/0076583

However, in the above-described conventional top-gate IGBT, since a large current flows through the cathode film 120 in the on state and a high electric field is applied at the time of blocking, the cathode film 120 is used to obtain good device characteristics. It is necessary to form a high-quality crystalline silicon semiconductor film with few (or no) crystal defects. For this reason, as a special process that does not exist in the conventional normal IGBT, as described above, the initial oxide film (hereinafter referred to as the stopper oxide film) 102 and the substrate oxide film 104 formed on the n ⁻ -type Si semiconductor substrate 101 are subjected to the first process. After forming each of the one opening 103 and the second opening 105, the first opening 103 is filled with an n-type silicon epitaxial growth layer 106, and then planarized to be flush with the surface of the stopper oxide film 102 by a polishing process. And an n ⁺ buffer region 106a, a p channel region 109, a p ⁺ body region 112, and an n ⁺⁺ emitter region 113 are selectively formed on the n type epitaxial growth layer 106 planarized after polishing.
Further, when the surface of the n-type epitaxial growth layer is planarized, a boundary surface where the surface of the stopper oxide film 102 used as a stopper for detecting the end point of the polishing operation and the surface of the n-type epitaxial growth layer 106 always appears. However, when the gate oxidation process is performed in the subsequent process, a phenomenon occurs in which the gate oxide film is thinned at the boundary due to the stress at the time of thermal oxidation. Further, when the polysilicon gate electrode is covered on the gate oxide film including the thinned portion, there arises a problem that the breakdown voltage of the gate oxide film is lowered at the thin film portion.

The cross-sectional view of the unit cell of the top gate type IGBT shown in FIG. 9K is a gate oxide film 107b on the boundary surface between the stopper oxide film 102 and the cathode film 120 and the polysilicon gate electrode 108 formed thereon. Since it is a cross section in a place where no is formed, the local thinning of the gate oxide film 107b is not shown. However, in practice, the polysilicon gate electrode 108 formed on each unit cell in the IGBT chip is pulled out and assembled outside the unit cell to make contact with a gate electrode metal (not shown). As shown in the enlarged sectional view in the vicinity of the boundary surface, there is always a portion of the structure in which the polysilicon gate electrode 108 is formed on the gate oxide film 107b on the boundary surface between the cathode film 120 and the stopper oxide film 102. As shown in FIG. 2, the local thin film portion 121 of the gate oxide film 107b causes a problem that the breakdown voltage of the gate oxide film 107b is significantly reduced.
The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device that can improve a gate breakdown voltage reduction failure in a semiconductor device having a top gate type structure. is there.

  According to the first aspect of the present invention, the initial insulating film arranged linearly on the surface of the one-conductivity-type semiconductor substrate with the first opening interposed therebetween, and the first insulating film is thinner than the initial insulating film. A first step of forming a substrate insulating film formed on the surface of the semiconductor substrate including the first opening; a second step provided in parallel to the initial insulating film on the substrate insulating film in the first opening; A second step of forming an opening; a third step of forming a one-conductivity-type semiconductor crystal layer that fills the first opening with a thickness similar to that of the initial insulating film; and the second opening in the semiconductor crystal layer Selectively on the surface of the semiconductor substrate, the other conductive type base region on the substrate insulating film adjacent to the one conductive type region, and the other conductive type base region surface layer. One conductivity type emitter region to be formed and the other conductivity type base region A fourth step of selectively forming another conductivity type body region formed at a higher concentration than the other conductivity type base region, the other conductivity type base region sandwiched between the one conductivity type region and the one conductivity type emitter region; And a fifth step of forming a gate electrode formed on the surface of the first insulating film via the gate insulating film, the first insulating film surface and the one step between the fourth step and the fifth step. The initial insulating film surface is lower by 50% to 100% of the thickness of the gate insulating film than the surface of the one conductive type semiconductor crystal layer at the boundary surface contacting the conductive type semiconductor crystal layer surface. A method for manufacturing a semiconductor device having a step of forming a step by etching.

According to the second aspect of the present invention, the semiconductor device manufacturing method according to the first aspect of the present invention is such that the processing temperature for forming the gate oxide film is 1000 ° C. or higher.
According to the third aspect of the present invention, the initial insulating film arranged linearly on the surface of the one-conductivity-type semiconductor substrate with the first opening interposed therebetween, and the first insulating film is thinner than the initial insulating film. A first step of forming a substrate insulating film formed on the surface of the semiconductor substrate including the first opening, a second opening parallel to the initial insulating film in the substrate insulating film in the first opening A second step of forming a one-conductivity-type semiconductor crystal layer in which the inside of the first opening is filled to the same thickness as the initial insulating film, and the second opening in the semiconductor crystal layer Selectively formed in one conductivity type region in contact with the semiconductor substrate surface, another conductivity type base region adjacent to the one conductivity type region on the substrate insulating film, and the other conductivity type base region surface layer Higher concentration than the one conductivity type emitter region and the other conductivity type base region. A fourth step of forming a conductive type body region, forming a gate electrode formed on a surface of the other conductive type base region sandwiched between the one conductive type region and the one conductive type emitter region via a gate insulating film; In the method of manufacturing a semiconductor device having the fifth step, the boundary surface between the initial insulating film surface and the one-conductivity-type semiconductor crystal layer surface is in contact between the fourth step and the fifth step, Manufacturing a semiconductor device including a step of forming a selective oxide film in contact with the boundary surface using a silicon nitride film formed on the surface of the one conductivity type semiconductor crystal layer side of the boundary surface covered by the gate electrode as a mask By the method, the object of the present invention is achieved.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor device with which a gate breakdown voltage fall defect is improved can be provided in the semiconductor device which has a top gate type structure.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.
FIG. 1 is a cross-sectional view of a unit cell of a top gate type IGBT according to the present invention. FIG. 2 is an enlarged sectional view of a local thin film portion of a gate oxide film of a conventional top gate type IGBT referred to for explaining the present invention. FIGS. 3 and 4 are enlarged cross-sectional views showing characteristic portions of the method for manufacturing the top gate IGBT according to the first embodiment of the present invention. FIG. 5 is an enlarged sectional view of a local thin film portion of the gate oxide film when the stopper oxide film is excessively etched. 10 and 11 are enlarged cross-sectional views showing characteristic portions of a method for manufacturing a top gate type IGBT according to Embodiment 2 of the present invention.

Example 1 according to the method for manufacturing a semiconductor device of the present invention will be described below with reference to FIGS. FIG. 1 is a sectional view of only the MOS gate side of a unit cell of a top gate type IGBT according to the first embodiment. As the MOS type semiconductor device, there are a MOSFET, an IGBT and the like. However, in the present invention, any of them may be used because the characteristic portion is on the MOS gate side. In the following description, the description is continued as an IGBT. As the silicon semiconductor substrate, the mirror polishing finish of the n-type FZ-silicon substrate 1 is used. The specific resistance of the substrate is preferably in the range of 30 to 200 Ωcm, and is selected according to the breakdown voltage required for the IGBT. For example, if a substrate 1 having 80 Ωcm is used, a top gate IGBT having a withstand voltage of 1200 V can be obtained.
The IGBT shown in FIG. 1 is substantially the same as FIG. 9 (k) in the range shown in this sectional view. The correspondence relationship between the reference numerals in FIG. 1 and the reference numerals in FIG. 1, 2, 7, 9, 10, 11, 12, 13, 14, 15, 16 are 101, 102, 106a, 107b, 108, 114, 115, 109, 113, 112 of FIG. 9 (k). , 120 in this order. The cathode film 16 in FIG. 1 is a film in which the n ⁺ buffer region 7, the p channel region 13, the n ⁺⁺ emitter region 14, and the p ⁺ body region 15 are combined.

FIG. 3A shows a boundary surface between the cathode film 16 and the initial oxide film 2 according to the present invention, which does not appear in the cross-sectional view of the IGBT shown in FIG. FIG. 4 is an enlarged cross-sectional view of a substrate surface portion that is to be covered with a conductive polysilicon film 10 in a later step. Specifically, FIG. 3A shows a CMP process using the selectively formed initial insulating film as a stopper oxide film 2 in the same manner as the step of FIG. 7D showing the above-described conventional top gate type IGBT manufacturing method. When the n-type epitaxial growth layer is polished flush with (Chemical Mechanical Polishing) to form a predetermined diffusion layer to form the cathode film 16, a buffer oxide film 19 with a thickness of 30 nm formed on the surface (FIG. 7). (H) is an enlarged sectional view of the vicinity of the boundary surface between the stopper oxide film 2 and the cathode film 16 in the manufacturing step having 107a).
The state shown in the cross-sectional view of FIG. 3A will be described in terms of a manufacturing method. FIG. 3A shows a manufacturing method of an IGBT having a conventional top gate structure as described above, FIG. Steps similar to the steps described with reference to FIGS. 7 and 8 are almost finished, and the next step before forming the gate oxide film 107b in FIG. 9 (j) is the step of FIG. 7 (i). In this state, the buffer oxide film 107a is left on the substrate surface. The buffer oxide film 19 (buffer oxide film 107a in FIG. 8) is formed by forming the p channel region 13, the p ⁺ body region 15 and the like (not shown in FIG. 3A) formed in the cathode film 16. Therefore, the process is performed immediately before the ion implantation on the surface of the cathode film 16, and the state of FIG. 3A has finished the driving process of the diffusion layers of the p channel region 13 and the p ⁺ body region 15 (not shown). Later. Since the buffer oxide film 19 is formed in this way, in FIG. 3A, the boundary surface has a step of about 30 nm (0.03 μm) or less (in FIG. 8H, the buffer oxide film 19). The film 107a is a flat film covering both surfaces of the cathode film and the initial oxide film, but actually has a step as shown in FIG. After that, as shown in FIG. 3B, the surface of the stopper oxide film 2 is etched to form a step having a predetermined size. Here, as a step having a predetermined size, the etching amount of the stopper oxide film 2 is set to 0.05 μm. The stopper oxide film 2 may be etched by either dry etching or wet etching with hydrofluoric acid. However, if the etching amount is 0.04 μm or less, the buffer oxide film 19 (thickness 0.03 μm) 19 may be etched. Etching residue may occur. If the thickness is 0.1 μm or more, the remaining thickness of the stopper oxide film 2 may be insufficient. In this way, a step is formed that makes the surface of the stopper oxide film 2 lower than the surface of the cathode film 16. This state is shown in FIG.

Next, as shown in FIG. 3C, sacrificial oxidation is performed by dilute pyrogenic oxidation at a high temperature of 1000 ° C. or higher. The thickness of the sacrificial oxide film 18 is 50 nm. By performing diluted pyrogenic oxidation at a high temperature in the state after the sacrificial oxidation, the oxide film 18 can be made to flow viscously while suppressing the oxidation rate, so that the oxide film 18 in the corner portion is formed more uniformly. be able to. In FIG. 4D, the sacrificial oxide film 18 is removed with hydrofluoric acid. In the step of removing the sacrificial oxide film 18 using hydrofluoric acid, if the over-etching is excessive, the thickness of the stopper oxide film is reduced. Therefore, the over-etching amount is set to 20% or less of the sacrificial oxide film thickness. The dashed line in FIG. 4D is the state before etching, and the solid line is the surface of the sacrificial oxide film 18 near the boundary after etching.
Thereafter, the gate oxide film 9 having a thickness of 80 nm is formed by high-temperature diluted pyrogenic oxidation at 1000 ° C. or higher. By performing oxidation at 1000 ° C. or higher as in the case of forming the sacrificial oxide film 18 described above, it is possible to avoid thinning the gate oxide film 9 at the corner as shown in FIG. Thereafter, as shown in FIG. 1, a polysilicon film is deposited to a thickness of 500 nm by a CVD method, and a polysilicon gate electrode 10 is formed by a photolithography technique. Thereafter, after the interlayer insulating film 11 is deposited, a general process is performed in which a contact opening with the emitter electrode is formed in the interlayer insulating film 11 and the emitter electrode is formed and a gate electrode metal wiring (not shown) is formed. As a result, the conventional top gate IGBT having a local thin film portion on the conventional gate oxide film has a gate oxide breakdown voltage of 30 V or less, whereas the top gate formed in Example 1 according to the present invention. In the type IGBT, it was possible to obtain a good insulation characteristic of a gate oxide film withstand voltage of 65 V or more.

In the stopper oxide film etching step for forming a step on the boundary surface described above, if the etching amount is 80 nm or more, which is the thickness of the gate oxide film 9 formed in the subsequent step, the step becomes too large. As shown in the sectional view of FIG. 5A, corners remain in the middle of the step, and after the formation of the gate oxide film 9, the n-type epitaxial growth layer 16 is finally formed as shown in FIG. A corner is formed in the gate oxide film 9 itself in the middle of the step at the boundary with the stopper oxide film 2, and the gate breakdown voltage is lowered due to the concentration of an electric field at the corner of the gate oxide film 9. On the other hand, if the etching amount is too large, the remaining film of the stopper oxide film 2 becomes thin, which is not preferable. Therefore, the etching amount of the stopper oxide film 2 is 50% to 100% of the final gate oxide film 9 thickness, that is, the gate oxide film thickness is 80 nm as described in the first embodiment. The etching amount of the stopper oxide film is desirably 40 nm to 80 nm.
As described above, as described in the first embodiment of the present invention, the stopper oxide film is etched before the sacrificial oxide film is formed, thereby forming a step on the boundary surface that makes the stopper oxide film surface lower than the cathode film surface. By doing so, it is possible to avoid the gate oxide film from being thinned at the boundary surface between the cathode film and the stopper oxide film, so that the gate oxide film breakdown voltage can be remarkably improved.

Example 2 according to the method for manufacturing a semiconductor device of the present invention will be described below with reference to FIGS. 1 and 10 to 12. FIG. 10 (a) is a step corresponding to the manufacturing step of FIG. 7 (d), in the vicinity of the boundary between the polished surface of the n ⁺ type epitaxial silicon layer 106 and the surface of the initial oxide film 102, FIG. 8D is an enlarged cross-sectional view of a portion that is not illustrated in FIG. 7D and is covered with a polysilicon gate electrode on the boundary surface. There is no step between the surface of the polished surface of the n ⁺ -type epitaxial silicon 7 and the surface of the initial oxide film 2 and is flush.
In FIG. 10B, a buffer oxide film 19 having a thickness of 30 nm is formed on the substrate surface of FIG. 10A. Further, after the buffer oxide film 19 is formed, a p-channel region 13 is formed to form a p channel region 13. A process of forming a p-channel region 13 by performing patterning by lithography, followed by ion implantation and drive diffusion processing is shown. Next, a silicon nitride film is deposited on the entire surface by low pressure CVD, and the silicon nitride film 20 is patterned to form a mask for forming the p ⁺ body region 15, and boron ion implantation is performed (FIG. 10C). ). Here, the silicon nitride film normally refers to a Si ₃ N ₄ film, but is not limited to a complete Si ₃ N ₄ composition ratio, and may include films having different composition ratios. In the following description, the silicon nitride film is used as the same meaning as described above.

After the boron ion implantation, an oxidation process is further performed using the patterned silicon nitride film 20. This oxidation process also serves as an activation process for the ion-implanted boron. The boron ion implantation layer becomes the p ⁺ body region 15 and at the same time, p ⁺ sandwiched between the silicon nitride film 20 and the initial oxide film 2. The surface of the body region 15 is selectively oxidized to form a thick silicon oxide film (LOCOS oxide film) 21 (FIG. 10D).
Thereafter, the silicon nitride film 20 is removed (FIG. 11E), sacrificial oxidation treatment is performed (FIG. 11F), a gate oxide film 9 is further formed (FIG. 11G), and the gate electrode A conductive polysilicon layer to be 10 is deposited to a thickness of 500 nm by a CVD method (FIG. 11 (h)) Next, the conductive polysilicon layer is patterned by photolithography to form a gate as shown in FIG. An electrode 10 is formed, followed by photolithography to form a photoresist pattern for forming the n ⁺⁺ emitter region 14 shown in Fig. 1, and using the gate electrode 10 and the photoresist pattern as a mask, n ⁺⁺ The emitter region 14 is formed by ion implantation, and subsequently, a PSG (phosphorus silicate glass) film is formed as the interlayer insulating film 11. Opening an emitter contact corresponding to both surfaces of the p ⁺ body region 15 and the n ⁺⁺ emitter region 14 in the PSG film. Then by forming the emitter electrode 12, the surface side of the MOS semiconductor device is substantially completed. Top In the case of forming the gate type IGBT, although not shown, the back surface of the semiconductor substrate is polished to a required thickness, and then the collector layer and the anode electrode are formed.

  In the top gate type IGBT according to the present invention prepared according to the second embodiment described above, a thick LOCOS oxide film is formed on the boundary surface of the portion covered with the conductive polysilicon film among the boundary surface between the cathode film and the initial oxide film. As a result, there is no locally thin gate oxide film portion that is likely to be formed on the boundary surface, so that the gate oxide film has a withstand voltage of 65 V as compared to the withstand voltage of 30 V or less of the gate oxide film of the conventional top gate IGBT. The gate breakdown voltage can be improved.

It is sectional drawing of the unit cell of the top gate type IGBT concerning Example 1 of this invention. It is sectional drawing which shows local thinning of the gate oxide film of the conventional top gate type IGBT. It is an expanded sectional view concerning the manufacturing method of the top gate type IGBT of Example 1 of the present invention (the 1). It is an expanded sectional view concerning the manufacturing method of the top gate type IGBT of Example 1 of the present invention (the 2). It is an expanded sectional view of the local thin film part of a gate oxide film at the time of excessive etching of a stopper oxide film. It is sectional drawing which shows the manufacturing method of the conventional top gate type IGBT (the 1). It is sectional drawing which shows the manufacturing method of the conventional top gate type IGBT (the 2). It is sectional drawing which shows the manufacturing method of the conventional top gate type IGBT (the 3). It is sectional drawing which shows the manufacturing method of the conventional top gate type IGBT (the 4). It is principal part sectional drawing (the 1) of the semiconductor substrate which shows the manufacturing method of the top gate type IGBT concerning Example 2 of this invention. It is principal part sectional drawing (the 2) of the semiconductor substrate which shows the manufacturing method of the top gate type IGBT concerning Example 2 of this invention.

Explanation of symbols

1 n ⁻ type Si semiconductor substrate 2 initial oxide film, stopper oxide film 7 n ⁺ buffer region 9 gate oxide film 10 polysilicon gate electrode 11 PSG, interlayer insulating film 12 emitter electrode 13 p channel region 14 n ⁺⁺ emitter region 15 p ⁺ Body region 16 Cathode film, one-conductivity-type semiconductor crystal layer 18 Sacrificial oxide film 19 Buffer oxide film 20 Silicon nitride film, Si ₃ N ₄ film 21 LOCOS oxide film

Claims (3)

An initial insulating film linearly disposed on the surface of the one-conductivity-type semiconductor substrate with the first opening interposed therebetween, and a thin film thinner than the initial insulating film, the surface of the semiconductor substrate including the first opening A first step of forming a substrate insulating film to be formed; a second step of forming a second opening parallel to the initial insulating film in the substrate insulating film in the first opening; and the initial in the first opening A third step of forming a one-conductivity-type semiconductor crystal layer buried in a thickness similar to that of the insulating film; a one-conductivity-type region in contact with the semiconductor substrate surface through the second opening in the semiconductor crystal layer; and the substrate The other conductivity type base region adjacent to the one conductivity type region on the insulating film, the one conductivity type emitter region selectively formed on the surface layer of the other conductivity type base region, and the other conductivity type base region A fourth step of forming a high concentration other conductivity type body region, A fifth step of forming a gate electrode formed on a surface of the other conductivity type base region sandwiched between the conductivity type region and the one conductivity type emitter region via a gate insulating film; Between the fourth step and the fifth step, at the boundary surface where the surface of the initial insulating film and the surface of the one-conductivity-type semiconductor crystal layer are in contact, the surface of the initial insulating film is more than the surface of the one-conductivity-type semiconductor crystal layer, A method of manufacturing a semiconductor device, comprising: forming a step by etching so as to be 50% to 100% lower than the thickness of the gate insulating film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a processing temperature for forming the gate oxide film is set to 1000 [deg.] C. or higher. An initial insulating film having a linear opening on the surface of the one-conductivity-type semiconductor substrate and having a first opening therebetween; and the semiconductor including the first opening and being thinner than the initial insulating film A first step of forming a substrate insulating film formed on the substrate surface, a second step of forming a second opening parallel to the initial insulating film in the substrate insulating film in the first opening, and in the first opening A third step of providing a one-conductivity-type semiconductor crystal layer to fill the same thickness as the initial insulating film, a one-conductivity-type region in contact with the semiconductor substrate surface at the second opening in the semiconductor crystal layer, Another conductivity type base region adjacent to the one conductivity type region on the substrate insulating film, one conductivity type emitter region selectively formed on the surface of the other conductivity type base region, and the other conductivity type base region Fourth step of forming a higher concentration other conductivity type body region And a fifth step of forming a gate electrode formed through a gate insulating film on the surface of the other conductivity type base region sandwiched between the one conductivity type region and the one conductivity type emitter region. In the fourth step and the fifth step, the boundary surface where the surface of the initial insulating film and the surface of the one-conductivity-type semiconductor crystal layer are in contact with each other, and the one-conductivity type of the boundary surface covered by the gate electrode A method of manufacturing a semiconductor device, comprising: forming a selective oxide film in contact with the boundary surface using a silicon nitride film formed on a surface on the semiconductor crystal layer side as a mask.

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