JP3952914B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a semiconductor device having a trench gate structure and a manufacturing method thereof, and more particularly to planarization of a gate electrode and a gate lead line formed in a trench.
[0002]
[Prior art]
  As one of high voltage semiconductor devices, there are a MOSFET having a trench gate structure, an IGBT (insulated gate bipolar transistor), and the like.
  FIGS. 33A and 33B are configuration diagrams of a conventional trench gate type MOSFET. FIG. 33A is a perspective cross-sectional view of the main part, and FIG. 33B is a plan view of the main part viewed from the arrow F in FIG. . In FIG. 5B, the interlayer insulating film 70 and the source electrode 71 are omitted.
[0003]
  FIG. 34 is a cross-sectional view of the main part of FIG. 33 (b). FIG.33The principal part sectional drawing cut | disconnected by the XX line of (b) and the figure (b) are principal part sectional drawings cut | disconnected by the YY line | wire of FIG.33 (b). In this semiconductor device, a MOSFET is shown as an example.
  33 and 34, this MOSFET having a trench gate structure includes a p base region 62 formed on the surface of an n semiconductor substrate 200 and an n source region 67 formed on the surface of the p base region 62 in contact with the trench 63. P contact region 68 for making contact with p base region 62, gate electrode 65 formed in trench 63 via gate insulating film 64, and gate electrode 65, and via gate insulating film 64. Formed on the back surface of the n semiconductor substrate 200, a source electrode 71 formed on the n source region 67 and the p contact region 68, and an n drain region.69And a drain electrode 72 formed thereon. The surface height K of the gate electrode 65 in the trench 63 is lower than the surface height of the n source region 67, and the drop D thereof is63Different on the left and rightRu. Further, the surface of the gate electrode 65 is wavy in the depth direction. This is because the polycrystalline silicon is etched back by isotropic etching. Also, as shown in FIG. 34, isotropic etching has poor shape controllability, and the surface height K of the gate electrode 65 in the trench 63 is still in the p base region 62 before the n source region 67 is formed. The height D becomes lower than the surface height, and the drop D varies in the trench 63. Therefore, as shown in FIG. 36, the diffusion depth of the n source regions 67a and 67 varies depending on the location. In the drawing, the diffusion depth W1 of the left n source region 67a is deeper than the diffusion depth W2 of the right n source region 67, and the diffusion depth W1 in the foreground of the same right n source region 67a is the same. Is deeper than the diffusion depth W3. This is because the surface height of the gate electrode 65 varies depending on the location, and the p base region62This is because impurities are implanted by ion implantation from the exposed trench sidewall.
[0004]
  The variation in the diffusion depth of the n source region 67 occurs within the wafer surface or between lots, and the variation becomes a variation in electrical characteristics such as a gate threshold voltage, which decreases the yield rate. In addition, as shown in FIG. 34B, the surface height H of the gate lead line 66 formed on the p base region 62 is higher than the surface height G of the gate electrode 65.
[0005]
  As for the planarization of polycrystalline silicon filling the trench 63 portion for forming the gate electrode 65, as a conventional technique, when planarization is performed by isotropic etching (for example, see Patent Document 1), LOCOS oxidation is performed. In an integrated circuit device in which a film is formed, the gate electrode is planarized by multi-stage oxidation and etching in which oxidation and etching are repeated several times (see, for example, Patent Document 2) or when planarization is performed using a CMP method. (For example, refer to Patent Document 2 and Patent Document 3).
[0006]
[Patent Document 1]
  Japanese Unexamined Patent Publication No. 2000-277531 (5th page, FIG. 14, FIG. 15)
[Patent Document 2]
  JP 2000-196075 A (pages 7-8, FIG. 7)
[Patent Document 3]
  Japanese Patent Laid-Open No. 11-74514 (page 6, FIG. 3)
[0007]
[Problems to be solved by the invention]
  However, as in Patent Document 1, in isotropic etching, as shown in FIG. 35, the thickness of the polycrystalline silicon around the opening of the trench, which is a connection point between the gate lead-out line and the gate electrode, is reduced. In some cases, the gate insulating film is exposed (when the over-etching is remarkable). As a result, the connection resistance between the gate lead-out line and the gate electrode increases or is disconnected.
[0008]
  In order to avoid this, if the amount of polycrystalline silicon etch-back is reduced, polycrystalline silicon etch residue may occur in the surface region, which may cause defects in the formation of the source region and reduce the yield rate. is there.
  Also, as shown in FIG. 37, since the opening of the trench 63 (upper part of the trench) is filled with the insulating film 70, the difference in thermal expansion coefficient between the semiconductor substrate (n source regions 67a, 67 and p base region 62) is increased. As a result, stress is generated in a high-temperature process, and the reliability such that a crack 80 enters the semiconductor substrate and a leakage current increases is reduced.
[0009]
  In addition, the multistage oxidation method disclosed in Patent Document 2 has low mass productivity and increases manufacturing costs.
  Further, Patent Document 2 describes that a CMP (Chemical Mechanical Polishing) method can also be applied. However, as shown in FIG. 38, if the distance between the LOCOS oxide film 81 and the p base region 62 is too small, the LOCOS oxide film is used. Polycrystalline silicon remains on the n source region 67 adjacent to 81 (residual polycrystalline silicon 82), and the subsequent formation of the n source region 67 is not performed normally, and good electrical characteristics cannot be obtained. Further, in the CMP method, since the polycrystalline silicon formed on the LOCOS oxide film 81 disappears, a gate lead-out line cannot be formed.
[0010]
  Further, although the application of the CMP method is described in Patent Document 3, the gate lead-out line which is a portion 6B in FIG. 3 of this Patent Document is removed by the planarization process of the CMP method (dotted line in FIG. 39). The gate lead line 66 shown in FIG.
  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device having a trench gate structure with high reliability and low cost, which can solve the above-described problems and obtain good electrical characteristics.
[0011]
[Means for Solving the Problems]
  To achieve the above objective,
1) In a method for manufacturing a semiconductor device having a trench gate,
  Forming a second conductive type second semiconductor region on a surface of the first conductive type first semiconductor region, and a first insulating film having an opening at a first portion for forming a trench on the second semiconductor region; Forming a trench, penetrating the second semiconductor region using the opened first insulating film as a mask, and forming a trench reaching the first semiconductor region; and forming a gate lead line connected to the gate electrode Opening the first insulating film at two locations, and the trainAlsoA gate insulating film is formed on the entire surface including the trench.AlsoIn addition, polycrystalline silicon serving as a gate electrode and a gate lead-out line is formed on the gate insulating film,WithFilling the opening of the first insulating film at the second location with polycrystalline silicon; and planarizing the polycrystalline silicon until the gate insulating film surface on the first insulating film is exposed. Remove the TrenToA step of making the surface height of the polycrystalline silicon to be the gate electrode formed equal to the surface height of the gate insulating film on the first insulating film, and the first insulating film and the gate insulating film on the second semiconductor region And selectively forming a third semiconductor region of the first conductivity type in contact with the trench on the surface of the second semiconductor region using the polycrystalline silicon serving as the gate electrode and a photoresist as a mask. Let it be a manufacturing method.
2) In a method for manufacturing a semiconductor device having a trench gate,
  A step of forming the second conductive type second semiconductor region on the surface of the first conductive type first semiconductor region, and opening a first portion for forming the trench, and forming a gate lead line connected to the gate electrode. Second locationForming a first insulating film having a recess in the second semiconductor region;Using the opened first insulating film as a mask, forming a trench that penetrates the second semiconductor region and reaches the first semiconductor region, forming a gate insulating film on the entire surface, and Forming polycrystalline silicon on the film,WithFilling the recess with the polycrystalline silicon; planarizing the polycrystalline silicon; removing the polycrystalline silicon until the gate insulating film surface on the first insulating film is exposed;ToA step of making the surface height of the polycrystalline silicon to be the gate electrode formed equal to the surface height of the gate insulating film on the first insulating film, and the first insulating film and the gate insulating film on the second semiconductor region And selectively forming a third semiconductor region of the first conductivity type in contact with the trench on the surface of the second semiconductor region using the polycrystalline silicon serving as the gate electrode and a photoresist as a mask. Let it be a manufacturing method.
3) In a method for manufacturing a semiconductor device having a trench gate,
  Forming a second conductive type second semiconductor region on the surface of the first conductive type first semiconductor region, and forming a first insulating film having an opening at a first location for forming a first trench to be a trench; A step of forming on the second semiconductor region; a step of forming a shallow trench using the opened first insulating film as a mask; and a first insulation at a second location for forming a gate lead line connected to the gate electrode. A shallow trench is etched deeper using the first insulating film having openings in the first and second locations as a mask, and reaches the first semiconductor region through the second semiconductor region. Forming the first groove to be a trench at the same time as forming the second groove in the second semiconductor region at the second location; forming a gate insulating film on the entire surface; Forming crystalline silicon, and said first groove and And filling a serial second groove in polycrystalline silicon, to planarize the polycrystalline silicon, removal of the polycrystalline silicon until the gate insulating film surface on the second semiconductor region is exposed, the trainToA step of making the surface height of the polycrystalline silicon to be the gate electrode formed equal to the surface height of the gate insulating film formed on the surface of the second semiconductor region, and removing the gate insulating film on the second semiconductor region; And a table of the second semiconductor regionOn the faceAnd a method of selectively forming a third semiconductor region of the first conductivity type in contact with the trench using the gate electrode and the photoresist as a mask.
4) In a method of manufacturing a semiconductor device having a trench gate and a LOCOS oxide film (selective oxide film),
  Forming a second conductive type second semiconductor region on a surface of the first conductive type first semiconductor region surrounded by the LOCOS oxide film; and forming a first insulating part having an opening in the first part forming the trench. Forming a film on the second semiconductor region and the LOCOS oxide film, and forming a trench reaching the first semiconductor region through the second semiconductor region using the opened first insulating film as a mask; A step, a step of opening a first insulating film at a second location for forming a gate lead line connected to the gate electrode including the LOCOS oxide film, a gate insulating film is formed on the entire surface, and the gate insulating film is formed on the gate insulating film. Forming polycrystalline silicon, andWithFilling the opening of the first insulating film in the second location with polycrystalline silicon, planarizing the polycrystalline silicon, and removing the polycrystalline silicon until the gate insulating film on the first insulating film is exposed And the TrenToA step of making the surface height of polycrystalline silicon to be the formed gate electrode equal to the surface height of the gate insulating film on the first insulating film;Not coated with the polycrystalline silicon,A first insulating film and a gate insulating film on the second semiconductor region and the LOCOS oxide film;ExcludingAnd a step of selectively forming a third semiconductor region of the first conductivity type in contact with the trench on the surface of the second semiconductor region using the polycrystalline silicon serving as the gate electrode and a photoresist as a mask. The method.
5) In a method for manufacturing a semiconductor device having a trench gate and a LOCOS oxide film,
  A step of forming the second conductive type second semiconductor region on the surface of the first conductive type first semiconductor region, and opening a first portion for forming the trench, and forming a gate lead line connected to the gate electrode. Forming a first insulating film having a recess in a second location on the second semiconductor region and the LOCOS oxide film; and using the opened first insulating film as a mask, Forming a trench penetrating and reaching the first semiconductor region; forming a gate insulating film on the entire surface; forming polycrystalline silicon on the gate insulating film;WithFilling the recess of the second portion including the LOCOS oxide film with polycrystalline silicon; planarizing the polycrystalline silicon; and polycrystalline silicon until the gate insulating film on the first insulating film is exposed. Remove the TrenToA step of making the surface height of polycrystalline silicon to be the formed gate electrode equal to the surface height of the gate insulating film on the first insulating film;Not coated with the polycrystalline silicon,A first insulating film and a gate insulating film on the second semiconductor region and the LOCOS oxide film;ExcludingAnd a step of selectively forming a third semiconductor region of the first conductivity type in contact with the trench on the surface of the second semiconductor region using the polycrystalline silicon serving as the gate electrode and a photoresist as a mask. The method.
6) In a method for manufacturing a semiconductor device having a trench gate and a LOCOS oxide film,
  Forming a second conductive type second semiconductor region on a surface of the first conductive type first semiconductor region;On the second semiconductor regionA first portion for forming the trench is opened, and a recess is formed in the second portion for forming the gate lead line connected to the gate electrode.The concave portion of the second location becomes a concave portion reaching the LOCOS oxide film on the LOCOS oxide film.A first insulating film on the second semiconductor region;And on the LOCOS oxide filmAnd forming a trench that penetrates the second semiconductor region and reaches the first semiconductor region using the opened first insulating film as a mask, forming a gate insulating film on the entire surface, and Forming polycrystalline silicon on the film;WithFilling the concave portion of the second portion with polycrystalline silicon; planarizing the polycrystalline silicon; removing the polycrystalline silicon until the gate insulating film surface on the second semiconductor region is exposed; and A step of making the surface height of the polycrystalline silicon equivalent to the surface height of the gate insulating film formed on the surface of the second semiconductor region;On the second semiconductor region and the LOCOS oxide film not covered with the polycrystalline siliconThe gate ofInsulation filmAnd the first insulating film is removed, and a surface of the second semiconductor region is removed.On the faceAnd a method of selectively forming a third semiconductor region of the first conductivity type in contact with the trench using the gate electrode and the photoresist as a mask.
7) In the manufacturing method of 1), 2), 4) to 6), the planarization may be performed using a CMP method using the first insulating film and the gate insulating film as stopper layers.
8) In the manufacturing method of 3), the planarization may be performed using a CMP method using the gate insulating film as a stopper layer.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
  FIG. 1 is a block diagram of a semiconductor device according to a first embodiment of the present invention. FIG. 1 (a) is a perspective sectional view of an essential part, and FIG. 1 (b) is a schematic view of FIG. FIG. In FIG. 5B, the interlayer insulating film 10 and the source electrode 11 are omitted.
  2 is a cross-sectional view of the main part of FIG. 1B, FIG. 2A is a cross-sectional view of the main part taken along line XX of FIG. 1B, and FIG. It is principal part sectional drawing cut | disconnected by the YY line of (b). In this semiconductor device, a MOSFET is shown as an example.
[0013]
  1 and 2, this trench gate structure MOSFET includes a p base region 2 formed on the surface of an n semiconductor substrate 100 and an n source region 7 formed in contact with the trench 3 on the surface of the p base region 2. A p contact region 8 for making contact with the p base region 2, a gate electrode 5 formed in the trench 3 via the gate insulating film 4, a gate electrode 5, and a gate insulating film 4 Formed on the back surface of the n semiconductor substrate 100, the n source region 7 and the p contact region.8It has a source electrode 11 formed on top and a drain electrode 12 formed on n drain region 9. The surface height A of the gate electrode is made equal to or higher than the surface height B of the n source region (same as the surface height of the p base region before forming the n source region) B. Further, the surface height A of the gate electrode and the surface height C of the gate lead-out line are made equal.
[0014]
  If a p collector region is formed instead of the n drain region 9, an IGBT having a trench gate structure is manufactured. In this case, the n source region 7 is called an n emitter region, the source electrode 11 is called an emitter electrode, and the drain electrode 12 is called a collector electrode. In addition to the MOSFET, the present invention may be applied to each device such as an IGBT having a trench gate structure on the surface and an insulated gate thyristor. Further, the trench pattern is exemplified as a stripe shape, but it is not necessarily a stripe shape, and may be a donut shape pattern, a lattice pattern, or a circular pattern.
[0015]
  FIGS. 3 to 9 are cross-sectional views of the main part manufacturing process shown in the order of steps in the method of manufacturing the semiconductor device of the first embodiment. The manufacturing process sectional view of (a) in each figure is a sectional view cut along line XX in FIG. 1 (b), (b) is a sectional view cut along line YY in FIG. 1 (b), ( c) is a perspective sectional view. First, the p base region 2 is formed in the surface layer of the high resistance n semiconductor substrate 100. Next, a thick insulating film 21 is formed on the surface of the p base region 2 by thermal oxidation or CVD. The material of the thick insulating film 21 is preferably an oxide film or a nitride film. At this time, the thickness of the thick insulating film 21 is at least 500 nm or more, preferably 800 nm or more and about 1 μm. Subsequently, an opening 22 is formed in the thick insulating film 21 using a mask (not shown). Next, using the remaining thick insulating film 21 as a mask, at least the p base region 2 is passed, and a trench 3 reaching the n semiconductor substrate 100 (undiffused region 1) is formed by dry etching or anisotropic wet etching (FIG. 3). .
[0016]
  Next, after the trench 3 is formed, a cleaning process is performed with a diluted solution of hydrofluoric acid to clean the inside of the trench 3. At this time, the end portion of the thick insulating film 21 is etched back so that it slightly recedes from the trench opening 22 (recessed portion 24). The receding distance is preferably in the range of 1/10 to 1/2 of the trench width.
  For example, when the trench width is 1 μm, the receding distance is set in the range of 100 nm to 500 nm. Next, damage removal by sacrificial oxidation and sacrificial oxidation are performed, and the inner wall of the trench is thinned to improve the crystal quality. At this time, when the sacrificial oxidation is finished, a part of the thick insulating film 21 is etched using a mask (not shown) to form the opening 23. The gate lead-out line 6 is formed using this opening 23. The step of forming the opening 23 does not necessarily have to be performed after the sacrificial oxidation, but since the photoresist enters the trench in this step, the surface of the p-type base region 2 is not contaminated on the inner wall of the trench. It is desirable to coat with. After the completion of this step, the sacrificial oxide film is removed, and the p base region 3 is exposed again on the inner wall of the trench (FIG. 4).
[0017]
  Next, the gate insulating film 4 is formed, and the trench 3 and the opening 23 are filled with polycrystalline silicon 25 doped with n-type which is a gate electrode material. The polycrystalline silicon 25 is preferably deposited by CVD. The polycrystalline silicon 25 completely fills the trench 3, and even when the surface height of the polycrystalline silicon 25 is the lowest, it is higher than the highest surface height of the thick insulating film 21 and the gate insulating film 4. It is desirable (FIG. 5).
[0018]
  Next, using the thick insulating film 21 and the gate insulating film 4 as a stop layer, a planarization process is performed on the polycrystalline silicon to be the gate electrode 5 and the gate lead line 6. In this step, a CMP (Chemical Mechanical Polishing) apparatus, a CDE (Chemical Dry Etching) apparatus, an RIE (Reactive Ion Etching) apparatus, or the like is preferably used. In particular, a CMP method using a CMP apparatus has a highly controllable process because the polishing rate selection ratio between the polycrystalline silicon film 25 and the oxide film (the gate insulating film 4 and the thick insulating film 21) is about 100 or more and about 500. Can do. In this step, the polycrystalline silicon to be the gate lead-out line 6 formed in the opening 23 remains without being removed and can be used effectively as the gate lead-out line 6. At this time, the surface height of the gate electrode 5 after the planarization is made equal to the surface height of the gate insulating film 4 on the thick insulating film 21 (FIG. 6).
[0019]
  Next, portions of the thick insulating film 21 and the gate insulating film 4 that are not covered with the gate electrode 5 and the gate lead-out line 6 are removed by dry etching or wet etching. In this step, it is desirable to perform anisotropic dry etching so that the gate insulating film 4 is not overetched and the gate electrode 5 and the gate lead-out line 6 are not lifted up. By this etching, the gate electrode 5 and the gate lead line 6 are also etched, but the surface height A of the gate electrode 5 is made equal to or higher than the surface height B of the p base region 2. The figure shows a high case (FIG. 7).
[0020]
  Next, a screen oxide film 26 is formed on the surface of the p base region 2 in order to form the n source region 7 of the MOSFET by ion implantation. At this time, the surface of the gate electrode 5 is also oxidized, and the corners of the gate electrode 5 are chamfered. Subsequently, ion implantation 28 of n-type impurity 29 is performed using the photoresist 27 as a mask (FIG. 8).
[0021]
  Next, driving is performed, and the n-type impurity 29 is sufficiently diffused and simultaneously activated to form the n source region 7. Next, a p-contact region 8, an interlayer insulating film 10 made of PSG or the like, and a source electrode 11 are formed, and an n-drain region 9 is formed on the surface layer on the back surface of the n-semiconductor substrate 100. The drain electrode 12 to be formed is formed, and the trench MOSFET is completed (FIG. 9).
[0022]
  According to this step, the n source region 7 can be formed in a self-aligning manner using the gate electrode 5 as a mask. In addition, since the corners of the gate electrode 5 are chamfered during the process, the risk of breaking through the interlayer insulating film 10 can be reduced.
  As described above, since the surface height of the gate electrode 5 is equal to or higher than the surface height of the p base region 2, the subsequent arsenic ion implantation for forming the n source region 7 is performed at the upper portion of the opening of the trench 3. Since it is driven from the surface of the p base region 2 without being driven from the side wall, the diffusion depth of the n source region 7 can be formed to have a predetermined depth. As a result, the variation in gate threshold voltage is reduced, and the yield rate can be improved.
[0023]
  Further, since the gate electrode 5 is filled up to the upper portion of the trench opening, the interlayer insulating film 10 does not fill the upper portion of the trench as in the prior art, and therefore, no crack is generated and the gate leakage current increases. And high reliability.
  In addition, even if the planarization process by the CMP method is performed by forming the opening 23 in the thick insulating film 21, the gate lead-out line 6 does not disappear, and the polycrystal is formed at the connection portion with the gate electrode 5. Silicon is neither thinned nor disconnected.
[0024]
  Further, since the planarization is performed by the CMP method, the cost can be reduced as compared with the multi-stage oxidation method.
  FIG. 10 is a block diagram of a semiconductor device according to the second embodiment of the present invention. FIG. 10 (a) corresponds to FIG. 2 (a), and FIG. 10 (b) corresponds to FIG. 2 (b). FIG.
  FIGS. 11A and 11B are main part manufacturing process diagrams of the semiconductor device of the second embodiment. FIG. 11A corresponds to FIG. 3A, and FIG. 11B corresponds to FIG. FIG. 3C is a diagram corresponding to FIG.
[0025]
  The difference from the first embodiment is that the recessed portion 31 is formed in the thick insulating film 21 in the gate lead-out line 6. That is, in addition to the opening 22 for forming the trench 3, the recess 31 for forming the gate lead line 6 is formed in the thick insulating film 21. The subsequent steps are the same as those in the first embodiment. Also in this case, the effect described in the first embodiment can be obtained.
[0026]
  A method for forming the recess will be described. A thick insulating film 21 is formed on the surface of the p base region 2, and a region corresponding to the trench 3 is formed as silicon in the p base region 2.ButEtch by dry etching until exposed. Next, the region of the lead line 6 is etched by a dry etching method or the like so that the insulating film 21 remains so that the silicon in the p base region 2 is not exposed. In the next trench 3 formation process, it is necessary to adjust the thickness of the insulating film 21 so that the insulating film 21 is not worn out and stepped out.
[0027]
  FIGS. 12A and 12B are configuration diagrams of a semiconductor device according to a third embodiment of the present invention. FIG. 12A is a perspective sectional view of an essential part, and FIG. 12B is a schematic view of FIG. FIG. In FIG. 5B, the interlayer insulating film 10 and the source electrode 11 are omitted.
  13 is a cross-sectional view of the main part of FIG. 12B, FIG. 13A is a cross-sectional view of the main part taken along line XX of FIG. 12B, and FIG. It is principal part sectional drawing cut | disconnected by the YY line of (b). In this semiconductor device, a MOSFET is shown as an example.
[0028]
  The difference from the first embodiment is that the gate lead-out line 6 is formed by forming a groove in the p base region 2 and filling the groove with polycrystalline silicon. Also in this case, the effect described in the first embodiment can be obtained.
  FIGS. 14 to 19 are cross-sectional views of the main part manufacturing process shown in the order of steps in the method of manufacturing the semiconductor device of the third embodiment. The manufacturing process sectional view of (a) of each figure is a sectional view cut along line XX of FIG. 12 (b), (b) is a sectional view cut along line YY of FIG. 12 (b), ( c) is a perspective sectional view.
[0029]
  When forming the opening 22 in the insulating film 41 and performing trench etching in a process corresponding to the process of FIG. 3, the trench etching is interrupted halfway, and the gate lead line 6 isDeployInsulating film 41 in the regionTo form another opening 23Then, trench etching is performed again. As a result, a shallow groove 42 (concave portion) is formed at the position of the gate lead-out line 6 (FIG. 14).
[0030]
  Next, a gate insulating film 4 is formed on the surface, and subsequently, polycrystalline silicon 25 as a gate electrode material is adhered to the entire surface (FIG. 15).
  Next, a planarization process is performed by a CMP method or the like, and the shape is controlled so that the surface of the polycrystalline silicon 25 and the surface of the gate insulating film 4 coincide. The polishing selectivity in the CMP method is 100 or more. If the thickness of the gate electrode 4 is set to 800 nm or less even in the thickest place, the gate insulating film 4 is usually 50 nm or more, so that there is no danger of the gate insulating film 4 being stepped out in the planarization step. At this time, the surface heights of the gate electrode 5 and the gate lead-out line 6 are equal (FIG. 16).
[0031]
  Next, a region of the gate insulating film 4 that is not covered with the gate electrode 5 and the gate lead line 6 is removed by wet etching or dry etching (FIG. 17).
  Next, a screen oxide film 26 is formed on the surface, and ion implantation 28 of n-type impurity 29 is performed using the photoresist 27 as a mask (FIG. 18).
[0032]
  Next, an n source region 7 is formed by driving, and a p contact region 8 is further formed. Next, the n-type drain region 9 is formed on the interlayer insulating film 10, the source electrode 11, and the surface layer on the back surface of the n-semiconductor substrate 100, and the drain electrode 12 in contact with the n-type drain region 9 is formed. Is completed (FIG. 19). Also in this case, the effect described in the first embodiment can be obtained.
[0033]
  20A and 20B are configuration diagrams of a semiconductor device according to a fourth embodiment of the present invention. FIG. 20A is a perspective sectional view of an essential part, and FIG. 20B is a view of FIG. FIG. In FIG. 5B, the interlayer insulating film 10 and the source electrode 11 are omitted.
  21 is a cross-sectional view of main parts cut along line XX in FIG. 20 (b), FIG. 22 is a cross-sectional view of main parts cut along line Y1-Y1 in FIG. 20 (b), and FIG. FIG. 24 is a fragmentary cross-sectional view taken along line Y3-Y3 of FIG. 20B. In this semiconductor device, a MOSFET is shown as an example. This shows the case where a LOCOS oxide film is provided.
[0034]
  20 to 24, this MOSFET having a trench gate structure includes a p base region 2 formed on the surface of an n semiconductor substrate 100, and an n source region 7 formed in contact with the trench 3 on the surface of the p base region 2. A p-contact region 8 that contacts the p-base region 2, a gate electrode 5 formed in the trench 3 via a gate insulating film 4, and a gate electrode 5, and a LOCOS oxidation via the gate insulating film 4. Gate lead line 6 also formed on film 51, n drain region 9 formed on the back surface of n semiconductor substrate 100, source electrode 11 formed on n source region 7 and p contact region 8, and n And a drain electrode 12 formed on the drain region 9. The surface height of the gate electrode 5 is made equal to or higher than the surface height of the n source region 7 (the surface height of the p base region 2 before forming the n source region).
[0035]
  Further, by setting the distance L between the end of the LOCOS oxide film and the end of the n source region 7 to 4 μm or more, it is possible to prevent polycrystalline silicon from remaining on the surface of the p base region 2 before forming the n source region 7, A predetermined n source region 7 can be formed.
  FIG. 25 to FIG. 28 are cross-sectional views of the main part manufacturing process shown in the order of steps in the semiconductor device manufacturing method of the fourth embodiment.
First, a LOCOS oxide film 51 having a thickness of 800 nm or more is formed on the surface of the high resistance n semiconductor substrate 100 (a thick oxide film is formed by thermal oxidation, leaving a portion corresponding to the LOCOS oxide film, The p base region 2 may be formed on the surface layer of the n semiconductor substrate 100 in the region surrounded by the LOCOS oxide film 51. The figure shows a part (FIG. 25).
[0037]
  Next, a thick insulating film 21 is formed on the surface of the p base region 2 and the LOCOS oxide film 51 by thermal oxidation or CVD. The material of the thick insulating film 21 is preferably an oxide film or a nitride film. At this time, the thickness of the thick insulating film 21 is at least 500 nm or more, preferably 800 nm or more and about 1 μm. Subsequently, an opening 22 is formed in the thick insulating film 21 using a mask (not shown). Next, using the remaining thick insulating film 21 as a mask, the trench 3 reaching at least the p base region 2 and reaching the n semiconductor substrate 100 (undiffused region 1) is formed by dry etching or anisotropic wet etching. Next, after the trench 3 is formed, a cleaning process is performed with a diluted solution of hydrofluoric acid to clean the inside of the trench 3. At this time, the end of the thick insulating film 21 is etched back so that it slightly recedes from the opening of the trench 3.
[0038]
  The receding distance is preferably in the range of 1/10 to 1/2 of the trench width. For example, when the trench width is 1 μm, the receding distance is set in the range of 100 nm to 500 nm. Next, damage removal by sacrificial oxidation and sacrificial oxidation are performed, and the inner wall of the trench is thinned to improve the crystal quality.
  At this time, an opening 23 for the gate lead-out line 6 is formed in the thick insulating film 21 including the thick insulating film 21 formed on the LOCOS oxide film 51 by using a mask (not shown) at the stage where the sacrificial oxidation is completed. Form. The gate lead line 6 is also formed on the LOCOS oxide film 51 using the opening 23. The step of forming the opening 23 is not necessarily performed after the sacrificial oxidation. However, since the photoresist enters the trench 3 in this step, the surface of the p base region 2 is not contaminated on the inner wall of the trench 3. It is desirable to cover with a sacrificial oxide film. After the completion of this step, the sacrificial oxide film is removed, and the p base region 2 is exposed again on the inner walls of the trench 3 and the opening 23 (FIG. 26).
[0039]
  Next, the gate insulating film 4 is formed, and the trench 3 and the opening 23 are filled with polycrystalline silicon doped in n-type which is a gate electrode material. This polycrystalline silicon is preferably deposited by CVD. The polycrystalline silicon completely fills the trench, and it is desirable that the position where the surface height of the polycrystalline silicon is the lowest is higher than the position where the surface height of the thick insulating film 21 and the gate insulating film 4 is the highest. . Next, using the thick insulating film 21 and the gate insulating film 4 as a stop layer, a planarization process is performed on the polycrystalline silicon to be the gate electrode 5 and the gate lead-out line 6. A CMP apparatus or a CDE apparatus is preferably used for this step. In particular, in the CMP method, since the selection ratio of the polishing rate between the polycrystalline silicon film and the oxide film is about 100 or more and about 500, processing with high controllability can be performed. In this step, the polycrystalline silicon to be the gate lead line 6 formed in the opening 23 remains without being removed and can be used as the gate lead line 6. At this time, the surface height of the gate electrode 5 after the planarization is equal to the surface height of the gate insulating film 4 on the thick insulating film 21. Next, portions of the thick insulating film 21 and the gate insulating film 4 that are not covered with the gate electrode 5 and the gate lead-out line 6 are removed by dry etching or wet etching. In this step, it is desirable to perform anisotropic dry etching so that the gate insulating film 4 is not overetched and the gate electrode 5 and the gate lead line 6 are not lifted. The surface height of the gate electrode 5 after this etching is made equal to or higher than the surface height of the p base region 2 (FIG. 27).
[0040]
  Next, a screen oxide film (not shown) is formed on the surface of the p base region 2 in order to form the n source region 7 of the MOSFET by ion implantation. At this time, the surface of the gate electrode 5 is also oxidized, and the corners of the gate electrode 5 are chamfered. Subsequently, n-type impurity ions are implanted using a photoresist (not shown) as a mask. Next, driving is performed, and n-type impurities are sufficiently diffused and activated at the same time to form an n source region 7. Next, a p-contact region 8, an interlayer insulating film 10 made of PSG or the like, and a source electrode 11 are formed, and an n-drain region 9 is formed on the surface layer on the back surface of the n-semiconductor substrate 100. The drain electrode 12 to be formed is formed, and the trench type MOSFET having the gate lead line 6 flattened by the CMP method on the LOCOS oxide film 51 is completed (FIG. 28).
[0041]
  In the planarization process when the distance L between the LOCOS oxide film edge and the n source region edge is short, polycrystalline silicon remains on the p base region where the n source region is to be formed.
  Therefore, the distance L is set to 4 μm or more in a normal LOCOS oxide film thickness (about several hundred nm), so that the p base region 2 where the n source region is to be formed is formed by CMP as shown in FIG. Polycrystalline silicon does not remain on the surface, and a predetermined n source region 7 can be formed. Therefore, the distance L is preferably 4 μm or more. Further, there is no problem because the thick insulating film 21 exists under the residual polycrystalline silicon 53, and the p base region 2 and the residual polycrystalline silicon 53 are electrically insulated by the thick insulating film 21 at this location. Further, since the amount of residual silicon is extremely small, it may be removed by performing isotropic etching for a short time. In this case, since the etching time is short, the surface height of the gate electrode 5 does not fall below the surface height of the n source region 7.
[0042]
  By using this manufacturing method, the gate lead line 6 can be formed on the LOCOS oxide film 51 by a planarization process by the CMP method.
  Also in this case, the effects described in the first embodiment can be obtained.
  FIG. 29 is a fragmentary cross-sectional view of the semiconductor device according to the fifth embodiment of the present invention, corresponding to FIG. This is also the case with a LOCOS oxide film.
[0043]
  The difference from the fourth embodiment is that the gate lead-out line 6 is formed in the thick insulating film 21 and formed in the recess 31.
  FIG. 30 is a perspective view of a manufacturing process of a main part of the semiconductor device according to the fifth embodiment. This figure corresponds to FIG. Trench3Opening for forming22In addition, a recess 31 for forming the gate lead-out line 6 is formed in the thick insulating film 21.Is different.The manufacturing process isThis is the same as the process of the fourth embodiment. Also in this case, the effect described in the first embodiment can be obtained.
[0044]
  As shown in FIG. 31, when the recess 31 is formed in the thick insulating film 21 on the LOCOS oxide film 51, it is thick.Insulationfilm21The recess 52 may be formed by breaking through the upper layer portion of the LOCOS oxide film 51.
[0045]
【The invention's effect】
  According to the present invention, by providing an opening or recess for a gate lead line in a thick insulating film that is a mask when forming a trench, planarization by CMP of polycrystalline silicon filling the trench and recess is achieved. It is possible to prevent the connection portion between the gate electrode and the gate lead-out line from being thinned or disconnected.
[0046]
  Further, by planarization by CMP, the surface height of the gate electrode can be made equal to the surface height of the n source region (the surface height of the p base region before forming the n source region). By equalizing the surface height, variation in the diffusion depth of the n source region is reduced, variation in electrical characteristics (gate threshold voltage, channel resistance, etc.) can be reduced, and the yield rate is increased. Can do.
[0047]
  In addition, since the surface height is equal, the upper part of the opening of the trench is filled with polycrystalline silicon, which can suppress the occurrence of cracks generated in the prior art, the leakage current is also suppressed, and high reliability is achieved. can do.
  Further, when the CMP method is used for the planarization treatment of the polycrystalline silicon, the mass productivity is superior to the multi-stage oxidation method, and the cost can be reduced.
[0048]
  Even when the LOCOS oxide film is provided, the gate lead-out line can be planarized by CMP on the LOCOS oxide film. Further, by setting the distance between the end of the LOCOS oxide film and the planned location of the n source region to 4 μm or more, the polycrystalline silicon on the p base region at the planned location of the n source region can be removed by planarization, A predetermined p base region can be formed.
[Brief description of the drawings]
1A and 1B are configuration diagrams of a semiconductor device according to a first embodiment of the present invention, in which FIG. 1A is a perspective cross-sectional view of a main part, and FIG. 1B is a plan view of a main part when FIG.
2A and 2B are cross-sectional views of the main part of FIG. 1B, where FIG. 1A is a cross-sectional view of the main part taken along line XX of FIG. 1B, and FIG. Cross-sectional view of main parts cut along line Y-Y
FIG. 3 is a cross-sectional view of the main part manufacturing process of the semiconductor device of the first embodiment.
4 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the first embodiment, following FIG. 3;
FIG. 5 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the first embodiment, following FIG. 4;
6 is a cross-sectional view of the essential part manufacturing process of the semiconductor device of the first embodiment, following FIG. 5;
7 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the first embodiment, following FIG. 6;
8 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the first embodiment, following FIG. 7;
9 is a cross-sectional view of the essential part manufacturing process of the semiconductor device of the first embodiment, following FIG. 8;
10A and 10B are configuration diagrams of a semiconductor device according to a second embodiment of the present invention, in which FIG. 10A is a diagram corresponding to FIG. 2A, and FIG. 10B is a diagram corresponding to FIG.
11A and 11B are main part manufacturing process diagrams of the semiconductor device of the second embodiment, in which FIG. 11A is a view corresponding to FIG. 3A, FIG. 11B is a view corresponding to FIG. ) Is a figure corresponding to FIG.
12A and 12B are configuration diagrams of a semiconductor device according to a third embodiment of the present invention, in which FIG. 12A is a perspective cross-sectional view of the main part, and FIG. 12B is a plan view of the main part when FIG.
13A and 13B are cross-sectional views of the main part of FIG. 12B, where FIG. 12A is a cross-sectional view of the main part taken along the line XX of FIG. 12B, and FIG. Cross-sectional view of main parts cut along line Y-Y
FIG. 14 is a cross-sectional view of the main part manufacturing process of the semiconductor device of the third embodiment.
FIG. 15 is a cross-sectional view of the essential part manufacturing process of the semiconductor device of the third embodiment, following FIG. 14;
FIG. 16 is a cross-sectional view of the essential part manufacturing process of the semiconductor device of the third embodiment, following FIG. 15;
FIG. 17 is a cross-sectional view of the essential part manufacturing process of the semiconductor device of the third embodiment, following FIG. 16;
FIG. 18 is a cross-sectional view of the essential part manufacturing process of the semiconductor device of the third embodiment, following FIG. 17;
FIG. 19 is a cross-sectional view of the essential part manufacturing process of the semiconductor device of the third embodiment, following FIG. 18;
20A and 20B are configuration diagrams of a semiconductor device according to a fourth embodiment of the present invention, where FIG. 20A is a perspective cross-sectional view of main parts and FIG. 20B is a plan view of main parts when FIG.
FIG. 21 is a cross-sectional view of the main part taken along line XX in FIG.
22 is a cross-sectional view of a principal part taken along the line Y1-Y1 in FIG.
23 is a cross-sectional view of a principal part taken along line Y2-Y2 in FIG. 20 (b).
24 is a cross-sectional view of a principal part taken along line Y3-Y3 in FIG. 20 (b).
25 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the fourth embodiment; FIG.
FIG. 26 is a cross-sectional view of the essential part manufacturing process of the semiconductor device of the fourth embodiment, following FIG. 25;
FIG. 27 is a cross-sectional view of the essential part manufacturing process of the semiconductor device of the fourth embodiment, following FIG. 26;
FIG. 28 is a cross-sectional view of the essential part manufacturing process of the semiconductor device of the fourth embodiment, following FIG. 27;
29 is a fragmentary cross-sectional view of the semiconductor device according to the fifth embodiment of the present invention, corresponding to FIG. 24.
30 is a perspective cross-sectional view of the essential part manufacturing process of the semiconductor device according to the fifth embodiment, corresponding to FIG. 26;Perspective sectional view
FIG. 31 shows a recess formed in the upper layer portion of the LOCOS oxide film.cross sectionFigure
FIG. 32 shows polycrystalline silicon remaining on the LOCOS oxide film and on the semiconductor substrate.Plan view showing
33 is a configuration diagram of a conventional trench gate type MOSFET, in which (a) is a perspective cross-sectional view of the main part, and (b) is a plan view of the main part viewed from the arrow F in FIG.
34 (b) is a cross-sectional view of the main part of FIG. 32 (b), (a) is a cross-sectional view of the main part taken along line XX of FIG. 1 (b), and (b) is a cross-sectional view of FIG. Cross-sectional view of main parts cut along line Y-Y
FIG. 35 The connection part between the gate lead-out line and the gate electrode is thinned.Sectional view showing the part
FIG. 36 shows the diffusion depth of the n source region depending on the location.A perspective sectional view showing
FIG. 37 shows a crack in the semiconductor substrate.Cross section showing state
FIG. 38 shows the case where residual polycrystalline silicon exists in the LOCOS oxide film.cross sectionFigure
FIG. 39 shows the gate lead line disappeared by the planarization process by the CMP method.Cross section showing stateFigure
[Explanation of symbols]
          1 Undiffused region (n drift region) of n semiconductor substrate
          2 p base region
          3 Trench
          4 Gate insulation film
          5 Gate electrode
          6 Gate leader line
          7 n source region
          8 p contact region
          9 n drain region
        10 Interlayer insulation film
        11 Source electrode
        12 Drain electrode
        21 Thick insulating film
        22 opening
        23 opening
        24 Retreating part
        25 Polycrystalline silicon
        26 Screen oxide film
        27 photoresist
        28 Ion implantation
        29 n-type impurities
        31 recess
        41 Insulating film
        42 groove
        51 LOCOS oxide film
        52 recess
        53 Residual polycrystalline silicon
      100 n semiconductor substrate
          A Surface height of gate electrode
          B Surface height of n source region (same as surface height of p base region before n source region formation)
          C Surface height of gate lead-out line

Claims (8)

In a method for manufacturing a semiconductor device having a trench gate,
Forming a second conductive type second semiconductor region on a surface of the first conductive type first semiconductor region, and a first insulating film having an opening at a first portion for forming a trench on the second semiconductor region; Forming a trench, penetrating the second semiconductor region using the opened first insulating film as a mask, and forming a trench reaching the first semiconductor region; and forming a gate lead line connected to the gate electrode a step of opening the first insulating film 2 locations, the train Chi also forming a gate insulating film on the entire surface including the train Chi becomes the gate electrode and the gate lead line on the gate insulating film including a polycrystalline silicon forming, said a step of the opening of the first insulating film is filled with polycrystalline silicon of the first portion train Chi and the second portion of, by flattening the polycrystalline silicon, the first insulating film The top gate insulating film surface is exposed A step of polycrystalline silicon is removed, which equal to the surface height of the gate insulating film on the train a switch to a gate electrode formed multi wherein the surface height of the crystalline silicon first insulating film until the second The first insulating film and the gate insulating film on the second semiconductor region are removed, and the first conductive type first electrode in contact with the trench is formed on the surface of the second semiconductor region using the polycrystalline silicon serving as the gate electrode and a photoresist as a mask. And a method of selectively forming three semiconductor regions. In a method for manufacturing a semiconductor device having a trench gate,
A step of forming the second conductive type second semiconductor region on the surface of the first conductive type first semiconductor region, and opening a first portion for forming the trench, and forming a gate lead line connected to the gate electrode. Forming a first insulating film having a recess in a second location on the second semiconductor region; and passing through the second semiconductor region using the opened first insulating film as a mask; forming a trench reaching the region, the steps formed on the entire surface of the gate insulating film, the polycrystalline silicon is formed on the gate insulating film, filling said recess with said train Ji in polycrystalline silicon, the the polycrystalline silicon is flattened, the polycrystalline silicon is removed until the gate insulating film surface on the first insulating film is exposed, the surface height of the polycrystalline silicon to be the trend Chi which is formed on the gate electrode first 1 on insulating film A step equivalent to the surface height of the insulating film, the first insulating film and the gate insulating film on the second semiconductor region are removed, and the second silicon film and the photoresist serving as the gate electrode are used as a mask. And a step of selectively forming a third semiconductor region of the first conductivity type in contact with the trench on the surface of the semiconductor region. In a method for manufacturing a semiconductor device having a trench gate,
Forming a second conductive type second semiconductor region on the surface of the first conductive type first semiconductor region, and forming a first insulating film having an opening at a first location for forming a first trench to be a trench; A step of forming on the second semiconductor region; a step of forming a shallow trench using the opened first insulating film as a mask; and a first insulation at a second location for forming a gate lead line connected to the gate electrode. A shallow trench is etched deeper using the first insulating film having openings in the first and second locations as a mask, and reaches the first semiconductor region through the second semiconductor region. Forming the first groove to be a trench at the same time as forming the second groove in the second semiconductor region at the second location; forming a gate insulating film on the entire surface; Forming crystalline silicon, and said first groove and And filling a serial second groove in polycrystalline silicon, to planarize the polycrystalline silicon, removal of the polycrystalline silicon until the gate insulating film surface on the second semiconductor region is exposed, formed in the train Ji Removing the gate insulating film on the second semiconductor region, the step of making the surface height of the polycrystalline silicon used as the gate electrode equal to the surface height of the gate insulating film formed on the surface of the second semiconductor region; , the front surface of the second semiconductor region, as a mask the gate electrode and the photoresist, wherein a and a step of selectively forming a third semiconductor region of the first conductivity type in contact with the trench Manufacturing method. In a method of manufacturing a semiconductor device having a trench gate and a LOCOS oxide film,
Forming a second conductive type second semiconductor region on a surface of the first conductive type first semiconductor region surrounded by the LOCOS oxide film; and forming a first insulating part having an opening in the first part forming the trench. Forming a film on the second semiconductor region and the LOCOS oxide film, and forming a trench reaching the first semiconductor region through the second semiconductor region using the opened first insulating film as a mask; A step, a step of opening a first insulating film at a second location for forming a gate lead line connected to the gate electrode including the LOCOS oxide film, a gate insulating film is formed on the entire surface, and the gate insulating film is formed on the gate insulating film. the polycrystalline silicon is formed, and flattening the filling, the polycrystalline silicon the opening of the first insulating film in the first place Tren Chi and the second portion of the polycrystalline silicon, the first Gate insulation film on insulation film Polysilicon to expose removed, a step of equal to the surface height of the gate insulating film on the train a switch to a gate electrode formed multi wherein the surface height of the crystalline silicon first insulating film, the not covered by polycrystalline silicon, as the second to divided semiconductor region and the first insulating film and the gate insulating film on the LOCOS oxide film, masking the polysilicon and the photoresist serving as the gate electrode, And a step of selectively forming a third semiconductor region of a first conductivity type in contact with the trench on a surface of the second semiconductor region. In a method of manufacturing a semiconductor device having a trench gate and a LOCOS oxide film,
A step of forming the second conductive type second semiconductor region on the surface of the first conductive type first semiconductor region, and opening a first portion for forming the trench, and forming a gate lead line connected to the gate electrode. Forming a first insulating film having a recess in a second location on the second semiconductor region and the LOCOS oxide film; and using the opened first insulating film as a mask, forming a penetrating trench reaching the first semiconductor region, a gate insulating film is formed該全surface, the polycrystalline silicon is formed on the gate insulating film, the first location train Chi and LOCOS oxide film Filling the recesses of the second portion including the top with polycrystalline silicon, planarizing the polycrystalline silicon, removing the polycrystalline silicon until the gate insulating film on the first insulating film is exposed, form the train Ji A step to have been equal to the surface height of the gate insulating film of the surface height of the polycrystalline silicon to be a gate electrode on the first insulating layer, the not covered with polycrystalline silicon, said second semiconductor region the was removed dividing the first insulating film and the gate insulating film over the LOCOS oxide film, a polycrystalline silicon and the photoresist serving as the gate electrode as a mask, a first conductive contact to the trench in the surface of the second semiconductor region and And a step of selectively forming a third semiconductor region of the mold. In a method of manufacturing a semiconductor device having a trench gate and a LOCOS oxide film,
A step of forming a second semiconductor region of the second conductivity type on the surface of the first semiconductor region of the first conductivity type, and a first portion where a trench is formed on the second semiconductor region are opened and connected to the gate electrode. A recess is formed at a second location where the gate lead line is formed , and the first semiconductor film is formed such that the recess at the second location becomes a recess reaching the LOCOS oxide film on the LOCOS oxide film. Forming on the region and the LOCOS oxide film, forming a trench that penetrates the second semiconductor region and reaches the first semiconductor region using the opened first insulating film as a mask, and a gate over the entire surface. forming an insulating film, a step of polycrystalline silicon is formed on the gate insulating film to fill the recess of the first portion train Chi and the second portion of the polycrystalline silicon, the polycrystalline silicon Planarized and said second semiconductor The polycrystalline silicon is removed until the gate insulating film surface on the region is exposed, and the surface height of the polycrystalline silicon serving as the gate electrode is equal to the surface height of the gate insulating film formed on the surface of the second semiconductor region. a step of the not coated with polycrystalline silicon, the said gate insulating film and the first insulating film is removed on the second semiconductor region and the LOCOS oxide film, the front surface of the second semiconductor region And a step of selectively forming a third semiconductor region of the first conductivity type in contact with the trench using the gate electrode and the photoresist as a mask. 7. The planarization is performed by a CMP (Chemical Mechanical Polishing) method using the first insulating film and the gate insulating film as a stopper layer. A method for manufacturing the semiconductor device according to the item. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the planarization is performed using a CMP method using the gate insulating film as a stopper layer.

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