JP2009058885A - Electro-optical device, driving method, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent so-called image sticking in a liquid crystal display. <P>SOLUTION: When a start pulse Dya is supplied, scan lines are sequentially selected in a period where a clock signal Cly is a L level with the scan line of a first row as a start point, while a polarity of a data signal supplied to a data line is made positive. When a start pulse Dyb is supplied, the scan lines are sequentially selected in a period where the clock signal Cly is a H level with the scan line of the first row as the start point, while a polarity of the data signal supplied to the data line is made negative. At this time, the start pulse Dyb is shifted before and after in timing P so that brightness of an upper half screen and that of a lower half screen may become the same in the timing P. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for preventing seizure of a so-called electro-optical device.

In general, in an electro-optical device such as a liquid crystal display device, a voltage applied to a pixel electrode is set to a high-order side (positive polarity) so that a DC component is not applied to a liquid crystal capacitor (pixel) in which liquid crystal is sandwiched between the pixel electrode and a counter electrode. ) And alternating-current drive that switches alternately between the lower voltage (negative polarity) and the voltage is the principle.
On the other hand, in the active matrix type in which the pixel electrode is driven by a thin film transistor (hereinafter referred to as “TFT”), so-called push-down (also referred to as field through or penetration) occurs. Further, the leakage of the liquid crystal capacitance is different between a case where a positive voltage is held and a case where a negative voltage is held.
For this reason, when the polarity reference of the voltage applied to the pixel electrode is matched with the voltage applied to the counter electrode, a positive voltage is maintained even when the voltage is positive or negative corresponding to the same gradation. The effective voltage value of the liquid crystal capacitance is different from the case where the negative voltage is held, and a DC component is applied to the liquid crystal capacitance.

  Note that when a DC component is applied to the liquid crystal capacitor, the liquid crystal deteriorates, and a still image displayed in the past may appear as an afterimage. Since this afterimage resembles the image sticking that occurs on the phosphor screen of a CRT, the phenomenon resulting from the application of a direct current component to the liquid crystal capacitance may be referred to as image sticking. Further, the difference in the effective voltage value of the liquid crystal capacitance appears as a difference in pixel gradation (brightness), which may cause flicker.

For this reason, a technique of adjusting the voltage of the counter electrode at the time of factory shipment so that flicker is minimized when positive and negative voltages corresponding to the same gradation are alternately applied (see, for example, Patent Document 1). In addition, a technique for imaging a screen with flicker and adding a correction amount of a component that cancels flicker to a data signal in advance (see, for example, Patent Document 2) has been proposed.
See Japanese Patent Application Laid-Open No. 2005-22169. See Japanese Patent Application Laid-Open No. 2003-234981

However, even if the counter electrode voltage is adjusted to be optimal at the time of shipment from the factory, flicker may occur due to aging. For this reason, it may be possible to readjust the voltage of the counter electrode after shipment from the factory. However, since various adjustment values made at the time of shipment from the factory become meaningless, the quality of the display image may be impaired.
On the other hand, in a configuration in which a component for canceling flicker is added to the data signal in advance, a circuit for storing the correction amount is separately required.
The present invention has been made in view of the above-described circumstances, and one of its purposes is to readjust the voltage of the counter electrode, and to add flicker canceling components to the data signal in advance. It is to provide a technique capable of suppressing the occurrence of the occurrence of the above.

  In order to achieve the above object, the electro-optical device according to the present invention is provided corresponding to the intersection of a plurality of scanning lines and a plurality of data lines, respectively, and when each of the scanning lines is selected, An electro-optical device having a plurality of pixels having gradations corresponding to voltages of data signals supplied to the data lines, wherein the plurality of scanning lines are arranged in each of the first and second fields constituting one frame. When a scanning line selection circuit for selecting in a predetermined order and one scanning line in the first field are selected, a voltage corresponding to the gradation of the pixel is applied to the pixel located on the one scanning line. A voltage having either a positive polarity that is higher or a negative polarity that is lower than a predetermined potential is supplied to the data line corresponding to the pixel as the data signal, and the second field One When an inspection line is selected, a voltage corresponding to the gray level of the pixel located on the one scanning line, the voltage having either the positive polarity or the negative polarity is applied. The one frame so that the data line driving circuit supplying the data line corresponding to the pixel as the data signal and the pixel located on the one scanning line have the same gradation in the first and second fields. And a control circuit for controlling the period length of the first and second fields with respect to the period length. According to the present invention, one frame is constituted by the first and second fields, and when a positive voltage is written in the first field in a certain pixel, a negative voltage is written in the second field, and Since the period lengths of the first and second fields are controlled, it is possible to suppress the occurrence of flicker without re-adjusting the counter electrode voltage and without adding a component that cancels flicker to the data signal in advance. .

In the present invention, it has a photosensor that images a pixel supplied with a positive voltage and a pixel supplied with a negative voltage, and the control circuit has a gradation of pixels picked up by the photosensor. The period lengths of the first and second fields may be controlled with respect to the period length of the one frame so as to be equal to each other. In this way, by providing the optical sensor and controlling so as to eliminate the difference in the actual gradation (brightness) of the pixels, flicker can be further suppressed.
In this invention, it has a temperature sensor which detects the temperature around the plurality of pixels, and the control circuit performs the first and second for the period length of the one frame according to the temperature detected by the temperature sensor. It may be configured to control the period length of the field. Since the leakage of the holding voltage varies depending on the temperature change, a configuration in which the temperature sensor is provided in this manner and the control is performed according to the detected temperature may be adopted.
In the present invention, the image forming apparatus includes a histogram generator that generates a histogram of gradations specified for the plurality of pixels, and the control circuit is configured to control the one frame according to the histogram generated by the histogram generator. A configuration may be adopted in which the period lengths of the first and second fields with respect to the period length are controlled. Since a DC component may be applied due to gradation deviation, control may be performed according to a gradation histogram.

In the present invention, the scanning line driving circuit sequentially selects a predetermined scanning line at a predetermined interval in a predetermined direction from a predetermined scanning line among the plurality of rows over the first and second fields of one frame. In addition, a configuration may be adopted in which selection is performed in the predetermined direction in order from the scanning line as the start point over the second field of the one frame and the first field of the next frame. As a result, region scanning driving by so-called interlaced scanning is performed.
The present invention can be conceptualized not only as an electro-optical device but also as a driving method of the electro-optical device and an electronic apparatus having the electro-optical device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
First, the electro-optical device according to the first embodiment of the invention will be described. FIG. 1 is a block diagram illustrating a configuration of the electro-optical device according to the first embodiment.
As shown in this figure, the electro-optical device 1 is roughly divided into a display panel 10, a processing circuit 50, and an optical sensor 70. Among these, the processing circuit 50 includes a control circuit 52, a display data processing circuit 54, and a D / A conversion circuit 56, and is a circuit module that controls the operation of the display panel 10, and the display panel 10 For example, they are connected by an FPC (flexible printed circuit) substrate.

  The control circuit 52 generates various control signals for controlling the display panel 10 in synchronization with a synchronization signal Vsync supplied from an external host device (not shown). These control signals will be described later as appropriate. The control circuit 52 generates various control signals and controls the display data processing circuit 54.

The optical sensor 70 is a two-dimensional sensor that captures an image (including a projected image) displayed by the display panel 10, and supplies an output signal to the control circuit 52.
The display data processing circuit 54 temporarily stores display data Video supplied from an external host device in an internal memory (not shown) under control of the control circuit 52 and then reads it in synchronization with driving of the display panel 10. It is.
Note that the display data Video is data for specifying the gradation of the pixels in the display panel 10, and the waveform is not particularly shown, but for one frame (total of the display panel 10 with a period of 16.7 milliseconds (frequency 60 Hz)). (For pixel). The D / A conversion circuit 56 converts the read display data into an analog data signal Vid.

Next, the display panel 10 will be described. FIG. 2 is a diagram illustrating a configuration of the display panel 10.
As shown in this figure, the display panel 10 is a peripheral circuit built-in type in which a scanning line driving circuit 130 and a data line driving circuit 140 are built around the display region 100. In the display area 100, 480 scanning lines 112 are provided so as to extend in the row (X) direction, and 640 columns of data lines 114 are provided so as to extend in the column (Y) direction. The pixels 110 are arranged so as to be electrically insulated from the scanning lines 112 and correspond to the intersections of the scanning lines 112 of 480 rows and the data lines 114 of 640 columns. Accordingly, in the present embodiment, the pixels 110 are arranged in a matrix of 480 rows × 640 columns in the display region 100, but the present invention is not limited to this arrangement.

  The configuration of the pixel 110 will be described with reference to FIG. FIG. 3 shows a total of 4 pixels of 2 × 2 corresponding to the intersection of the i row and the (i + 1) row adjacent to it by 1 row and the j column and the (j + 1) column adjacent to the right by 1 column. The structure of is shown. Note that i and (i + 1) are symbols for generally indicating the row in which the pixels 110 are arranged, and are integers of 1 to 480 in this description. J and (j + 1) are symbols for generally indicating a column in which the pixels 110 are arranged, and are integers of 1 to 640.

As shown in FIG. 3, each pixel 110 includes an n-channel TFT 116 and a liquid crystal capacitor 120.
Here, since each pixel 110 has the same configuration, the gate electrode of the TFT 116 in the pixel 110 in the i row and j column will be described as the pixel in the i row and j column. On the other hand, the source electrode is connected to the data line 114 in the j-th column, and the drain electrode is connected to the pixel electrode 118 which is one end of the liquid crystal capacitor 120. The other end of the liquid crystal capacitor 120 is connected to the counter electrode 108. The counter electrode 108 is common to all the pixels 110, and a voltage LCcom constant in time is applied.

Although not specifically shown, the display panel 10 has a configuration in which a pair of substrates of an element substrate and a counter substrate are bonded together with a certain gap therebetween, and liquid crystal is sealed in the gap. Among these, the scanning line 112, the data line 114, the TFT 116, and the pixel electrode 118 are formed on the element substrate together with the scanning line driving circuit 130 and the data line driving circuit 140, while the counter electrode 108 is formed on the counter substrate. These electrode forming surfaces are bonded together with a certain gap so as to face each other. For this reason, in this embodiment, the liquid crystal capacitor 120 is configured by sandwiching the liquid crystal 105 between the pixel electrode 118 and the counter electrode 108.
In this embodiment, if the effective voltage value held in the liquid crystal capacitor 120 is close to zero, the transmittance of light passing through the liquid crystal capacitor is maximized to display white, while the effective voltage value increases. The normally white mode in which the amount of transmitted light decreases and finally the black display with the minimum transmittance is set.

In this configuration, a selection voltage is applied to the scanning line 112 to turn on the TFT 116, and the voltage corresponding to the gradation (brightness) is applied to the pixel electrode 118 via the data line 114 and the on-state TFT 116. When the data signal is supplied, the liquid crystal capacitor 120 corresponding to the intersection of the scanning line 112 to which the selection voltage is applied and the data line 114 to which the data signal is supplied can hold the effective voltage value corresponding to the gradation.
Therefore, the light transmitted through the liquid crystal capacitor 120 can be different for each pixel, whereby an image is formed in the display region 100. The formed image is viewed directly by the user or enlarged and projected like a projector described later. In any case, the formed image is picked up by the optical sensor 70.

  Note that when the scanning line 112 becomes a non-selection voltage, the TFT 116 is turned off (non-conducting). However, since the off resistance at this time is not ideally infinite, the charge accumulated in the liquid crystal capacitor 120 is small. Leak. In order to reduce the influence of off-leakage, a storage capacitor 109 is formed for each pixel. One end of the storage capacitor 109 is connected to the pixel electrode 118 (the drain of the TFT 116), and the other end is commonly connected to the capacitor line 107 over all pixels. The capacitor line 107 is maintained at a constant potential, for example, the same voltage LCcom as the counter electrode 108.

  The scanning line driving circuit 130 supplies scanning signals G1, G2, G3,..., G480 to the scanning lines 112 in the 1, 2, 3,. Here, the scanning line driving circuit 130 sets the scanning signal to the selected scanning line to the H level corresponding to the voltage Vdd, and sets the scanning signals to the other scanning lines to L corresponding to the non-selection voltage (ground potential Gnd). Level.

FIG. 4 is a timing chart showing the scanning signals G1 to G480 output from the scanning line driving circuit 130 in relation to the start pulses Dya and Dyb and the clock signal Cly.
As shown in the figure, each scanning line 112 is selected twice in one frame period. Here, the frame refers to a period required to display one image on the display panel 10, but the display data Video is supplied at a period of 16.7 milliseconds as described above, so Corresponds to 16.7 milliseconds of this period.
The control circuit 52 outputs a clock signal Cly having a duty ratio of 50% for 480 periods equal to the number of scanning lines over a period of one frame. Note that a period of one cycle of the clock signal Cly is denoted as H.
Further, the control circuit 52 outputs start pulses Dya and Dyb having a pulse width corresponding to one cycle of the clock signal Cly when the clock signal Cly rises to the H level as follows. That is, the control circuit 52 outputs the start pulse Dya at the beginning of one frame period (that is, the beginning of the first field), while outputting the start pulse Dyb for 240 cycles of the clock signal Cly after outputting the start pulse Dyb. Is output at a timing T at which a half period of one frame has passed. However, the control circuit 52 generates the start pulse Dyb in accordance with the output result of the optical sensor 70 in terms of the time from the timing T to the front side or the rear side in time by the unit of the period of the clock signal Cly. May be output.

Note that the period from the start pulse Dya output until the start pulse Dyb is output in the period of one frame is defined as the first field, and the next start pulse Dya is output after the start pulse Dyb is output. The period until is the second field.
Here, the start pulses Dya and Dyb are alternately output, and among these, the start pulse Dya is output at the start timing of one frame, that is, every 16.7 milliseconds. For this reason, if the start pulse Dya is specified, the start pulse Dyb can inevitably be specified. Therefore, in FIG. 1, FIG. 2, etc., the start pulse Dy may be indicated without particularly distinguishing between them.

The scanning line driving circuit 130 outputs the scanning signals G1 to G480 shown in FIG. 4 from the start pulses Dya and Dyb and the clock signal Cly. That is, when the start pulse Dya is supplied to the scanning signals G1 to G480, the scanning line driving circuit 130 sequentially sets the clock signal Cly to the H level during the L level period, while when the start pulse Dyb is supplied. The clock signal Cly is sequentially set to H level during the H level period.
For this reason, by supplying the start pulse Dya, the scanning line is shifted in the order of the first, second, and second fields of a frame in the order of the first, second, third, fourth,. On the other hand, when the start pulse Dyb is supplied, the scanning line is selected from the second field of a certain frame to the first field of the next frame toward the bottom of the screen. 4,..., In the order of the 480th row, they are selected between selections triggered by the supply of the start pulse Dya.

  The data line driving circuit 140 includes a sampling signal output circuit 142 and n-channel TFTs 146 provided corresponding to the data lines 114, respectively. As shown in FIG. 5 or FIG. 6, the sampling signal output circuit 142 selects one of the scanning lines 112 according to the control signal Ctrl-x from the control circuit 52, and the scanning signal supplied to the scanning line is at the H level. In this period, sampling signals S1, S2, S3,..., S640 that sequentially become H level exclusively are output so as to correspond to each of the data lines 114. Note that the control signal Ctrl-x is actually a start pulse or a clock signal, but it is not directly related to the present invention, so the description is omitted. Further, the period during which the scanning signal is at the H level is actually slightly narrower than the half period of the clock signal Cly as shown in FIG. 5 or FIG.

Incidentally, the D / A conversion circuit 56 in FIG. 1 converts display data Video for one row of pixels located on the scanning line 112 selected by the scanning line driving circuit 130 into sampling signals S 1 to S 640 by the sampling signal output circuit 142. The data signal Vid having the following polarity is converted in accordance with the output.
That is, the D / A conversion circuit 56 has positive polarity for the display data Vid of the pixels located in the selected row when the clock signal Cly is at L level, and the selected row when the clock signal Cly is at H level. The display data Vid of the pixel located at is converted to negative polarity. In other words, the D / A conversion circuit 56 has a positive polarity for the display data Vid of the pixels located in the row selected in response to the supply of the start pulse Dya, and the row selected in response to the supply of the start pulse Dyb. The display data Vid of the pixel located at is converted to negative polarity.

  The positive polarity means a voltage higher than the reference voltage Vc (see FIG. 5) set higher than the applied voltage LCcom to the counter electrode 108, and the negative polarity means the reference voltage Vc. On the other hand, it refers to the lower voltage. In this embodiment, the polarity of the data signal is based on the voltage Vc. However, unless otherwise specified, the ground potential Gnd corresponding to the L level of the logic level is used as the reference for the voltage zero. .

Next, the operation of the electro-optical device will be described.
First, the control circuit 52 stores the display data Video supplied from the external host device in the internal memory of the display data processing circuit 54, and then selects a scanning line of a row on the display panel 10, and The display signal is read out at a speed twice the storage speed, and the sampling signal output circuit 142 is connected via the control signal Ctrl-x so that the sampling signals S1 to S640 sequentially become H level in accordance with the reading of the display data. Control. The read display data is converted into an analog data signal Vid by the D / A conversion circuit 56.

Here, when the control circuit 52 supplies the start pulse Dyb at the timing T, in the first field, the scanning lines 112 are in the order of the 241, 241, 2, 243,. Selected. For this reason, the control circuit 52 controls the scanning line driving circuit 130 so that the scanning line 112 in the 241st row is selected first, while the display data processing circuit 54 is controlled in the 241st row stored in the memory. The corresponding display data Video is read at double speed, and the D / A conversion circuit 56 is controlled to convert it to the negative data signal Vid. The sampling signals S1 to S640 are in this order in accordance with this reading. The sampling signal output circuit 142 is controlled so as to be exclusively at the H level. When the sampling signals S1 to S640 are sequentially set to the H level, the TFTs 146 are sequentially turned on and the data signals Vid supplied to the image signal lines 171 are sequentially sampled on the data lines 114 in the 1st to 640th columns.
On the other hand, when the scanning line 112 in the 241st row is selected and the scanning signal G241 becomes H level, all the TFTs 116 in the pixels 110 located in the 241st row are turned on. Therefore, the negative voltage of the data signal Vid sampled on the data line 114 is applied to the pixel electrode 118 as it is. For this reason, the negative voltage corresponding to the gradation specified by the display data Video is written into the liquid crystal capacitor 120 in the pixels of the 241st row and the columns 1, 2, 3, 4,..., 639, 640. Will be held.

Next, the control circuit 52 controls the scanning line driving circuit 130 so that the scanning line 112 in the first row is selected, while corresponding to the first row stored in the memory with respect to the display data processing circuit 54. The display data Video to be read is read at double speed, and the D / A conversion circuit 56 is controlled to convert it to the positive polarity data signal Vid, and the sampling signals S1 to S640 are in this order in accordance with this reading. The sampling signal output circuit 142 is controlled so as to be exclusively at the H level.
When the scanning line 112 of the first row is selected and the scanning signal G1 becomes the H level, all the TFTs 116 in the pixels 110 located in the first row are turned on, thereby the voltage of the data signal Vid sampled on the data line 114 Is applied to the pixel electrode 118. For this reason, the positive voltage corresponding to the gradation specified by the display data Video is written and held in the liquid crystal capacitor 120 in the pixels of the first row and the 1st to 640th columns.

Hereinafter, in the first field, the same voltage writing operation is executed in the order of the 242nd, 2nd, 24th, 3rd,..., 480th, and 240th rows. Thereby, a positive voltage corresponding to the gradation is written to the pixels in the first to 240th rows, and a negative voltage corresponding to the gradation is written to the pixels in the 241st to 480th rows. Each will be held.
In the case where the start pulse Dyb is supplied at the timing T, the scanning lines 112 are referred to as the first, second, second, second, second, third, fourth, fourth, 244,. While being selected in order, the write polarity in the same row is inverted. Therefore, a negative voltage corresponding to the gradation is written to the pixels in the first to 240th rows, and a positive voltage corresponding to the gradation is written to the pixels in the 241st to 480th rows. Each will be held.

FIG. 5 is a diagram illustrating an example of a voltage waveform of the data signal Vid in a period in which the (i + 240) -th scanning line and the i-th scanning line in the first field are selected.
In this figure, voltages Vb (+) and Vb (−) are positive and negative voltages corresponding to the black of the lowest gradation, respectively, and are symmetrical with respect to the reference voltage Vc. In the present embodiment, when the decimal value of the gradation value specified by the display data Video is “0”, black of the lowest gradation is specified, and thereafter, a bright gradation is specified as the decimal value increases. Is a normally white mode, so that the voltage of the data signal Vid becomes a voltage swung from the voltage Vb (+) to the lower side as the gradation value increases in the case of converting to the positive polarity. In the case of converting to V, the voltage is swung from the voltage Vb (−) to the higher side.

In the first field, since the (i + 240) -th scanning line is selected before the i-th row, for example, the sampling signal S1 is at the H level during the period in which the scanning signal G (i + 240) is at the H level. During this period, the data signal Vid becomes a negative voltage corresponding to the gradation of the pixel in the i row and the first column, and the pixels in the second, third, fourth,. The voltage changes to a negative polarity voltage corresponding to the gradation.
In the i-th row that is subsequently selected, since positive polarity writing is designated, the data signal Vid is i during the period when the scanning signal Gi is at the H level, for example, during the period when the sampling signal S1 is at the H level. It becomes a positive voltage according to the gradation of the pixel in the row 1 column, and thereafter changes to a positive voltage according to the gradation of the pixel in the 2, 3, 4,... .
In the second field, since the (i + 240) -th scanning line is selected after the i-th row, the scanning signal Gi first goes to the H level and the writing polarity is inverted, so that the data signal Vid The voltage waveform is as shown in FIG.
In FIG. 5 and FIG. 6, the vertical scale indicating the voltage of the data signal Vid is enlarged for convenience in comparison with the vertical scales of other signals. Further, the voltage corresponds to black over a period from when the sampling signal S640 changes to the L level to when the sampling signal S1 changes to the H level. This is because it does not contribute to the display even if it is written on.

FIG. 7 is a diagram showing the writing state of each row as time passes over successive frames when the start pulse Dyb is supplied at the timing T. FIG. As shown in this figure, in the present embodiment, in the first field, negative polarity writing is performed on the pixels of 241, 242, 243,. In the pixel, the positive writing is performed and held until the next writing, while in the second field, the negative writing is performed in the pixels in the first, second, third,..., 240th rows, and 241, 242, 243,. In the pixel on the 480th row, positive writing is performed and similarly held until the next writing.
When the start pulse Dyb is supplied at the timing T, the period of the first and second fields is 240 periods of the clock signal Cly. Therefore, the period in which the positive voltage is held in the liquid crystal capacitor 120 in each pixel and the negative electrode The period during which the sexual voltage is held is halved.

Incidentally, as shown in FIG. 5, the voltage LCcom applied to the counter electrode 108 is set to a lower side than the reference voltage Vc at the time of factory shipment. This is because of a difference in pushdown and leak amount as described in the background art section. If the voltage LCcom is matched with the reference voltage Vc, the effective voltage value of the liquid crystal capacitor 120 by negative polarity writing is slightly larger than the effective value by positive polarity writing (when the TFT 116 is n-channel). The voltage LCcom is set to an optimum value so that this difference is offset by offsetting the voltage LCcom to the lower side than the reference voltage Vc.
In the present embodiment, when the start pulse Dyb is supplied at the timing T, the first and second field periods are equal to each other, and the positive voltage is held in the liquid crystal capacitor 120 and the negative voltage is held in each pixel. Since the period to be performed is half of the period of the frame, a direct current component should not be applied to the liquid crystal capacitor 120.
However, when the TFT pushdown amount and the amount of leakage in the liquid crystal capacitance change from the time of shipment from the factory due to aging, etc., the voltage LCcom is no longer the optimum value, and a DC component is applied to the liquid crystal capacitance 120. . Therefore, in the present embodiment, an operation for preventing a direct current component from being applied to the liquid crystal capacitance even when aging occurs will be described next.

  In FIG. 7, when viewed at the timing P at the start (end) of the frame, the upper half of the screen holds a negative voltage, and the lower half of the screen holds a positive voltage. Yes. Therefore, when the same gradation is displayed in all the pixels of the screen, particularly when the intermediate gradation between the highest white and the lowest black is displayed, if no direct current component is applied to the liquid crystal capacitor, it is shown in FIG. Thus, the same brightness is obtained in the upper half and the lower half. For this reason, if the imaging result by the optical sensor 70 at the timing P is the same brightness in the upper half and the lower half of the screen, the control circuit 52 does not change the operation at all. In FIG. 8, the brightness of the screen is represented by the density of diagonal lines.

  On the other hand, when the imaging result by the optical sensor 70 at the timing P is relatively brighter in the upper half of the screen than in the lower half, as shown in FIG. It shows the state of being applied. Specifically, the voltage effective value held negative in the upper half pixel (liquid crystal capacitance) is lower than the voltage effective value held positive in the lower half pixel (liquid crystal capacitance). Show (normally white mode).

At this time, as shown in FIG. 9, when the control circuit 52 changes the start pulse Dyb to a timing T (−1) that is earlier than the timing T by one cycle of the clock signal Cly and outputs it, the first field This period is 239 periods of the clock signal Cly, whereas the period of the second field is 241 periods of the clock signal Cly.
For this reason, as shown in FIG. 10, the holding period of the negative voltage written by the selection triggered by the supply of the start pulse Dyb is the holding of the positive voltage written by the selection triggered by the supply of the start pulse Dya. Longer than the period. Therefore, the effective voltage value held negative in the upper half pixel is increased and lower than the effective voltage value held positive in the lower half pixel (liquid crystal capacitance). It changes in the direction darker than half.

The control circuit 52 fixes the start pulse Dyb at the timing T (-1) if the same brightness is obtained in the upper half and the lower half of the screen by this control, while the upper half of the screen is still in the lower half. If it is relatively brighter, the start pulse Dyb is output at a timing T (-2) that is further advanced by one cycle of the clock signal Cly from the timing T (-1) (not shown).
The control circuit 52 fixes the start pulse Dyb at the timing T (−2) when the brightness is the same in the upper half and the lower half of the screen by this control. The control circuit 52 repeats the operation of increasing the start pulse Dyb step by step by one cycle of the clock signal Cly until the upper half and the lower half of the screen have the same brightness.

On the other hand, when the imaging result by the optical sensor 70 at the timing P is relatively darker in the upper half of the screen than in the lower half, as shown in FIG. It is shown that the effective voltage value held in the negative polarity in the (capacitance) is higher than the effective voltage value held in the positive polarity in the lower half pixel (liquid crystal capacitance).
At this time, as shown in FIG. 11, the control circuit 52 changes the start pulse Dyb to the timing T (+1) delayed from the timing T by one cycle of the clock signal Cly and outputs it. Therefore, the period of the first field is 241 cycles of the clock signal Cly, while the period of the second field is 239 cycles of the clock signal Cly.
For this reason, as shown in FIG. 12, the holding period of the negative voltage written by the selection triggered by the supply of the start pulse Dyb is the holding of the positive voltage written by the selection triggered by the supply of the start pulse Dya. Shorter than the period. Therefore, the voltage effective value held in the negative polarity in the upper half pixel is lowered and higher than the voltage effective value held in the positive polarity in the lower half pixel (liquid crystal capacitance). It changes in a direction that becomes brighter than the lower half.
The control circuit 52 fixes the start pulse Dyb at the timing T (+1) when the same brightness is obtained in the upper half and the lower half of the screen by this control, while the upper half of the screen is still in the lower half. If it is relatively darker, the operation of delaying the start pulse Dyb step by step by one cycle of the clock signal Cly is repeated until the upper half and the lower half of the screen have the same brightness.

  Therefore, by such control, the start pulse Dyb is output at the same brightness in the upper half and the lower half of the screen, so the voltage effective value held in the negative polarity and the voltage held in the positive polarity The effective value is almost equal. For this reason, according to the first embodiment, it is possible to suppress the occurrence of flicker without re-adjusting the voltage of the counter electrode and without adding a component that cancels flicker to the data signal in advance.

Note that the timing for adjusting the output point of the start pulse Dyb is, for example, when a predetermined time has elapsed since the power was turned on, when there is a separate instruction from the user, when there is a power-off instruction, and at regular time intervals. It can be considered.
In the first embodiment, the pixel located in the row selected by the supply of the start pulse Dya is positive, and the pixel located in the row selected by the supply of the start pulse Dyb is negative. In contrast, each pixel is converted, but on the contrary, the pixel located in the row selected by the supply of the start pulse Dya is negative, and the pixel located in the row selected by the supply of the start pulse Dyb is positive. May be converted to each.
Further, the control circuit 52 detects whether or not the brightness of the pixels in the upper half area and the pixels in the lower half area detected by the optical sensor are equal to each other. This is because the error is considered to be small because the average value is seen, and if the difference in characteristics of a plurality of pixels (liquid crystal capacitance) can be ignored, the voltage corresponding to the effective voltage value held positive for the same pixel This is because it can be equated with comparing brightness with brightness according to the effective voltage value held in negative polarity.

Second Embodiment
Next, an electro-optical device according to a second embodiment of the invention will be described. FIG. 13 is a block diagram illustrating a configuration of the electro-optical device according to the second embodiment.
The electro-optical device 1 shown in this figure is different from the electro-optical device according to the first embodiment (see FIG. 1) in that it has a temperature sensor 72 instead of the optical sensor 70, and the control circuit 52 has a temperature sensor. The display panel is controlled in consideration of the detection result by 72. Therefore, in the following, this difference will be mainly described.

The charge accumulated in the liquid crystal capacitor 120 tends to leak as the temperature increases, and conversely, the charge tends to be difficult to leak as the temperature decreases. Moreover, as described above, there is a difference in leakage depending on the polarity. For this reason, in the liquid crystal capacitor 120, for example, as the temperature increases, the voltage of the pixel electrode written when the scanning line is selected quickly approaches the voltage LCcom applied to the counter electrode 108.
Since the voltage LCcom set at the time of shipment from the factory is premised on use at room temperature (25 degrees), for example, a DC component is applied to the liquid crystal capacitor 120 as it deviates from room temperature. Therefore, in the second embodiment, the temperature characteristic of the leak amount is obtained in advance, and the control circuit 52 starts according to the temperature characteristic, that is, considering the leak amount corresponding to the temperature detected by the temperature sensor 72. The shift direction of the pulse Dyb (before or after in time) and the amount (for how many cycles of the clock signal Cly) are determined.
Even with such a configuration, it is possible to suppress the occurrence of flicker without re-adjusting the voltage of the counter electrode and without adding a component for canceling flicker to the data signal in advance.

In addition to the temperature, the factors that change the leak amount of the liquid crystal capacitor 120 may include the cumulative lighting time of the light source, the gradation histogram, and the usage time of the display panel.
Here, the cumulative lighting time of the light source and the use time of the display panel can be handled as a secular change of the display panel. However, a circuit for measuring these times is provided, and the start pulse Dyb is taken into consideration with the measurement time. The shift direction and amount may be determined.

The voltage LCcom set at the time of factory shipment is set so that the flicker is minimized when a specific gradation (in many cases, an intermediate gradation in which flicker is easily visible) is displayed. Therefore, when displaying this specific gradation, the occurrence of flicker can be suppressed. However, when a large number of gradations other than the specific gradation are displayed after shipment from the factory, a direct current component may be applied because the amount of charge leakage differs between positive polarity and negative polarity. Therefore, as shown in FIG. 14, while providing a histogram generator 74 that generates a histogram of gradation values specified by the display data Video, the control circuit 52 determines whether or not the generated gradation value has a histogram. The shift direction and amount of the start pulse Dyb may be determined.
In this configuration, the optimum shift direction and amount of the start pulse Dyb are determined in advance with respect to the accumulated value of the gradation value histogram for each model, production lot, or individual of the display panel 10 and expressed in a formula or a table. It is necessary to keep.

  The application of the direct current component of the liquid crystal capacitance is caused by the difference between the voltage written in the positive polarity and the voltage written in the negative polarity. Therefore, the histogram creator 74 creates a histogram of the gradation value written with the positive polarity and the gradation value written with the negative polarity, and the control circuit 52 shifts the start pulse Dyb in accordance with the histogram. The direction and amount may be determined.

  Thus, in the configuration having the temperature sensor 72 and the histogram generator 74, only the shift direction and amount of the start pulse Dyb are determined according to these results, and flicker is not actually detected. For this reason, since the possibility that a direct current component is applied to the liquid crystal capacitor 120 cannot be denied, the optical sensor 70 in the first embodiment is provided together with the temperature sensor 72 and the histogram generator 74, and the detection result of the screen is displayed as the start pulse Dyb. It may be fed back to the determination of the shift direction and amount.

<Application and deformation>
Various applications and modifications can be made to the above-described embodiment.
For example, in the first embodiment, if the start pulse Dyb is output at the timing T, the scanning line 112 is 241, 1, 242, 2, 243, 3,... 480, 240 in the first field. In the second field, the selection is performed in the order of the first row, and in the second field, the scanning is performed in the order of the first, 241, 2, 242, 3, 243, ..., 240, 480th rows. As shown in FIG. 15, the first and second fields may be selected in the order of 1, 2, 3, 4,... 479, 480th row.

In the drive method shown in FIG. 15 as well, the display data Video supplied from the external host device is supplied to the display panel 10 at twice the speed. For this reason, after being written into the display data Video at the supply speed, it is read in the order of the 1st to 480th rows in the first and second fields. In such double speed driving, the scanning line driving circuit 130 scans the scanning signals G1 to G480 in a period corresponding to a half cycle of the clock signal each time the logic level of the clock signal Cly changes when the start pulse Dya or Dyb is supplied. It becomes the structure made to become H level one by one.
Therefore, as shown in FIG. 15, the scanning line is selected in response to the supply of the start pulse Dya in the first field, and the scanning line is selected in response to the supply of the start pulse Dyb in the second field.

At this time, a blanking period Fb1 is provided from the selection of the 480th scanning line in the first field to the selection of the first scanning line in the next second field. Similarly, a blanking period Fb2 is provided from the selection of the 480th scanning line in the second field to the selection of the first scanning line in the first field of the next frame. Further, for example, a positive voltage is written in the first field, and a negative voltage is written in the second field.
Here, if the blanking periods Fb 1 and Fb 2 are each half of the blanking period of the display data Video, the first and second field periods are equal to each other. The voltage effective value held at the negative polarity and the voltage effective value held at the negative polarity are almost equal. Therefore, at the intermediate timing Q of the second field, the upper half area (area where the negative voltage is held) and the lower half area (area where the positive voltage is held) in the display area 100 As shown in FIG. 8A, the brightness is substantially equal.

However, for example, when a direct current component is applied due to the influence of secular change, at the intermediate timing Q, the upper half area (area where the negative voltage is held) and the lower half area (positive polarity) in the display area 100. In the region where the voltage is held, a difference in brightness appears as shown in FIG. 8B or 8C.
At this time, as shown in FIG. 8B, if the upper half area is brighter than the lower half area, the voltage effective value held in the negative polarity in the normally white mode is held in the positive polarity. 16, the control circuit 52 advances the start pulse Dyb by one stage from the timing T, and holds the negative voltage as shown in FIG. The period of the field is lengthened, and the period of the first field that holds the positive voltage is shortened. Such an operation is repeated until the brightness of the upper half area and the lower half area becomes equal at timing P.
Here, when the start pulse Dyb is advanced from the timing T, the limit is until the blanking period Fb1 becomes zero, as shown in FIG.

On the other hand, as shown in FIG. 8B, if the upper half area is darker than the lower half area, the voltage effective value held in the negative polarity in the normally white mode is held in the positive polarity. The control circuit 52 delays the start pulse Dyb by one stage with respect to the timing T and holds the negative voltage as shown in FIG. This period is shortened, and the period of the first field for holding the positive voltage is lengthened. Such an operation is repeated until the brightness of the upper half area and the lower half area becomes equal at timing P.
Here, when the start pulse Dyb is delayed from the timing T, the limit is until the blanking period Fb2 becomes zero as shown in FIG.

  In the driving method shown in FIG. 15 (FIGS. 16 and 17), the positive polarity writing is executed in the first field and the negative polarity writing is executed in the second field. On the contrary, the negative polarity writing is executed in the first field. And positive polarity writing may be executed in the second field.

In the embodiment, the supply timing of the start pulse Dya is fixed and the supply timing of the start pulse Dyb is changed. Conversely, the supply timing of the start pulse Dyb is fixed and the supply timing of the start pulse Dya is changed. May be.
Further, the supply timing of both start pulses Dya and Dyb may be changed. However, if both the supply timings of the start pulses Dya and Dyb are changed, the display data supplied to the display panel is not synchronized with the supply of the display data Video and the frames do not match. Asynchronous (frame dropping or memory re-reading) occurs at both rates.
Furthermore, in the embodiment, a normally white mode in which white is displayed in a state in which no voltage is applied is used. However, a normally black mode in which black is displayed in a state in which no voltage is applied may be used.

<Electronic equipment>
Next, an example of an electronic apparatus using the electro-optical device according to the above-described embodiment will be described. FIG. 18 is a plan view illustrating a configuration of a three-plate projector using the display panel 10 of the electro-optical device 1 described above as a light valve.
In this projector 2100, the light to be incident on the light valve is supplied with three primary colors of R (red), G (green), and B (blue) by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. And led to the light valves 100R, 100G and 100B corresponding to the respective primary colors. Note that B light has a longer optical path than other R and G colors, and therefore, in order to prevent the loss, B light passes through a relay lens system 2121 including an incident lens 2122, a relay lens 2123, and an exit lens 2124. Led.

Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the display panel 10 in the above-described embodiment, and image data corresponding to each color of R, G, and B supplied from an external host device (not shown). Are driven respectively.
The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight. Therefore, after the images of the respective colors are combined, they are projected forward and enlarged by the lens unit 1820, so that a color image is displayed on the screen 2120.

  The transmitted images of the light valves 100R and 100B are projected after being reflected by the dichroic prism 2112, whereas the transmitted image of the light valve 100G is projected as it is, and thus the images formed by the light valves 100R and 100B The image formed by the light valve 100G has a left-right reversal relationship.

  In addition to the electronic devices described with reference to FIG. 18, rear projection televisions and direct-view types such as mobile phones, personal computers, video camera monitors, car navigation devices, pagers, electronic Examples include notebooks, calculators, word processors, workstations, videophones, POS terminals, digital still cameras, and devices equipped with touch panels. Needless to say, the electro-optical device according to the present invention is applicable to these various electronic devices.

1 is a block diagram illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. 2 is a diagram showing a configuration of a display panel in the same electro-optical device. FIG. It is a figure which shows the structure of the pixel in the display panel. It is a figure which shows operation | movement of the scanning-line drive circuit in the same display panel. It is a figure which shows the voltage waveform example of the data signal in the display panel. It is a figure which shows the voltage waveform example of the data signal in the display panel. It is a figure which shows transition of the writing of the pixel in a display area. It is an example which shows the state of the display area in the timing P. It is a figure which shows the flicker suppression operation | movement in the same electro-optical apparatus. It is a figure which shows transition of the writing of the pixel in a flicker suppression operation | movement. It is a figure which shows the flicker suppression operation | movement in the same electro-optical apparatus. It is a figure which shows transition of the writing of the pixel in a flicker suppression operation | movement. FIG. 6 is a block diagram illustrating a configuration of an electro-optical device according to a second embodiment of the invention. FIG. 3 is a block diagram illustrating an applied configuration of an electro-optical device according to the invention. It is a figure which shows the double speed drive system applicable to this invention. It is a figure which shows the double speed drive system applicable to this invention. It is a figure which shows the double speed drive system applicable to this invention. 1 is a diagram illustrating a configuration of a projector using an electro-optical device according to an embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Electro-optical apparatus, 10 ... Display panel, 50 ... Processing circuit, 52 ... Control circuit, 54 ... Display data processing circuit, 56 ... D / A conversion circuit, 105 ... Liquid crystal, 108 ... Counter electrode, 110 ... Pixel, 112 ... Scanning line, 114 ... Data line, 116 ... TFT, 118 ... Pixel electrode, 120 ... Liquid crystal capacitor, 130 ... Scanning line driving circuit, 140 ... Data line driving circuit, 142 ... Sampling signal output circuit, 146 ... TFT, 2100 ... projector

Claims (7)

A plurality of scanning lines and a plurality of data lines, respectively, corresponding to the intersections of the plurality of scanning lines and the plurality of data lines, each having a gradation according to a voltage of a data signal supplied to the data line when the scanning line is selected; An electro-optical device having a plurality of pixels,
A scanning line selection circuit that selects the plurality of scanning lines in a predetermined order in each of the first and second fields constituting one frame;
When one scanning line is selected in the first field, the voltage corresponding to the gradation of the pixel is higher than the pixel positioned on the one scanning line with reference to a predetermined potential. Supply the voltage of either the positive polarity or the negative polarity, which is lower, to the data line corresponding to the pixel as the data signal,
When the one scanning line is selected in the second field, the voltage corresponding to the gradation of the pixel is set to the positive polarity or the negative polarity with respect to the pixel located on the one scanning line. A data line driving circuit for supplying a voltage of the other polarity to the data line corresponding to the pixel as the data signal;
A control circuit for controlling the period length of the first and second fields with respect to the period length of the one frame so that the pixels located on the one scanning line have the same gradation in the first and second fields; ,
An electro-optical device comprising: An optical sensor that images a pixel supplied with a positive voltage and a pixel supplied with a negative voltage;
The control circuit controls a period length of the first and second fields with respect to a period length of the one frame so that gradations of pixels picked up by the photosensor are equal to each other. The electro-optical device according to 1. A temperature sensor that detects temperatures around the plurality of pixels;
2. The electro-optic according to claim 1, wherein the control circuit controls a period length of the first field and a second field with respect to a period length of the one frame according to a temperature detected by the temperature sensor. apparatus. A histogram creator for creating a histogram of gradations specified for the plurality of pixels;
2. The electric circuit according to claim 1, wherein the control circuit controls a period length of the first field and a second field with respect to a period length of the one frame according to a histogram created by the histogram creator. Optical device. The scanning line driving circuit sequentially selects a predetermined scanning line at a predetermined interval in a predetermined direction from a predetermined scanning line among the plurality of rows over the first and second fields of one frame. 2. The electro-optic according to claim 1, wherein the selection is performed in the predetermined direction in order from the scanning line as the start point over the second field of the next frame and the first field of the next frame. apparatus. A plurality of scanning lines and a plurality of data lines, respectively, corresponding to the intersections of the plurality of scanning lines and the plurality of data lines, each having a gradation according to a voltage of a data signal supplied to the data line when the scanning line is selected; A driving method of an electro-optical device having a plurality of pixels,
Selecting the plurality of scanning lines in a predetermined order in each of the first and second fields constituting one frame;
When one scanning line is selected in the first field, the voltage corresponding to the gradation of the pixel is higher than the pixel positioned on the one scanning line with reference to a predetermined potential. Supply the voltage of either the positive polarity or the negative polarity, which is lower, to the data line corresponding to the pixel as the data signal,
When the one scanning line is selected in the second field, the voltage corresponding to the gradation of the pixel is set to the positive polarity or the negative polarity with respect to the pixel located on the one scanning line. Supply the voltage of the other polarity as the data signal to the data line corresponding to the pixel,
The period length of the first and second fields is controlled with respect to the period length of the one frame so that the pixels located on the one scanning line have the same gradation in the first and second fields. A driving method of the electro-optical device.   An electronic apparatus comprising the electro-optical device according to claim 1.

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