JP2009058595A - Active matrix display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix display device capable of improving image quality, even when parasitic capacitance between pixels exists. <P>SOLUTION: In the active matrix display device, a first post-write pixel and a first pre-write pixel are adjacently arranged, and at an opposite side of the first pre-write pixel, a second pre-write pixel adjacent to the first post-write pixel is arranged on both sides of a first data signal line, and at an opposite side of the first post-write pixel, the second post-write pixel adjacent to the first pre-write pixel is arranged on both sides of the second data signal line. The first post-write pixel and the second pre-write pixel share the first data signal line, and the first pre-write pixel and the second post-write pixel share the second data signal line. Each pre-write pixel is connected to a first scan signal line and each post-write pixel is connected to a second scan signal line. A write adjustment period Dd is provided between a temporary write period Dsr and a main write period Dmr of each post-write pixel, and a scan line driving circuit which finishes the main write period Dmf of each post write pixel within the write adjustment period Dd, is provided in the display device. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an active matrix display device.

  In recent years, active matrix display devices using thin film transistors (TFTs) as switching elements have been developed.

  An active matrix display device supplies a display region with a plurality of pixels arranged in a matrix, a plurality of scanning signal lines for sequentially scanning each pixel row by row, and data to be written to each pixel. A plurality of data signal lines are formed. Each pixel is set to a common potential in each pixel, a TFT as a switching element having a gate electrode connected to the scanning signal line and a drain electrode connected to the data signal line, a pixel electrode connected to the source electrode of the TFT, and And a storage capacitor for accumulating charges for keeping the potential difference between the pixel electrode and the common electrode at a predetermined potential difference. Here, between the pixel electrode and the common electrode, for example, a liquid crystal whose alignment state changes according to a potential difference between the pixel electrode and the common electrode is disposed.

  Around the display area, each scanning signal line is connected to each gate, and through each scanning signal line, each TFT is scanned (on / off control), and each data signal line is connected. A data driver for outputting a predetermined data voltage to each pixel (each auxiliary capacitor or liquid crystal) via each data signal line is formed.

  By the way, an active matrix display device may be incorporated as a monitor unit of a small portable device such as a mobile phone or a digital camera. In such a case, it is preferable that the frame as the outer peripheral portion of the display area can be narrowed, and gate drivers and source drivers that occupy a relatively large area are concentratedly arranged on either side of the frame. In addition, these mounting processes can be simplified by collectively arranging gate drivers and source drivers. However, in such a case, depending on the arrangement position of the gate driver and the source driver, the scanning signal line or the data signal line is drawn around the display area (frame) over a long distance. In order to further reduce the routing area, instead of doubling the number of scanning signal lines, a pixel connection configuration in which the number of data signal lines is halved is considered. (For example, FIG. 5 of patent document 1)

  FIG. 15 is a schematic diagram of an example of pixel connection in a display screen, which is considered as one method for achieving such a narrow frame. In this case, one data signal line S (i) is shared by two adjacent pixels P (i, j). In this case, the TFTs corresponding to these two pixels P (i, j) are connected to different scanning signal lines G (j).

  For example, in FIG. 15, the TFT corresponding to the upper left pixel P (1,1) is connected to the scanning signal line G (1) and the data signal line S (1), and the pixel P (1,2) on the right side thereof. ) Is connected to the scanning signal line G (2) and the data signal line S (1).

FIG. 16 shows the scanning direction (each scanning signal waveform) of the scanning signal line G (j) when the video signal Vsig is written to each pixel P (i, j) in such an active matrix display device, and the data signal line. The writing order between adjacent pixels P (i, j) sharing S (i) is shown. For example, each pixel P (1, j) connected to the data signal line S (1) includes a pixel P (1, 1), a pixel P (1, 2), a pixel P (1, 3), and a pixel P ( 1, 4) are written in this order.
JP 2004-185006 A

  In the pixel connection for halving the number of data signal lines as described above, there are portions where there is a data signal line between pixels adjacent in the extending direction of the scanning signal line. Further, between adjacent pixels having no data signal line between the pixels, the inter-pixel parasitic capacitance Cpp generated between the adjacent pixels is very large as compared to between adjacent pixels having the data signal line between the pixels. FIG. 17 is a diagram showing an equivalent circuit at this time. Between adjacent pixels having no data signal line between the pixels, voltage leakage occurs due to the influence of the inter-pixel parasitic capacitance Cpp. For this reason, the adjacent pixels affect the other pixel when data is written to the one pixel.

  At this time, among the above-described adjacent pixels, a pixel in which data is written later in each frame (referred to as “post-write pixel Pr”) is a pixel in which data is written first (referred to as “pre-write pixel Pf”). After data is affected by the potential when data is written, new data is written during one scanning period. However, the pre-write pixel Pf remains affected until new data is written in the next frame after being influenced by the potential when the post-write pixel Pr is written with data. That is, the two adjacent pixels have different degrees of influence given by the inter-pixel parasitic capacitance Cpp, and thus appear as display unevenness on the screen. In particular, when the polarity of the voltage applied to the liquid crystal is inverted between the previous frame and the current frame (for example, frame inversion driving), when writing a new data potential to the post-write pixel Pr, the pre-write pixel Pf Since the difference between the newly written data potential (current frame data potential) and the data potential previously written to the post-write pixel Pr (previous frame data potential) increases, the inter-pixel parasitic capacitance Cpp As a result, the potential fluctuation to the pre-written pixel Pf also increases, and the display unevenness becomes remarkable. Further, since the pixel writing order does not change as shown in FIG. 16, display unevenness caused by the inter-pixel parasitic capacitance Cpp is caused in the direction along the data signal line, for example, as shown in FIG. Striped display unevenness occurs.

  The present invention has been made in view of such a conventional problem, and an object of the present invention is to provide an active matrix display device capable of improving the image quality even when an inter-pixel parasitic capacitance exists.

  In order to achieve the above-described object, an active matrix display device according to the first aspect of the present invention has a first pixel and a second pixel arranged adjacent to each other in a predetermined direction. A third pixel adjacent to the first pixel is disposed in the opposite direction across the first data signal line, and the second data signal line is sandwiched in the direction opposite to the first pixel. A fourth pixel adjacent to the second pixel is disposed, the first pixel and the third pixel share the first data signal line, and the second pixel and the fourth pixel Pixels share the second data signal line, the first pixel and the fourth pixel are connected to the first scanning signal line, and the second pixel and the third pixel are the second An active matrix display device connected to a scanning signal line, wherein The first scanning signal line and the second scanning signal line are simultaneously selected for the first period, and the second scanning signal line is selected before the selection of the first scanning signal line is canceled. And a scanning line driving circuit for canceling the selection of the first scanning signal line until the next selection of the second scanning signal line.

  In the active matrix display device according to the second aspect of the present invention, the first post-write pixel and the first pre-write pixel are arranged adjacent to each other in a predetermined direction, and the first pre-write pixel A second pre-write pixel adjacent to the first post-write pixel is disposed across the first data signal line in a direction opposite to the pixel, and is opposite to the first post-write pixel. A second post-write pixel adjacent to the first pre-write pixel across the second data signal line in the direction of the first post-write pixel and the second pre-write pixel Embedded pixels share the first data signal line, the first pre-write pixel and the second post-write pixel share the second data signal line, and each pre-write pixel is An active matrix connected to a first scanning signal line, wherein each post-write pixel is connected to a second scanning signal line In the display device, a predetermined writing adjustment period is provided between the temporary writing period and the main writing period of each post-writing pixel, and the main writing of each of the pre-written pixels is performed during the writing adjustment period. A scan line driver circuit for ending the period is provided.

  According to the present invention, it is possible to improve image quality even when there is an inter-pixel parasitic capacitance.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  The schematic overall configuration of the active matrix display device 1 according to the present invention includes a liquid crystal display unit 10 in which a plurality of pixels to be described later are arranged as shown in FIGS. 1 and 2, and each pixel of the liquid crystal display unit 10 is driven. The driver circuit 11 to be controlled and the Vcom circuit 12 that supplies the common voltage Vcom to the liquid crystal display unit 10 are configured.

  The liquid crystal display unit 10 has a configuration in which a liquid crystal LC is sandwiched between two substrates 10a and 10b which are arranged opposite to each other and bonded by a sealing material 10c. On the opposite surface side of one substrate 10b, as shown in FIGS. 3 and 4, a plurality of pixels P (i, j) arranged in a matrix and each pixel P (i, j) are arranged. A plurality of scanning signal lines G (j) for sequentially scanning each time and a plurality of data signal lines S (i) for supplying data to be written to each pixel P (i, j) are formed. Each pixel P (i, j) is connected to a TFT as a switching element having a gate electrode connected to the scanning signal line G (j) and a drain electrode connected to the data signal line S (i), and a source electrode of the TFT. And a storage capacitor Ccs that accumulates charges for maintaining the potential difference between the pixel electrode pix and the common electrode GND formed on the other substrate 10a at a predetermined potential difference. I = 1, 2, 3,..., X. j = 1, 2, 3,..., y. The common electrode GND is configured to have the same potential in each pixel. That is, the common electrode GND is formed over the entire surface, for example, on the opposite surface side of the other substrate 10a.

  Here, the data signal line S (i) and the scanning signal line G (j) are arranged so as to cross each other. Then, each pixel P (i, j) crosses each other with any one of the data signal lines S (i) and any one of the scanning signal lines G (j) through the TFTs as switching elements as described above. Connected nearby. Further, every two pixels are connected so that one data signal line S (i) is shared by two adjacent pixels P (i, j). Further, the TFTs corresponding to the two pixels P (i, j) are connected to different scanning signal lines G (j), respectively.

  For example, in FIGS. 3 and 4, the TFT corresponding to the upper left pixel P (1,1) is connected to the scanning signal line G (1) and the data signal line S (1), and the pixel P ( The TFTs corresponding to 1 and 2) are connected to the scanning signal line G (2) and the data signal line S (1).

  The pixel P (1,2) is disposed adjacent to the pixel P (1,1) with the data signal line S (1) interposed therebetween. What is the direction of the pixel P (1,1)? The pixel P (2, 1) adjacent in the opposite direction is adjacently disposed without sandwiching the data signal line S (i). The pixel P (2,1) is disposed adjacent to the pixel P (2,2) with the data signal line S (2) interposed therebetween.

  Although details of the structure of each pixel P (i, j) will be described later, each pixel P (i, j) connected to the odd-numbered scanning signal line G (j) has a structure of a TFT or an auxiliary capacitor. The arrangement relationship with the scanning signal line G (j) and the data signal line S (i) corresponding to them is configured to be equal. Each pixel P (i, j) connected to the even-numbered scanning signal line G (j) has a TFT and auxiliary capacitance structure, and the corresponding scanning signal line G (j) and data signal line S. The arrangement relationship with (i) is configured to be equal.

  Here, a specific configuration of each pixel P (i, j) will be described with reference to FIGS. One substrate 10 b is provided with a scanning signal line G (j) including a gate electrode 51. A storage capacitor line 48 is provided in the same layer as the scanning signal line G (j). That is, the scanning signal line G (j) and the auxiliary capacitance line 48 are formed in a lump. A gate insulating film 52 is provided on the entire upper surface. A semiconductor thin film 53 made of intrinsic amorphous silicon is provided on the upper surface of the gate insulating film 52. A channel protective film 54 is provided at substantially the center of the upper surface of the semiconductor thin film 53. Contact layers 55 and 56 made of n-type amorphous silicon are provided on both sides of the upper surface of the channel protective film 54 and on the upper surface of the semiconductor thin film 53 on both sides thereof.

  A source electrode 57 is provided on the upper surface of one contact layer 55. A data signal line S (i) including a drain electrode 58 is provided on the upper surface of the other contact layer 56 and the upper surface of the gate insulating film 52.

  The gate electrode 51, the gate insulating film 52, the semiconductor thin film 53, the channel protective film 54, the contact layers 55 and 56, the source electrode 57 and the drain electrode 58 constitute a TFT.

  A planarizing film 59 is provided on the entire upper surface of the gate insulating film 52 including the TFT and the like. A contact hole 60 is provided in a portion corresponding to a predetermined portion of the source electrode 57 of the planarizing film 59. A pixel electrode pix made of ITO is provided at a predetermined position on the upper surface of the planarizing film 59. The pixel electrode pix is connected to the source electrode 57 through the contact hole 60.

  Here, the portion of the auxiliary capacitance line 48 that overlaps the pixel electrode pix is an auxiliary capacitance electrode. An auxiliary capacitor Ccs is formed by the overlapped portion. In addition, the size of the auxiliary capacitance Ccs in each pixel P (i, j) is configured to be equal. The auxiliary capacitance line 48 is electrically connected to the common electrode GND (has the same potential).

  In each pixel P (i, j), the alignment state of the liquid crystal to be disposed between the pixel electrode pix and the common electrode GND is determined based on the potential difference between the pixel electrode pix and the common electrode GND. By changing it, the display state can be controlled.

  Since the liquid crystal LC is sandwiched between the pixel electrode pix and the common electrode GND, a liquid crystal capacitance Clc is formed by these. The liquid crystal capacitors Clc are configured to be equal between the pixels. In other words, for example, the thickness of the liquid crystal layer in the corresponding region and the area of the pixel electrode pix are equal between the pixels P (i, j).

  Further, the common electrode GND may be configured to be provided on one substrate 10b. That is, in this embodiment, a horizontal electric field method in which a potential difference is generated in the in-plane direction of the substrate and applied to the liquid crystal, or a vertical electric field method in which a potential difference is generated between the two substrates and applied to the liquid crystal. It is applicable to any of these.

  1 and 2, the data signal lines S (i) and the scanning signal lines G (j) are connected to the wiring groups 20 </ b> S and 20 </ b> G routed on one substrate 10 b in the peripheral region of the liquid crystal display unit 10. Therefore, the driver circuit 11 is electrically connected to the right side of the liquid crystal display unit 10. The common electrode GND is electrically connected to the Vcom circuit 12.

  In the liquid crystal display unit 10, the data signal line S (i) is formed to be extended in a direction parallel to the driver circuit 11, and the scanning signal line G (j) is a driver on the extension direction side. The circuit 11 is formed to come. In addition, with the wiring configuration as described above, the width of the wiring group 20S can be halved compared to a configuration in which different data signal lines are associated with each pixel arranged in the scanning signal line direction. It has become a structure.

  As shown in FIG. 7, the driver circuit 11 includes a gate driver block 22, a source driver block 24, a level shifter circuit 26, a timing generator (hereinafter abbreviated as TG) logic circuit 28, and a gamma (hereinafter abbreviated as γ). The circuit block 30, the charge pump / regulator block 32, the analog block 34, and other blocks are included.

  Here, the gate driver block 22 sequentially selects each scanning signal line G (j), and the source driver block 24 applies a video signal according to information to be displayed to each data signal line S (i). Vsig is output.

  The level shifter circuit 26 shifts the level of an externally supplied signal to a predetermined level. The TG unit logic circuit 28 generates a necessary timing signal and control signal based on the signal shifted to a predetermined level by the level shifter circuit 26 and a signal supplied from the outside, and supplies it to each unit in the driver circuit 11. To do.

  The γ circuit block 30 is for performing γ correction so that the video signal Vsig output from the source driver block 24 has good gradation characteristics.

  The charge pump / regulator block 32 generates various voltages of a required logic level from an external power supply, and the analog block 34 further generates various voltages from the voltage generated by the charge pump / regulator block 32. Is. The Vcom circuit 12 generates a common potential Vcom from the voltage VVCOM generated in the analog block 34 and supplies it to the common electrode GND.

  FIG. 8 is a diagram illustrating a configuration example of the gate driver block 22. Here, for simplicity of explanation and illustration, the number of scanning signal lines G (j) is assumed to be eight. In this case, the gate driver block 22 includes a 3-bit counter 36, nine AND gates, two OR gates, three NOT gates, and one NAND gate.

  That is, a gate clock and an up / down (hereinafter abbreviated as U / D) signal are supplied from the TG unit logic circuit 28 to the 3-bit counter 36. The U / D signal is “1” during non-inversion shift driving, which is normal display, and “0” during up-down inversion shift driving, in which a display image is inverted upside down. This is because the scanning direction of the scanning signal line is reversed upside down during non-inversion shift driving and upside down shift driving. As a result, the pixel to which data is written first (the pre-written pixel Pf) and the data are written later. This is because the pixel (post-write pixel Pr) to be reversed is reversed, and the operation needs to be switched accordingly.

  The Q1 output of the 3-bit counter 36 is supplied to an AND gate for even-numbered scanning signal lines G (2), G (4), G (6), G (8) through an OR gate. An output signal of an AND gate that performs a logical operation between the U / D signal and a gate double (hereinafter referred to as GDOUBLE) signal supplied from the TG unit logic circuit 28 is supplied to the OR gate. Here, the GDOUBLE signal is “0” in the normal mode, which is a normal display state, and “2” in the gate double writing mode in which the display unevenness reduction driving (hereinafter referred to as “gate double writing driving”) according to this embodiment is performed. 1 ". The Q1 output of the 3-bit counter 36 is further connected to an AND gate for odd-numbered scan signal lines G (1), G (3), G (5), G (7) via a NAND gate. Given to. The NAND gate is supplied with an output signal of an OR gate gate that performs a logical operation on the U / D signal and a signal obtained by inverting the GDOUBLE signal at the NOT gate, and the output of the NAND gate is an odd-numbered scanning signal line G ( 1), G (3), G (5), and G (7).

  The Q2 output of the 3-bit counter 36 is supplied to the AND gate for the scanning signal lines G (3), G (4), G (7), G (8), and via a NOT gate. The scanning signal lines G (1), G (2), G (5), and G (6) are supplied to AND gates.

  The Q3 output of the 3-bit counter 36 is supplied to the AND gate for the scanning signal lines G (5), G (6), G (7), G (8), and via the NOT gate. The scan signal lines G (1), G (2), G (3), and G (4) are supplied to AND gates.

  FIG. 9 is a diagram showing a timing chart at the time of non-inversion shift driving in the gate double writing mode executed by the gate driver block 22 having such a configuration. FIG. 10 is also a diagram showing a timing chart at the time of vertical inversion shift driving.

  At the time of non-inverted shift driving, as shown in FIG. 9, the odd-numbered scanning signal lines G (1), G (3), G (5), G (7) have a period corresponding to one gate clock, Hi level signals are sequentially output to the even-numbered scanning signal lines G (2), G (4), G (6), and G (8) for a period corresponding to two gate clocks. . That is, in terms of timing, only the scanning signal line G (1) and the scanning signal line G (2) are selected → only the scanning signal line G (2) is selected → the scanning signal line G (3) and the scanning signal line Only G (4) is selected → Only the scanning signal line G (4) is selected → Only the scanning signal line G (5) and the scanning signal line G (6) are selected → Only the scanning signal line G (6) is selected Selection state → only the scanning signal line G (7) and the scanning signal line G (8) are in the selection state → only the scanning signal line G (8) is in the selection state. The pixels connected corresponding to the odd-numbered scanning signal lines G (1), G (3), G (5), G (7), that is, the pixels P (i, 1), P (i , 3), P (i, 5), P (i, 7) are pre-written pixels Pf, and even-numbered scanning signal lines G (2), G (4), G (6), G (8) , That is, the pixels P (i, 2), P (i, 4), P (i, 6), and P (i, 8) are the post-writing pixels Pr.

  Further, at the time of upside down shift driving, as shown in FIG. 10, the even-numbered scanning signal lines G (2), G (4), G (6), G (8) correspond to one gate clock. The high level signal is sequentially applied in the reverse direction to the odd-numbered scanning signal lines G (1), G (3), G (5), and G (7) in a period corresponding to two gate clocks. Will be output. That is, in terms of timing, only the scanning signal line G (8) and the scanning signal line G (7) are selected → only the scanning signal line G (7) is selected → the scanning signal line G (6) and the scanning signal line Only G (5) is selected → Only the scanning signal line G (5) is selected → Only the scanning signal line G (4) and the scanning signal line G (3) are selected → Only the scanning signal line G (3) is selected Selection state → only the scanning signal line G (2) and the scanning signal line G (1) are in the selection state → only the scanning signal line G (1) is in the selection state. The pixels connected in correspondence with the even-numbered scanning signal lines G (2), G (4), G (6), G (8), that is, the pixels P (i, 2), P (i , 4), P (i, 6), P (i, 8) are pre-written pixels Pf, and odd-numbered scanning signal lines G (1), G (3), G (5), G (7) That is, the pixels connected in correspondence with each other, that is, the pixels P (i, 1), P (i, 3), P (i, 5), and P (i, 7) are the post-writing pixels Pr.

  In the non-inversion shift driving, the driver circuit 11 includes pixels P (i, 1), P (i, 3), P (i, 5), and P (i, 7) as the pre-written pixels Pf. When writing new data via the data signal line S (i), the same data as that pixel is also written to the post-writing pixel Pr adjacent to the pixel. Further, at the time of vertical inversion shift driving, the data signal line is connected to the pixels P (i, 2), P (i, 4), P (i, 6), and P (i, 8) as the pre-written pixels Pf. When writing new data via S (i), the same data as that pixel is also written to the post-writing pixel Pr adjacent to the pixel.

  That is, the driver circuit 11 performs provisional writing of the post-writing pixel Pr at the time of main writing to the pre-writing pixel Pf and performs main writing of the post-writing pixel Pr after main writing to the pre-writing pixel Pf. To do.

  Therefore, in the active matrix display device 1 according to the present embodiment, data having the same polarity as the data of the pre-written pixel Pf in the current frame is supplied to the post-written pixel Pr in both the non-inverted shift driving and the up / down inverted shift driving. Since data can be written in advance, the difference between the data potential of the pre-write pixel Pf and the data potential of the post-write pixel Pr when writing original data to the post-write pixel Pr can be reduced. As a result, display unevenness caused by the inter-pixel parasitic capacitance Cpp can be reduced.

  By the way, in the active matrix display device 1 of the present embodiment, as shown in FIG. 4, between the scanning signal line G (j) and the pixel electrode pix, or between the gate electrode 51 and the source electrode 57 in the TFT. In addition, parasitic capacitance Cgs is generated.

  Therefore, as shown in FIG. 11, at the timings T1 and T3 when the TFT corresponding to the prewritten pixel Pf is turned off, the pull-in voltage ΔVFa is generated in the prewritten pixel Pf due to the parasitic capacitance Cgs of the pixel. . At this time, since the TFT corresponding to the post-write pixel Pr is kept on, the post-write pixel Pr maintains the write potential to the pixel at this time.

  Further, at the timings T2 and T4 when the TFT corresponding to the post-write pixel Pr is turned off, the pull-in voltage ΔVR is generated in the post-write pixel Pr by the parasitic capacitance Cgs in the pixel. At this time, since the TFT corresponding to the pre-write pixel Pf is in the OFF state, in the pre-write pixel Pf, due to the inter-pixel parasitic capacitance Cpp between the pre-write pixel Pf and the post-write pixel Pr, The pull-in voltage ΔVFb is generated under the influence of the pull-in voltage ΔVR at the post-write pixel Pr.

  For this reason, in most of the pixel potential holding period (during the period when the TFT is off), a potential shift of ΔVFc (ΔVFc = ΔVFa + ΔVFb) occurs in the pre-written pixel Pf with respect to the potential to be written. At the same time, a potential shift of ΔVR occurs in the post-writing pixel Pr.

  The potential shift of the pixel electrode pix as described above due to the influence of the parasitic capacitance Cgs affects the execution voltage applied to the liquid crystal LC and appears in the display as a flicker phenomenon. In the present embodiment, the potential shift of the common electrode GND is performed to correct the change in the effective voltage applied to the liquid crystal LC generated by the potential shift of the pixel electrode pix. By the way, in order to make the active matrix display device simpler, it is preferable that the potential of the common electrode GND is common among the pixels. In order to eliminate both of the flicker phenomenon occurring in the pre-write pixel Pf and the post-write pixel Pr while making the potential of the common electrode GND common among the pixels, it occurs in the pre-write pixel Pf. It is preferable that the pull-in voltage ΔVFc is equal to the pull-in voltage ΔVR generated in the post-writing pixel Pr.

  Here, the relationship between the pre-write pixel Pf and the post-write pixel Pr is, for example, that if the pixel P (1,2) is the pre-write pixel Pf, the pixel P (2,1) is the post-write corresponding to it. The embedded pixel Pr can be used. Cpp is an inter-pixel parasitic capacitance between the pixel P (2,1) and the pixel P (1,2). For example, if the pixel P (1, 4) is the pre-write pixel Pf, the pixel P (2, 3) can be the post-write pixel Pr corresponding thereto. Cpp is an inter-pixel parasitic capacitance between the pixel P (2, 3) and the pixel P (1, 4).

  Hereinafter, ΔVFc and ΔVR will be described in detail based on FIG. FIG. 12 is an equivalent circuit diagram obtained by partially extracting and expanding the equivalent circuit diagram shown in FIG. Further, it is assumed that the capacitance values of the parasitic capacitance Cgs generated corresponding to the pre-write pixel Pf and the post-write pixel Pr are equal. That is, it is assumed that the structure of the TFT corresponding to each pixel and the distance relationship between the pixel electrode pix and the scanning signal line are equal between the pixels. Further, the auxiliary capacitance Ccs corresponding to the pre-writing pixel Pf and the auxiliary capacitance Ccs corresponding to the post-writing pixel Pr are assumed to have the same capacitance value. That is, the area A of the auxiliary capacitance electrode constituting the auxiliary capacitance, and the dielectric constant and thickness of the dielectric (gate insulating film 52 and planarization film 59) sandwiched between the auxiliary capacitance electrode and the pixel electrode pix are set. It is assumed that the auxiliary capacitance is equalized between the pixels by adjusting appropriately.

  In the equivalent circuit shown in FIG. 12, if the potential fluctuation at the node Na generated by the potential fluctuation ΔVg1 of the scanning signal line G (q) is ΔVna1, and the potential fluctuation at the node Nb is ΔVnb1, Equation 1 is established. Note that here, the common electrode GND is fixed to a predetermined potential and the potential does not change.

(Equation 1)
Cgs · (ΔVna1−ΔVg1) + ΔVna1 (Ccs + Clc) + Cpp (ΔVna1−ΔVnb1) = 0

  Further, if the potential fluctuation at the node Nb that occurs with the potential fluctuation ΔVg2 of the scanning signal line G (q + 1) is ΔVnb2, and the potential fluctuation at the node Na is ΔVna2, (Equation 2) holds. In this case as well, the common electrode GND is fixed to a predetermined potential and the potential does not change.

(Equation 2)
Cgs · (ΔVnb2−ΔVg2) + ΔVnb2 (Ccs + Clc) + Cpp (ΔVnb2−ΔVna2) = 0

  Here, it is assumed that the scanning signal lines G (q) and G (q + 1) are driven so that the potential fluctuation width (difference between the gate potential H when turned on and the gate potential L when turned off) is equal. ΔVg1 = ΔVg2 = Vg can be rewritten, and (Equation 1) and (Equation 2) can be rewritten as (Equation 3) and (Equation 4), respectively.

(Equation 3)
Cgs · (ΔVna1−Vg) + ΔVna1 (Ccs + Clc) + Cpp (ΔVna1−ΔVnb1) = 0

(Equation 4)
Cgs · (ΔVnb2−Vg) + ΔVnb2 (Ccs + Clc) + Cpp (ΔVnb2-ΔVna2) = 0

  Based on (Equation 3) and (Equation 4), the pull-in voltage ΔVFa generated in the pre-written pixel Pf at the timings T1 and T3 shown in FIG. 11 can be expressed as (Equation 5).

  Further, the pull-in voltage ΔVFb generated in the pre-written pixel Pf at the timings T2 and T4 shown in FIG. 11 can be expressed as (Equation 6).

  Therefore, the final pull-in voltage ΔVFc generated in the pre-written pixel Pr can be expressed as (Equation 7).

  On the other hand, the pull-in voltage ΔVR generated in the post-write pixel Pr at the timings T2 and T4 shown in FIG. 11 can be expressed as (Equation 8).

  Therefore, for example, when each scanning signal line is driven by the scanning signal as shown in FIG. 11, the final pull-in voltage ΔVFc generated in the pre-written pixel Pf is generated in the post-written pixel Pr. The final pull-in voltage ΔVFc to be increased by Γ × Cpp / (Clc + Ccs).

  Therefore, while it becomes possible to previously write data having the same polarity as the data of the pre-write pixel Pf in the current frame to the post-write pixel Pr, the final pull-in voltage generated in the pre-write pixel Pf is further increased. FIG. 13 shows an example of a scanning signal that can equalize the final pull-in voltage generated in the post-writing pixel Pr.

  In the scanning signal shown in FIG. 13, with respect to the scanning signal for the post-writing pixel Pr, a writing adjustment period Dd for temporarily turning off the TFT is provided between the temporary writing period Dsr and the main writing period Dmr. . The writing adjustment period Dd starts during the main writing period Dmf of the scanning signal for the previous writing pixel Pf and ends after the main writing period Dmf of the scanning signal for the previous writing pixel Pf ends.

  That is, the main writing period Dmf of the scanning signal for the previous writing pixel Pf is ended during the writing adjustment period Dd of the scanning signal for the post-writing pixel Pr.

  Hereinafter, the pull-in voltage when driven by the scanning signal shown in FIG. 13 will be described in detail. At the timing Ta, Te at which the TFT corresponding to the post-write pixel Pr is turned off (at the end of the temporary write period Dd), the pull-in voltage ΔVR1 is generated in the post-write pixel Pr due to the parasitic capacitance Cgs of the pixel. At this time, since the TFT corresponding to the pre-write pixel Pf is kept on, the pre-write pixel Pf maintains the write potential to the pixel at this time. The pull-in voltage ΔVR1 can be expressed as (Equation 9).

  In addition, at the timings Tb and Tf when the TFT corresponding to the pre-write pixel Pf is turned off (at the end of the main write period Dmf), the pull-in voltage ΔVF2 is generated in the pre-write pixel Pf by the parasitic capacitance Cgs of the pixel. To do. At this time, since the TFT corresponding to the post-write pixel Pr is in the OFF state, in the post-write pixel Pr, due to the inter-pixel parasitic capacitance Cpp between the pre-write pixel Pf and the post-write pixel Pr, A pull-in voltage ΔVR2 is generated under the influence of the pull-in voltage ΔVF2 at the pre-write pixel Pf. The pull-in voltages ΔVF2 and ΔVR2 can be expressed as (Equation 10) and (Equation 11), respectively.

  Further, at the timings Tc and Tg when the TFT corresponding to the post-write pixel Pr is turned on (at the start of the main write period Dmr), the target potential is written into the post-write pixel Pr, so that the original write is performed. It recovers to the potential that should be. That is, the pull-in voltage ΔVR1 + ΔVR2 generated in the post-write pixel Pr by the timings Tc and Tg is eliminated. On the other hand, at this time, in the pre-write pixel Pf, since the TFT corresponding to the pre-write pixel Pf is in the OFF state, the inter-pixel parasitic capacitance Cpp between the pre-write pixel Pf and the post-write pixel Pr. Thus, the pull-in cancellation voltage ΔVF3 is generated under the influence of the potential fluctuation in the post-writing pixel Pr. The pull-in cancellation voltage ΔVF3 can be expressed as (Equation 12).

  At the timings Td and Th at which the TFT corresponding to the post-write pixel Pr is turned off (at the end of the main write period Dmr), the pull-in voltage ΔVR4 is generated in the post-write pixel Pr due to the parasitic capacitance Cgs of the pixel. To do. At this time, since the TFT corresponding to the pre-write pixel Pf is in the OFF state, in the pre-write pixel Pf, due to the inter-pixel parasitic capacitance Cpp between the pre-write pixel Pf and the post-write pixel Pr, Under the influence of the pull-in voltage ΔVR4 at the post-writing pixel Pr, the pull-in voltage ΔVF4 is generated. The pull-in voltages ΔVR4 and ΔVF4 can be expressed as (Equation 13) and (Equation 14), respectively.

  That is, it can be seen that the final pull-in voltage ΔVF5 generated in the pre-write pixel Pf is equal to the final pull-in voltage ΔVR4 generated in the post-write pixel Pr as shown in (Formula 15).

  As described above, if the main writing period Dsf of the scanning signal for the pre-writing pixel Pf is ended during the writing adjustment period Dd of the scanning signal for the post-writing pixel Pr, the data of the pre-writing pixel Pf in the current frame While it is possible to write data of the same polarity in advance in the post-write pixel Pr, the final pull-in voltage generated in the pre-write pixel Pf and the final voltage generated in the post-write pixel Pr The pull-in voltage can be made equal. Thus, by performing the potential shift of the common electrode GND, it is possible to eliminate both the flicker phenomenon occurring in the pre-write pixel Pf and the post-write pixel Pr, and as a result, the image quality can be improved. it can.

  In the above-described embodiment, the case of the stripe arrangement in which the pixels are arranged in a stripe shape has been described. However, the present invention can also be applied to the case of a delta arrangement as shown in FIG.

  Further, in the above-described embodiment, each pixel is formed so that the parasitic capacitance Cgs, the auxiliary capacitance Ccs, and the like are equal between the pixels, and at the time of turning on between the pre-write pixel Pf and the post-write pixel Pr. However, the present invention is not limited to this, and the pull-in voltage between the pre-write pixel Pf and the post-write pixel Pr is not limited to this. Need only be configured to be equal. That is, in the above-described embodiment, the pull-in voltage ΔVF5 and the pull-in voltage ΔVR4 may be configured to be equal.

Schematic plan view of an active matrix display device according to the present invention Schematic cross-sectional configuration diagram of an active matrix display device according to the present invention Layout of each pixel in the liquid crystal display Equivalent circuit diagram for liquid crystal display Pixel configuration diagram Cross-sectional diagram of the pixel Block diagram of driver circuit Configuration example of gate driver block Timing chart for non-inverted shift drive in gate double write mode Timing chart when driving upside down shift in gate double writing mode Explanatory diagram of generation amount and generation timing of each pull-in voltage Equivalent circuit diagram Explanatory diagram of generation amount and generation timing of each pull-in voltage Illustration of delta arrangement Schematic diagram of pixel connection example Scanning method in the prior art Illustration of parasitic capacitance between pixels Example of uneven display

Explanation of symbols

1: Active matrix display device 10: Liquid crystal display unit 11: Driver circuit 12: Vcom circuit S (i): Data signal line (i = 1, 2, 3,..., X)
G (j): scanning signal line (j = 1, 2, 3,..., Y)
P (i, j): Pixel pix: Pixel electrode Clc: Liquid crystal capacitance Ccs: Auxiliary capacitance Cgs: Parasitic capacitance Cpp: Interpixel parasitic capacitance Dmf: Full writing period of scanning signal for pre-written pixels Dsr: For post-written pixels Temporary writing period of scanning signal Dmr: Full writing period of scanning signal for post-writing pixel Dd: Writing adjustment period of scanning signal for post-writing pixel

Claims (2)

A first pixel and a second pixel are arranged adjacent to each other in a predetermined direction;
A third pixel adjacent to the first pixel is disposed in a direction opposite to the second pixel across the first data signal line;
A fourth pixel that is adjacent to the second pixel across the second data signal line in a direction opposite to the first pixel;
The first pixel and the third pixel share the first data signal line;
The second pixel and the fourth pixel share the second data signal line;
The first pixel and the fourth pixel are connected to a first scanning signal line;
An active matrix display device in which the second pixel and the third pixel are connected to a second scanning signal line,
The first scanning signal line and the second scanning signal line are simultaneously selected for a first period, and the second scanning signal line is selected before the selection of the first scanning signal line is canceled. An active matrix display device comprising: a scanning line driving circuit that cancels selection and cancels selection of the first scanning signal line until the next selection of the second scanning signal line. A first post-write pixel and a first pre-write pixel are arranged adjacent to each other in a predetermined direction;
A second pre-write pixel adjacent to the first post-write pixel is disposed across the first data signal line in a direction opposite to the first pre-write pixel;
A second post-write pixel adjacent to the first pre-write pixel is disposed across the second data signal line in a direction opposite to the first post-write pixel;
The first post-write pixel and the second pre-write pixel share the first data signal line;
The first pre-write pixel and the second post-write pixel share the second data signal line;
An active matrix display device in which each of the pre-written pixels is connected to a first scanning signal line and each of the post-written pixels is connected to a second scanning signal line;
A predetermined write adjustment period is provided between the temporary write period and the main write period of each post-write pixel,
An active matrix display device comprising: a scanning line driving circuit for ending the main writing period of each of the pre-written pixels during the writing adjustment period.

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