JP5360083B2 - Liquid crystal display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of preventing degradation of image quality, even when the positional shift of a pixel electrode is caused in a vertical direction component with respect to the extension direction of a scan line. <P>SOLUTION: In the liquid crystal display device, a first pixel P(i, 1) and a second pixel P(i, 2) adjacent to each other in a predetermined direction share one data line S(i). The first pixel P(i, 1) is connected to a first scan line G(1), and the second pixel P(i,2) is connected to a second scan line G(2), and a display signal voltage Vd is written to the first pixel P(i, 1) with timing different from the second pixel P(i, 2), and the display signal voltage Vd has two different voltage levels for a predetermined grayscale level. When the display signal voltage Vd is written to the pixel, a common signal Vcom is supplied to a common electrode Gn so that potential differences Vc1 and Vc2 with center voltages Vdc of the two voltage levels between the first pixel P(i, 1) and the second pixel P(i, 2) become different. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  In the present invention, a first pixel and a second pixel adjacent in a predetermined direction share one data line, the first pixel is connected to a first scan line via a first switching element, and the second pixel A liquid crystal display in which a pixel is connected to a second scan line via a second switching element, and the first pixel and the second pixel are disposed between the first scan line and the second scan line Relates to the device.

  In recent years, an active matrix liquid crystal display device using a thin film transistor (TFT) as a switching element has been developed.

  An active matrix liquid crystal display device supplies a plurality of pixels arranged in a matrix, a plurality of scanning lines for sequentially scanning each pixel row by row, and data to be written to each pixel. A plurality of data lines are formed. Each pixel is set to a common potential between the TFT as a switching element having a gate electrode connected to the scanning line and a drain electrode connected to the data line, and a pixel electrode connected to the source electrode of the TFT. And a storage capacitor for accumulating charges for keeping the potential difference between the pixel electrode and the common electrode at a predetermined potential difference. Here, between the pixel electrode and the common electrode, for example, a liquid crystal whose alignment state changes according to a potential difference between the pixel electrode and the common electrode is disposed.

  The display area is connected to each scanning line, and connected to each data line through a gate driver for scanning (turning on and off) each TFT through each scanning line. A data driver that outputs a predetermined data voltage to each pixel (each auxiliary capacitor or liquid crystal) via a data line is formed.

  By the way, an active matrix liquid crystal display device may be incorporated as a monitor unit of a small portable device such as a mobile phone or a digital camera. In such a case, it is preferable that the frame as the outer peripheral portion of the display area can be narrowed, and gate drivers and source drivers that occupy a relatively large area are concentratedly arranged on either side of the frame. In addition, these mounting processes can be simplified by collectively arranging gate drivers and source drivers. However, in such a case, depending on the arrangement position of the gate driver and the source driver, the scanning line or the data line is drawn around the display area (frame) over a long distance. In order to further reduce the number of pixels, instead of doubling the number of scanning lines, a pixel connection configuration in which the number of data lines is halved is considered. (For example, FIG. 5 of patent document 1)

  FIG. 18 is a schematic diagram of an example of pixel connection in a display screen, which is considered as one method for achieving such a narrow frame. In this case, one data line S (i) is shared by two adjacent pixels P (i, j). In this case, the TFTs corresponding to these two pixels P (i, j) are connected to different scanning lines G (j).

  For example, in FIG. 18, the TFT corresponding to the upper left pixel P (1,1) is connected to the scanning line G (1) and the data line S (1), and the right adjacent pixel P (1,2) is connected. The corresponding TFT is connected to the scanning line G (2) and the data line S (1). The pixel P (1,1) and the pixel P (1,2) are arranged between the scanning line G (1) and the scanning line G (2).

  FIG. 19 shows the scanning direction (each scanning signal waveform) of the scanning line G (j) when the video signal Vsig is written to each pixel P (i, j) in such an active matrix type liquid crystal display device, and the data line. The writing order between adjacent pixels P (i, j) sharing S (i) is shown. For example, each pixel P (1, j) connected to the data line S (1) includes a pixel P (1, 1), a pixel P (1, 2), a pixel P (1, 3), and a pixel P (1 , 4).

JP 2004-185006 A

  In the pixel connection for halving the number of data lines as described above, the pixels in each row are connected to scanning lines arranged in different directions with respect to the pixels between adjacent pixels in the row direction. For this reason, in the manufacturing process, for example, as shown in FIG. 20, when a displacement of the pixel electrode occurs in a direction component perpendicular to the extending direction of the scanning line, parasitic capacitance generated between the pixel electrode and the scanning line. Cgs1 and Cgs2 have different values between adjacent pixels in the extending direction of the scanning line. In such a case, even when a display signal voltage having the same potential is written to each of the pixels adjacent in the extending direction of the scan line, the pixels adjacent to each other in the extending direction of the scan line are shown in FIG. As shown, the level shift voltages ΔV1 and ΔV2 at the end of the display signal voltage capture are different, which causes a problem that the image quality is deteriorated. FIG. 21 shows potential fluctuations in the pixel P (1,1) and the pixel P (1,2) in FIG.

  The present invention has been made in view of such conventional problems. For example, even when a pixel electrode is misaligned in a direction component perpendicular to the extending direction of the scanning line, it is possible to prevent deterioration in image quality. An object is to provide a liquid crystal display device.

In order to achieve the above object, according to the first aspect of the present invention, a gate electrode is connected to a first scan line, and one of a source electrode and a drain electrode is connected to a data line. A first pixel connected to the other of the source electrode and the drain electrode in the first thin film transistor and to which a display signal voltage supplied to the data line is applied via the first thin film transistor An electrode, a gate electrode connected to the second scan line, and one of a source electrode and a drain electrode connected to the data line; the source electrode in the second thin film transistor; A display signal voltage connected to the other of the drain electrodes and supplied to the data line is A second pixel electrode applied via a second thin film transistor; a common electrode arranged to face the first pixel electrode and the second pixel electrode via a liquid crystal layer; The first pixel line and the second pixel line are adjacent to each other along the extending direction of the first scan line, and the first scan line and the second scan line The first scanning line and the second liquid crystal display device are arranged so as to be positioned between the first scanning line and the second scanning line so that the first thin film transistor and the second thin film transistor are turned on at different timings. First driving means for outputting a scanning signal to the scanning line, a display signal voltage as a first potential, and a display signal voltage as a second potential different from the first potential at a predetermined gradation level. Against raw And a second driving means for outputting the display signal voltage to the data line and a third driving means for outputting a common signal whose potential is switched at a predetermined cycle to the common electrode. A parasitic capacitance between the second pixel electrode and the second scan line is formed larger than a parasitic capacitance between the first pixel electrode and the first scan line, and the common signal is When the first thin film transistor is set to the on state, the potential of the common signal becomes a third potential that is lower than the center potential between the first potential and the second potential. In addition, the potential is switched so that the potential of the common signal becomes a fourth potential lower than the third potential when the second thin film transistor is set to an on state.

According to a second aspect of the invention, there is provided a first thin film transistor in which a gate electrode is connected to a first scan line and one of a source electrode and a drain electrode is connected to a data line; A first pixel electrode connected to the other one of the source electrode and the drain electrode of the thin film transistor, to which a display signal voltage supplied to the data line is applied via the first thin film transistor, and a gate electrode A second thin film transistor connected to the second scan line and having one of a source electrode and a drain electrode connected to the data line; and the source electrode and the drain electrode of the second thin film transistor The display signal voltage connected to the other and supplied to the data line is connected to the second thin film transistor. A second pixel electrode applied via a liquid crystal layer, and a common electrode disposed so as to face the first pixel electrode and the second pixel electrode via a liquid crystal layer, The first pixel electrode and the second pixel electrode are adjacent to each other along the extending direction of the first scan line, and between the first scan line and the second scan line. A liquid crystal display device disposed so as to be positioned , wherein the first scan line and the second scan line are set so that the first thin film transistor and the second thin film transistor are turned on at different timings. And a display signal voltage as a first potential and a display signal voltage as a second potential different from the first potential with respect to a predetermined gradation level. And generate A second driving means for outputting a display signal voltage to the data line; and a third driving means for outputting a common signal whose potential is switched at a predetermined cycle to the common electrode. And the second scan line are formed to be shorter than the distance between the first pixel electrode and the first scan line, and the common signal is generated from the first thin film transistor. And the second thin film transistor so that the potential of the common signal becomes a third potential lower than the center potential between the first potential and the second potential when is set to the on state. The potential is switched so that the potential of the common signal becomes a fourth potential lower than the third potential when is set to the on state .

According to a third aspect of the present invention, in the liquid crystal display device according to the first or second aspect, the first thin film transistor and the second thin film transistor are n-MOS thin film transistors. .

  According to the present invention, for example, it is possible to prevent the image quality from deteriorating even when the pixel electrode is misaligned in the direction component perpendicular to the extending direction of the scanning line.

1 is a schematic plan configuration diagram of a liquid crystal display device according to the present invention. 1 is a schematic cross-sectional configuration diagram of a liquid crystal display device according to the present invention. FIG. 5 is a layout diagram of each pixel in a liquid crystal display unit. The equivalent circuit diagram in a liquid crystal display part. FIG. The cross-sectional block diagram of a pixel. The block block diagram of a driver circuit. Explanatory drawing of the scanning signal in each scanning line. 1 is a schematic configuration diagram of a scanning line driving circuit. Explanatory drawing of a holding circuit. The schematic block diagram of a data line drive circuit. It is explanatory drawing of a common signal, (a) is when the absolute value of (DELTA) V2 is larger than the absolute value of (DELTA) V1, (b) is when the absolute value of (DELTA) V1 and the absolute value of (DELTA) V2 are equal, (c) is (DELTA) V1 When the absolute value of ΔV2 is smaller than the absolute value. Explanatory drawing of the relationship between the common signal in case the absolute value of (DELTA) V2 is larger than the absolute value of (DELTA) V1, and the voltage written in a liquid crystal. Explanatory drawing of the relationship between the common signal and the voltage written in a liquid crystal in case the absolute value of (DELTA) V2 is smaller than the absolute value of (DELTA) V1. The modification of the scanning signal in each scanning line. This is a modification of the common signal, where (a) shows a case where the absolute value of ΔV2 is larger than the absolute value of ΔV1, and (b) shows a case where the absolute value of ΔV2 is smaller than the absolute value of ΔV1. It is explanatory drawing of the relationship between the display signal voltage at the time of line inversion drive or dot inversion drive, and a common signal, (a) is larger than the absolute value of (DELTA) V1, and (b) is (DELTA) V1. When the absolute value of ΔV2 is smaller than the absolute value. FIG. 6 is a layout diagram of each pixel in the prior art. Explanatory drawing of the selection order of each scanning line in a prior art. Explanatory drawing of the parasitic capacitance of each pixel in a prior art. Explanatory drawing of the drawing voltage in a prior art.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In the present embodiment, after the liquid crystal display device is manufactured, predetermined information corresponding to the finish of the liquid crystal display device is stored for each liquid crystal display device, and the liquid crystal display device is based on the stored information. A case where the driving voltage at is corrected will be described.

  The schematic overall configuration of the liquid crystal display device 1 according to the present invention is a liquid crystal display unit 10 in which a plurality of pixels, which will be described later, are arranged as shown in FIGS. 1 and 2, and each pixel of the liquid crystal display unit 10 is driven and controlled. The driver circuit 11 is configured.

  The liquid crystal display unit 10 has a configuration in which a liquid crystal LC is sandwiched between two substrates 10a and 10b that are arranged to face each other and are bonded by a sealing material 10c. Then, as shown in FIGS. 3 and 4, a plurality of pixels P (i, j) arranged in a matrix and each pixel P (i, j) are provided on the opposite surface side of one substrate 10b. A plurality of scanning lines G (j) for sequentially scanning every number and a plurality of data lines S (i) for supplying a display signal voltage to be written to each pixel P (i, j) are formed. . Each pixel P (i, j) is connected to a TFT as a switching element whose gate electrode is connected to the scan line G (j) and whose drain electrode is connected to the data line S (i), and to the source electrode of the TFT. The pixel electrode pix, and an auxiliary capacitor Ccs that accumulates charges for maintaining the potential difference between the pixel electrode pix and the common electrode Gn formed on the other substrate 10a at a predetermined potential difference are provided. I = 1, 2, 3,..., X. j = 1, 2, 3,..., y. The common electrode Gn is configured to have a common counter voltage in each pixel when the common signal Vcom is supplied. That is, the common electrode Gn is formed over the entire surface, for example, on the opposite surface side of the other substrate 10a.

  Here, the data line S (i) and the scanning line G (j) are arranged so as to cross each other. Each pixel P (i, j) is in the vicinity of the intersection of one of the data lines S (i) and one of the scanning lines G (j) as described above via the TFT as a switching element. It is connected. Further, every two pixels are connected so that one data line S (i) is shared by two adjacent pixels P (i, j). Further, the TFTs corresponding to these two pixels P (i, j) are connected to different scanning lines G (j).

  For example, in FIGS. 3 and 4, the TFT corresponding to the upper left pixel P (1,1) is connected to the scanning line G (1) and the data line S (1), and the pixel P (1,1, The TFT corresponding to 2) is connected to the scanning line G (2) and the data line S (1). The pixel P (1,1) and the pixel P (1,2) are arranged between the scanning line G (1) and the scanning line G (2).

  The pixel P (1,2) is arranged adjacent to the pixel P (1,1) with the data line S (1) interposed therebetween, but the direction of the pixel P (1,1) Are adjacent to the pixel P (2, 1) adjacent in the opposite direction without interposing the data line S (i). The pixel P (2,1) is disposed adjacent to the pixel P (2,2) with the data line S (2) interposed therebetween.

  Here, a specific configuration of each pixel P (i, j) will be described with reference to FIGS. One substrate 10b is provided with a scanning line G (j) including a gate electrode 51. A storage capacitor line 48 is provided in the same layer as the scanning line G (j). That is, the scanning line G (j) and the auxiliary capacitance line 48 are formed together. A gate insulating film 52 is provided on the entire upper surface. A semiconductor thin film 53 made of intrinsic amorphous silicon is provided on the upper surface of the gate insulating film 52. A channel protective film 54 is provided at substantially the center of the upper surface of the semiconductor thin film 53. Contact layers 55 and 56 made of n-type amorphous silicon are provided on both sides of the upper surface of the channel protective film 54 and on the upper surface of the semiconductor thin film 53 on both sides thereof.

  A source electrode 57 is provided on the upper surface of one contact layer 55. A data line S (i) including a drain electrode 58 is provided on the upper surface of the other contact layer 56 and the upper surface of the gate insulating film 52.

  The gate electrode 51, the gate insulating film 52, the semiconductor thin film 53, the channel protective film 54, the contact layers 55 and 56, the source electrode 57 and the drain electrode 58 constitute a TFT.

  A planarizing film 59 is provided on the entire upper surface of the gate insulating film 52 including the TFT and the like. In the planarizing film 59, a contact hole 60 is provided in a portion corresponding to a predetermined portion of the source electrode 57. A pixel electrode pix made of ITO is provided at a predetermined location on the upper surface of the planarizing film 59. The pixel electrode pix is connected to the source electrode 57 through the contact hole 60. The shape of the pixel electrode pix is formed so as to be a rotationally symmetric shape between pixels adjacent in the extending direction of the scanning line G (j).

  Here, the portion of the auxiliary capacitance line 48 that overlaps the pixel electrode pix is an auxiliary capacitance electrode. An auxiliary capacitor Ccs is formed by the overlapped portion. In addition, the size of the auxiliary capacitance Ccs in each pixel P (i, j) is configured to be equal. The auxiliary capacitance line 48 is electrically connected to the common electrode Gn (has the same potential). That is, the common signal Vcom is also supplied to the auxiliary capacitance line 48 as with the common electrode Gn.

  In each pixel P (i, j), the alignment state of the liquid crystal to be arranged between the pixel electrode pix and the common electrode Gn is based on the voltage difference between the pixel electrode pix and the common electrode Gn. By changing the display, the display state can be controlled.

  Since the liquid crystal LC is sandwiched between the pixel electrode pix and the common electrode Gn, the liquid crystal capacitance Clc is formed by these. The liquid crystal capacitors Clc are configured to be equal between the pixels. Further, the common electrode Gn may be configured to be provided on the one substrate 10b side. That is, in the present embodiment, a lateral electric field method in which a voltage difference is generated in the in-plane direction of the substrate and applied to the liquid crystal, or a vertical electric field method in which a potential difference is generated between the two substrates and applied to the liquid crystal. Any of the electric field methods can be applied.

  1 and 2, each data line S (i) and each scanning line G (j) are connected by wiring groups 20 </ b> S and 20 </ b> G routed on one substrate 10 b in the peripheral region of the liquid crystal display unit 10. The driver circuit 11 is arranged on the right side of the liquid crystal display unit 10 and is electrically connected. The common electrode Gn is electrically connected to the driver circuit 11 by being electrically connected to the wiring on one substrate 10b by, for example, a resinous conductive material.

  In the liquid crystal display unit 10, the data line S (i) is formed by extending in a direction parallel to the driver circuit 11, and the scanning line G (j) is formed in the driver circuit 11 on the extending direction side. It is formed to come. In addition, with the wiring configuration as described above, the width of the wiring group 20S can be halved compared to a configuration in which different data signal lines are associated with each pixel arranged in the scan line direction. It has a configuration.

  As shown in FIG. 7, the driver circuit 11 includes a scanning line driving circuit 22 that drives each scanning line G (j), a data line driving circuit 23 that drives each data line S (i), a common electrode Gn, and an auxiliary capacitor. A common electrode drive circuit 28 for driving the line 48, a power supply adjustment circuit 24 for adjusting a predetermined reference power supply Vcc and outputting various drive voltages necessary for the driver circuit 11, for example, temporarily storing image data input from the outside An image memory 25, a unique information storage unit 26 that stores unique information of the liquid crystal display device 1, a control unit 27 that obtains synchronization of each drive unit by outputting various control signals to be described later to each drive unit described above, and the like. It is prepared for.

  As shown in FIG. 8, the scanning line driving circuit 22 is based on the vertical synchronization signal Vs output from the control unit 27 and the first gate clock signal GCK1 and the second gate clock signal GCK2 as the horizontal synchronization signal Hs. A scanning signal is output to each scanning line G (j). The first gate clock signal GCK1 and the second gate clock signal GCK2 are rectangular signals having opposite phases.

  As shown in FIG. 9, the schematic configuration of the main part of the scanning line driving circuit 22 is configured by, for example, holding circuits 101, 102, 103, 104,... Corresponding to the number of scanning lines (y stages) arranged in series. Is done. Each holding circuit has an input terminal IN, an output terminal OUT, a reset terminal RST, a clock signal input terminal CK, a high potential power input terminal Th, and a low potential power input terminal Tl. . The vertical synchronization signal Vs is supplied to the input terminal IN of the first stage holding circuit 101 as the first stage input signal. Further, the output signal of the previous holding circuit is supplied to the input terminal IN of the second and subsequent holding circuits. Further, the output signal of the holding circuit at the next stage is supplied to the reset terminal RST of each holding circuit. Note that a reset signal END may be separately supplied to the reset terminal RST of the holding circuit (not shown) in the final stage (for example, the y-th stage), or the output signal of the first-stage holding circuit 101 may be supplied. It is good also as a structure supplied.

  Further, the first gate clock signal GCK1 is supplied to the clock signal input terminal CK of the odd-numbered holding circuit, and the clock signal input terminal CK of the even-numbered holding circuit is supplied to the first gate clock signal GCK1. The second gate clock signal GCK2 having the opposite phase is supplied. In addition, a predetermined high voltage Vgh is supplied to the high potential power input terminal Th of each holding circuit, and a predetermined low voltage Vgl is supplied to the low potential power input terminal Tl of each holding circuit.

  As shown in FIG. 10, each holding circuit 101, 102, 103, 104,... Includes six MOS field effect transistors (hereinafter referred to as MOS transistors) T11 to T16, and a capacitor C. Have.

  As shown in FIG. 8, the scan line driving circuit 22 starts scanning in the frame in response to the vertical synchronization signal Vs, and in response to the first gate clock signal GCK1 and the second gate clock signal GCK2. A voltage output such as switching from the low level voltage Vgl to the high level voltage Vgh for a predetermined period is performed for each scanning line in order from the scanning line G (1) at the front stage to the scanning line G (y) at the last stage.

  That is, the scanning line driving circuit 22 sequentially turns on the TFTs (i, j) corresponding to the scanning line G (j) for each scanning line G (j), and at this time, the data line S (i) is turned on. The output display signal voltage is written to the corresponding pixel P (i, j).

  Therefore, when the odd-numbered scan line is selected, the display signal voltage is written to the pixels corresponding to the odd-numbered scan line, and when the even-numbered scan line is selected, the display signal voltage corresponds to the even-numbered scan line. A display signal voltage is written to the pixel to be operated. In other words, the odd-numbered scan lines and the even-numbered scan lines that are adjacent to each other through the pixels are sequentially selected, so that the display signal voltage is written to the pixels for one row arranged between these scan lines. .

  The data line driving circuit 23 receives each data line S (i) provided in the display panel 11 based on the horizontal synchronizing signal Hs, the vertical synchronizing signal Vs, the image data Data, and the reference clock signal CLK input from the control unit 27. On the other hand, the display signal voltage corresponding to each data line S (i) is output at a predetermined timing.

  As shown in FIG. 11, the functional block configuration of the data line driving circuit 23 includes a sampling memory 151, a data latch unit 152, a D / A conversion circuit (DAC) 153, and a display signal voltage generation circuit 154.

  The sampling memory 151 is synchronized with the horizontal synchronization signal Hs and the reference clock signal CLK output from the control unit 27 in units of image data (image data for one horizontal period) corresponding to pixels for one scanning line. The image data corresponding to each pixel is taken in from the image memory 25 in order from the one corresponding to the preceding scanning line, and has the same number of data storage areas as the number of data lines S (i). That is, the sampling memory 151 captures image data corresponding to the scan line for each scan line, and stores each of the captured image data in the data storage area of the corresponding data line S (i). Here, the image data includes a gradation level to be displayed on each pixel, and this gradation level is represented as, for example, 8-bit digital data for each pixel. Each data storage area stores the 8-bit digital data.

  The image data for one horizontal period captured by the sampling memory 151 is transferred from the sampling memory 151 to the data latch unit 152 in accordance with a request from the data latch unit 152 at the subsequent stage. When the image data is transferred to the data latch unit 152, the sampling memory 151 shifts to an image data capturing state corresponding to the scanning line of the next row as image data for the next one horizontal period. This is performed in synchronization with the horizontal synchronization signal HS.

  The data latch unit 152 simultaneously acquires image data for one horizontal period from the sampling memory 151 based on the horizontal synchronization signal Hs, and outputs the acquired image data to the D / A conversion circuit 153 at the subsequent stage.

  The D / A conversion circuit 153 includes a plurality of DAC units 241 and an output amplifier circuit 242, and the data latch unit 152 is selected by the display signal voltage supplied from the display signal voltage generation circuit 154 by the DAC unit 241. Each image data output from is converted into a display signal voltage as a corresponding analog signal, and is applied to each data line S (i) by the output amplifier circuit 242.

  At this time, the D / A conversion circuit 153 converts the digital image data output from the data latch unit 152 into a display signal voltage as an analog voltage so as to correspond to the polarity inversion signal Pol output from the control unit 27. Convert. Specifically, the D / A conversion circuit 153 performs D / A conversion so that the image data output from the data latch unit 152 becomes a positive display signal voltage when the polarity inversion signal Pol is in the high state Vsh. If the polarity inversion signal Pol is in the low state Vsl, the D / A conversion is performed so that the image data output from the data latch unit 152 has a negative display signal voltage. In other words, when the polarity inversion signal Pol is in the high state Vsh, the D / A conversion circuit 153 performs D / A conversion so that the voltage applied to the liquid crystal is positive, and the polarity inversion signal Pol is in the low state. When it is Vsl, D / A conversion is performed so that the voltage applied to the liquid crystal is negative.

  The common electrode drive circuit 28 generates a common signal Vcom and supplies the common signal Vcom to the common electrode Gn and the auxiliary capacitance line 48. Based on the polarity inversion signal Pol, a voltage level corresponding to a predetermined gradation level is set at a predetermined cycle. As shown in FIGS. 12 (a), 12 (b), and 12 (c), two types of correction voltages Vc1 and Vc2 (to be described later) are added to the amplitude center voltage Vdc of the display signal voltage Vd that swings, as shown in FIG. Or by alternately superimposing them based on the horizontal synchronizing signal Hs, the common signal Vcom is generated. The amplitude center voltage Vdc is preset together with the display signal voltage Vd set corresponding to each gradation level, and is configured to be supplied from the power supply adjustment circuit 24 to the common electrode drive circuit 28. Has been.

  The first correction voltage Vc1 is a pixel corresponding to an odd-numbered scanning line (for example, scanning line G (1)), that is, a pixel (an odd-numbered column of pixels) arranged adjacent to the left side of each data line S (i). Is a voltage that is superimposed on the amplitude center voltage Vdc when the display signal voltage Vd is applied to the pixel, and when the display signal voltage capture is completed at the pixels connected to the odd-numbered scan lines (TFT shifts from the on state to the off state) (Ie, when the scanning signal shifts from Vgh to Vgl), it is set to a value corresponding to the pull-in voltage ΔV1.

  The second correction voltage Vc2 is a pixel corresponding to an even-numbered scan line (for example, scan line G (2)), that is, a pixel adjacent to the right side of each data line S (i) (pixel in an even column). Is a voltage that is superimposed on the amplitude center voltage Vdc when the display signal voltage Vd is applied to the pixel, and has a value based on the pull-in voltage ΔV2 generated at the end of the display signal voltage capture in the pixels connected to the even-numbered scan lines. Is set.

  The first correction voltage Vc1 and the second correction voltage Vc2 are the same as the interval L1 between the odd-numbered scan line and the pixel electrode corresponding to the scan line and the even-numbered scan line in the liquid crystal display device 1. The value is set based on the distance L2 from the pixel electrode corresponding to the scanning line. In other words, the first correction voltage Vc1 and the second correction voltage Vc2 are connected to the odd-numbered scan lines, for example, when the pixel electrode is misaligned in the direction component perpendicular to the extending direction of the scan lines. Even if the value of the parasitic capacitance Cgs differs between the pixel and the pixel connected to the even-numbered scanning line, it is applied to the liquid crystal after the display signal voltage is captured for a predetermined gradation level to be displayed. The voltage can be equalized between both pixels, and is stored in advance in the unique information storage unit 26 as unique information Inf of the liquid crystal display device 1.

  Here, the pull-in voltage ΔV1 generated at the end of capturing the display signal voltage in the pixels connected to the odd-numbered scan lines, and the pull-in voltage generated at the end of capturing the display signal voltages in the pixels connected to the even-numbered scan lines. ΔV2 can be derived by (Equation 1), respectively.

(Equation 1)
ΔV1 = (Vgh−Vgl) × Cgs1 / (Clc + Ccs + Cgs1)
≈ (Vgh−Vgl) × (α / L1) / {Clc + Ccs + (α / L1)}
ΔV2 = (Vgh−Vgl) × Cgs2 / (Clc + Ccs + Cgs2)
≈ (Vgh−Vgl) × (α / L2) / {Clc + Ccs + (α / L2)}

  Here, Cgs1 is a parasitic capacitance between the odd-numbered scan line and the pixel electrode corresponding to the scan line, and Cgs2 is a parasitic capacitance between the even-numbered scan line and the pixel electrode corresponding to the scan line. It is. Α is the product of the dielectric constant of the dielectric constituting the parasitic capacitance and the electrode area.

  In this embodiment, since the amplitude center voltage Vdc is supplied from the power supply adjustment circuit 24, the first correction voltage Vc1 is set to ΔV1 and the second correction voltage Vc2 is set to ΔV2. The unique information Inf is stored in advance in the unique information storage unit 26, and the first correction voltage Vc1 and the second correction voltage Vc2 are alternately superimposed on the amplitude center voltage Vdc in the direction in which the pull-in voltage is generated. For example, as shown in FIG. 21, when the pull-in voltages ΔV1 and ΔV2 are generated on the negative polarity side with respect to the display signal voltage Vd at the time of writing, correction is performed on the negative polarity side with respect to the amplitude center voltage Vdc. The voltages Vc1 and Vc2 are superimposed.

  FIG. 12A shows the case where the absolute value of ΔV2 is larger than the absolute value of ΔV1, that is, the even-numbered scan line than the interval L1 between the odd-numbered scan line and the pixel electrode corresponding to the scan line. In this example, the pixel electrode is misaligned in the direction component perpendicular to the extending direction of the scan line so that the distance L2 between the scan line and the pixel electrode corresponding to the scan line is narrower (shorter). FIG. 12B shows the above-described case where the absolute value of ΔV1 is equal to the absolute value of ΔV2, that is, the pixel electrode is not displaced in the direction component perpendicular to the extending direction of the scanning line. In this case, the intervals L1 and L2 are equal. Further, FIG. 12C shows the case where the absolute value of ΔV2 is smaller than the absolute value of ΔV1, that is, the even-numbered scan line than the interval L1 between the odd-numbered scan line and the pixel electrode corresponding to the scan line. This shows a case where the positional deviation of the pixel electrode occurs in the direction component perpendicular to the extending direction of the scanning line so that the distance L2 between the scanning line and the pixel electrode corresponding to the scanning line is wider (longer). In addition, “odd” in the figure indicates the timing at which one of the odd-numbered scan lines is selected, and “even” in the figure indicates the timing at which one of the even-numbered scan lines is selected. Yes.

  Then, by supplying the common signal Vcom to the common electrode Gn and the auxiliary capacitance electrode (auxiliary capacitance line 48) in this way, a positional deviation of the pixel electrode is generated in a direction component perpendicular to the extending direction of the scanning line. Even if the value of the parasitic capacitance Cgs differs between the pixels connected to the odd-numbered scan lines and the pixels connected to the even-numbered scan lines, as shown in FIG. 13 and FIG. The display signal voltages Vd that are equal to each other are written between a pixel connected to the scan line (for example, P (i, 1)) and a pixel connected to the even-numbered scan line (for example, P (i, 2)). In this case, the voltages Vlcd (i, 1) and Vlcd (i, 2) applied to the respective liquid crystals can be kept equal to each other, and the image quality can be prevented from deteriorating.

  FIG. 13 shows the case where the absolute value of ΔV2 is larger than the absolute value of ΔV1, that is, the even-numbered scan line and the scan line with respect to the interval L1 between the odd-numbered scan line and the pixel electrode corresponding to the scan line. This shows a case where the positional deviation of the pixel electrode occurs in the direction component perpendicular to the extending direction of the scanning line so that the distance L2 from the pixel electrode corresponding to is narrower (shorter). FIG. 14 shows the case where the absolute value of ΔV2 is smaller than the absolute value of ΔV1, that is, the even-numbered scan line and the scan line with respect to the interval L1 between the odd-numbered scan line and the pixel electrode corresponding to the scan line. In this example, the pixel electrode is displaced in the direction component perpendicular to the extending direction of the scanning line so that the distance L2 from the pixel electrode corresponding to is wider (longer). 13 and 14, the timing at which the scanning signal in the odd-numbered scanning line is switched from Vgh to Vgl and the scanning signal in the even-numbered scanning line from Vgl so that the transition of the voltage fluctuation becomes clearer. The time between the timing of switching to Vgh is exaggerated than the timing charts shown in FIG. 8 and FIG.

  By the way, the unique information storage unit 26 can use, for example, an EEPROM (Electrically Erasable Programmable ROM) which is one of nonvolatile memories, and the so-called “white background” in which no information is written at the time of manufacture of the liquid crystal display device 1. "Is in the state. Then, after the liquid crystal display device 1 is manufactured, for example, when the EEPROM writing system device is connected to the write signal terminal 27, the predetermined information as described above corresponding to the finish of the liquid crystal display device 1 is obtained. It is stored in the unique information storage unit 26. The write voltage Vpp to the unique information storage unit 26 is configured to require a voltage higher than the reference power supply Vcc input to the power supply adjustment circuit 24, and the information stored in the unique information storage unit 26 is the reference power supply. It is prevented from being erased inadvertently under the influence of Vcc.

  By adopting such a configuration, it is possible to set the correction voltages Vc1 and Vc2 having optimum values for each liquid crystal display device even when there is a difference in the positional deviation amount of the pixel electrode.

  In the above-described embodiment, a case has been described in which an even-numbered scan line is selected after an odd-numbered scan line is selected between two scan lines arranged adjacently via pixels. As shown in FIG. 5, the odd-numbered scan line may be selected after the even-numbered scan line is selected between two scan lines that are adjacently arranged via the pixel.

  In the above-described embodiment, the case where the power supply adjustment circuit 24 supplies the amplitude center voltage Vdc to the common electrode drive circuit 28 has been described, but the power supply adjustment circuit 24 supplies a voltage different from the amplitude center voltage Vdc to the common electrode drive. The voltage supplied to the circuit 28 and the common electrode driving circuit 28 may convert the voltage supplied from the power supply adjustment circuit 24 based on preset information.

  In the above-described embodiment, the case where the power supply adjustment circuit 24 supplies a DC voltage as the amplitude center voltage Vdc to the common electrode drive circuit 28 has been described. FIG. 16A and FIG. As described above, the power supply adjustment circuit 24 supplies the rectangular AC voltage Vac whose amplitude center voltage is the amplitude center voltage Vdc as described above to the common electrode driving circuit 28, and the common electrode driving circuit 28 corrects the rectangular AC voltage Vac to this rectangular AC voltage Vac. The voltages Vc1 and Vc2 may be superimposed. It is preferable that a relatively large voltage can be applied to the liquid crystal while the value of the display signal voltage Vd is set small.

  In the above-described embodiment, the case of the frame inversion driving in which the polarity of the voltage written to the liquid crystal in the frame is equal between the pixels corresponding to each scanning line has been described, but FIG. 17A and FIG. As shown in b), the present invention can also be applied to line inversion driving and dot inversion driving in which the polarity of the voltage written to the liquid crystal in the frame is different between pixels corresponding to adjacent scanning lines.

  In the above-described embodiment, the case of the stripe arrangement in which the pixels are arranged in a stripe shape has been described. However, the present invention can also be applied to a delta arrangement.

  The above-described embodiment is merely an example of the present invention, and it goes without saying that the specific configuration of each functional block can be changed and designed as appropriate within the scope of the effects of the present invention.

DESCRIPTION OF SYMBOLS 1: Liquid crystal display device 10: Liquid crystal display part 11: Driver circuit 22: Scan line drive circuit 23: Data line drive circuit 24: Power supply adjustment circuit 25: Image memory 26: Specific information storage part 27: Control part 28: Common electrode drive Circuit 153: D / A conversion circuit 154: Display signal voltage generation circuit S (i): Data line (i = 1, 2, 3,..., X)
G (j): scanning line (j = 1, 2, 3,..., Y)
P (i, j): Pixel Clc: Liquid crystal capacitance Ccs: Auxiliary capacitance Cgs1, Cgs2: Parasitic capacitance

Claims (3)

A first thin film transistor having a gate electrode connected to the first scan line and one of the source electrode and the drain electrode connected to the data line;
A first pixel electrode connected to the other one of the source electrode and the drain electrode in the first thin film transistor and to which a display signal voltage supplied to the data line is applied via the first thin film transistor;
A second thin film transistor having a gate electrode connected to the second scan line and one of the source electrode and the drain electrode connected to the data line;
A second pixel electrode connected to the other one of the source electrode and the drain electrode in the second thin film transistor and to which a display signal voltage supplied to the data line is applied via the second thin film transistor;
A common electrode disposed so as to face the first pixel electrode and the second pixel electrode through a liquid crystal layer;
With
The first pixel electrode and the second pixel electrode are adjacent to each other along the extending direction of the first scan line, and between the first scan line and the second scan line. A liquid crystal display device arranged to be located,
First driving means for outputting a scanning signal to the first scanning line and the second scanning line so that the first thin film transistor and the second thin film transistor are turned on at different timings;
A display signal voltage as a first potential and a display signal voltage as a second potential different from the first potential are generated for a predetermined gradation level, and the display signal voltage is applied to the data line. Second driving means for outputting;
Third driving means for outputting a common signal whose potential is switched at a predetermined period to the common electrode;
With
A parasitic capacitance between the second pixel electrode and the second scan line is formed larger than a parasitic capacitance between the first pixel electrode and the first scan line;
The common signal is a third potential in which the potential of the common signal is lower than a center potential between the first potential and the second potential when the first thin film transistor is set to an on state. And the potential is switched so that the potential of the common signal becomes a fourth potential lower than the third potential when the second thin film transistor is set to an on state. A liquid crystal display device. A first thin film transistor having a gate electrode connected to the first scan line and one of the source electrode and the drain electrode connected to the data line;
A first pixel electrode connected to the other one of the source electrode and the drain electrode in the first thin film transistor and to which a display signal voltage supplied to the data line is applied via the first thin film transistor;
A second thin film transistor having a gate electrode connected to the second scan line and one of the source electrode and the drain electrode connected to the data line;
A second pixel electrode connected to the other one of the source electrode and the drain electrode in the second thin film transistor and to which a display signal voltage supplied to the data line is applied via the second thin film transistor;
A common electrode disposed so as to face the first pixel electrode and the second pixel electrode through a liquid crystal layer;
With
The first pixel electrode and the second pixel electrode are adjacent to each other along the extending direction of the first scan line, and between the first scan line and the second scan line. A liquid crystal display device arranged to be located,
First driving means for outputting a scanning signal to the first scanning line and the second scanning line so that the first thin film transistor and the second thin film transistor are turned on at different timings;
A display signal voltage as a first potential and a display signal voltage as a second potential different from the first potential are generated for a predetermined gradation level, and the display signal voltage is applied to the data line. Second driving means for outputting;
Third driving means for outputting a common signal whose potential is switched at a predetermined period to the common electrode;
With
An interval between the second pixel electrode and the second scan line is shorter than an interval between the first pixel electrode and the first scan line;
The common signal is a third potential in which the potential of the common signal is lower than a center potential between the first potential and the second potential when the first thin film transistor is set to an on state. And the potential is switched so that the potential of the common signal becomes a fourth potential lower than the third potential when the second thin film transistor is set to an on state. A liquid crystal display device.   3. The liquid crystal display device according to claim 1, wherein the first thin film transistor and the second thin film transistor are n-MOS type thin film transistors.

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