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JP2009055200A - Controller and control method for silicon carbide static induction transistor - Google Patents

Controller and control method for silicon carbide static induction transistor Download PDF

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JP2009055200A
JP2009055200A JP2007218525A JP2007218525A JP2009055200A JP 2009055200 A JP2009055200 A JP 2009055200A JP 2007218525 A JP2007218525 A JP 2007218525A JP 2007218525 A JP2007218525 A JP 2007218525A JP 2009055200 A JP2009055200 A JP 2009055200A
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voltage
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induction transistor
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gate voltage
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JP4853928B2 (en
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Tsutomu Yao
勉 八尾
Yasunori Tanaka
保宣 田中
Akio Takatsuka
章夫 高塚
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National Institute of Advanced Industrial Science and Technology AIST
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

<P>PROBLEM TO BE SOLVED: To suppress a considerable increase in on-resistance loss at excess current of an electric power transducer, in order to manufacture a small, light-weighted and low-price electric power transducer. <P>SOLUTION: A static induction transistor made from silicon carbide is applied to an electric power transducer, where surge current of 5 times or 20 times higher than the rated current capacity flows. During normal operation below the rated current when the static induction transistor is ON, a value below a built-in voltage for gate bonding is used as the gate voltage to perform high-speed, low-loss, and efficient power conversion. But the gate voltage is raised above the built-in voltage, only when excess current exceeding the rated current flows. Thereby, a control method preventing element damage due to excess current enables the current capacity of the silicon carbide static induction transistor used at the transducer to be small, which does not exceed considerably the one of conversion. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、炭化ケイ素を素材とする高電圧、低オン抵抗の縦型静電誘導トランジスタの制御装置及び制御方法に関し、とくに定格を超える過電流が流れるときの制御方法に関する。   The present invention relates to a control apparatus and a control method for a high voltage, low on-resistance vertical electrostatic induction transistor made of silicon carbide, and more particularly to a control method when an overcurrent exceeding a rating flows.

電力用半導体素子を用いた各種の電力変換装置は、電力の供給源(電源)と電力を消費する各種の電気器機(負荷)の間にあって、電力を交流から直流に、あるいは直流から交流に変換する交直変換、電流の遮断、通過電力量を制御して負荷の出力を調整するなどの役割を担う。このような電力変換装置には、負荷の短時間の過電流動作に耐えるような過負荷耐性が求められる。通常、変換装置の定格容量の1.5倍ないし2倍程度の出力で数分間の運転が続いても装置が正常に動作しなければならない。   Various power conversion devices using power semiconductor elements are located between a power supply source (power supply) and various electric appliances (loads) that consume power, and convert power from AC to DC or from DC to AC. It plays the role of adjusting the output of the load by controlling AC / DC conversion, cutting off the current, and controlling the amount of power passing through. Such a power conversion device is required to have an overload resistance capable of withstanding a short-time overcurrent operation of the load. Normally, the device must operate normally even if the operation continues for several minutes at an output of about 1.5 to 2 times the rated capacity of the conversion device.

数分間の動作では、その間の過電流によって生ずる電力用半導体素子の温度上昇を半導体素子の熱容量のみでは吸収できない。そのため、変換装置に使われる半導体素子は定格の1.5倍ないし2倍の過負荷動作においても素子の最高温度が動作上限温度を超えないようにしなければならない。その結果、使用される半導体素子の容量は変換装置の定格容量の割には大きくなり、その上、変換器の冷却システムもそれにともなって大型化されることになる。このことが、変換装置の大型・重量化をもたらし、特に配電系統などに使用されるような大容量の電力変換装置の高価格化の大きな要因となり、その広い活用と普及拡大が著しく妨げられている。   In the operation for several minutes, the temperature rise of the power semiconductor element caused by the overcurrent during that time cannot be absorbed only by the heat capacity of the semiconductor element. For this reason, the maximum temperature of the semiconductor element used in the converter must be kept from exceeding the upper limit temperature even in an overload operation of 1.5 to 2 times the rated value. As a result, the capacity of the semiconductor elements used is larger than the rated capacity of the converter, and the converter cooling system is also enlarged accordingly. This leads to an increase in the size and weight of the conversion device, which is a major factor in increasing the price of large-capacity power conversion devices that are used especially in power distribution systems, etc. Yes.

この問題に対しては、動作上限温度がシリコンを素材とする電力用素子より100℃以上も高くできる炭化ケイ素を素材とする電力用半導体素子を使用することが考えられている。すなわち、炭化ケイ素電力用半導体素子では、定格運転時における素子の温度は動作上限温度に対して十分に余裕があるので、使用素子の容量や変換器の冷却系を大きくしなくても定格の1.5倍ないし2倍の過電流状態で素子の最高温度が動作上限温度を超えないようにすることが比較的容易にできるからである。このように、定格容量における動作の損失がシリコン素子より著しく小さく、かつ動作上限温度が高い炭化ケイ素の電力用半導体素子を利用すれば、変換装置の定格運転時の変換効率を高くするだけでなく、装置の小型・軽量化にも大きな効果が期待できる。   In order to solve this problem, it is considered to use a power semiconductor element made of silicon carbide whose upper limit temperature of operation can be higher by 100 ° C. or more than a power element made of silicon. That is, in the semiconductor element for silicon carbide power, the temperature of the element at the rated operation has a sufficient margin with respect to the upper limit temperature of the operation, so that the rated capacity is 1 without increasing the capacity of the element used or the cooling system of the converter. This is because it is relatively easy to prevent the maximum temperature of the element from exceeding the upper limit temperature of operation in an overcurrent state of 5 to 2 times. Thus, if silicon carbide power semiconductor elements having a significantly lower operating loss at the rated capacity than silicon elements and having a high operating upper limit temperature are used, not only the conversion efficiency during rated operation of the converter is increased. Also, a great effect can be expected in reducing the size and weight of the device.

しかしながら、電力の送配電系統の安定化や電力品質の維持の目的で系統内に接続される電力変換装置では、以下に述べる理由から、単に従来のシリコン半導体素子を炭化ケイ素の半導体素子に置換えるだけでは十分とは言えない。すなわち、電力系統では系統に連携された負荷側の各種電気器機の短絡事故や送配電線での相間短絡や地絡などの事故時に備えて、系統に使用される変換装置には定格電流の10倍ないし20倍の過電流が半サイクルないし数サイクル(5m秒ないし100m秒間)の期間にわたって通電しても変換装置の機能が喪失しないよう厳しい仕様が付けられ、半導体素子にとってきわめて過酷な過負荷状態に耐えることが要求されるからである。   However, in the power conversion device connected in the system for the purpose of stabilizing the power transmission / distribution system and maintaining the power quality, the conventional silicon semiconductor element is simply replaced with the silicon carbide semiconductor element for the following reasons. It's not enough. That is, in the electric power system, the converter used in the system has a rated current of 10 in case of a short circuit accident of various electric devices on the load side linked to the system, an accident such as an interphase short circuit or a ground fault in the transmission and distribution lines. Strict specifications are attached so that the function of the converter is not lost even if the overcurrent of double to 20 times is applied for a period of half cycle to several cycles (5 msec to 100 msec). It is because it is required to endure.

電動機の回転速度制御などのような電力変換装置の場合、負荷である電動機の近くに設置されることが多いので、負荷の短絡などの異常時にはその異常を素早く変換装置の制御回路に伝達して変換器を遮断するか、または出力を絞るなどの制御が比較的容易にできる。しかし、電力の送配電系統に使われる変換装置では、通常は系統の事故地点と変換装置が設置されている地点との間の距離が長いので制御に長い時間を要するだけでなく、系統内の他の正常な地点の電力供給にできるだけ支障がないようにするためには、系統内の一部の変換装置のみを直ちに遮断、もしくは電流を絞り込むような操作は許されない。すなわち、電力系統内には保護継電器や電磁力を利用して電流を遮断する機械接点式の遮断器機が多数接続されているが、これらの器機は異常時に流れる過電流の作用によって素早い電流の遮断ができるようになっているものが多く、これらの器機を安全に動作させて系統全体の安定を図るためにも系統の一部に異常が発生した場合に連携されている変換装置を瞬時に遮断することや電流を絞り込むことは許されないからである。そのため電力系統用の変換装置には、前項[0005]のようなきわめて厳しいサージ電流の通電に耐える過負荷耐性が要求されるのである。   In the case of power conversion devices such as motor rotation speed control, it is often installed near the motor that is the load, so in the event of an abnormality such as a short circuit of the load, the abnormality is quickly transmitted to the control circuit of the conversion device. Controls such as shutting off the converter or reducing the output can be made relatively easy. However, in converters used in power transmission / distribution systems, the distance between the fault point of the grid and the point where the converter is installed is usually long, so it takes a long time to control the system. In order to prevent the power supply from other normal points as much as possible, it is not permitted to immediately shut off only a part of the converters in the system or to reduce the current. In other words, there are a number of mechanical contact type circuit breaker devices that cut off the current using a protective relay and electromagnetic force in the power system, but these devices can quickly cut off current due to the overcurrent that flows in the event of an abnormality. In order to operate these devices safely and to stabilize the entire system, when a part of the system malfunctions, the linked converter is instantly shut off. This is because it is not allowed to do or to narrow down the current. For this reason, the converter for the power system is required to have an overload resistance that can withstand energization of extremely severe surge current as described in the previous section [0005].

かかるサージ電流の通電に耐える過負荷耐性を有した送配電系統用の従来の電力変換装置には、シリコンの電力用半導体の中でとりわけサージ電流に対する耐性の高いサイリスタやゲートタンオフサイリスタ(GTOサイリスタ)あるいは絶縁ゲート型バイポーラトランジスタ(IGBT)などのバイポーラ動作型の素子が使われている。サイリスタ素子は通電状態にはカソードおよびアノードの二つのエミッタからの電子およびホールの注入によって内部の高抵抗層の伝導度が著しく増加するので、定格電流の10ないし20倍の電流が流れても素子の電圧降下の増分は比較的小さく、半サイクルまたは数サイクルの短期間であれば破壊にいたらないという有利な特長がある。また、IGBT素子は、アノードエミッタからのホールの注入によって高抵抗層の伝導度変調がおこるので、素子の電流容量を定格容量の2ないし3倍程度に大きくしておけば、過大のサージ電流が通電した場合でもオン電圧の著しい増加をともなうことなく安全に動作することが可能である。   Conventional power converters for power transmission and distribution systems that have resistance to overload that can withstand the application of surge current include thyristors and gate tan-off thyristors (GTO thyristors) that are particularly resistant to surge current among silicon power semiconductors. ) Or a bipolar operation type element such as an insulated gate bipolar transistor (IGBT) is used. In the thyristor element, the conductivity of the internal high resistance layer is remarkably increased by injecting electrons and holes from the two emitters of the cathode and the anode in the energized state, so that even if a current of 10 to 20 times the rated current flows, the element The voltage drop increment is relatively small and has the advantageous feature of not leading to breakdown for short periods of half or several cycles. In addition, since the IGBT element modulates the conductivity of the high resistance layer by injecting holes from the anode emitter, if the current capacity of the element is increased to about 2 to 3 times the rated capacity, an excessive surge current can be generated. Even when energized, it can operate safely without a significant increase in on-voltage.

しかしながら、前項[0004]に記載した理由から送配電系統用の電力用変換装置に炭化ケイ素を素材とする電力用半導体素子を使用するにあたり、前記[0008]に示したサイリスタやGTO、あるいはIGBTなどのバイポーラ動作型の電力用半導体素子を適用した場合、以下に述べるように装置の定格あるいはそれ以下での正常運転時の変換効率を著しく損ねるという問題がある。すなわち、これらのバイポーラ型素子がオン状態にあるときは、pn接合からの少数キャリアの注入によって伝導度変調が起こり大きな電流が流れるという動作をする。このキャリアの注入が起こるためにはpn接合にそのビルトイン電圧(閾値電圧)以上の順方向電圧が印加されねばならない。ところで、pn接合のビルトイン電圧は半導体素子の結晶素材のバンドギャップ(禁制帯幅)の大きさに依存する。バンドギャップが大きい炭化ケイ素のpn接合のビルトイン電圧は約2.5Vと、シリコンの約1.0Vより2倍以上大きいので、炭化ケイ素のバイポーラ型素子がオン状態にあるときは、順方向電圧降下には、この2.5Vの電圧がいつも加わり、この分の損失が素子の発生損失ひいては変換装置の電力損失を増大する。その結果、定格電流やそれ以下での正常な運転状態における装置の変換効率を著しく損ねることになる。さらに、配電系統などのような高電圧の電力変換装置では、半導体素子を直列接続の形態で使われることが多いが、素子の直列数に比例してビルトイン電圧分の通電損失が累積されるので、このようなバイポーラ動作型素子は変換器の高効率化の点で不利である。   However, when using a power semiconductor device made of silicon carbide for a power converter for a power transmission / distribution system for the reason described in [0004], the thyristor, GTO, or IGBT shown in [0008] is used. When the bipolar operation type power semiconductor element is applied, there is a problem that the conversion efficiency during normal operation at or below the rating of the apparatus is significantly impaired as described below. That is, when these bipolar devices are in the ON state, conductivity modulation occurs due to minority carrier injection from the pn junction, and a large current flows. In order for this carrier injection to occur, a forward voltage higher than the built-in voltage (threshold voltage) must be applied to the pn junction. By the way, the built-in voltage of the pn junction depends on the size of the band gap (forbidden band width) of the crystal material of the semiconductor element. Since the built-in voltage of a silicon carbide pn junction with a large band gap is about 2.5 V, which is more than twice as large as about 1.0 V of silicon, when the silicon carbide bipolar device is in the ON state, the forward voltage drop In this case, the voltage of 2.5 V is always applied, and this loss increases the generation loss of the element and the power loss of the converter. As a result, the conversion efficiency of the apparatus in a normal operation state at a rated current or lower is remarkably impaired. Furthermore, in high-voltage power converters such as power distribution systems, semiconductor elements are often used in the form of series connection, but current loss due to built-in voltage is accumulated in proportion to the number of elements in series. Such a bipolar operation type element is disadvantageous in terms of increasing the efficiency of the converter.

これに対して、電力用変換装置に用いられる炭化ケイ素を素材とする電力用半導体素子としてユニポーラ動作型の静電誘導トランジスタ(接合型電界効果トランジスタ;JFETと呼ばれることもある)を適用するのが有利である。図1は、炭化ケイ素静電誘導トランジスタの代表的な例として特許文献1に記載されたものを示す。炭化ケイ素の高濃度n型単結晶基板1に低濃度n型層2が積層され、該低濃度n型層2の内部に高濃度p型層3が複数個埋め込まれ、低濃度n型層2に高濃度n型層4が積層されている。そして、前記高濃度n型単結晶基板1の表面にドレイン電極5、前記高濃度n型層4の表面にソース電極6,および前記高濃度p型層3の表面の一部にゲート電極7がそれぞれ低抵抗オーミック接触されている。二つの高濃度p型層3に挟まれたn型領域21をチャネルと呼び、ゲート電極7とソース電極6の間に印加されるゲート電圧Vgの極性や大きさによって制御されるチャネル内に広がる空乏層によってオン状態やオフ状態になる。すなわち、十分な大きさの逆方向のゲート電圧Vgによってチャネルがピンチオフされてオフ状態となり、また、ゲート電圧Vgを取り除くか、もしくは順方向に低い電圧を印加すればオン状態になる。炭化ケイ素静電誘導トランジスタとしてはこの例の他に種々の構造のトランジスタが提案されているが、動作が同じなので、以下では本例をもとに動作および特徴を詳細に説明する。   On the other hand, a unipolar operation type electrostatic induction transistor (junction field effect transistor; sometimes referred to as JFET) is applied as a power semiconductor element made of silicon carbide used in a power converter. It is advantageous. FIG. 1 shows what was described in Patent Document 1 as a typical example of a silicon carbide static induction transistor. A low-concentration n-type layer 2 is laminated on a silicon carbide high-concentration n-type single crystal substrate 1, and a plurality of high-concentration p-type layers 3 are embedded in the low-concentration n-type layer 2. A high-concentration n-type layer 4 is laminated. A drain electrode 5 is formed on the surface of the high-concentration n-type single crystal substrate 1, a source electrode 6 is formed on the surface of the high-concentration n-type layer 4, and a gate electrode 7 is formed on a part of the surface of the high-concentration p-type layer 3. Each has a low resistance ohmic contact. The n-type region 21 sandwiched between the two high-concentration p-type layers 3 is called a channel and spreads in the channel controlled by the polarity and magnitude of the gate voltage Vg applied between the gate electrode 7 and the source electrode 6. The depletion layer turns on and off. That is, the channel is pinched off by a sufficiently large reverse gate voltage Vg to be turned off, and turned on when the gate voltage Vg is removed or a low voltage is applied in the forward direction. In addition to this example, various structures of transistors have been proposed as the silicon carbide static induction transistor, but the operation is the same. Therefore, the operation and features will be described in detail below based on this example.

図2は炭化ケイ素静電誘導トランジスタの出力特性の代表例を示す。ゲート・ソース間に0V、1.0V,2.5Vおよび3.0〜5.0Vのゲート電圧Vgを印加したときのドレイン電圧Vdとドレイン電流Idの間の電圧・電流特性である。Idは、Vg=0Vではほとんど流れないが、Vg≧0VではVdの増加に伴って直線的に増加しやがて飽和する。この直線領域のオン抵抗はVg=1.0Vのとき約0.1オーム、Vg=2.5Vのとき0.05オーム、さらにVg=3.0〜5.0Vのとき約0.01オームと、いずれもきわめて低いオン抵抗でありVgの増加とともに小さくなる。また、飽和電流もVgの増加に伴って増加する。これは、Vg≦2.5Vでは順方向のゲート電圧の印加によって前記チャネル領域に広がる空乏層の広がりが抑制され、電流通路となるチャネル領域の実質的な幅が拡大される結果によるものであり、また、Vg=3.0〜5.0Vでは、上記のチャネル領域の実質的な拡大に加えて高濃度p型層3からチャネル領域21に正孔が注入されてそこでの伝導度が著しく高くなった結果によりものである。Vg=2.5Vは炭化ケイ素のゲート・ソース間pn接合のビルトイン電圧にほぼ等しい。この2.5V以下のバイアス状態ではゲート電極からの小数キャリアの注入が起こらないので高速にスイッチングするというユニポーラ動作型半導体素子の特徴を保有するためにはVg≦2.5Vである必要がある。これに対して、ゲート電圧として炭化ケイ素のpn接合のビルトイン電圧2.5Vを超える3.0Vないし5.0Vの高電圧を投入した場合、直線領域のオン抵抗がさらに減少して0.01オーム以下になり、かつ、飽和電流も200A程度に激増し、Vg=2.5Vの定常動作時と比較してオン抵抗は約1/5に減少、飽和電流は約10倍に増加する。しかしながら、Vg>2.5Vでは少数キャリアの蓄積効果のためスイッチング速度はバイポーラ動作型と同様に遅くなり、動作の高周波化による回路部品の小型化ができなくなるという特性上の問題がある。   FIG. 2 shows a representative example of output characteristics of a silicon carbide static induction transistor. This is a voltage / current characteristic between the drain voltage Vd and the drain current Id when a gate voltage Vg of 0 V, 1.0 V, 2.5 V, and 3.0 to 5.0 V is applied between the gate and the source. Id hardly flows when Vg = 0V, but when Vg ≧ 0V, Id increases linearly as Vd increases and eventually saturates. The on-resistance of this linear region is about 0.1 ohm when Vg = 1.0V, 0.05 ohm when Vg = 2.5V, and about 0.01 ohm when Vg = 3.0 to 5.0V. These are extremely low on-resistances and become smaller as Vg increases. Further, the saturation current also increases as Vg increases. This is because when Vg ≦ 2.5V, the application of the forward gate voltage suppresses the spread of the depletion layer extending to the channel region, and the substantial width of the channel region serving as a current path is increased. When Vg = 3.0 to 5.0 V, holes are injected from the high-concentration p-type layer 3 into the channel region 21 in addition to the substantial expansion of the channel region, and the conductivity there is remarkably high. Is due to the result. Vg = 2.5V is approximately equal to the built-in voltage of the gate-source pn junction of silicon carbide. In the bias state of 2.5 V or less, since minority carrier injection from the gate electrode does not occur, Vg ≦ 2.5 V needs to be satisfied in order to retain the characteristics of the unipolar operation type semiconductor device that switches at high speed. On the other hand, when a high voltage of 3.0V to 5.0V exceeding the built-in voltage 2.5V of the silicon carbide pn junction is applied as the gate voltage, the on-resistance in the linear region is further reduced to 0.01 ohm. The saturation current also increases drastically to about 200 A, the on-resistance is reduced to about 1/5, and the saturation current is increased about 10 times compared to the steady operation at Vg = 2.5V. However, when Vg> 2.5 V, the switching speed is slow as in the bipolar operation type due to the effect of minority carrier accumulation, and there is a problem in characteristics that circuit components cannot be miniaturized due to high frequency operation.

また、これらの出力特性ではドレイン電流はドレイン電圧Vd=0Vから立ち上がるので、前項[0008]で述べたバイポーラ動作型素子のような通電損失にpn接合でのビルトイン電圧分の損失が加わることはなく、導通損失を小さくできる。また、直列接続の高電圧動作においても直列数に比例してビルトインで電圧分の損失が累積されることはない。さらに、温度の上昇にともなって素子のオン抵抗が大きくなる性質があるので電流集中が起こりにくく、変換装置内の素子の並列接続や1素子内の半導体チップの並列実装も比較的に容易に実現できるという特長があり従来のサイリスタやIGBTなどのバイポーラ動作型素子にくらべて優れている。   In these output characteristics, since the drain current rises from the drain voltage Vd = 0V, the loss due to the built-in voltage at the pn junction is not added to the conduction loss as in the bipolar operation type element described in the previous section [0008]. The conduction loss can be reduced. Also, even in series-connected high voltage operation, voltage loss is not accumulated by built-in in proportion to the number of series. In addition, since the on-resistance of the element increases as the temperature rises, current concentration is unlikely to occur, and parallel connection of elements in the converter and parallel mounting of semiconductor chips in one element can be realized relatively easily. This is superior to conventional bipolar operation type elements such as thyristors and IGBTs.

また、電界効果トランジスタとして広く使われているMOSFETと比べると、両者ともゲート・ソース間に印加されるゲート回路からの電圧信号によってターンオンやターンオフされる素子であるが、MOSFETではゲート・ソース間は酸化膜などによって絶縁され、ゲート電圧信号の印加によってゲート絶縁膜の直下の半導体表面に電流通電路となるチャネルが形成されオン状態になる。オン抵抗はこのチャネル内の電子移動度に強く依存するが、MOSFETのチャネルの移動度は炭化ケイ素半導体と酸化絶縁膜との界面欠陥の存在のためバルク移動度の10分の1以下と低い値であり、このためMOSFETのオン抵抗はあまり小さくならない。これに対して、静電誘導トランジスタでは、チャネル移動度はバルクの移動度と等しく高い値であり、低いオン抵抗を実現し易いという特徴がある。また、MOSFETでは、ゲートと炭化ケイ素との間にはSiO2などの絶縁膜が介在するので、静電誘導トランジスタのようにゲート電極からのキャリアの注入によってオン抵抗を低減したり、飽和電流を増大したりする制御ができない。   Compared to MOSFETs that are widely used as field effect transistors, both are elements that are turned on and off by a voltage signal from a gate circuit applied between the gate and the source. Insulated by an oxide film or the like, a channel serving as a current conduction path is formed on the semiconductor surface immediately below the gate insulating film by application of the gate voltage signal, and is turned on. Although the on-resistance strongly depends on the electron mobility in this channel, the channel mobility of the MOSFET is as low as 1/10 or less of the bulk mobility due to the presence of interface defects between the silicon carbide semiconductor and the oxide insulating film. Therefore, the on-resistance of the MOSFET is not so small. On the other hand, the electrostatic induction transistor has a feature that the channel mobility is as high as the bulk mobility, and a low on-resistance is easily realized. In addition, since an insulating film such as SiO2 is interposed between the gate and silicon carbide in the MOSFET, the on-resistance is reduced or the saturation current is increased by injecting carriers from the gate electrode as in the electrostatic induction transistor. Control is not possible.

図2の出力特性を有する炭化ケイ素静電誘導トランジスタにおいて、定常動作におけるユニポーラ動作を意図してVg≦2.5Vでの動作を行った場合、定格の2倍を超える過電流が通電すると素子内での通電損失が著しく増大するという問題がある。すなわち、Vg=2.5Vでの順方向のオン状態において、この素子の定格を10A程度に設定しておけば定格電流以下での動作における素子の通電損失は充分小さくでき、たとえ定格の2倍程度の過電流が流れてもドレイン電圧Vdの著しい増加もなく発生損失を小さく押えることができる。しかし、出力電流が飽和する電流値以上の電流が流れた場合、ドレイン電圧Vdが急増し、素子内での通電損失の著しい増大をもたらし、通電時間が長いときは素子温度が上限温度を超えて、素子破壊に至る場合もある。そのため、定格の10倍ないしは20倍のサージ電流が流れるような変換器に適用するには相当に大きな面積の素子が必要とされる。   In the silicon carbide static induction transistor having the output characteristics shown in FIG. 2, when an operation with Vg ≦ 2.5 V is performed with the intention of a unipolar operation in a steady operation, an overcurrent exceeding twice the rated value is energized. There is a problem that the energization loss at the time increases significantly. In other words, in the forward ON state at Vg = 2.5 V, if the rating of this element is set to about 10 A, the energization loss of the element in the operation below the rated current can be made sufficiently small, even twice the rating. Even if an overcurrent of a certain level flows, the generated loss can be kept small without a significant increase in the drain voltage Vd. However, when a current greater than the current value at which the output current saturates flows, the drain voltage Vd increases rapidly, resulting in a significant increase in current loss in the device. When the current flow time is long, the device temperature exceeds the upper limit temperature. In some cases, the device may be destroyed. Therefore, a device having a considerably large area is required to be applied to a converter in which a surge current 10 to 20 times the rated value flows.

一方、定格電流以下の正常な運転状態において順方向通電時のオン抵抗の低減を意図してVg=3.0V〜5.0Vのようなビルトイン電圧を超える高電圧をゲートに供給した場合、オン抵抗を小さくできるが小数キャリアの蓄積効果によってスイッチング速度が損なわれるといういわゆるバイポーラ動作型素子の問題が生ずる。さらに、ゲート接合の順バイアスによって、オン動作時には常にゲート電流が通電するのでゲート回路の大型化のみならずそこでの制御電力の損失は無視できなくなるという問題がある。
特開2006−253292号公報
On the other hand, when a high voltage exceeding the built-in voltage such as Vg = 3.0V to 5.0V is supplied to the gate in order to reduce the on-resistance during forward energization in the normal operating state below the rated current, the Although the resistance can be reduced, there arises a problem of a so-called bipolar operation type element in which the switching speed is impaired by the effect of accumulation of minority carriers. Furthermore, since the gate current is always applied during the ON operation due to the forward bias of the gate junction, there is a problem that not only the gate circuit is enlarged but also the loss of control power cannot be ignored.
JP 2006-253292 A

電力用変換器の定格容量以下の正常動作における高い変換効率と高速スイッチング動作および定格の2倍程度の過負荷電流に対する高い耐性が得られるためユニポーラ動作型の炭化ケイ素静電誘導トランジスタを適用した配電系統用などの大電力の電力用変換器では、変換器に定格の10倍ないしは20倍のサージ電流が流れた場合、使用するトランジスタのサージ電流領域におけるオン抵抗の著しい増大に起因した過大の通電損失のためトランジスタが熱的破壊し、電力変換器がブレークダウンするという問題があった。   Distribution using a silicon carbide static induction transistor of unipolar operation because high conversion efficiency in normal operation below the rated capacity of the power converter, high-speed switching operation, and high resistance to overload current twice the rating are obtained. In a power converter for high power such as for a system, when a surge current of 10 to 20 times the rated current flows in the converter, excessive energization due to a significant increase in on-resistance in the surge current region of the transistor used There is a problem that the transistor is thermally destroyed due to loss, and the power converter is broken down.

これらの問題に鑑み本発明の目的は、電力用変換器の過電流においてオン抵抗損失の著しい増大が抑制される炭化ケイ素静電誘導トランジスタ素子の制御装置及び制御方法を提供することである。   In view of these problems, an object of the present invention is to provide a control device and a control method for a silicon carbide static induction transistor element in which a significant increase in on-resistance loss is suppressed in an overcurrent of a power converter.

本発明の他の目的は、炭化ケイ素静電誘導トランジスタを用いて小型、軽量化、および低コスト化された高い変換効率の電力用変換器を実現するためのトランジスタ制御装置及び制御方法を提供することである。   Another object of the present invention is to provide a transistor control device and a control method for realizing a power converter with high conversion efficiency that is small, light, and low in cost using a silicon carbide static induction transistor. That is.

上記課題解決のため本発明は、炭化ケイ素静電誘導トランジスタを使った電力変換器の定格容量以内での正常動作時にはトランジスタをオン状態にするための制御信号としてのゲート電圧をトランジスタのゲート・ソース間のpn接合のビルトイン電圧(閾値電圧)以下とし、過負荷通電時のみビルトイン電圧(閾値電圧)以上の電圧とするにより該トランジスタのオン抵抗を著しく低減し素子の熱的破壊を防止することを特徴とする。   In order to solve the above problems, the present invention provides a gate voltage as a control signal for turning on a transistor during normal operation within the rated capacity of a power converter using a silicon carbide electrostatic induction transistor. The built-in voltage (threshold voltage) of the pn junction between the transistors is set to a voltage lower than the built-in voltage (threshold voltage) only during overload energization to significantly reduce the on-resistance of the transistor and prevent thermal destruction of the element. Features.

前記ゲート電圧として定常動作時には2.5V以下の電圧を、前記過負荷通電時には3.0Vないし5.0Vの範囲の電圧とする。前記過負荷通電時として変換器の定格容量の5倍以上の電流とする。   As the gate voltage, a voltage of 2.5 V or less during steady operation is set to a voltage in the range of 3.0 V to 5.0 V during overload energization. At the time of the overload energization, the current is at least five times the rated capacity of the converter.

以上記述したように本発明によれば、以下のような効果を奏する。高速、低損失、かつ過電流耐性に強い炭化ケイ素静電誘導トランジスタを適用した電力用変換器の素子の定格容量を大幅に超えるサージ過電流の通電時においても適用素子の発生損失を著しく増加することのないトランジスタの制御方法によって、使用するトランジスタの電流容量を装置の定格容量より著しく大きくしなくてもよくなり、電力用変換装置の小型化、軽量化、高効率化ならびに低価格化が同時に実現できる。   As described above, the present invention has the following effects. Even when a surge overcurrent is applied that significantly exceeds the rated capacity of the power converter element to which a silicon carbide static induction transistor with high speed, low loss and strong overcurrent resistance is applied, the loss generated by the applied element is significantly increased. The transistor's current control method eliminates the need for the current capacity of the transistor used to be significantly larger than the rated capacity of the device, and simultaneously reduces the size, weight, efficiency, and cost of power converters. realizable.

以下、本発明の具体的実施形態を図面により詳細に説明する。図3は本発明の炭化ケイ素静電誘導トランジスタの制御装置の1実施例を示すものである。この装置は、大きく分けると、ゲート駆動回路、ゲート電圧制御回路、および電流検出回路より構成される。該ゲート駆動回路は、2.5Vのオンゲート電圧源となるコンデンサーC1,15Vのオフゲート電圧源となるコンデンサーC2、フォトカプラからのオン、オフ指令に従ってC1,C2の電圧をゲート抵抗Rを介して炭化ケイ素静電誘導トランジスタのゲート端子Gに供給するためのスイッチTrs1およびTrs2などから構成されており、炭化ケイ素静電誘導トランジスタに定格容量以下もしくは定格の2倍程度の電流が流れる正常動作時の駆動回路である。また、ゲート電圧制御回路は、5Vのオンゲート電圧源となるコンデンサーC3、C3に直列接続されたスイッチTrs4、およびTrs4のゲート回路より構成され、前記ゲート駆動回路の前記2.5Vのオンゲート電圧源C1に並列に接続されており、炭化ケイ素静電誘導トランジスタに流れる電流が定格電流を大幅に超えた時に起動して該トランジスタのゲート端子Gに2.5Vを超えるゲート電圧、本例では5.0V,を供給するための回路である。電流検出回路は、炭化ケイ素静電誘導トランジスタに流れる電流を素子に直列に接続された抵抗RLと、その両端での電圧降下によって検出される電流値を規定の値と比較する回路より構成され、電流値がトランジスタの定格電流を大幅に超えたことを判断して前記ゲート電圧制御回路のスイッチTrs4をターンオンする指令信号を出力する。
この制御装置は、トランジスタに流れる電流が定格電流以下もしくは定格の2倍程度の正常動作時にはオン時のゲート電圧を、前記ゲート駆動回路によって、トランジスタのゲート・ソース間のpn接合のビルトイン電圧(ほぼ2.5V)以下の電圧に制御する。そして、定格を大幅に超える電流が流れた時には、前記電流検出回路によって検出された電流が既定値を超えると出力される信号によって前記ゲート電圧制御回路のスイッチTrs4がターンオンして、ビルトイン電圧を超えるゲート電圧(本例では5.0V)に制御する。かかる制御装置を用いた本発明の制御方法の具体例を以下に説明する。
Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings. FIG. 3 shows one embodiment of the control apparatus for the silicon carbide static induction transistor of the present invention. This device is roughly composed of a gate drive circuit, a gate voltage control circuit, and a current detection circuit. The gate driving circuit includes a capacitor C1 serving as a 2.5V on-gate voltage source, a capacitor C2 serving as a 15V off-gate voltage source, and a voltage of C1 and C2 via a gate resistor RG according to an on / off command from a photocoupler. It is composed of switches Trs1 and Trs2 for supplying to the gate terminal G of the silicon carbide electrostatic induction transistor, and the like, during normal operation in which a current less than the rated capacity or about twice the rated current flows through the silicon carbide electrostatic induction transistor. It is a drive circuit. The gate voltage control circuit is composed of capacitors C3 and Cs3 that are connected in series to capacitors C3 and C3 serving as a 5V on-gate voltage source, and a gate circuit of Trs4, and the 2.5V on-gate voltage source C1 of the gate driving circuit. Are connected in parallel, and when the current flowing through the silicon carbide static induction transistor greatly exceeds the rated current, the gate terminal G of the transistor has a gate voltage exceeding 2.5V, in this example 5.0V , Is a circuit for supplying. The current detection circuit is composed of a resistor RL connected in series with a current flowing through the silicon carbide electrostatic induction transistor, and a circuit that compares a current value detected by a voltage drop at both ends thereof with a specified value. It is determined that the current value has greatly exceeded the rated current of the transistor, and a command signal for turning on the switch Trs4 of the gate voltage control circuit is output.
This control device uses a gate drive circuit to turn on the gate voltage at the time of normal operation when the current flowing through the transistor is equal to or lower than the rated current or about twice the rated value, and the built-in voltage of the pn junction between the gate and source of the transistor (almost 2.5 V) or less. When a current significantly exceeding the rating flows, the switch Trs4 of the gate voltage control circuit is turned on by a signal output when the current detected by the current detection circuit exceeds a predetermined value, and exceeds the built-in voltage. The gate voltage (5.0 V in this example) is controlled. A specific example of the control method of the present invention using such a control device will be described below.

図4は本発明の炭化ケイ素静電誘導トランジスタの制御方法を説明するものである。上段には静電誘導トランジスタをオンまたはオフ状態に保持するための指令信号、中段にはゲート回路から静電誘導トランジスタに印加されるゲート電圧Vg、そして下段には静電誘導トランジスタのドレイン・ソース間の電圧(ドレイン電圧)Vdおよびドレイン・ソース間に流れる電流(ドレイン電流)Idを示す。それぞれの値の変化を同時化した時間経過で表わしている。時刻t1より以前のオフ指令状態では、Vg=−15Vのゲート電圧によって静電誘導トランジスタはオフ状態となりドレイン電圧Vdが印加されたままドレイン電流Id=0の状態が保持される。なお、このオフ時のゲート電圧Vgは必ずしも−15Vである必要はなく、トランジスタによってはVg=0あるいは−50Vなどの他の値であっても構わない。時刻t1において指令信号がオフからオンに切り替わるとゲートにはVg=2.5Vの電圧が印加されトランジスタはターンオンし、ドレイン電流Idが通電し始める。ドレイン電圧はIdの大きさに比例した1V前後の低い値に保持される。なお、このオン時のゲート電圧Vgも必ずしも2.5Vである必要はない。ユニポーラ型の動作によって高速のスイッチング動作を起こさせるためにゲート接合からの少数キャリアが注入されない炭化ケイ素静電誘導トランジスタのゲート接合のビルトイン電圧(閾値電圧)以下であれば良く、1.0Vや1.5Vなどの他の値であっても構わない。図2で示した通り、Vgが高ければ高いほどオン抵抗が小さくなるのでビルトイン電圧を超えない2.0〜2.5Vの範囲の電圧が良い。動作が正常な場合は、t5で指令信号がオフに切り替わり再びVg=−15Vのゲート電圧が印加されてトランジスタがターンオフするまでは、このままのゲート電圧Vgが印加されて(図中点線(a)で示す)オン状態を継続する。   FIG. 4 illustrates a method for controlling the silicon carbide static induction transistor of the present invention. The upper stage is a command signal for holding the electrostatic induction transistor on or off, the middle stage is a gate voltage Vg applied from the gate circuit to the electrostatic induction transistor, and the lower stage is a drain / source of the electrostatic induction transistor. A voltage (drain voltage) Vd between the drain and the source (drain current) Id is shown. The change of each value is represented by the time elapsed. In the off command state before time t1, the electrostatic induction transistor is turned off by the gate voltage of Vg = -15V, and the state of the drain current Id = 0 is maintained while the drain voltage Vd is applied. Note that the gate voltage Vg in the off state is not necessarily -15V, and may be another value such as Vg = 0 or -50V depending on the transistor. When the command signal is switched from OFF to ON at time t1, a voltage of Vg = 2.5V is applied to the gate, the transistor is turned on, and the drain current Id starts to flow. The drain voltage is held at a low value of about 1 V in proportion to the magnitude of Id. Note that the gate voltage Vg at the time of turning on does not necessarily need to be 2.5V. It may be less than the built-in voltage (threshold voltage) of the gate junction of the silicon carbide static induction transistor in which minority carriers from the gate junction are not injected in order to cause a high-speed switching operation by the unipolar type operation. Other values such as .5V may be used. As shown in FIG. 2, the higher the Vg, the lower the on-resistance, so a voltage in the range of 2.0 to 2.5 V that does not exceed the built-in voltage is good. When the operation is normal, the command signal is turned off at t5, and the gate voltage Vg is applied as it is until the gate voltage of Vg = -15V is applied again and the transistor is turned off (dotted line (a) in the figure). Continue on state.

図4においてt1からt5のオン指令信号が投入されている期間中、予測されないある時刻t2においてトランジスタにその定格電流を大幅に超える電流が流れ始めた場合、ゲート電圧Vgを直ちに時刻t3において5.0Vに昇圧する。Vgの昇圧はドレイン電流Idがトランジスタの定格電流を5倍以上超えるサージ電流が流れて、この所定の電流値以下に減少する時刻t4までの期間中続けられる。ここでは時刻t4が、指令信号がオンからオフに切り替わる時刻t5より以前の場合を例示したが、時刻t5以降になる場合もある。その場合は、指令信号に優先してVgの昇圧を継続するような制御を行う。また、時刻t3から時刻t4までの過電流の期間のゲート電圧Vgは必ずしも5.0Vである必要はなく、前記ビルトイン電圧を超える電圧であれば良い。   In FIG. 4, during the period when the on-command signal from t1 to t5 is applied, if a current that greatly exceeds the rated current starts flowing through the transistor at a certain time t2 that is not predicted, the gate voltage Vg is immediately set to 5. Boost to 0V. The step-up of Vg is continued during a period up to time t4 when a drain current Id decreases by a surge current exceeding 5 times the rated current of the transistor and decreases below this predetermined current value. Although the case where the time t4 is before the time t5 when the command signal is switched from on to off is illustrated here, the time t4 may be after the time t5. In that case, control is performed so as to continue boosting Vg in preference to the command signal. Further, the gate voltage Vg during the overcurrent period from the time t3 to the time t4 is not necessarily 5.0V, and may be a voltage exceeding the built-in voltage.

図4の具体的実施例において過電流の異常時でもゲート電圧を正常動作時と同じ2.5Vとした図中のゲート電圧の点線(a)のような従来の制御方法では、図中の時刻t3から時刻t4の素子のドレイン電圧Vdは点線(a)のようにオフ時と同じ電源電圧に等しい高電圧が印加されるため素子内での発生損失がきわめて大きくなる。これに対して、この具体的実施例のように過電流の異常時のゲート電圧を5.0Vに昇圧した図中のゲート電圧の実線(b)の制御方法では、時刻t3から時刻t4の素子のドレイン電圧Vdは実線(b)のように低い値になり素子内での発生損失が小さく抑えられる。なお、時刻t3の付近の過電流が検出されてゲート電圧が昇圧されるまでの期間はVdは高い値を持つが、この期間は10マイクロ秒以下のきわめて短い時間なので素子の発生損失に与える影響は少ない。   In the specific embodiment of FIG. 4, in the conventional control method such as the dotted line (a) of the gate voltage in the figure in which the gate voltage is set to 2.5 V which is the same as in normal operation even when the overcurrent is abnormal, the time in the figure As the drain voltage Vd of the element from t3 to time t4 is applied with a high voltage equal to the same power supply voltage as in the off state as indicated by a dotted line (a), the loss generated in the element becomes extremely large. On the other hand, in the control method of the solid line (b) of the gate voltage in the figure in which the gate voltage at the time of overcurrent abnormality is boosted to 5.0 V as in this specific embodiment, the element from time t3 to time t4 The drain voltage Vd becomes a low value as shown by the solid line (b), and the generated loss in the device is suppressed to a small value. Note that Vd has a high value during the period from when an overcurrent in the vicinity of time t3 is detected until the gate voltage is boosted, but since this period is an extremely short time of 10 microseconds or less, it has an effect on the generation loss of the element. There are few.

以上、炭化ケイ素を素材として静電誘導トランジスタを電力変換器に応用するときの過電流時の装置並びに制御方法について説明したが、静電誘導トランジスタが適用される電力変換器としてはインバータ装置やコンバータ装置などの電力の順、逆変換装置、電圧を昇降圧する各種チョッパー装置および交、直流の遮断装置なども含まれる。また、炭化ケイ素の静電誘導トランジスタとして図示の制御回路および制御方法の例に基づき説明したが、この発明は上述の例に限定されるものでなく、特許請求の範囲の記載の範囲内で当業者が容易に改変し得る他の構成をも含むものである。   As described above, the device and the control method at the time of overcurrent when the electrostatic induction transistor is applied to the power converter using silicon carbide as a material have been described. As the power converter to which the electrostatic induction transistor is applied, an inverter device or a converter is used. Also included are power order, reverse conversion devices, various chopper devices that increase and decrease the voltage, and AC and DC circuit breakers. Further, the silicon carbide electrostatic induction transistor has been described based on the example of the control circuit and the control method shown in the figure, but the present invention is not limited to the above-described example, and within the scope of the claims. It includes other configurations that can be easily modified by a trader.

代表的な炭化ケイ素静電誘導トランジスタのセル断面図Cell cross section of a typical silicon carbide static induction transistor 炭化ケイ素静電誘導トランジスタの出力特性の代表例Typical example of output characteristics of silicon carbide electrostatic induction transistor 本発明の炭化ケイ素静電誘導トランジスタの制御装置の1実施形態One Embodiment of Control Device for Silicon Carbide Static Induction Transistor of the Present Invention 本発明の炭化ケイ素静電誘導トランジスタの制御方法の1実施形態One Embodiment of Control Method of Silicon Carbide Static Induction Transistor of the Present Invention

符号の説明Explanation of symbols

1. 高濃度n型単結晶基板
2. 低濃度n型堆積膜(ドリフト層)
3. 高濃度p型層
4. 高濃度n型ソース層
5. ドレイン電極
6. ソース電極
7. ゲート電極
21.n型チャネル領域
51.ドレイン電極端子
61.ソース電極端子
71.ゲート電極端子
1. 1. High concentration n-type single crystal substrate Low concentration n-type deposited film (drift layer)
3. 3. High concentration p-type layer 4. High concentration n-type source layer 5. drain electrode 6. Source electrode Gate electrode 21. n-type channel region 51. Drain electrode terminal 61. Source electrode terminal 71. Gate electrode terminal

Claims (5)

炭化ケイ素を素材とした静電誘導トランジスタの制御装置において、
該静電誘導トランジスタに流れる素子電流を検出する回路と、
該素子電流検出回路の出力に基づき、ゲート電圧を制御する回路と、を備え、
前記ゲート電圧制御回路は、定格電流以下の正常動作時にはオン時のゲート電圧を、前記静電誘導トランジスタのゲート・ソース間のpn接合のビルイン電圧以下の電圧に制御し、かつ、定格を超える過電流が流れた場合にかぎりゲート電圧をビルトイン電圧以上に昇圧することにより過電流による素子破壊を防止することから成る静電誘導トランジスタの制御装置。
In an electrostatic induction transistor control device made of silicon carbide,
A circuit for detecting an element current flowing in the electrostatic induction transistor;
A circuit for controlling the gate voltage based on the output of the element current detection circuit,
The gate voltage control circuit controls the gate voltage at the time of on-state during normal operation below the rated current to a voltage below the pn junction built-in voltage between the gate and source of the electrostatic induction transistor and exceeds the rating. A device for controlling an electrostatic induction transistor comprising preventing a device breakdown due to an overcurrent by boosting a gate voltage to a built-in voltage or higher only when a current flows.
前記ビルトイン電圧以下のゲート電圧として2.5Vを越えない範囲とし、かつ前記ビルトイン電圧を超えるゲート電圧として3.0ないし5.0Vの範囲の値とした請求項1に記載の静電誘導トランジスタの制御装置。   2. The electrostatic induction transistor according to claim 1, wherein the gate voltage not exceeding 2.5 V as the gate voltage less than the built-in voltage and the gate voltage exceeding the built-in voltage is 3.0 to 5.0 V. 3. Control device. 前記定格電流を超える過電流が、定格電流のほぼ5倍以上の電流である請求項1又は2に記載の静電誘導トランジスタの制御装置。   3. The electrostatic induction transistor control device according to claim 1, wherein the overcurrent exceeding the rated current is a current that is approximately five times or more the rated current. 4. 前記定格電流を超える過電流が、定格電流のほぼ10倍以上の電流である請求項1又は2に記載の静電誘導トランジスタの制御装置。   3. The electrostatic induction transistor control device according to claim 1, wherein the overcurrent exceeding the rated current is a current that is approximately 10 times or more the rated current. 4. 炭化ケイ素を素材とした静電誘導トランジスタの制御方法において、
該静電誘導トランジスタに流れる素子電流を検出する回路と、該素子電流検出回路の出力に基づき、ゲート電圧を制御する回路とを備え、
前記ゲート電圧制御回路は、定格電流以下の正常動作時にはオン時のゲート電圧を、前記静電誘導トランジスタのゲート・ソース間のpn接合のビルイン電圧以下の電圧に制御し、かつ、定格を超える過電流が流れた場合にかぎりゲート電圧をビルトイン電圧以上に昇圧することにより過電流による素子破壊を防止することから成る静電誘導トランジスタの制御方法。
In the control method of the electrostatic induction transistor made of silicon carbide,
A circuit for detecting an element current flowing in the electrostatic induction transistor, and a circuit for controlling a gate voltage based on an output of the element current detection circuit;
The gate voltage control circuit controls the gate voltage at the time of on-state during normal operation below the rated current to a voltage below the pn junction built-in voltage between the gate and source of the electrostatic induction transistor and exceeds the rating. A method for controlling an electrostatic induction transistor, comprising preventing element destruction due to overcurrent by boosting a gate voltage to a built-in voltage or higher only when a current flows.
JP2007218525A 2007-08-24 2007-08-24 Control device and control method for silicon carbide static induction transistor Expired - Fee Related JP4853928B2 (en)

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