JP3771135B2 - Semiconductor switch - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an AC power distribution system and a semiconductor switch for switching an electric circuit using AC as a power source to an open or closed state.
[0002]
[Prior art]
In order to open and close commercial AC systems, various electrical converters connected to AC power sources, and loads such as motors, electromagnetic circuit breakers, electromagnetic switches, and electromagnetic contactors that open and close metal contacts are used. ing.
[0003]
Japanese Patent Laid-Open No. 5-122040 discloses a contactless switch using a semiconductor element for switching. FIG. 2 shows a contactless switch disclosed in Japanese Patent Laid-Open No. 5-122040. In FIG. 2, 1 is a contactless switch, 100 is an AC power supply of 100V or 200V, 101 is an operating power supply of the same voltage, and 200 is a load such as an electric motor. AC power supplied from the power supply 100 to the load 200 is opened and closed by a triac S1 in the contactless switch. The open state is controlled by turning on the operating power, and the gate signal to the triac is given through the photocoupler PC. The triac, also called a bidirectional thyristor, is a semiconductor AC control element in which two thyristors are integrated in antiparallel, and is often used as a simple AC switch for applications with a relatively small voltage and current capacity. For large capacity applications, two individual thyristor elements are connected in antiparallel. Such a semiconductor switch has features such as long life, high frequency switching, no noise, and maintenance-free.
[0004]
JP-A-10-12926 and JP-A-9-17660 disclose a switch using a GTO thyristor, bipolar transistor, IGBT, MOSFET, SIT, etc. having a self-turn-off function.
[0005]
[Problems to be solved by the invention]
The prior art switch has the following problems.
[0006]
For mechanical contacts such as electromagnetic circuit breakers, electromagnetic switches, and electromagnetic contactors that open and close the metal contacts, 1) the operating speed is slow (usually a switching time of 0.1 to 0.2 seconds), 2) contact wear Therefore, there is a problem that the opening / closing frequency is limited, so that it cannot be easily applied to a power utilization system that requires high-speed operation and high reliability.
[0007]
In the contactless switch disclosed in Japanese Patent Application Laid-Open No. 5-122040, the internal voltage drop is 2V to 5V in the thyristor element when current is applied, so that the power loss is large or the switch shifts from open to closed. However, there is a problem that an energization time of an alternating half-wave, that is, a time of 8 milliseconds to 10 milliseconds is required at the minimum, and an extremely large short-circuit current that is 20 to 30 times the rated current is generated.
[0008]
In addition, when the switches disclosed in Japanese Patent Laid-Open No. 10-12926 and Japanese Patent Laid-Open No. 9-17660 are applied to high-voltage power distribution such as 100 V, 200 V, 400 V, 3 kV, 6 kV of commercial power supply, Since the loss generated when the high-voltage element is on is larger than that of a normal thyristor, the above-described loss problem becomes more serious. Since the current is cut off as soon as possible after the abnormal current is detected, the supply of power to the electrical equipment connected to the load side of the switch is instantaneously stopped by cutting off the switch. There arises a new problem that an electrical response to a device malfunction cannot be made until the next power is supplied.
[0009]
An object of the present invention is to provide a non-contact switch that is low in loss when current is applied and that is small in size and fast.
[0010]
Another object of the present invention is to provide a novel structure of a semiconductor composite element for alternating current control that constitutes a small-sized, low-loss, high-speed non-contact switch.
[0011]
[Means for Solving the Problems]
In the contactless AC switch of the present invention, the power semiconductor element of the switch part is made of a wide gap semiconductor crystal whose band gap energy between the valence band and the conduction electron band (abbreviated as band gap energy) is 2.0 eV or more. In addition, it is a unipolar transistor having a linear output characteristic with respect to the control signal. The AC switch circuit includes a control circuit in which at least two semiconductor elements are connected in series with opposite polarities, and each of the semiconductor elements is supplied with a control signal that opens and closes almost simultaneously.
[0012]
The non-contact AC switch of the present invention limits the power semiconductor element energization current by adjusting the ON control signal level of the power semiconductor element of the switching part or adjusting the pulse width of the ON control signal.
[0013]
Furthermore, the contactless AC switch of the present invention integrates the components of the AC switch circuit in the same semiconductor chip.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail based on specific examples.
[0015]
  (Example 1)
  FIG. 1 is a configuration diagram for one phase of a semiconductor switch according to this embodiment of the present invention. The circuit of FIG. 1 is connected in parallel by the number of AC phases. In FIG. 1, the semiconductor switch 1 has main terminals 81 and 82 on the AC power supply 100 side, main terminals 83 and 84 on the load 200 side, and a control terminal 85 as external terminals. .2 to 3.3 eV silicon carbideDoTwo electrostatic induction transistors (SIT) 2 and 3 and a control circuit 4 made of a single crystal of (SiC) are provided. In the SIT2 and SIT3, the drain electrodes 7 and 8 are electrically connected to each other through the conductor 13, and the source electrodes 9 and 10 are connected to the main terminals 82 and 84 of the switch by the internal conductors 31 and 32, respectively. Yes. The control circuit 4 includes a power supply unit 14 that receives operation power from the internal conductors 31 and 33 connected to the main terminals 82 and 81 on the AC power supply side, an OCS circuit 15 that generates high-frequency pulses, and a control signal latching process. Logic unit 16 that performs signal processing such as detection of current and overcurrent, current sense unit 6 connected to the logic unit 16, an internal conductor 20 that introduces a release signal or the like from the control terminal 85, an insulation transformer 17, and the transformer It comprises gate circuits 18 and 19 for supplying control signals to the gate terminals 11 and 12 of the two SITs 2 and 3. In FIG. 1, the gate circuits 18 and 19 exemplify a circuit configuration in which the pulse signals from the insulation transformer are rectified by the diodes D1 and D2 to charge the capacitors C1 and C2, but this embodiment is not limited to this circuit configuration.
[0016]
  FIG. 3 is an equivalent circuit of FIG. The reference numerals in FIG. 3 correspond to the same reference numerals in FIG. In FIG. 3, silicon carbide connected in series with the polarity reversed.DoEnergy absorption for the two SIT2 and SIT3circuit5 are connected in parallel. Energy absorptioncircuit5 is composed of, for example, a capacitor, a resistance element, and a surge absorbing element, and absorbs the energy of the circuit when the current of the transistor is cut off so that a high voltage is not applied to the element.
[0017]
The operation of this embodiment will be described with reference to FIGS. It is a necessary requirement as a switch that the current is cut off in the initial state of normal operation in which the main terminals 81 and 82 on the power supply side are connected to the AC power supply 100 and the main terminals 83 and 84 on the load side are connected to the load 200, respectively. is there. In this embodiment, while the OCS circuit 15 of the control circuit 4 gives negative gate signals to the source terminals 9 and 10 to the gate terminals 11 and 12 of SIT2 and SIT3, the two SITs are Keep off. Since the two SITs are connected in opposite directions, the AC voltage from the power source is blocked in both directions.
[0018]
The transition of the switch in the off state to the on state is started by inputting the command 20 for releasing the latching state of the logic unit 16 instructing the maintenance of the gate bias to the control terminal 85. The SIT shifts to the on state when the reverse bias state of the gate is released, but the energization current in the on state further increases when a positive bias gate voltage is applied. For this reason, normally, a positive-biased gate signal is applied to hold the ON state. Since the two SITs are turned on almost simultaneously, bidirectional alternating current flows to the load. Since switching from the on state to the off state is a transition to the first state, the bias direction of the gate signal may be reversed.
[0019]
  FIG. 4 is an operation explanatory diagram when an overcurrent flows due to an abnormality in the wiring system or load. If an abnormality occurs at the time t1, the normal circuit current 22 that has flowed until then increases sharply at the time t1, as shown in FIG. When the current increase rate or current value detected by the current sensor 6 exceeds a predetermined value, the logic unit 16 detects an abnormality. The time for which the logic unit 16 detects an abnormality is a short time of microseconds or less.AbnormalThe logic unit 16 that detects this immediately reflects it in the gate signal and starts compressing the energization current. FIG. 4 shows two control methods.
[0020]
FIG. 4B shows a method of controlling the energization current by adjusting the voltage value 28 of the gate control signal supplied to SIT2 and SIT3. That is, the gate voltage of the positive bias is decreased over time until time t2, and the energization current is decreased as indicated by 25 to 26 in FIG. In this case, the current values indicated by reference numerals 25 and 26 may be set to about 2 to 3 times the steady state. Thereafter, the gate voltage is kept low until time t3. Here, the time t3 is a time when it is determined whether to completely cut off the current or to return based on energization in response to an accident recovery signal. Until the time t3, a current 27 having a magnitude within 5 times, preferably 2 to 3 times the normal current 23 is applied. Of course, the interruption operation can be started at any time depending on the situation. That is, if the gate voltage is biased to zero or in the reverse direction, the cut-off state can be entered within 10 microseconds. Since SIT2 and 3 are unipolar devices, there is no internal accumulation of minority carriers as in bipolar devices such as bipolar transistors, IGBTs, and GTO thyristors, and switching to the off state is extremely fast.
[0021]
FIG. 4C shows a method of controlling the energization current by adjusting the gate pulse width. The gate pulse 29 is supplied at a constant frequency several times to 10 times the commercial AC frequency (50 to 60 Hz), and the energization period of the current flowing through SIT2 and SIT3 is adjusted by changing the respective pulse widths tw. Control the current. In FIG. 4B, since the power consumption inside the SIT is large during the period of reducing the current, there is a possibility that the transient power tolerance of the element may be exceeded depending on the load state and the compression period. In the method of FIG. 4C, since the power consumption inside the SIT is small, such problems are few.
[0022]
In this embodiment, the generated loss is greatly reduced. This will be described below. The voltage drop (VF) and energization current (IF) during energization of the power semiconductor element are generally expressed by the following relational expression.
[0023]
VF = a + b · IF (1)
Here, a and b are constants, a is a junction voltage depending on the diffusion potential of the junction in the pn junction, and b represents a gradient between current and voltage. In an alternating sine wave, if the effective current is IRMS, the energization current (IF) is
IF = 1.414 · IRMS · sinωt (ω is angular velocity) (2)
Therefore, the internally generated loss <P> per element due to energization of alternating current is
<P> = 0.9 · a · IRMS + b · (IRMS)²             ... (3)
It is expressed as
[0024]
When two thyristors are connected in antiparallel as in the prior art, a half-wave current flows through each thyristor, so the total loss of the two is equal to the value of the above equation, but as in this embodiment When two SITs are connected in series, the total loss is twice the value of the above equation.
[0025]
  FIG. 5 shows the relationship between the effective current and the internally generated loss of the element for one phase of the switch when a semiconductor element with a withstand voltage of 600 V is applied to the switch of AC voltage 220V. In FIG. 5, 34 is silicon carbide.DoThe case of the switch of this embodiment in which two SITs of (SiC) are connected in series is shown, and 35 is the case of a prior art switch in which two thyristors of the same withstand voltage are connected in parallel. , 36 is silicon carbideDoThe generated loss when two thyristors are connected in parallel is shown. In either case, the area per semiconductor element was calculated under the same conditions. Curve 34 silicon carbideDoThe loss of this embodiment using the SIT is greatly reduced as compared with the loss of the prior art using the silicon thyristor. For example, when the effective current is 30 A, the loss is 2 W and 40 W, respectively, which is about 1/20. Loss can be reduced to 0.1% or less of the voltage / current capacity of the switch. Such a difference in loss is caused not only by differences in semiconductor materials but also by differences in output characteristics of elements. That is, in SIT, the current flowing between the drain (D) and the source (S) of the main terminal does not have a conduction path that passes through the pn junction. Therefore, SIT shows a linear output characteristic. That is, a = 0 because of the relationship between the voltage drop (VF) and the energization current (IF) in the above equation (1). As a result, the first term on the right side of the generated loss <P> in the above equation (3) becomes zero, and the loss is greatly reduced. On the other hand, silicon carbideDoIn the case of this semiconductor, the junction voltage of the pn junction is about 2.5V, which is 1.5V higher than 1.0V of the pn junction of silicon. Therefore, as shown by the curve 36 in FIG.DoThe loss of the thyristor is larger than that of silicon. In the case of a thyristor, the first term on the right side of <P> in the above formula (3) is dominant, so even if the area of the semiconductor element is increased, the overall loss is not reduced. On the other hand, the loss of SIT can be further reduced by increasing the element area.
[0026]
  (Example 2)
  FIG. 6 shows a configuration diagram of one phase of the semiconductor switch of this embodiment. FIG. 7 is an equivalent circuit of the present embodiment shown in FIG. 6 and 7 correspond to the same reference numerals in FIGS. In this embodiment, silicon carbide is provided between the main terminals 82 and 84 of the switch.DoTwo SIT2 and SIT3 manufactured from the single crystal are connected in series. The source electrodes 9 and 10 of SIT2 and SIT3 are electrically connected to each other by a conductor 37, and the drain electrodes 7 and 8 are connected to main terminals 82 and 84 of the switch by internal conductors, respectively. The only difference from the first embodiment is that the electrodes in which the two SITs are directly connected by the internal conductor are different. That is, although the drain electrode is directly connected in the first embodiment, the source electrode is directly connected in this embodiment, and the basic configuration of the other control circuit 4 is the same. In this embodiment, since the gate drive signal from the OCS circuit can be shared by the two SITs, the gate circuit can be simplified.
[0027]
  (Example 3)
  FIG. 8 shows another embodiment of the static induction transistor (SIT) used in the switch according to the present invention. 8A and 8B show the cross-sectional structure of the SIT cell.FIG. 8 (a)Then, the semiconductor substrate 40 is silicon carbide.DoIn the semiconductor material, a relatively low resistance n-type substrate 41, a relatively high resistance n-type drift layer 42, a relatively low resistance p-type gate layer 43 and a low resistance n-type source layer 44 are contained therein. The drain electrode 7, the gate electrode 11, and the source electrode 9 are connected to the surfaces of the n-type substrate 41, the p-type gate layer 43, and the n-type source layer 44, respectively. Further, a p-type layer 45 having a relatively low resistance is partially disposed on the n-type source layer 44 from the surface of the base 40 toward the inside thereof, and makes a low-resistance contact with the source electrode 9 on the surface of the base. Yes. This embodiment is characterized in that the p-type layer 45 is provided, and is equivalent to a configuration in which a pn junction diode in antiparallel is built in a normal SIT. However, since almost no current flows through the diode, the area occupied by the diode, that is, the area occupied by the p-type layer 45 is very small.
[0028]
When this SIT is applied to the switch of FIGS. 1 and 6, the internal conductor (conductor 13 in FIG. 1, conductor 37 in FIG. 6) that connects two SITs connected in series by a built-in pn junction diode. The potential can be held in a fixed relationship with respect to the main terminals 82 and 84. That is, in the case of FIG. 1, the potentials of both drain electrodes (D) 7 and 8 are set to the potential of the main terminal 82 or the main terminal 84, respectively, and in FIG. In contrast, the junction potential of the built-in diode can be held at a low value. As a result, even if two SITs connected in series cannot simultaneously start on / off operations due to a gate signal for some reason, each SIT can reliably start on / off operations.
[0029]
The reference numerals in FIG. 8B correspond to the same reference numerals in FIG. FIG. 8B is different from FIG. 8A in that a pn junction diode is provided and a Schottky diode is formed. That is, a missing portion 440 is provided in some places of the source layer 44, a part of the n-type drift layer 42 is exposed there, and a Schottky electrode 46 is formed on the surface of the substrate, and the Schottky electrode 46 is connected to the source electrode. 44 was brought into low resistance contact. In FIG. 8B, the junction potential of the pn junction diode in FIG. 8A is the same as the Schottky barrier potential of the Schottky diode.
[0030]
  (Example 4)
  FIG. 9 shows another embodiment of the SIT used in the switch according to the present invention. FIG. 9A and FIG. 9B show a plan view of the SIT and a cross-sectional view at the position of the line segment AA ′, respectively. The semiconductor substrate 40 is silicon carbide.DoThe two SITs (SIT2 and SIT3) having the same polarity are integrated in parallel. Each SIT basically has the same configuration. That is, a relatively low-resistance n-type substrate 41, a relatively high-resistance n-type drift layer 42, a relatively low-resistance p-type gate layer 43, and a low-resistance n-type source layer 44 are formed. On the surface of the substrate 41, the p-type gate layer 43 and the n-type source layer 44, the drain electrode 7 (common), the gate electrode 11 and gate lead 111 of SIT2, the gate electrode 12 and gate lead 121 of SIT3, and the source of SIT2 The electrode 9 and the source electrode 10 of SIT3 are each connected to a low resistance. However, although these electrodes are omitted in FIG. 9A, the source electrode and the gate electrode are electrically insulated by the silicon oxide film 47 shown in FIG. 9B. The built-in SIT2 region and SIT3 region are divided by p-type guard rings 481 and 482 of relatively low resistance arranged so as to surround the respective operation regions. FIG. 9A shows an example in which one guard ring is provided, but a plurality of guard rings are arranged when the withstand voltage of the element is high.
[0031]
The composite SIT of this embodiment shown in FIGS. 9A and 9B includes two SIT2 and SIT3 connected in series shown in Embodiment 1 shown in FIG. It is an integrated product. Since the source electrodes 9 and 10 of the SIT main element of this embodiment are connected to the main terminals 82 and 84 by the internal conductors 31 and 32, respectively, the main semiconductor parts of the switch can be connected. It is possible to reduce the size of the device and simplify the assembly.
[0032]
  (Example 5)
  FIG. 10 shows another embodiment of the SIT used in the switch of the present invention. 10 (a) and 10 (b))The plan view of SIT and the sectional view of the position of line segment AA ′ are shown respectively. The semiconductor substrate 40 is silicon carbide.DoIt is composed of semiconductor materials. As shown in FIG. 10 (b), the semiconductor substrate 40 has 2 × 10 boron on a semi-insulating silicon carbide substrate 49.¹⁶cm ^-2 A p-type layer 50 doped to a concentration of about 5 μm is formed by an epitaxial method to a thickness of about 8 μm, and 1.5 × 10 5 at an implantation energy of 100 keV from the surface of the p-type layer 50.¹³cm^-2An n-type drift layer 51 having a depth of about 0.3 μm formed by implanting an amount of nitrogen, and 1.5 × 10 5 at an implantation energy of 30 keV from the surface of the n-type drift layer 51.¹⁵cm^-2A band-shaped n having an interval and a width of about 30 μm formed by implanting nitrogen at a high concentration of⁺Layers 441, 442, and n⁺The implantation energy is 30 keV and the implantation amount is 1 × 10 from the surface approximately 3.5 μm away from both sides of the layers 441 and 442.¹⁵cm^-2P formed by implanting boron or aluminum at a high concentration of⁺Layers 431 and 432. Further, a metal film 52 is bonded to the surface of the semi-insulating silicon carbide substrate 49, and the n⁺Main electrodes 9 and 10 such as nickel are further formed on the surfaces of the layers 441 and 442, and the p⁺Gate electrodes 11 and 12 such as aluminum are in low resistance contact with the surfaces of the layers 431 and 432, respectively.
[0033]
As shown in FIG. 10A, the nickel electrodes 9 and 10 are formed so as to mesh with each other, and regions 91, 92 and 102 of the respective electrodes are provided with portions to which external leads are connected. Further, external leads are connected to the respective electrode regions of the gate electrodes 11 and 12 at portions 111 and 121.
[0034]
This embodiment shown in FIG. 10 is a horizontal AC control type SIT. That is, the semiconductor element constituted by two opposing main electrodes 9 and 10 and two intervening gate electrodes 11 and 12 are connected in series by connecting the drains (D) to each other in the first embodiment of FIGS. The equivalent circuit is equivalent to the two SITs. The difference from the first embodiment is that each drain region is shared. Therefore, the on-loss caused by the resistance component of the drain region when two transistors are connected in series can be halved by the configuration of this embodiment. Such a configuration can be realized by a horizontal structure in which the arrangement of the main terminals and the direction of current flow are horizontal. In this embodiment, a lateral SIT with a withstand voltage of 450 V is used, so that the drift resistance is reduced while maintaining the withstand voltage by using a so-called RESURF structure, and approximately 5 mΩ · cm.²ON resistance can be realized.
[0035]
  (Example 6)
  FIG. 11 shows the configuration of one phase of the semiconductor switch of this embodiment. The same reference numerals in FIG. 11 as those in FIG. 6 correspond to the same parts. Two semiconductor elements 2 and 3 connected in series inside the switch 1 are made of silicon carbide.DoThis is different from the second embodiment in that it is a MOSFET made of a single crystal. In FIG. 11, MOSFET 62 and MOSFET 63 are silicon carbide.DoMade of a single crystal of n, and n⁺Substrate, n^-Drift layer, p⁺Well layer, n⁺Source layer is silicon carbideDoThe gate layers (electrodes) 11 and 12, the source electrodes 9 and 10, and the drain electrodes 7 and 8 are arranged on the surface and insulated by a silicon oxide film or the like. In the two MOSFETs 62 and 63, the source electrodes 9 and 10 are connected by a conductor 38, the gate electrodes 11 and 12 are electrically connected by a conductor 37, and the drain electrodes 7 and 8 are connected by an inner conductor 31, 32 is connected to the main terminals 82 and 84 of the switch. A signal line to which a gate signal is supplied from the OCS circuit 15 of the control circuit 1 is connected to the conductor 37 and the conductor 38.
[0036]
The operation of the present embodiment can be explained by replacing the SIT of the first embodiment with a MOSFET and changing the bias direction of the gate signal slightly. That is, the current is cut off in the initial state of normal operation in which the main terminals 81 and 82 on the power supply side are connected to the AC power supply 100 and the main terminals 83 and 84 on the load side are connected to the load 200, respectively. In the present embodiment, while the OCS circuit 15 in the control circuit 4 gives a gate signal of zero or negative voltage to the gate terminals 11 and 12 of the MOSFET 62 and MOSFET 63 to the source terminals 9 and 10, respectively, The two MOSFETs remain off. Since the two MOSFETs are connected in opposite directions, AC voltage from the power source can be blocked in both directions. The transition from the OFF state to the ON state of the switch starts when a command 20 for releasing the latching state of the logic unit 16 instructing the maintenance of the gate bias is input from the control terminal 85. The MOSFET has a property that the energization current in the on-state increases as the gate voltage of the positive bias increases. For this reason, normally, a positive-biased gate signal is applied to hold the ON state. Since the two MOSFETs are turned on almost simultaneously, a bidirectional alternating current flows to the load. Since switching from the on state to the off state is a transition to the first state, the bias direction of the gate signal may be reversed. Further, in the case where an abnormality occurs in the wiring system or the load and an overcurrent flows, the SIT may be replaced with the MOSFET in the description of FIGS. 4A to 4B in the first embodiment. Further, the description that can reduce the loss by the present embodiment may be similarly replaced with the MOSFET from the SIT in the description of the corresponding portion of the first embodiment.
[0037]
  (Example 7)
  In this embodiment, as shown in FIG.surgeA surge absorption element made from a novel silicon carbide single crystal was used as the absorption element. The same reference numerals as those in FIG. 3 are used for the main terminals 81 to 84 of the switch, the semiconductor elements 2 and 3 for switching, the logic section 16 in the control circuit, the OSC circuit 15, the power supply section 14, and the control terminal 85. Corresponds to the part. In FIG. 12, reference numeral 71 denotes a constant voltage diode or bipolar surge absorbing element made of a silicon carbide single crystal, which has excellent flatness of the holding voltage from the operation start voltage and high surge energy that can be absorbed. And unlike ceramic arresters such as zinc oxide, it can withstand repeated surge absorption. In a snubber circuit in which a capacitor and a resistor, which are often used as a surge absorbing circuit, are connected, an AC current loss occurs. In this embodiment, this loss can be eliminated.
  (Example 8)
  FIG. 13 shows a mounting structure of an AC 220V, 30A rated three-phase AC switch according to the present invention. Fig.13 (a) shows internal planar arrangement | positioning, FIG.13 (b) is sectional drawing, Comprising: The main part is shown. Al on a metal plate 502 with mounting holes 500₂O_ThreeThe internal electrode 13 is disposed via an electrical insulating plate 504 such as. The drain electrodes of two semiconductor chips are bonded to the internal electrodes 13 of each phase. In the U phase, the semiconductor chips U2 and U3 are bonded, and the source electrode of the semiconductor chip and the main terminals U82 and U84 are electrically connected by aluminum wires 31 and 32, respectively. Although details are omitted, the gate electrode of each semiconductor chip is also connected to a control circuit or the like by a wire 503. Although the U-phase portion has been described above, the description is omitted because the arrangement is the same for the V-phase and the W-phase.
[0038]
Each phase semiconductor chip is molded with an epoxy resin 506 together with a gate control circuit 505. In this embodiment rated for AC 220V, 30A, the outer dimensions are 60 mm in length, 50 mm in width, and 20 mm in height, which is about ½ of the volume of a conventional electromagnetic switch. In this embodiment, the case of 220V, 30A rating is shown. However, if the number of parallel semiconductor chips is increased, it is possible to easily cope with an increase in current capacity.
[0039]
In the above embodiments, silicon carbide has been described as an example of a semiconductor crystal material having a wide band gap. However, the present invention can be applied to any semiconductor crystal having a band gap of 2.0 eV or more. The semiconductor crystal having a band gap of 2.0 eV or more may be not only silicon carbide but also gallium nitride or diamond. In addition, as an example of the semiconductor element type, an electrostatic induction transistor (SIT) or a MOSFET has been described as an example, but any device having a linear output characteristic can be applied, so not only the SIT and MOSFET, A device such as a junction field effect transistor, MESFET, or MISFET may be used.
[0040]
【The invention's effect】
According to the present invention, it is possible to easily realize a non-contact AC switch having a function of operating at high speed with low power loss and limiting the current during an abnormality to several times the steady value or less. According to the present invention, not only can the semiconductor element used for the switch be downsized, but also the short circuit withstand capability of various electrical equipment attached to the load side of the switch can be reduced, so that not only the switch body but also the accompanying equipment can be reduced. Improved reliability and lower price.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a semiconductor switch according to an embodiment of the present invention.
FIG. 2 is a circuit configuration diagram of a conventional solid state conductor.
FIG. 3 is a simplified configuration diagram of a semiconductor switch according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating a current limiting operation of the semiconductor switch according to the present invention.
FIG. 5 is a graph showing the relationship between effective current and generated loss for explaining the loss reduction effect of the present invention.
FIG. 6 is a configuration diagram of a semiconductor switch according to an embodiment of the present invention.
FIG. 7 is a simplified configuration diagram of a semiconductor switch according to an embodiment of the present invention.
FIG. 8 is a cross-sectional view of the static induction transistor of the present invention applied to the switch of the present invention.
FIG. 9 is a cross-sectional view of the electrostatic induction transistor of the present invention applied to the switch of the present invention.
FIG. 10 is a cross-sectional view of the electrostatic induction transistor of the present invention applied to the switch of the present invention.
FIG. 11 is a configuration diagram of a semiconductor switch according to an embodiment of the present invention.
FIG. 12 is a configuration diagram of a switch according to the present invention.
FIG. 13 is a diagram showing the structure of an embodiment of a switch according to the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor switch, 2, 3 ... Semiconductor element which has linear output characteristic, 4 ... Control circuit, 5 ... Energy absorption circuit, 6 ... Current sensor, 7, 8 ... Drain electrode, 9, 10 ... Source electrode, 11, DESCRIPTION OF SYMBOLS 12 ... Gate electrode, 13, 37 ... Internal conductor, 14 ... Gate power supply part, 15 ... Gate OSC circuit, 16 ... Gate logic part, 17 ... Insulation pulse transformer, 18, 19 ... Gate circuit, 20 ... Signal wiring, 22, 23 ... AC current at normal time, 24 ... Short-circuit current, 25 ... Current limiting start current, 26 ... Current limiting initial current, 27 ... Current flowing at current limiting, 28 ... Gate signal at current limiting control, 29 ... Current limiting Pulse signal at the time of control, 31, 32, 33... Internal conductor, 34... Generation loss of silicon carbide transistor of the present invention, 35... Generation loss of silicon thyristor, 36. Loss, 38 ... conductor, 40 ... semiconductor substrate, 41 ... low-resistance semiconductor substrate, 42 ... relatively high resistance of the semiconductor layer, 43 ... gate layer, 44 ... source layer, 45 ... p⁺ Layer, 46 ... Schottky electrode, 47 ... insulating film, 50 ... p epitaxial layer, 51, 441, 442 ... n⁺ Ion implantation layer, 52 ... metal layer, 62, 63 ... MOSFET, 71 ... surge absorption element, 81,82,83,84 ... main terminal, 85 ... gate control terminal, 91,92,102,111,121 ... wire bonding Pad, 100 ... AC power supply, 101 ... Operation power supply, 200 ... Load, 431, 432 ... p⁺ Ion implantation layer, 440 ... n⁺ Defects, 481, 482 ... guard ring, 500 ... mounting hole, 501 ... main terminal hole, 502 ... metal plate, 503 ... gate wire, 504 ... insulating plate, 505 ... control circuit board, 506 ... epoxy resin.

Claims (8)

In a semiconductor switch that opens and closes an AC power supply with a power semiconductor element,
Between two main terminals of one phase of the AC, the silicon carbide single crystal as a substrate, at least two semiconductor transistors having a linear A output characteristics in response to control signal level of the gate, to reverse the polarity of each other A bidirectional AC switch circuit connected in series, a control circuit for supplying a control signal to the transistor, a circuit for detecting a current-carrying state of the transistor, and circuit energy of a load wired in parallel to the transistor connected in series A semiconductor switch comprising: a circuit that absorbs the current , wherein the transistor having linear output characteristics is an electrostatic induction transistor . In a semiconductor switch that opens and closes an AC power supply with a power semiconductor element ,
Between two main terminals of one-phase alternating current, at least two semiconductor transistors having a silicon carbide single crystal as a base material and having a linear output characteristic according to the gate control signal level are reversed in polarity. A bidirectional AC switch circuit connected in series, a control circuit for supplying a control signal to the transistor, a circuit for detecting a current-carrying state of the transistor, and circuit energy of a load wired in parallel to the transistor connected in series and a absorbing circuit, a semiconductor switch, wherein the circuit to absorb the circuit energy is a surge absorbing element of the constant voltage diode or bipolar produced silicon carbide single crystal as a material. 3. The semiconductor switch according to claim 2 , wherein the transistor having the linear output characteristic is a MOSFET formed in a silicon carbide single crystal. 2. The semiconductor switch according to claim 1 , wherein the electrostatic induction transistor is a static induction transistor in which a pn junction or a Schottky barrier provided adjacent to the source layer is short-circuited by a source electrode. vessel. 2. The semiconductor switch according to claim 1, wherein a plurality of the electrostatic induction transistors are formed on a single silicon carbide single crystal substrate. In a semiconductor switch that opens and closes an AC power supply with a power semiconductor element,
Between two main terminals of one phase of the AC, the silicon carbide single crystal as a substrate, at least two static induction transistor having a linear A output characteristics in response to control signal level of the gate, the polarity of each other Conversely, a bidirectional AC switch circuit connected in series, a control circuit for supplying a control signal to the transistor, a circuit for detecting the energization state of the transistor, and a load wired in parallel to the transistor connected in series And a circuit for absorbing circuit energy, wherein the control circuit detects an overcurrent, and a current flowing through the transistor for a predetermined period of time is limited within five times the steady state. 7. The semiconductor switch according to claim 6 , wherein the control circuit controls a flowing current by adjusting a voltage level of a control signal of the transistor. 7. The semiconductor switch according to claim 6 , wherein the flowing current is controlled by adjusting the pulse width of the control signal of the transistor.

Images