JP2008211202A - Wiring board and semiconductor package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board capable of obtaining high reliability even if a core substrate is large. <P>SOLUTION: The wiring board 10 is provided with the core substrate 11, a ceramic capacitor 101 and a main surface side wiring laminate 31. The core substrate 11 has the largest length of 50 mm, and a component housing hole 90 opened at a core main surface 12 side and a core rear surface 13 side. The ceramic capacitor 101 is housed in the component housing hole 90 in a state that the core main surface 12 and a capacitor main surface 102 face the same side. A component mounting region 23 capable of mounting an IC chip 21 is set on the surface 39 of the main surface side wiring laminate 31. The ceramic capacitor 101 is disposed immediately below the component mounting region 23, and the outer dimension of the ceramic capacitor 101 is set smaller than the outer dimension of the component mounting region 23. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention has a structure in which a wiring laminated portion is formed on the surface of a core substrate, and includes a wiring substrate in which a plate-like component is accommodated, and the wiring substrate and a plate-like component mounted thereon. The present invention relates to a semiconductor package having a structure in which a gap is sealed with a resin material.

  In recent years, semiconductor integrated circuit chips (IC chips) used as computer microprocessors and the like have become increasingly faster and more functional, with an accompanying increase in the number of terminals and a tendency to narrow the pitch between terminals. . In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, a method is generally employed in which a semiconductor package is prepared by mounting an IC chip on an IC chip mounting wiring board, and the semiconductor package is mounted on a motherboard. In this type of semiconductor package, it has been proposed to provide a capacitor (also referred to as “capacitor”) in order to reduce switching noise of the IC chip and stabilize the power supply voltage. As an example, a semiconductor package in which an IC chip is mounted on a wiring substrate in which a capacitor is built in a core substrate made of a polymer material and a buildup layer is formed on the front surface and the back surface of the core substrate has been conventionally used. It has been proposed (see, for example, Patent Document 1).

Recently, as shown in FIG. 23, there is a semiconductor package 200 in which the external dimension of the capacitor 205 built in the core substrate 201 is set larger than the external dimension of the IC chip 204 mounted on the wiring substrate 202. Proposed. A gap between the wiring board 202 and the IC chip 204 is sealed with an underfill material 206. In this way, since the IC chip 204 is located in the region directly above the capacitor 205, the IC chip 204 can be stably supported by the capacitor 205.
JP 2000-261124 (FIG. 1 etc.)

  However, during cooling after bonding the IC chip 204, the back-side buildup layer 207 located on the back side of the core substrate 201 contracts, but the front-side buildup layer 203 located on the front side of the core substrate 201 Since the chip 204 and the underfill material 206 are present, they hardly shrink. Therefore, the wiring board 202 tends to warp to the back side (see FIG. 24). In particular, when the core substrate 201 is large (specifically, when the length of the largest side of the core substrate 201 is 40 mm or more), the warp of the wiring substrate 202 becomes significant. At this time, the capacitor 205 having a plasticity smaller than that of the core substrate 201 and the buildup layers 203 and 207 cannot follow the warp of the wiring substrate 202, so that stress concentrates and is easily broken. In addition, stress is concentrated on the joint between the capacitor 205 and the build-up layers 203 and 207, so that the capacitor 205 is easily broken. As a result, the reliability of the wiring board 202, and hence the semiconductor package 200, is reduced.

  The present invention has been made in view of the above problems, and an object thereof is to provide a wiring board capable of obtaining high reliability even when the core board is large. Another object of the present invention is to provide a suitable semiconductor package having the above wiring board.

  And as a means (means 1) for solving the above-mentioned problem, a component housing hole having a core main surface and a core back surface and opening at least on the core main surface side is formed, and the length of the largest side is Made of a first inorganic material having a core substrate of 40 mm or more, a component main surface and a component back surface, and being accommodated in the component accommodation hole in a state where the core main surface and the component main surface are directed to the same side A plate-shaped component, a main surface side interlayer insulating layer, and a main surface side conductor layer are laminated on the core main surface, and a component mounting area on which a second inorganic material plate-shaped component can be mounted is on the surface. The first inorganic material plate, comprising: a set main surface side wiring laminated portion; and a back surface side wiring laminated portion formed by laminating a back surface side interlayer insulating layer and a back surface side conductor layer on the core back surface. A component is disposed immediately below the component mounting area and made of the first inorganic material. There is a wiring board, characterized in that the external dimensions of Jo component is set smaller than the outside dimension of the component mounting region.

  Therefore, according to the wiring board of means 1, even if the warp of the wiring board becomes significant due to the length of the largest side of the core board being 40 mm or more, the first inorganic material plate-like component is warped. Since it is arranged directly under the component mounting area that is not easily affected by the above-mentioned and is set to an outer dimension smaller than the outer dimension of the component mounting area, stress is less likely to concentrate. As a result, the first inorganic material plate-like component, the joint portion between the first inorganic material plate-like component and the wiring laminated portion, and the like are not easily broken, and the reliability of the wiring board is increased.

  In addition, since the main surface side wiring laminated portion is formed on the core main surface and the back surface side wiring laminated portion is formed on the core rear surface, both the main surface side wiring laminated portion and the back surface side wiring laminated portion are formed. An electrical circuit can be formed. Therefore, it is possible to improve the functionality of the wiring board.

  The core substrate constituting the wiring substrate is formed in a plate shape having a core main surface and a core back surface located on the opposite side. The shape of the core substrate is preferably a polygonal shape having a plurality of sides, and examples thereof include a substantially rectangular shape in plan view, a substantially triangular shape in plan view, and a substantially hexagonal shape in plan view. It is preferable that the shape is a generally rectangular shape in plan view. Here, the “substantially rectangular shape in plan view” does not mean only a complete rectangular shape in plan view but also includes a shape with chamfered corners and a shape in which a part of the side is curved. . The core substrate has the largest side length of 40 mm or more, but may be, for example, 50 mm or more and 100 mm or less.

  Further, the core substrate has a component accommodation hole for accommodating the first inorganic material plate-like component. This component accommodation hole may be a non-through hole that opens only in the core main surface, or may be a through hole that opens in both the core main surface and the core back surface. Further, the first inorganic material plate-like component may be accommodated in the component accommodation hole in a completely embedded state, or may be accommodated in the component accommodation hole in a state in which a part protrudes from the opening of the component accommodation hole. May be.

  In addition, it is preferable that the shape of the opening part of the said component accommodation hole is a shape substantially the same as the shape of the said component mounting area. In addition, the outer dimension of the opening of the component housing hole is preferably set smaller than the outer dimension of the component mounting area, and specifically, 0.8 times or more the outer dimension of the component mounting area. And it is preferable to set to less than 1.0 times. If the outer dimension of the opening of the component housing hole is 1.0 times or more of the outer dimension of the component mounting area, the gap between the inner surface of the component housing hole and the side surface of the ceramic capacitor is filled with, for example, a resin material made of a polymer material When it is filled with the part, the filling amount of the resin filling part increases. In addition, it is difficult to position the first inorganic material plate-shaped component in the component accommodation hole. Further, since there is no portion directly under the component mounting area in the core substrate, it becomes impossible to form an electric circuit in that portion. On the other hand, if the outer dimension of the opening of the component housing hole is less than 0.8 times the outer dimension of the component mounting area, the gap between the inner surface of the component housing hole and the side surface of the ceramic capacitor is reduced. It becomes difficult to accommodate the first inorganic material plate-like component having a predetermined size.

  A material for forming the core substrate is not particularly limited, but a preferable core substrate is mainly formed of a polymer material. Specific examples of the polymer material for forming the core substrate include, for example, EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide / triazine resin), PPE resin (polyphenylene ether resin), etc. There is. In addition, composite materials of these resins and glass fibers (glass woven fabric or glass nonwoven fabric) or organic fibers such as polyamide fibers may be used.

  Here, when the wiring board has the configuration of the means 1, the thermal expansion coefficient of the first inorganic material plate-like component is that of the core board, the main surface side wiring laminated portion, and the back surface side wiring laminated portion. It may be smaller than the thermal expansion coefficient. In this way, a difference in thermal expansion coefficient occurs between the first inorganic material plate-like component and the other part of the wiring board (core substrate, main surface side wiring laminated portion and back side wiring laminated portion). For this reason, a problem that a large force is applied to the vicinity of the first inorganic material plate-like component is easily generated. However, since the wiring board has the configuration of the means 1, the above problem can be solved.

  “Thermal expansion coefficient” means the thermal expansion coefficient in the direction (XY direction) perpendicular to the thickness direction (Z direction). TMA (thermomechanical analyzer) between 0 ° C. and 100 ° C. (Hereinafter the same). “TMA” refers to thermomechanical analysis, such as that defined in JPCA-BU01.

  Suitable examples of the first inorganic material plate-like component include a ceramic plate-like component, a metal plate-like component, and a glass plate-like component. Examples of the ceramic material constituting the ceramic plate-like component include low-temperature fired materials such as alumina, glass ceramic, and crystallized glass, aluminum nitride, silicon carbide, and silicon nitride. Examples of the metal material constituting the metal plate-like component include iron, gold, silver, copper, copper alloy, iron nickel alloy, silicon, and gallium arsenide. Examples of the metal plate-like component include a semiconductor integrated circuit chip (IC chip) and a MEMS (Micro Electro Mechanical Systems) element manufactured by a semiconductor manufacturing process. Here, “semiconductor integrated circuit chip” refers to an element mainly used as a microprocessor of a computer.

  On the other hand, examples of suitable ceramic plate-like parts include a chip capacitor and a via array type ceramic capacitor having a plurality of via conductors in the capacitor. In the ceramic capacitor, the plurality of via conductors in the capacitor are preferably arranged in an array as a whole. With such a structure, the inductance of the ceramic capacitor can be reduced, and high-speed power supply for noise absorption and power supply fluctuation smoothing can be performed. In addition, the entire ceramic capacitor can be easily reduced in size, and as a result, the entire wiring board can be easily reduced in size. Moreover, a high electrostatic capacity is easily achieved for a small amount, and a more stable power supply can be achieved.

  As the ceramic dielectric layer constituting the ceramic capacitor, a sintered body of high-temperature fired ceramic such as alumina, aluminum nitride, boron nitride, silicon carbide, silicon nitride is preferably used, and borosilicate glass or borosilicate A sintered body of low-temperature fired ceramic such as glass ceramic obtained by adding an inorganic ceramic filler such as alumina to lead glass is preferably used. In this case, it is also preferable to use a sintered body of a dielectric ceramic such as barium titanate, lead titanate, or strontium titanate depending on the application. When a dielectric ceramic sintered body is used, a ceramic capacitor having a large capacitance can be easily realized.

  In addition, a component mounting area is set on the surface of the main surface side wiring laminated portion constituting the wiring board, and the first inorganic material plate-shaped component is disposed immediately below the component mounting area. A plate-like component made of the second inorganic material can be mounted in such a component mounting region. The “component mounting region” is a region located immediately below the lower surface of the second inorganic material plate-shaped component when the second inorganic material plate-shaped component is mounted. It has substantially the same outer shape as the lower surface of the plate-shaped component made of material. Further, the area of the component mounting area is set to be equal to or smaller than the area of the lower surface of the second inorganic material plate-shaped component. The “component mounting area” refers to an area where a plurality of terminals exposed on the surface of the main surface side wiring laminated portion are present.

  It is preferable that the area of the first inorganic material plate-like component is set to be equal to or smaller than the area of the component mounting region. Specifically, the area of the component mounting region is 0%. It is preferably set to 25 times or more and less than 1 time, particularly 0.4 times or more and less than 0.7 times the area of the component mounting region. If the area of the first inorganic material plate-like component is set to be less than 0.25 times the area of the component mounting region, the first inorganic material plate-like component becomes too small. It becomes difficult to achieve high functionality of the plate-shaped parts made of material. On the other hand, when the area of the first inorganic material plate-like component is set to be equal to or larger than the area of the component mounting region, the outer dimension of the first inorganic material plate-like component is larger than the outer dimension of the component mounting region. Easy to grow. As a result, a large force is applied to the vicinity of the first inorganic material-made plate-like component and it is easily broken, and the reliability of the wiring board is lowered.

  Here, a component mounting portion on which a third inorganic material plate-shaped component made of a silicon-based material can be mounted is set on the surface of the back surface side wiring laminated portion, and the component mounting portion is mounted on the wiring board with the component mounting. The external dimensions of the component mounting portion may be set smaller than the external dimensions of the component mounting area. With such a configuration, even if the warping of the wiring board becomes significant, the component mounting portion on which the third inorganic material plate-like component can be mounted is on the back side of the component mounting region that is not easily affected by the warping. In addition to being disposed, the outer dimension is set to be smaller than the outer dimension of the component mounting area, so that stress is less likely to concentrate. As a result, the third inorganic material plate-like component, the joint portion between the third inorganic material plate-like component and the back-side wiring laminated portion, and the like are not easily broken, and the reliability of the wiring board is increased. Since the third inorganic material plate-like component is made of a silicon-based material having a thermal expansion coefficient of about 3 to 6 ppm / ° C., the outer dimensions of the component mounting portion should be set smaller than the outer dimensions of the component mounting area. The above effect can be obtained. If the third inorganic material plate-like component is made of barium titanate having a thermal expansion coefficient of about 12 to 13 ppm / ° C., the size relationship between the component mounting portion and the component mounting region is not changed. The effect cannot be obtained.

  Examples of the third inorganic material plate-like component made of a silicon-based material include the semiconductor integrated circuit chip (IC chip), the MEMS element, and a DRAM (Dynamic Random Access Memory) element.

  The “component mounting portion” is an area located immediately above the top surface of the third inorganic material plate-shaped component when the third inorganic material plate-shaped component is mounted. The outer shape is substantially the same as the upper surface of the material plate-like component. Further, the area of the component mounting portion is set to be equal to or smaller than the area of the upper surface of the third inorganic material plate-shaped component. The “component mounting portion” refers to a region where there are a plurality of terminals exposed on the surface of the back surface side wiring laminated portion. The shape of the component mounting portion is preferably substantially the same as the shape of the component mounting area.

  Furthermore, on the surface of the back surface side wiring laminated portion, when the wiring board is viewed from the front surface side of the back surface side wiring laminated portion, on the outline of the first inorganic material plate-like component, and the second It is preferable that the surface-mounted component is mounted at a position avoiding a corresponding location (that is, a location where stress is concentrated) on the outline of the inorganic material plate-like component. In this way, the surface-mounted component and the joint between the surface-mounted component and the back-side wiring laminated portion are less likely to be destroyed, and the reliability of the wiring board is increased.

  Further, as another means (means 2) for solving the problems of the present invention, a structure in which a gap between a wiring board and a second inorganic material plate-like component mounted thereon is sealed with a resin material In this semiconductor package, the wiring board has a core main surface and a core back surface, is formed with a component accommodation hole that opens at least on the core main surface side, and the length of the longest side is 40 mm or more. A first inorganic material plate-like component that has a core substrate, a component main surface, and a component back surface, and is accommodated in the component accommodation hole in a state in which the core main surface and the component main surface are directed to the same side; The main surface side interlayer insulating layer and the main surface side conductor layer are laminated on the core main surface, and a component mounting area for mounting the second inorganic material plate-shaped component is set on the surface thereof. The main surface side wiring laminated portion, the back surface side interlayer insulating layer and the back surface side conductor layer are connected to the core. The first inorganic material plate-like component is disposed immediately below the component mounting region, and the first inorganic material plate-like component is disposed on the surface. There is a semiconductor package characterized in that the outer dimension of the package is set smaller than the outer dimension of the component mounting area.

  Therefore, according to the semiconductor package of the means 2, even if the warp of the wiring substrate becomes remarkable due to the length of the largest side of the core substrate being 40 mm or more, the first inorganic material plate-like component is warped. Since it is arranged directly under the component mounting area that is not easily affected by the above-mentioned and is set to an outer dimension smaller than the outer dimension of the component mounting area, stress is less likely to concentrate. As a result, the first inorganic material plate-like component, the joint portion between the first inorganic material plate-like component and the wiring laminated portion, and the like are not easily broken, and the reliability of the semiconductor package is increased.

  Here, examples of the second inorganic material plate-like component include the ceramic plate-like component, the metal plate-like component, the glass plate-like component, and the like. The semiconductor integrated circuit chip is preferable. In this case, since the first inorganic material plate-like component is disposed immediately below the semiconductor integrated circuit chip mounted in the component mounting region, the first inorganic material plate-like component, the semiconductor integrated circuit chip, The wiring connecting the wires is shortened, and an increase in the inductance component of the wiring is prevented. Therefore, when the first inorganic material plate-like component is a ceramic capacitor, the switching noise of the semiconductor integrated circuit chip due to the ceramic capacitor can be reliably reduced, and the power supply voltage can be reliably stabilized.

  When the semiconductor package has the configuration of the means 2, the thermal expansion coefficient of the second inorganic material plate-like component is the heat of the core substrate, the main-surface-side wiring laminated portion, and the back-side-side wiring laminated portion. It may be smaller than the expansion coefficient. If it does in this way, since it will become difficult to deform | transform a 2nd inorganic material plate-shaped component following the curvature of a wiring board, it has been arrange | positioned directly under the 2nd inorganic material plate-shaped component (component mounting area). The vicinity of the first inorganic material plate-like component is also difficult to deform.

  Hereinafter, an embodiment of a semiconductor package according to the present invention will be described in detail with reference to the drawings.

  The semiconductor package 1 shown in FIGS. 1 and 2 has a structure in which an IC chip 21 (semiconductor integrated circuit chip), which is a second inorganic material plate-like component, is mounted on a wiring substrate 10. The IC chip 21 having a function as an MPU has a rectangular flat plate shape of 12.0 mm long × 12.0 mm wide × 0.7 mm thick, and has a thermal expansion coefficient of about 3 to 4 ppm / ° C. (specifically 3 (About 5 ppm / ° C.). Circuit elements (not shown) are formed on the lower surface layer of the IC chip 21. On the lower surface side of the IC chip 21, a plurality of surface connection terminals 22 are provided in a grid pattern at a pitch of about 150 μm.

  Further, a gap between the wiring substrate 10 and the IC chip 21 is filled with an underfill material 20 that is a resin material. As a result, the wiring substrate 10 and the IC chip 21 are fixed to each other with the interface sealed. The underfill material 20 of the present embodiment is made of an epoxy resin having a thermal expansion coefficient of about 20 to 60 ppm / ° C. (specifically, about 20 ppm / ° C.). Note that when viewed from the thickness direction of the wiring substrate 10, the protrusion amounts A <b> 1 (see FIG. 2) of the underfill material 20 from the four sides constituting the IC chip 21 are each 2 mm. That is, the underfill material 20 is present in a substantially square area in plan view of 16.0 mm in length × 16.0 mm in width on the wiring board 10.

  As shown in FIG. 1, the wiring board 10 is a wiring board for mounting an IC chip, on a substantially rectangular plate-shaped core board 11 and a core main surface 12 (upper surface in FIG. 1) of the core board 11. Main surface side buildup layer 31 (main surface side wiring laminated portion) to be formed, and back surface side buildup layer 32 (back surface side wiring laminated portion) formed on core back surface 13 (lower surface in FIG. 1) of core substrate 11. ).

  The main surface side buildup layer 31 formed on the core main surface 12 of the core substrate 11 includes a main surface side interlayer insulating layer (main surface side resin insulating layers 33 and 35) made of epoxy resin, and a main surface made of copper. The side conductor layers 42 are alternately stacked. In this embodiment, the thermal expansion coefficient of the main surface side buildup layer 31 is about 10 to 60 ppm / ° C. (specifically, about 20 ppm / ° C.). In addition, the thermal expansion coefficient of the main surface side buildup layer 31 says the average value of the measured value between 30 degreeC-glass transition temperature (Tg). In addition, terminal pads 44 are formed in an array at a plurality of locations on the surface of the second-layer main-surface-side resin insulation layer 35. Further, the surface of the main surface side resin insulation layer 35 is almost entirely covered with a solder resist 37. An opening 46 for exposing the terminal pad 44 is formed at a predetermined position of the solder resist 37. A plurality of solder bumps 45 are provided on the surface of the terminal pad 44. Each solder bump 45 is electrically connected to the surface connection terminal 22 of the IC chip 21. The region where each terminal pad 44 and each solder bump 45 is located is a component mounting region 23 in which the IC chip 21 can be mounted. The component mounting area 23 is set on the surface 39 of the main surface side buildup layer 31 and is a square area in plan view of 12.0 mm in length × 12.0 mm in width. That is, the component mounting area 23 is an area arranged immediately below the lower surface of the IC chip 21 in the semiconductor package 1, and has the same outer shape and area as the lower surface of the IC chip 21 when viewed from the thickness direction of the semiconductor package 1. have. In addition, via conductors 43 and 47 are provided in the main surface side resin insulation layers 33 and 35, respectively. The via conductors 43 and 47 electrically connect the main surface side conductor layer 42 and the terminal pads 44 to each other.

  As shown in FIG. 1, the back surface side buildup layer 32 formed on the core back surface 13 of the core substrate 11 has substantially the same structure as the main surface side buildup layer 31 described above. That is, the back side buildup layer 32 has a thermal expansion coefficient of about 10 to 60 ppm / ° C. (specifically, about 20 ppm / ° C.), and a back side interlayer insulating layer (back side resin insulating layer 34, 36) and backside conductor layers 41 are alternately laminated. BGA pads 48 that are electrically connected to the back-side conductor layer 41 through via conductors 43 are formed in a lattice pattern at a plurality of locations on the lower surface of the second-layer back-side resin insulation layer 36. Further, the lower surface of the back side resin insulation layer 36 is almost entirely covered with a solder resist 38. An opening 40 for exposing the BGA pad 48 is formed at a predetermined portion of the solder resist 38. On the surface of the BGA pad 48, a plurality of solder bumps 49 are provided for electrical connection with a mother board (not shown). The wiring board 10 shown in FIG. 1 is mounted on a mother board (not shown) by each solder bump 49.

  As shown in FIG. 1, the core substrate 11 of the present embodiment has a substantially rectangular plate shape in plan view of 50 mm length × 50 mm width × 0.4 mm thickness. The core substrate 11 has a thermal expansion coefficient in the plane direction (XY direction) of about 10 to 30 ppm / ° C. (specifically, 18 ppm / ° C.). In addition, the thermal expansion coefficient of the core board | substrate 11 says the average value of the measured value between 0 degreeC-glass transition temperature (Tg). The core substrate 11 includes a base material 161 made of glass epoxy, a sub-base material 164 formed on an upper surface and a lower surface of the base material 161 and made of an epoxy resin to which an inorganic filler such as silica filler is added, and an upper surface of the base material 161. And a conductor layer 163 made of copper and formed on the lower surface. In the core substrate 11, a plurality of through-hole conductors 16 are formed so as to penetrate the core main surface 12, the core back surface 13, and the conductor layer 163. The through-hole conductor 16 connects and conducts the core main surface 12 side and the core back surface 13 side of the core substrate 11 and is electrically connected to the conductor layer 163. The inside of the through-hole conductor 16 is filled with a closing body 17 such as an epoxy resin. The upper end of the through-hole conductor 16 is electrically connected to a part of the main-surface-side conductor layer 42 on the surface of the main-surface-side resin insulation layer 33, and the lower-end of the through-hole conductor 16 is the back-surface-side resin insulation. It is electrically connected to a part of the back side conductor layer 41 on the lower surface of the layer 34.

  As shown in FIGS. 1 and 2, the core substrate 11 has one rectangular component housing hole 90 in a plan view that opens at the center portion of the core main surface 12 and the center portion of the core back surface 13. Yes. That is, the component accommodation hole 90 is a through hole portion. The outer dimension of the opening of the component accommodation hole 90 is set smaller than the outer dimension of the component mounting area 23. Specifically, the component housing hole 90 is a hole having a substantially square cross section having a length of 11.0 mm × a width of 11.0 mm and a radius or a taper having a radius of 1.5 mm at four corners. Further, the component accommodation hole 90 is disposed immediately below the component mounting region 23 (that is, the IC chip 21) in the semiconductor package 1, and when viewed from the thickness direction of the semiconductor package 1, the opening portion of the component accommodation hole 90 is provided. The amount of protrusion A2 (see FIG. 2) of the IC chip 21 from the four sides constituting each is 0.5 mm.

And in the component accommodation hole 90, the ceramic capacitor 101 (1st inorganic material plate-shaped component) which is a ceramic plate-shaped component is accommodated in the embedded state. The ceramic capacitor 101 is housed in the component housing hole 90 with the capacitor main surface 102 facing the same side as the core main surface 12 of the core substrate 11. As shown in FIGS. 1 and 2, the ceramic capacitor 101 is disposed immediately below the component mounting region 23 in the core substrate 11, and when viewed from the thickness direction of the ceramic capacitor 101, the capacitor main surface 102 is a component. It is located in the mounting area 23. The ceramic capacitor 101 of the present embodiment has a substantially rectangular plate shape in plan view with a length of 9.0 mm, a width of 9.0 mm, and a thickness of 0.4 mm. It is set small. Specifically, the vertical and horizontal lengths of the ceramic capacitor 101 are smaller than the vertical and horizontal lengths of the component mounting region 23. Therefore, the area of the capacitor main surface 102 of the ceramic capacitor 101 is set smaller than the area of the component mounting region 23. In the present embodiment, since the area of the capacitor main surface 102 is 81 mm ² and the area of the component mounting region 23 is 144 mm ² , the area of the capacitor main surface 102 is 0.5625 times the area of the component mounting region 23. Become. The distances between the four side surfaces of the ceramic capacitor 101 and the inner surface of the component housing hole 90 are each set to 1 mm. That is, the outer dimension of the opening of the component housing hole 90 is set larger than the outer dimension of the ceramic capacitor 101.

  As shown in FIG. 1 and the like, the gap between the inner surface of the component accommodation hole 90 and the side surface of the ceramic capacitor 101 is filled with a resin filling portion 92 made of a polymer material (in this embodiment, a thermosetting resin such as epoxy). It has been. The resin filling portion 92 has a function of fixing the ceramic capacitor 101 to the core substrate 11 and absorbing the deformation of the ceramic capacitor 101 and the core substrate 11 in the surface direction and the thickness direction by its own elastic deformation. . 2, 4, and 5, the ceramic capacitor 101 has a substantially square shape in plan view, and has chamfering dimensions of 0.55 mm or more at the four corners (the chamfering dimension is 0.6 mm in this embodiment). Has a chamfer. Thereby, when the resin filling portion 92 is deformed due to a temperature change, the stress concentration on the corner portion of the ceramic capacitor 101 can be alleviated, so that the occurrence of cracks in the resin filling portion 92 can be prevented.

  As shown in FIGS. 1, 3 to 5, etc., the ceramic capacitor 101 of this embodiment is a so-called via array type capacitor. The thermal expansion coefficient of the ceramic sintered body 104 constituting the ceramic capacitor 101 is smaller than the thermal expansion coefficients of the core substrate 11, the main surface side buildup layer 31, and the back surface side buildup layer 32. In this embodiment, the thermal expansion coefficient of the ceramic sintered body 104 is less than 15 ppm / ° C., specifically about 12 to 13 ppm / ° C. The thermal expansion coefficient of the ceramic sintered body 104 refers to an average value of measured values between 30 ° C. and 250 ° C.

  The ceramic sintered body 104 constituting the ceramic capacitor 101 has a plate shape having a capacitor main surface 102 (upper surface in FIG. 1) as a component main surface and a capacitor back surface 103 (lower surface in FIG. 1) as a component back surface. It is a thing. The ceramic sintered body 104 has a structure in which a power supply internal electrode layer 141 and a ground internal electrode layer 142 are alternately stacked via a ceramic dielectric layer 105. The ceramic dielectric layer 105 is made of a sintered body of barium titanate, which is a kind of high dielectric constant ceramic, and functions as a dielectric between the power supply internal electrode layer 141 and the ground internal electrode layer 142. Each of the power supply internal electrode layer 141 and the ground internal electrode layer 142 is a layer formed mainly of nickel, and is disposed in every other layer in the ceramic sintered body 104.

  As shown in FIGS. 1 and 3 to 5, a large number of via holes 130 are formed in the ceramic sintered body 104. These via holes 130 penetrate the ceramic sintered body 104 in the thickness direction and are arranged in an array (for example, a lattice) over the entire surface. In each via hole 130, a plurality of in-capacitor via conductors 131 and 132 that communicate between the capacitor main surface 102 and the capacitor back surface 103 of the ceramic sintered body 104 are formed using nickel as a main material. Each power supply capacitor internal via conductor 131 passes through each power supply internal electrode layer 141 and electrically connects them to each other. Each ground capacitor via conductor 132 passes through each ground internal electrode layer 142 and electrically connects them to each other. Each power source capacitor via conductor 131 and each ground capacitor inner via conductor 132 are arranged in an array as a whole. In the present embodiment, for convenience of explanation, the via conductors 131 and 132 in the capacitor are illustrated in 5 columns × 5 columns, but there are actually more columns.

  As shown in FIG. 3 and the like, a plurality of main surface side power supply electrodes 111 and a plurality of main surface side ground electrodes 112 protrude from the capacitor main surface 102 of the ceramic sintered body 104. . Each main surface side ground electrode 112 is individually formed on the capacitor main surface 102, but may be formed integrally. The main surface side power supply electrode 111 is directly connected to the end surface of the plurality of power supply capacitor internal via conductors 131 on the capacitor main surface 102 side, and the main surface side ground electrode 112 is connected to the plurality of ground capacitor internal electrodes. The via conductor 132 is directly connected to the end surface on the capacitor main surface 102 side.

  On the capacitor back surface 103 of the ceramic sintered body 104, a plurality of back surface side power supply electrodes 121 and a plurality of back surface side ground electrodes 122 project. Each back surface side ground electrode 122 is individually formed on the capacitor back surface 103, but may be formed integrally. The back surface side power supply electrode 121 is directly connected to the end surface on the capacitor back surface 103 side of the plurality of power supply capacitor internal via conductors 131, and the back surface side ground electrode 122 is connected to the plurality of ground capacitor internal via conductors 132. Is directly connected to the end surface on the capacitor back surface 103 side. Therefore, the power supply electrodes 111 and 121 are electrically connected to the power supply capacitor internal via conductor 131 and the power supply internal electrode layer 141, and the ground electrodes 112 and 122 are connected to the ground capacitor internal via conductor 132 and the ground internal electrode layer 142. Is conducting.

  As shown in FIG. 1, the electrodes 111 and 112 on the capacitor main surface 102 side are the via conductor 47, the main surface side conductor layer 42, the via conductor 43, the terminal pad 44, the solder bump 45, and the surface of the IC chip 21. It is electrically connected to the IC chip 21 via the connection terminal 22. On the other hand, the electrodes 121 and 122 on the capacitor back surface 103 side have via conductors 47, back surface side conductor layers 41, via conductors 43, BGA pads 48, and solder bumps 49 with respect to electrodes (contactors) included in a mother board (not shown). It is electrically connected via.

  As shown in FIG. 3 and the like, the electrodes 111, 112, 121, and 122 are made of nickel as a main material, and the surface is covered with a copper plating layer (not shown). The electrodes 111, 112, 121, 122 and the via conductors 131, 132 in the capacitor are disposed directly below the central portion of the IC chip 21. In the present embodiment, the diameters of the electrodes 111, 112, 121, and 122 are set to about 500 μm, and the minimum pitch length is set to about 580 μm.

  For example, when energization is performed from the motherboard side via the electrodes 121 and 122 and a voltage is applied between the power supply internal electrode layer 141 and the ground internal electrode layer 142, for example, positive charges are accumulated in the power supply internal electrode layer 141. For example, negative charges accumulate in the ground internal electrode layer 142. As a result, the ceramic capacitor 101 functions as a capacitor. Further, in the ceramic sintered body 104, the power-source capacitor inner via conductor 131 and the ground capacitor inner via conductor 132 are arranged adjacent to each other. Thereby, the inductance component is reduced.

  Next, a method for manufacturing the semiconductor package 1 of the present embodiment will be described.

  In the preparation step, the intermediate product of the core substrate 11 and the ceramic capacitor 101 are respectively prepared by a conventionally known technique and prepared in advance.

  The intermediate product of the core substrate 11 is manufactured as follows. First, a copper-clad laminate (see FIG. 6) in which a copper foil 162 is attached to both surfaces of a base material 161 having a length of 300 mm × width of 300 mm × thickness of 0.2 mm (or length of 400 mm × width of 400 mm × thickness of 0.2 mm). prepare. Next, the copper foil 162 on both sides of the copper-clad laminate is etched to pattern the conductor layer 163 by, for example, a subtractive method (see FIG. 7). Specifically, after the electroless copper plating, electrolytic copper plating is performed using the electroless copper plating layer as a common electrode. Further, the dry film is laminated, and the dry film is exposed and developed to form a dry film in a predetermined pattern. In this state, unnecessary electrolytic copper plating layer, electroless copper plating layer and copper foil 162 are removed by etching. Thereafter, the dry film is peeled off. Next, after roughening the upper and lower surfaces of the base material 161 and the conductor layer 163, an epoxy resin film (thickness of 80 μm) to which an inorganic filler has been added is attached to the upper and lower surfaces of the base material 161 by thermocompression bonding. Then, the sub-base material 164 is formed (see FIG. 8). Although not shown, after the sub-base material 164 is formed, a conductor layer (for example, a thickness of 50 μm) is formed on the upper surface of the upper sub-base material 164 and the lower surface of the lower sub-base material 164, respectively. Specifically, after performing electroless copper plating on the upper surface of the upper sub-base material 164 and the lower surface of the lower sub-base material 164, an etching resist is formed, and then electrolytic copper plating is performed.

  Next, the laminated body composed of the base material 161 and the sub base material 164 is drilled using a router to form the component accommodation holes 90 at predetermined positions, thereby obtaining an intermediate product of the core substrate 11 (FIG. 9). reference). The intermediate product of the core substrate 11 is a multi-piece core substrate having a structure in which a plurality of regions to be the core substrate 11 are arranged vertically and horizontally along the plane direction.

  The ceramic capacitor 101 is manufactured as follows. That is, a ceramic green sheet is formed, and nickel paste for internal electrode layers is screen printed on the green sheet and dried. As a result, a power internal electrode portion that will later become the power internal electrode layer 141 and a ground internal electrode portion that will be the ground internal electrode layer 142 are formed. Next, the green sheet on which the internal electrode portion for power supply is formed and the green sheet on which the internal electrode portion for ground is formed are stacked, and a pressing force is applied in the sheet stacking direction. Thereby, each green sheet is integrated and a green sheet laminated body is formed.

  Further, a number of via holes 130 are formed through the green sheet laminate using a laser processing machine, and a via conductor nickel paste is filled into each via hole 130 using a paste press-fitting and filling device (not shown). Next, a paste is printed on the upper surface of the green sheet laminate, and the main surface side power supply electrode 111 and the main surface side ground electrode 112 so as to cover the upper end surface of each conductor portion on the upper surface side of the green sheet laminate. Form. Further, a paste is printed on the lower surface of the green sheet laminate, and the back-side power supply electrode 121 and the back-side ground electrode 122 are formed so as to cover the lower end surface of each conductor portion on the lower surface side of the green sheet laminate. .

  Thereafter, the green sheet laminate is dried to solidify the electrodes 111, 112, 121, and 122 to some extent. Next, the green sheet laminate is degreased and fired at a predetermined temperature for a predetermined time. As a result, barium titanate and nickel in the paste are simultaneously sintered to form a ceramic sintered body 104.

  Next, electroless copper plating (thickness of about 10 μm) is performed on each electrode 111, 112, 121, 122 included in the obtained ceramic sintered body 104. As a result, a copper plating layer is formed on each of the electrodes 111, 112, 121, 122, and the ceramic capacitor 101 is completed.

  In the subsequent fixing step, the ceramic capacitor 101 is accommodated in each of the plurality of component accommodation holes 90 using a mounting device (manufactured by Yamaha Motor Co., Ltd.) (see FIG. 10). At this time, the back side opening of each component accommodation hole 90 is sealed with a peelable adhesive tape 171. The adhesive tape 171 is supported by a support base (not shown). The ceramic capacitor 101 is affixed and temporarily fixed to the adhesive surface of the adhesive tape 171.

  Thereafter, the gap between the inner surface of the component housing hole 90 and the side surface of the ceramic capacitor 101 is filled by the resin filling portion 92 (see FIG. 11). Thereafter, when heat treatment is performed, the resin filling portion 92 is cured and the ceramic capacitor 101 is fixed to the core substrate 11. At this point, the adhesive tape 171 is peeled off.

  Next, a buildup layer forming step is performed. In the buildup layer forming step, the main surface side buildup layer 31 is formed on the core main surface 12 and the back surface side buildup layer 32 is formed on the core back surface 13 based on a conventionally known method. Specifically, a photosensitive epoxy resin is deposited on the core main surface 12 and the core back surface 13, and exposure and development are performed, so that blind holes 181 and 182 are formed at positions where the via conductors 47 are to be formed. Resin insulating layers 33 and 34 are formed (see FIG. 12). In place of depositing the photosensitive epoxy resin, an insulating resin or a liquid crystal polymer (LCP) may be deposited. In this case, blind holes 181 and 182 are formed at positions where the via conductors 47 are to be formed by a laser processing machine or the like. In addition, as a liquid crystal polymer, Kuraray Co., Ltd. liquid crystal polymer film (Bexter), Toray Industries, Inc. liquid crystal polymer (LX series), etc. can be used. Next, electrolytic copper plating is performed in accordance with a conventionally known method to form via conductors 47 in the blind holes 181 and 182 and conductor layers 41 and 42 on the resin insulating layers 33 and 34 (FIG. 13). reference).

  Further, a photosensitive epoxy resin is deposited on the resin insulation layers 33 and 34, and exposure and development are performed, whereby the resin insulation layers 35 and 36 having blind holes 183 and 184 at positions where the via conductors 43 are to be formed. Form. Instead of depositing the photosensitive epoxy resin, an insulating resin or a liquid crystal polymer may be deposited. In this case, blind holes 183 and 184 are formed at positions where the via conductors 43 are to be formed by a laser processing machine or the like. Next, electrolytic copper plating is performed according to a conventionally known method to form the via conductors 43 in the blind holes 183 and 184, and the terminal pads 44 are formed on the main surface side resin insulation layer 35, and the back surface side resin is formed. A BGA pad 48 is formed on the insulating layer 36.

  Next, solder resists 37 and 38 are formed by applying and curing a photosensitive epoxy resin on the resin insulating layers 35 and 36. Next, exposure and development are performed with a predetermined mask placed, and the openings 40 and 46 are patterned in the solder resists 37 and 38. Further, solder bumps 45 are formed on the terminal pads 44 and solder bumps 49 are formed on the BGA pads 48. It can be understood that the product in this state is a multi-cavity wiring board having a structure in which a plurality of product regions to be the wiring board 10 are arranged vertically and horizontally along the plane direction. Furthermore, when the multi-cavity wiring board is divided, a large number of wiring boards 10 which are individual products can be obtained simultaneously.

  Next, the IC chip 21 is placed in the component mounting area 23 of the main surface side buildup layer 31 constituting the wiring board 10. At this time, the surface connection terminals 22 on the IC chip 21 side and the solder bumps 45 are aligned. Then, the solder bump 45 is reflowed by heating to a temperature of about 220 ° C. to 240 ° C., thereby joining the solder bump 45 and the surface connection terminal 22 and electrically connecting the wiring substrate 10 side and the IC chip 21 side. Connecting. Further, the gap between the wiring board 10 and the IC chip 21 is filled with the underfill material 20 and subjected to a curing process, and the gap is sealed with resin. In addition, since the main surface side buildup layer 31 is covered with the solder resist 37 with little unevenness, the underfill material 20 flows smoothly on the solder resist 37. As a result, the semiconductor package 1 having a desired structure shown in FIG. 1 is completed.

  During cooling after bonding the IC chip 21, the back-side buildup layer 32 positioned on the core back surface 13 side of the core substrate 11 contracts, but the main surface-side build positioned on the core main surface 12 side of the core substrate 11. The up layer 31 hardly shrinks due to the presence of the IC chip 21 and the underfill material 20. Therefore, the semiconductor package 1 is warped to the back side (see FIG. 15). In particular, when the core substrate 11 is large as in the present embodiment (specifically, when the length of the largest side (vertical, horizontal) of the core substrate 11 is 50 mm), the warpage of the semiconductor package 1 becomes significant. .

  Next, an evaluation method for the reliability of the semiconductor package and the result will be described.

  First, a measurement sample was prepared as follows. As shown in FIG. 16, a core substrate (16) having a thickness of 1 mm, 0.8 mm, 0.6 mm, and 0.4 mm, and vertical and horizontal lengths (external dimensions) of 20 mm, 30 mm, 40 mm, and 50 mm. Prepared). Moreover, the built-in components (4 types) whose vertical and horizontal lengths (external dimensions) were 5 mm, 9 mm, 14 mm, and 18 mm were prepared. Further, IC chips (two types) having a vertical and horizontal length (external dimensions) of 10 mm or 16 mm were prepared. And while incorporating the built-in components in the prepared core substrate, on the wiring substrate formed with build-up layers on the front and back surfaces of the core substrate, a plurality of types of semiconductor packages on which the prepared IC chip is mounted are manufactured, These were used as measurement samples. The built-in component is a ceramic capacitor similar to the present embodiment.

  Next, a thermal shock test was performed on each measurement sample. Specifically, the step of heating the measurement sample to 128 ° C. and the step of cooling the measurement sample to −57 ° C. were alternately performed 2000 times. Thereafter, the state of the measurement sample was observed, and it was confirmed whether or not there was an abnormality in the built-in component or the joint between the built-in component and the buildup layer.

  As a result of this observation, as shown in FIG. 16, when the external dimension of the built-in component is larger than the external dimension of the IC chip, and the thickness of the core substrate is 0.6 mm or 0.4 mm In addition, abnormalities (cracks and delamination) are likely to occur in built-in components and joints. Also, even when the external dimensions of the built-in components are larger than the external dimensions of the IC chip, if the thickness of the core substrate is 1 mm or 0.8 mm, no abnormality may occur. When the dimension was 40 mm or 50 mm, an abnormality occurred in the built-in component or the joint. In addition, when abnormality occurred, the measurement sample warped significantly.

  Therefore, when the thickness of the core substrate is 0.6 mm or less, or when the outer dimension of the core substrate is 40 mm or more, if the outer dimension of the built-in component is smaller than the outer dimension of the IC chip, It was found that the occurrence of abnormalities at the joint could be prevented.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) According to the semiconductor package 1 of the present embodiment, even when the warp of the wiring substrate 10 becomes significant due to the length of the largest side (vertical, horizontal) of the core substrate 11 being 40 mm or more, ceramic Since the capacitor 101 is arranged immediately below the component mounting area 23 that is not easily affected by warpage and is set to an outer dimension smaller than the outer dimension of the component mounting area 23, stress is less likely to concentrate. As a result, the ceramic capacitor 101 and the joint portions (near the electrodes 111, 112, 121, and 122) between the ceramic capacitor 101 and the buildup layers 31 and 32 are not easily broken, and the reliability of the semiconductor package 1 is increased. . Therefore, even if a ceramic capacitor using barium titanate, which is generally considered to be brittle, is used as the ceramic capacitor 101, the ceramic capacitor 101 is not easily destroyed.

  (2) In this embodiment, since the ceramic capacitor 101 is disposed immediately below the IC chip 21 mounted in the component mounting region 23, the wiring connecting the ceramic capacitor 101 and the IC chip 21 is shortened, and the inductance component of the wiring Is prevented from increasing. Therefore, the switching noise of the IC chip 21 due to the ceramic capacitor 101 can be reliably reduced, and the power supply voltage can be reliably stabilized. In addition, since noise entering between the IC chip 21 and the ceramic capacitor 101 can be suppressed to a very low level, high reliability can be obtained without causing malfunction such as malfunction.

  In addition, you may change embodiment of this invention as follows.

  In the semiconductor package 1 of the above embodiment, the ceramic capacitor 101 is built in the core substrate 11, and the silicon IC chip 21 is mounted on the component mounting region 23. It was configured by setting it smaller than the external dimensions. However, as shown in FIGS. 17 to 19, a silicon IC chip 191 is built in the core substrate 11, and a ceramic capacitor 192 is mounted on the component mounting region 23. The semiconductor packages 193, 198, and 199 may be smaller than the external dimensions of the capacitor 192. In other words, the IC chip 191 may be used as the “first inorganic material plate-like component” and the ceramic capacitor 192 may be used as the “second inorganic material plate-like component”. In this way, even if an IC chip using silicon (Si), which is generally considered to be brittle, or gallium arsenide (GaAs) is used as the IC chip 191, the IC chip 191 is not easily destroyed.

  As shown in FIGS. 18 and 19, a mounting area 212 is set on the front surface 211 of the back-side buildup layer 32, and “surface mounted components such as a chip capacitor 213 and a register (not shown) are provided on the mounting area 212. ] May be installed. For example, the chip capacitor 213 has a structure in which power supply internal electrode layers and ground internal electrode layers are alternately stacked via dielectric layers. A power supply electrode 214 connected to the power supply internal electrode layer and a ground electrode 215 connected to the ground internal electrode layer are provided on a pair of side surfaces facing each other in the chip capacitor 213. .

  As shown in FIGS. 18 and 19, the chip capacitor 213 (and the mounting region 212) is preferably arranged at a convenient location when the wiring 210 extending from the upper surface side of the IC chip 191 is extended downward. . In this way, the wiring 210 (in FIG. 18, via conductors 43 and 47, the main surface side conductor layer 42, the electrical connection between the surface connection terminal 22 of the IC chip 191 and the power supply electrode 214 of the chip capacitor 213) The wiring composed of the through-hole conductor 16, the back-side conductor layer 41, the pad 216, and the solder bump 217) is shortened, and an increase in the inductance component of the wiring is prevented. Further, the chip capacitor 213 is formed on the outline L1 of the IC chip 191, the outline L2 of the ceramic capacitor 192, and in the housing portion of the IC chip 191 when the wiring board 10 is viewed from the front surface 211 side of the backside buildup layer 32. It is preferable to be mounted at a position avoiding a corresponding portion on an extension line of a wall surface (not shown). That is, it is preferable that the chip capacitor 213 is mounted at a position that avoids a location where stress is concentrated on the front surface 211 of the back surface side buildup layer 32. In this way, the chip capacitor 213 and the joint between the chip capacitor 213 and the back-side buildup layer 32 are not easily broken, and the reliability of the wiring board 10 is increased. Note that the chip capacitor 213 can be mounted at any position on the surface 211 as long as it avoids the corresponding positions on the outlines L1 and L2 and the extension lines. It is preferably mounted between the line L2. In this way, the wiring 210 is more reliably shortened, and an increase in the inductance component of the wiring is more reliably prevented.

  18 has a signal wiring 218 for sending signals from the IC chip 191 to an electronic component (not shown) mounted on the surface 39 of the main surface side buildup layer 31. You may have. The signal wiring 218 is a wiring including the main surface side conductor layer 42, via conductors 43 and 47, and terminal pads 44.

  As shown in FIG. 19, a DRAM made of silicon is formed on a component mounting portion 219 disposed on the back side of the component mounting region 23 (specifically, the front surface 211 of the back side buildup layer 32) in the wiring board 10. A semiconductor package 199 on which the element 220 is mounted may be used. Then, the outer dimension of the component mounting portion 219 may be set smaller than the outer dimension of the component mounting area 23 and further set smaller than the outer dimension of the IC chip 191. That is, the DRAM element 220 may be used as a “third inorganic material plate-like component”. With such a configuration, even if the warp of the wiring substrate 10 becomes significant due to the length of the largest side of the core substrate 11 being 50 mm, the component mounting portion 219 has the outer dimensions of the component mounting region 23. Since the outer dimension is set to be smaller than the outer dimension of the IC chip 191, the stress is more difficult to concentrate. As a result, the reliability of the wiring substrate 10 is improved because the DRAM element 220 and the joint between the DRAM element 220 and the back-side buildup layer 32 are not easily destroyed.

  The area of the component mounting portion 219 is preferably set to be 0.25 times or more and less than 1.0 times the area of the IC chip 191. That is, when viewed from the thickness direction of the wiring substrate 10, the component mounting portion 219 is preferably located within the mounting area of the IC chip 191. If the area of the component mounting portion 219 is set to be less than 0.25 times the area of the IC chip 191, the component mounting portion 219 becomes too small, so that the high performance of the DRAM element 220 mounted on the component mounting portion 219 is increased. It becomes difficult to plan. On the other hand, when the area of the component mounting part 219 is set to 1.0 times or more of the area of the IC chip 191, the external dimension of the component mounting part 219 tends to be larger than the external dimension of the IC chip 191. As a result, a large force is applied to the vicinity of the DRAM element 220 mounted on the component mounting portion 219, and the circuit board 10 is likely to be destroyed, and the reliability of the wiring board 10 is lowered.

  Further, when the component mounting portion 219 and the IC chip 191 are square in plan view, the length of one side of the component mounting portion 219 is larger than the dimensional tolerance of the IC chip 191 and the length of one side of the IC chip 191. More preferably, it is set smaller by the sum of the position tolerance of the mounting position. If the dimensional tolerance A of the IC chip 191 is 50 μm, the positional tolerance B of the IC chip 191 is 100 μm, and the length C of one side of the IC chip 191 is 20 mm, the length D of one side of the component mounting portion 219 is ( A + B + D) ≦ 20 mm, and D = 19.85 mm or less. In this case, the area of the component mounting part 219 is 0.985 times or less of the area of the IC chip 191. When D = 18 mm, the area of the component mounting portion 219 is 0.81 times or less the area of the IC chip 191.

  In the semiconductor package 1 of the above embodiment, the ceramic capacitor 101 is built in the core substrate 11, and the silicon IC chip 21 is mounted on the component mounting region 23. It was configured by setting it smaller than the external dimensions. However, as shown in FIG. 20, a silicon IC chip 194 different from the IC chip 21 on the component mounting area 23 is built in the core substrate 11, and the external dimensions of the IC chip 194 are changed to the external dimensions of the IC chip 21. The semiconductor package 195 may be set smaller than that. In other words, the IC chip 194 may be used as the “first inorganic material plate-like component”. In this way, even if an IC chip using a material that is generally considered brittle is used as the IC chip 194, the IC chip 194 is less likely to be destroyed.

  The semiconductor package 1 of the above embodiment is configured by mounting the IC chip 21 on the component mounting region 23 and setting the outer dimension of the ceramic capacitor 101 to be smaller than the outer dimension of the IC chip 21. However, as shown in FIG. 21, a semiconductor in which a ceramic interposer 196 having an IC chip 21 mounted thereon is mounted on a component mounting area 23, and the external dimensions of the ceramic capacitor 101 are set smaller than the external dimensions of the interposer 196. A package 197 may be used. That is, the interposer 196 may be used as a “second inorganic material plate-like component”.

  In the above embodiment, the gap between the inner surface of the component accommodation hole 90 and the side surface of the ceramic capacitor 101 is filled with the resin filling portion 92. However, as shown in FIG. It may be filled with a part of 33.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) A core substrate having a core main surface and a core back surface, formed with a component receiving hole that opens at least on the core main surface side, and having a largest side length of 40 mm or more, a component main surface, and a component A ceramic plate-like component housed in the component housing hole with the back surface and the core main surface and the component main surface facing the same side, a main surface side interlayer insulating layer, and a main surface side conductor layer On the main surface of the core, a main surface side wiring laminated portion in which a component mounting area on which a second inorganic material plate-like component can be mounted is set on the surface, and a back surface side interlayer insulating layer And a back surface side wiring laminated portion formed by laminating a back surface side conductor layer on the back surface of the core, and the ceramic plate-like component is disposed immediately below the component mounting region, and the ceramic plate-like component The external dimensions of the product are set smaller than the external dimensions of the component mounting area. Wiring board, characterized in that it is.

  (2) A semiconductor package having a structure in which a gap between a wiring board and a second inorganic material plate-like component mounted thereon is sealed with a resin material, the wiring board including a core main surface and a core back surface And a core substrate that has a component receiving hole that opens at least on the core main surface side, has a largest side length of 40 mm or more, and is warped on the core back surface side, a component main surface, and a component A first inorganic material plate-shaped component housed in the component housing hole in a state having a back surface, with the core main surface and the component main surface facing the same side, a main surface side interlayer insulating layer, and a main surface A main-surface-side wiring laminated portion in which a surface-side conductor layer is laminated on the core main surface, and a component-mounting area for mounting the second inorganic material plate-like component is set on the surface thereof; A back side formed by laminating a back side interlayer insulating layer and a back side conductor layer on the core back side The first inorganic material plate-like component is disposed immediately below the component mounting region, and the outer dimension of the first inorganic material plate-like component is the outer shape of the component mounting region. A semiconductor package characterized by being set smaller than a dimension.

  (3) A semiconductor package having a structure in which a gap between a wiring board and a second inorganic material plate-like component mounted thereon is sealed with a resin material, the wiring board including a core main surface and a core back surface A core substrate having a component receiving hole that opens at least on the core main surface side, the length of the largest side being 40 mm or more, a component main surface, and a component back surface, and the core main surface And a ceramic plate-like component housed in the component housing hole with the component main surface facing the same side, a main surface side interlayer insulating layer and a main surface side conductor layer are laminated on the core main surface The main surface side wiring laminated portion in which the component mounting region for mounting the second inorganic material plate-shaped component is set on the surface, the back surface side interlayer insulating layer and the back surface side conductor layer A backside wiring laminate formed on the backside of the core, and the ceramic With manufacturing plate-like part is located directly below the component mounting region, the semiconductor package external dimensions of the ceramic plate-like part which is characterized in that is set smaller than the outside dimension of the component mounting region.

  (4) A core substrate having a core main surface and a core back surface, formed with a component receiving hole that opens at least on the core main surface side, and having a maximum side length of 40 mm or more, a component main surface, and a component A first inorganic material plate-shaped component housed in the component housing hole in a state having a back surface, with the core main surface and the component main surface facing the same side, a main surface side interlayer insulating layer, and a main surface A main-surface-side wiring laminated portion in which a surface-side conductor layer is laminated on the core main surface, and a component mounting area on which a second inorganic material plate-like component can be mounted is set on the surface; A back side wiring laminated portion formed by laminating a side interlayer insulating layer and a back side conductor layer on the back side of the core, and the first inorganic material plate-like component is disposed immediately below the component mounting region. In addition, the outer dimension of the first inorganic material plate-like component is equal to the outer dimension of the component mounting region. Wiring board is also set to be smaller, the outer dimension of the opening of the component accommodation hole, characterized in that it is set larger than the outside dimension of the first inorganic material-made plate-like component.

  (5) A core substrate having a core main surface and a core back surface, formed with a component accommodation hole that opens at least on the core main surface side, and having a maximum side length of 40 mm or more, a component main surface, and a component A first inorganic material plate-shaped component housed in the component housing hole in a state having a back surface, with the core main surface and the component main surface facing the same side, a main surface side interlayer insulating layer, and a main surface A main-surface-side wiring laminated portion in which a surface-side conductor layer is laminated on the core main surface, and a component mounting area on which a second inorganic material plate-like component can be mounted is set on the surface; A side-layer insulating layer and a back-side conductor layer are laminated on the back side of the core, and a component mounting portion on which a third inorganic material plate-like component made of a silicon-based material can be mounted is set on the surface. The first inorganic material plate-like component is the component mounting region. The component mounting portion is disposed immediately below the component mounting area on the wiring board, and the outer dimension of the first inorganic material plate-shaped component is smaller than the outer dimension of the component mounting area. The wiring board is characterized in that the outer dimension of the component mounting portion is set smaller than the outer dimension of the component mounting area and the outer dimension of the first inorganic material plate-shaped component.

  (6) A core substrate having a core main surface and a core back surface, formed with a component receiving hole that opens at least on the core main surface side, and having a largest side length of 40 mm or more, a component main surface, and a component A first inorganic material plate-shaped component housed in the component housing hole in a state having a back surface, with the core main surface and the component main surface facing the same side, a main surface side interlayer insulating layer, and a main surface A main-surface-side wiring laminated portion in which a surface-side conductor layer is laminated on the core main surface, and a component mounting area on which a second inorganic material plate-like component can be mounted is set on the surface; A side-layer insulating layer and a back-side conductor layer are stacked on the back side of the core, and a component mounting portion on which a third inorganic material plate-shaped component made of a silicon-based material can be mounted, and a surface-mounted component mounted A backside wiring laminated portion having a possible mounting area set on the front surface, and The inorganic material plate-shaped component is disposed immediately below the component mounting region, the component mounting portion is disposed on the back side of the component mounting region on the wiring board, and the first inorganic material plate-shaped component An outer dimension is set smaller than an outer dimension of the component mounting area, an outer dimension of the component mounting portion is set smaller than an outer dimension of the component mounting area, and the mounting area is made of the first inorganic material plate. A wiring board characterized in that it is electrically connected to a shaped part via wiring.

  (7) A core substrate having a core main surface and a core back surface, formed with a component receiving hole that opens at least on the core main surface side, and having a maximum side length of 40 mm or more, a component main surface, and a component A first inorganic material plate-shaped component housed in the component housing hole in a state having a back surface, with the core main surface and the component main surface facing the same side, a main surface side interlayer insulating layer, and a main surface A main-surface-side wiring laminated portion in which a surface-side conductor layer is laminated on the core main surface, and a component mounting area on which a second inorganic material plate-like component can be mounted is set on the surface; A back side wiring laminated portion formed by laminating a side interlayer insulating layer and a back side conductor layer on the back side of the core, and the first inorganic material plate-like component is disposed immediately below the component mounting region. In addition, the outer dimension of the first inorganic material plate-like component is equal to the outer dimension of the component mounting region. Is set to be small, and on the surface of the back-side wiring laminated portion, the extension line on the side surface of the first inorganic material plate-like component and the extension line on the side surface of the second inorganic material plate-like component are avoided. A wiring board characterized in that a surface mounting component is mounted at a position.

1 is a schematic cross-sectional view showing a semiconductor package of an embodiment embodying the present invention. The schematic plan view which shows the upper surface of a semiconductor package. The schematic sectional drawing which shows a ceramic capacitor. Schematic explanatory drawing for demonstrating the connection in the inner layer of a ceramic capacitor. Schematic explanatory drawing for demonstrating the connection in the inner layer of a ceramic capacitor. Explanatory drawing of the manufacturing method of a semiconductor package. Explanatory drawing of the manufacturing method of a semiconductor package. Explanatory drawing of the manufacturing method of a semiconductor package. Explanatory drawing of the manufacturing method of a semiconductor package. Explanatory drawing of the manufacturing method of a semiconductor package. Explanatory drawing of the manufacturing method of a semiconductor package. Explanatory drawing of the manufacturing method of a semiconductor package. Explanatory drawing of the manufacturing method of a semiconductor package. Explanatory drawing of the manufacturing method of a semiconductor package. 1 is a schematic cross-sectional view showing a semiconductor package. The table | surface which shows the result of a thermal shock test. The schematic sectional drawing which shows the semiconductor package of other embodiment. The schematic sectional drawing which shows the semiconductor package of other embodiment. The schematic sectional drawing which shows the semiconductor package of other embodiment. The schematic sectional drawing which shows the semiconductor package of other embodiment. The schematic sectional drawing which shows the semiconductor package of other embodiment. The schematic sectional drawing which shows the semiconductor package of other embodiment. The schematic sectional drawing which shows the semiconductor package in a prior art. The schematic sectional drawing for demonstrating the problem of a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,193,195,197,198,199 ... Semiconductor package 10 ... Wiring board 11 ... Core board 12 ... Core main surface 13 ... Core back surface 20 ... Underfill material 21 as resin material ... 2nd inorganic material plate shape IC chip 23 as component and semiconductor integrated circuit chip ... component mounting region 31 ... main surface side buildup layer 32 as main surface side wiring laminated portion ... back surface side buildup layers 33, 35 as main surface side wiring laminated portion. Main surface side resin insulation layers 34, 36 as surface side interlayer insulation layers ... Back surface side resin insulation layers 39 as back surface side interlayer insulation layers ... Surface 41 of main surface side wiring laminated portion ... Back surface side conductor layer 42 ... Main surface side Conductor layer 90... Component housing hole 101... Ceramic capacitor 102 as a first inorganic material plate-shaped component... Capacitor main surface 103 as component main surface. ... Capacitor via conductor 132 for power supply as via conductor in capacitor ... Capacitor via conductors 191 and 194 for ground as via conductors in capacitor ... IC chip 192 as plate component made of first inorganic material ... Second inorganic Ceramic capacitor 196 as a material-made plate-shaped component ... Interposer 211 as a second inorganic-material-made plate-shaped component ... Surface 213 of the back-side wiring laminated portion ... Chip capacitor 219 as a surface-mounted component ... Component mounting portion 220 ... Third DRAM element L1 as a plate-like component made of inorganic material ... Outline line L2 of plate component made of first inorganic material ... Outline line of plate-like component made of second inorganic material

Claims (15)

A core substrate having a core main surface and a core back surface, formed with a component housing hole that opens at least on the core main surface side, and having a length of the largest side of 40 mm or more;
A first inorganic material plate-like component housed in the component housing hole in a state having a component main surface and a component back surface, with the core main surface and the component main surface facing the same side;
A main surface side interlayer insulating layer and a main surface side conductor layer are laminated on the core main surface, and a component mounting region in which a second inorganic material plate-shaped component can be mounted is set on the surface. A surface-side wiring laminate,
A back side wiring laminated portion formed by laminating a back side interlayer insulating layer and a back side conductor layer on the back side of the core, and the first inorganic material plate-like component is disposed immediately below the component mounting region. In addition, an external dimension of the first inorganic material plate-like component is set smaller than an external dimension of the component mounting region.   2. The wiring board according to claim 1, wherein an area of the first inorganic material plate-like component is 0.25 times or more and less than 1 time of an area of the component mounting region.   The wiring board according to claim 1, wherein an outer dimension of the opening of the component housing hole is set smaller than an outer dimension of the component mounting region.   2. The thermal expansion coefficient of the first inorganic material plate-like component is smaller than the thermal expansion coefficients of the core substrate, the main surface side wiring laminated portion, and the back surface side wiring laminated portion. 4. The wiring board according to any one of 3 above.   5. The wiring board according to claim 1, wherein the first inorganic plate-shaped component is a via array type ceramic capacitor having a plurality of via conductors in the capacitor. On the surface of the back side wiring laminated portion, a component mounting portion capable of mounting a third inorganic material plate-shaped component made of a silicon-based material is set,
The component mounting part is disposed on a back side of the component mounting area on the wiring board, and an outer dimension of the component mounting part is set smaller than an outer dimension of the component mounting area. The wiring board according to any one of 1 to 5.   When the wiring board is viewed from the front surface side of the back surface side wiring laminated portion on the surface of the back surface side wiring laminated portion, on the outline line of the first inorganic material plate-like component, and the second inorganic material The wiring board according to any one of claims 1 to 6, wherein a surface mounting component is mounted at a position avoiding a corresponding portion on the outline of the plate-like component. A semiconductor package having a structure in which a gap between a wiring board and a second inorganic material plate-like component mounted thereon is sealed with a resin material,
The wiring board is
A core substrate having a core main surface and a core back surface, formed with a component housing hole that opens at least on the core main surface side, and having a length of the largest side of 40 mm or more;
A first inorganic material plate-like component housed in the component housing hole in a state having a component main surface and a component back surface, with the core main surface and the component main surface facing the same side;
A main surface side interlayer insulating layer and a main surface side conductor layer are laminated on the core main surface, and a component mounting region for mounting the second inorganic material plate-shaped component is set on the surface thereof. A main-surface-side wiring laminated portion,
A back side wiring laminated portion formed by laminating a back side interlayer insulating layer and a back side conductor layer on the core back side,
The first inorganic material plate-like component is disposed immediately below the component mounting region, and the outer dimension of the first inorganic material plate-like component is set smaller than the outer dimension of the component mounting region. A semiconductor package characterized by comprising:   9. The semiconductor package according to claim 8, wherein an area of the first inorganic material plate-like component is 0.25 times or more and less than 1 time of an area of the component mounting region.   10. The semiconductor package according to claim 8, wherein an outer dimension of the opening of the component housing hole is set smaller than an outer dimension of the component mounting region.   The thermal expansion coefficient of the first inorganic material plate-like component is smaller than the thermal expansion coefficients of the core substrate, the main-surface-side wiring laminated portion, and the back-surface-side wiring laminated portion. The semiconductor package according to any one of 10.   12. The semiconductor package according to claim 8, wherein the first inorganic plate-shaped component is a via array type ceramic capacitor having a plurality of via conductors in the capacitor.   13. The semiconductor package according to claim 8, wherein the second inorganic material plate-like component is a semiconductor integrated circuit chip. On the surface of the back side wiring laminated portion, a component mounting portion capable of mounting a third inorganic material plate-shaped component made of a silicon-based material is set,
The component mounting part is disposed on a back side of the component mounting area on the wiring board, and an outer dimension of the component mounting part is set smaller than an outer dimension of the component mounting area. 14. The semiconductor package according to any one of 8 to 13.   When the wiring board is viewed from the front surface side of the back surface side wiring laminated portion on the surface of the back surface side wiring laminated portion, on the outline line of the first inorganic material plate-like component, and the second inorganic material The semiconductor package according to any one of claims 8 to 14, wherein a surface-mounted component is mounted at a position avoiding a corresponding portion on the outline of the plate-like component.

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