JP2004072124A - Wiring board with built-in electric element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a wiring board in which an electric element such as a capacitor is built in an insulating substrate thereof, which has superior mountability and mounting reliability even when a semiconductor device or the like is mounted on the substrate surface by flip-chip bonding, and superior reliability of the connection between the built-in electric element and the wiring circuit layer provided to the wiring board. <P>SOLUTION: The insulating substrate 1 comprises a layered structure of a first insulating layer 1a including a mixture of thermosetting resin and inorganic filler and a second insulating layer 1b including a fiber body impregnated with the thermosetting resin. The first insulating layer 1a builds the electric element into itself, the second insulating layer 1b is arranged on the top surface of the insulating substrate 1, and the difference of thermal expansion coefficient between the electric element and the first insulating layer 1a is equal to or less than 7×10<SP>-6</SP>/°C and the difference of thermal expansion coefficient between the first insulating layer 1a and the first insulating layer 1b is equal to or less than 8.6×10<SP>-6</SP>/°C. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a wiring board with a built-in electric element in which an electronic component such as an LSI chip can be mounted on the surface and an electric element such as a capacitor is built in an insulating substrate.

In recent years, with the spread of communication devices, electronic devices that require high-speed operation have been widely used, and with this, packages capable of high-speed operation have been required. In order to perform such a high-speed operation, it is necessary to reduce the inductance of the passive electric element and the wiring part by incorporating a passive electric element such as a capacitor inside the insulating substrate.

As a method for dealing with such a problem, for example, Japanese Patent Application Laid-Open No. H11-220262 discloses a module with a built-in circuit component and a method for manufacturing the same, in which all insulating layers constituting an insulating substrate include an inorganic filler and a thermosetting resin. A wiring board formed from a mixture has been proposed.
JP-A-11-220262

However, in the circuit board disclosed in JP-A-11-220262, the absolute strength of the board is low, and the rigidity is low. For example, when a semiconductor element is mounted on the surface of the wiring board by a flip chip method, the wiring board is deformed. However, there is a problem that the flip chip portion is warped.

As a method of increasing the strength, it has been proposed to form the insulating substrate by a so-called prepreg obtained by impregnating a glass cloth with a resin. However, the fibrous body is made of a very limited material such as glass, and as a result, the thermal expansion difference between the fibrous body and an electric element such as a capacitor element incorporated in the prepreg may be large. The connectivity with the wiring circuit layer in the wiring board changes, or the wiring board is deformed by the stress generated due to the difference in thermal expansion between the two, so that the flatness of the wiring board surface is lost and the semiconductor element is flip-chip mounted. There was a problem that it could not be implemented.

Therefore, the present invention has excellent mountability and mounting reliability even when a semiconductor element or the like is flip-chip mounted on a surface of a wiring board in which an electric element such as a capacitor is built inside an insulating substrate. It is another object of the present invention to obtain a wiring board with a built-in electric element which has excellent connection reliability between the built-in electric element and a wiring circuit layer provided on the wiring board.

The present inventors have made the above-mentioned problems in a wiring board with a built-in electric element including a mounting surface for mounting an electronic component on a surface of the insulating substrate while incorporating an electric element such as a capacitor element inside the insulating substrate. As a result of repeated investigations, the first insulating layer made of a mixture of a thermosetting resin and an inorganic filler and the second insulating layer made by impregnating a fibrous body with a thermosetting resin were obtained. Forming a void in the first insulating layer, incorporating an electric element in the void, and disposing the second insulating layer on the outermost surface of the insulating substrate; The difference in thermal expansion between the electric element and the first insulating layer is set to 7 × 10 ⁻⁶ / ° C. or less, and the difference in thermal expansion coefficient between the first insulating layer and the second insulating layer is 8.6 ×. The above object is achieved by controlling the temperature to 10 ⁻⁶ / ° C. or less.

That is, by incorporating the electric element in the first insulating layer made of a mixture of the thermosetting resin and the inorganic filler, the insulator can easily change the thermal expansion coefficient of the insulating layer depending on the type and amount of the filler. Therefore, it is possible to easily match the thermal expansion coefficient of the built-in electric element. Therefore, it is possible to suppress the generation of stress due to the difference in thermal expansion, and to improve the deformation of the wiring board and the connection reliability between the wiring circuit layer of the wiring board and the electric element.

However, if the insulating substrate is composed of only the first insulating layer made of a mixture of the thermosetting resin and the inorganic filler, the strength of the entire substrate is low, and particularly the flatness of the surface is easily damaged. Therefore, according to the present invention, a second insulating layer formed by impregnating a fibrous body with a thermosetting resin is laminated on the upper or lower surface of the insulating layer made of a mixture of the thermosetting resin and the inorganic filler. By doing so, it is possible to obtain a wiring board which can suppress the reduction in strength due to the first insulating layer, improve the flatness of the surface of the wiring board, and can be sufficiently applied even when flip-chip mounting a semiconductor element or the like. it can.

In particular, in the above configuration, it is preferable that the first insulating layer contains a thermosetting resin in an amount of 30 to 65% by volume and an inorganic filler in an amount of 35 to 70% by volume. ₂ , at least one selected from Al ₂ O ₃ , AlN and Si ₃ N ₄ .

As the thermosetting resin in the first insulating layer and the second insulating layer, at least one selected from a polyphenylene ether-based resin, an epoxy-based resin, and a cyanate-based resin is preferably used.

Further, by incorporating a multilayer ceramic capacitor as the electric element, signal noise can be removed.

{Circle around (1)} The first insulating layer and / or the second insulating layer are formed with via-hole conductors filled with metal powder, whereby the size of the wiring board can be reduced.

That is, as described above, according to the present invention, in a wiring board having a built-in electric element such as a capacitor element, a high-strength prepreg is used for an insulating layer in a surface layer portion on which a semiconductor element and the like are mounted. By using an insulating layer consisting of a mixture of inorganic filler and thermosetting resin for the inner insulating layer to be built in, the semiconductor element is flip-chip mounted on the surface layer of the wiring board, and at the same time, the capacitor element is built in the inner insulating layer Thus, a low-inductance multilayer wiring board can be manufactured.

Embodiment 1 A detailed description will be given based on FIG. 1 showing a schematic sectional view of an embodiment of a wiring board with a built-in electric element of the present invention. In the wiring board A of the present invention, a cavity 2 is formed inside an insulating substrate 1, and a capacitor element 3 is built in the cavity 2. A semiconductor element 4 is mounted as an electronic component directly above the wiring element A on which the capacitor element 3 is built.

In the present invention, the insulating substrate 1 of the wiring board A is configured by a first insulating layer (hereinafter, simply referred to as a CPC layer) 1a in which a portion in which the capacitor element 3 is built is made of a mixture of a thermosetting resin and an inorganic filler. At least one or more layers of fibrous material are provided on the front side of the insulating substrate 1 on which the semiconductor element 4 is mounted and / or the back side on which connection terminals such as solder ball pads and connection pins are provided. A second insulating layer (hereinafter, simply referred to as a prepreg layer) 1b impregnated with a curable resin is formed by lamination.

(CPC layer)
The CPC layer 1a containing the capacitor element 3 is made of a composite of a thermosetting resin and an inorganic filler. Examples of the inorganic filler include SiO ₂ , Al ₂ O ₃ , AlN, and Si ₃ N _4. At least one member selected from the group of can be suitably used. The inorganic filler is desirably contained at a rate of 35 to 70% by volume based on the thermosetting resin, and the average particle diameter of the inorganic filler to be used is optimally in the range of 1.0 to 20 μm. The CPC layer has a thickness of about 50 to 150 μm per layer, and is appropriately laminated according to the size of an electric element such as a built-in capacitor element, and is formed to a predetermined thickness.

Further, this CPC layer makes use of the advantage that the coefficient of thermal expansion can be arbitrarily controlled, and has a thermal expansion difference of −65 to 250 ° C. with a built-in electric element of 7 × 10 ⁻⁶ / ° C. or less, particularly 5.5 or less. It is necessary to. This is because, even if an electric element is incorporated in the CPC layer, if the difference in thermal expansion is large, the stress generated by the difference in thermal expansion will increase, thereby making it difficult to mount the flip chip due to deformation of the wiring board and the like. This is because the connectivity with the wiring circuit layer in the wiring board is impaired, and characteristics due to the electric element cannot be obtained.

(Prepreg layer)
On the other hand, the prepreg layer 1b is made of a fibrous body and a thermosetting resin impregnated in the fibrous body. The thickness per layer is about 150 μm or less. The conductive resin has a ratio of 60 to 40% by volume.

少 な く と も At least one selected from the group consisting of glass and aramid resin is used as the fibrous body. The fiber diameter of the fibrous body is preferably 10 μm or less in order to increase the strength.

The fibrous body may be uniformly dispersed, but is desirably made of a woven or nonwoven fabric in order to increase the rigidity of the substrate.

熱 As the thermosetting resin contained in the CPC layer and the prepreg layer, at least one selected from the group consisting of an APPE (allylated polyphenylene ether) resin, an epoxy resin and a cyanate resin is preferable. The APPE resin is particularly preferable because it has a low relative dielectric constant, a low dielectric loss, a low water absorption, and a high glass transition point, and particularly has high heat resistance. Further, the mixture may contain a dispersing agent or a coupling agent to improve the wettability with the filler.

The capacitor element 3 incorporated in the CPC layer preferably has two or more positive electrodes and two or more negative electrodes. One example of such a capacitor element 3 is shown in the schematic perspective view of FIG.

The capacitor element 3 shown in FIG. 2 is a laminated ceramic capacitor composed of a rectangular parallelepiped formed by laminating ceramic dielectric layers 5 containing BaTiO ₃ as a main component. On the outer surface, four positive electrodes 6a and four negative electrodes 6b are independently and evenly formed. In the capacitor element of FIG. 2A, the negative electrode 6b is formed at the center of each side, and the positive electrode 6a is formed at each corner.

Also, between the ceramic dielectric layers 5 of the laminate, a positive electrode internal electrode 7a having a pattern as shown in FIG. 2B and a negative electrode internal electrode 7b having a pattern as shown in FIG. Are alternately formed, and the positive electrode internal electrode 7a is electrically connected to the positive electrode 6a, and the negative electrode internal electrode 7b is electrically connected to the negative electrode 6b at the end face of the laminate.

On the other hand, the first conductor layer 8 and the second conductor layer 9 are formed on the prepreg layer 1b between the capacitor component 3 having the above structure and the surface of the electronic component mounting surface embedded in the CPC layer 1a. ing. Then, as shown in the pattern diagram of FIG. 3A, the first conductor layer 8 vertically penetrates the four positive electrodes 6a of the capacitor element 3 and the insulating layer directly above the positive electrodes 6a. It is electrically connected via the formed via-hole conductor 10.

Similarly, as shown in the pattern diagram of FIG. 3B, the second conductor layer 9 is formed by vertically connecting the four negative electrodes 6b of the capacitor element 3 and the insulating layer directly above the negative electrodes 6b. They are electrically connected via via-hole conductors 11 formed therethrough. The first conductor layer 8 has an opening 12 in which a conductor is formed so as not to contact the via-hole conductor 11 connecting the negative electrode 6b and the second conductor layer 9.

In the first conductor layer 8 connected to the positive electrode 6a of the capacitor element 3, a via-hole conductor 13 is further formed over the electronic component mounting surface. Similarly, a via-hole conductor 15 is formed on the second conductor layer 9 connected to the negative electrode 6b of the capacitor element 3 so as to reach the electronic component mounting surface, and is provided on the substrate surface. Connected to the negative electrode land 16.

The bumps of the semiconductor element 4 mounted on the surface of the insulating substrate 1 are electrically connected to the positive electrode lands 14 and the negative electrode lands 16.

In the wiring board with a built-in electric element of the present invention, the difference in thermal expansion coefficient between the first insulating layer and the second insulating layer constituting the substrate is 8.6 × 10 ⁻⁶ / ° C. or less, and particularly, 2. It is desirable to be 3 × 10 ⁻⁶ / ° C. or less.

(Production method)
Next, a method for manufacturing the wiring board with a built-in electric element of the present invention will be described. First, an uncured insulating sheet made of a mixed material of a thermosetting resin such as an epoxy resin and a polyphenylene ether resin and an inorganic filler such as silica and alumina is formed for forming a CPc layer. For the prepreg layer, an uncured insulating sheet is prepared by impregnating a fibrous body made of a woven or non-woven fabric such as glass fiber or aramid fiber with a thermosetting resin such as an epoxy resin.

{Circle around (1)} First, as shown in the process diagram of FIG. 4, a cavity 21 containing a capacitor element is formed in the CPC layer insulating sheet 20 by punching or the like (a). On the other hand, via holes 23 are formed in the prepreg layer insulating sheet 22 by a laser processing method, and the via holes 23 are filled with a conductive paste containing a conductive powder such as Cu powder to form via hole conductors 24 (b). ). Thereafter, a conductor layer 25 is formed on the surface of the prepreg layer insulating sheet 22 (c). The conductor layer 25 is formed, for example, by attaching a metal foil such as a Cu foil or an Al foil to the surface of the insulating sheet, and then forming a conductor layer having a predetermined pattern by a process of resist application, exposure, development, etching, and resist removal. Or a method in which the metal foil is pasted on the surface of a resin film and a conductor layer having a predetermined pattern is formed in the same manner as described above, and then transferred to the surface of the insulating sheet. Among them, the latter method is preferable because the insulating sheet is not exposed to an etching solution or the like and the insulating sheet is not deteriorated.

Then, the capacitor element 26 is placed in the cavity 21 of the insulating sheet 20 for the CPC layer, and the via hole conductor 27 and the conductor layer are formed above and below the insulating sheet 20 by applying the manufacturing method of (b) and (c). 28, prepreg layer insulating sheets 30a, 30b, 30c, 30d, and 30e on which connection pads 29 for connecting to a semiconductor element are formed are laminated, and the laminate is thermoset in the CPC insulating sheet and the prepreg layer insulating sheet. By heating at a temperature sufficient to cure the resin, it is possible to produce a wiring board incorporating a capacitor element as shown in FIG.

In order to electrically connect the positive electrode and the negative electrode of the capacitor element 26 provided in the CPC layer insulating sheet 20 and the via hole conductor 27 of the prepreg layer insulating sheet 30, the capacitor of the via hole conductor 27 is used. By applying a solder that can be melted at a thermosetting temperature to the connection portion with the element 26 and / or the surface of the positive electrode and the negative electrode of the capacitor element 26, the connection between the capacitor element and the via-hole conductor can be reliably performed. it can.

Example (1) The patterns of the internal electrodes for the positive electrode and the internal electrodes for the negative electrode as shown in FIG. 2 were screen-printed on the surfaces of a plurality of BaTiO ₃ -based ceramic dielectric sheets using a metal paste of Ag-Pd. . Thereafter, the sheets were laminated and adhered at a temperature of 55 ° C. under a pressure of 150 kg / cm ² , cut in a green state using a cutter, and then fired at a temperature of 1220 ° C. in an air atmosphere to produce a capacitor body.

Then, on the outer surface of the capacitor body, an Ag-Pd paste is applied to the positive electrode forming portion and the negative electrode forming portion and baked at a temperature of 850 ° C., as shown in FIG. 2 having a plurality of positive and negative electrodes. Such an eight-terminal multilayer ceramic capacitor was manufactured.

This capacitor element has a coefficient of thermal expansion of 10.2 × 10 ⁻⁶ / ° C. at −65 to 250 ° C., a size of 1.6 × 1.6 × 0.59 (mm ³ ), and a capacitance of 0. .22 μF, self-inductance was 80 (pH), and four positive electrodes and four negative electrodes were formed.

(2) A resin and a powder in a varnish state were mixed so that the ratio of silica powder to PPE (polyphenylene ether) resin was 50% by volume, and a plurality of insulating sheets A having a thickness of 150 μm were prepared by a doctor blade method. In the insulating sheet A, a cavity of 1.6 mm in length and 1.6 mm in width, which is slightly larger than the size of the capacitor to be housed, was formed by trepanning using a carbon dioxide gas laser.

Similarly, a via hole is formed by a carbon dioxide gas laser, and the via hole is filled with a conductive paste containing a conductive powder such as Cu powder to form a via hole conductor. As a via hole conductor for connecting the conductor layer to the bump of the semiconductor element and a via hole conductor for connecting the capacitor element to the conductor layer, a conductor paste containing copper powder having an average particle diameter of 5 μm and having a silver-plated surface is used. The via hole conductor was formed by filling. As the via-hole conductor, 252 via-hole conductors were formed in conformity with the number of bumps of the semiconductor element.

(3) A-PPE (thermosetting polyphenylene ether) resin (curing temperature = 220) was prepared as an insulating sheet B made of a prepreg of 52 to 68% by volume and glass cloth of 32 to 48% by volume. Similarly, a via hole 23 is formed in a part of the prepreg by trepanning using a carbon dioxide gas laser, and the via hole 23 is filled with a conductive paste containing a conductive powder such as Cu powder to form a via hole conductor 24.

(4) On the other hand, an adhesive was applied to the surface of a transfer sheet made of polyethylene terephthalate (PET) resin, and a copper foil having a thickness of 12 μm and a surface roughness of 0.8 μm was adhered to one surface. Then, after applying a photoresist (dry film) and performing exposure and development, it was immersed in a ferric chloride solution to remove non-pattern portions by etching to form a conductor layer for a positive electrode and a conductor layer for a negative electrode. . In addition, a wiring circuit layer composed of a fine pattern having a line width of 20 μm and an interval between wirings of 20 μm was also formed.

(5) Then, the conductor layer side of the transfer sheet is pressure-bonded to the surface of the insulating sheet B prepared in (3) at a pressure of 30 kg / cm ^{2 on} the insulating sheet B, and then the transfer sheet is peeled off to insulate the conductor layer. The image was transferred to sheet B.

(6) Next, the insulating sheet A having the cavity formed in (2) is laminated by the thickness of the capacitor element, and the multilayer ceramic capacitor chip manufactured in (1) is temporarily installed in the cavity, and the chip is mounted. The surrounding gap was filled with 40% by volume of epoxy resin and 60% by volume of silica, and was temporarily fixed.

(7) Then, an insulating sheet B having a conductor layer and via-hole conductors produced through (3) and (4) was temporarily laminated on the front and back surfaces of the insulating sheet A containing the capacitor element.

(8) Then, the laminate was heated at 220 ° C. for 1 hour and completely cured to produce a multilayer wiring board. The gap of the insulating sheet was shrunk by the flow of the resin due to the heating, and the insulating layer and the capacitor chip were brought into close contact with each other, and the gap between the chip and the insulating layer was almost eliminated. Thus, a wiring board with a built-in capacitor having a total thickness of 1.2 mm was produced.

(4) The following study was conducted on the manufactured wiring board with a built-in capacitor.

Then, the linear thermal expansion coefficient at -65 to 250 ° C of the entire manufactured substrate was measured. Further, the Si chip on which the Au stud bump was formed was flip-chip mounted on a substrate heated at about 60 ° C., and the circulating resistance between the pad of the substrate and the circuit on the Si chip side was measured to confirm the presence or absence of continuity. The mechanical strength of the entire wiring board was measured using an Instron evaluation device.

Furthermore, using an impedance analyzer at a frequency 1.0MHz～1.8MHz to measure the frequency characteristic of the impedance, at the same time, to measure the capacitance of the capacitor at 1 MHz, _{and, f 0 = 1 / (2π} (L (C) ^1/2 ) (where f ₀ : resonance frequency (Hz), C: capacitance (F), and L: inductance (H)), the inductance was calculated from the resonance frequency.

イ ン ピ ー ダ ン ス In this measurement, the impedance was also measured at room temperature and after 300 cycles of the thermal shock test. In addition, changes in characteristics were measured while changing the thickness of the insulating layer on the upper surface of the capacitor element as shown in Table 1. In the thermal shock test, a temperature cycle of −55 to 125 ° C. was applied 100 times at intervals of 5 minutes in a chamber at a pressure of 1 atm using carbon dioxide as a refrigerant and an electric heater as a heating source.

(Comparative Example 1)
A wiring board was manufactured using only the insulating sheet made of the mixture of the thermosetting resin and the inorganic filler of (3) in the example, and the same evaluation as above was performed.

(Comparative Example 2)
In the examples, a wiring board was produced in exactly the same manner as above except that the arrangement of the insulating sheets A and B was completely reversed and the capacitor element was built in the insulating sheet B, and the same evaluation as above was performed. .

As is apparent from the results in Table 1, based on the present invention, the insulating layer made of prepreg is formed on the surface layer of the wiring board, and the insulating layer formed of a mixture of inorganic filler and thermosetting resin is formed on the inner layer containing the capacitor element. The wiring board of the present invention formed by (CPC) had a high mechanical strength of 300 MPa or more, and could be flip-chip mounted. In addition, the change in inductance due to the capacitor element did not change even after the initial characteristics at room temperature and after the thermal shock test, and was highly reliable.

1 is a schematic sectional view of a wiring board with a built-in electric element of the present invention. It is for explaining the capacitor element used by this invention, (a) is a schematic perspective view, (b) is a pattern diagram of a positive electrode internal electrode, (c) is a negative electrode internal electrode pattern diagram. . FIG. 3A is a pattern diagram of a first conductor layer and FIG. 3B is a pattern diagram of a second conductor layer in the wiring board of the present invention. FIG. 3 is a process chart for manufacturing the wiring board with a built-in electric element of the present invention.

Explanation of reference numerals

A Wiring substrate 1 Insulating substrate 1a First insulating layer 1b Second insulating layer 2 Cavity 3 Capacitor element 4 Semiconductor element 5 Ceramic dielectric layer 6a Positive electrode 6b Negative electrode 7a Positive internal electrode 7b Negative internal electrode 8 First Conductor layer 9 Second conductor layers 10, 11, 17 Via hole conductor

Claims (6)

A wiring board comprising a wiring circuit layer formed on the surface and / or inside of an insulating substrate, wherein an electric element is built in the insulating substrate, wherein the insulating substrate is formed of a thermosetting resin and an inorganic filler. A laminated structure of a first insulating layer made of a mixture and a second insulating layer in which a fibrous body is impregnated with a thermosetting resin, and an electric element is built in the first insulating layer The second insulating layer is disposed on the outermost surface of the insulating substrate, and a difference in thermal expansion between the electric element and the first insulating layer is 7 × 10 ⁻⁶ / ° C. or less; A wiring board with a built-in electric element, wherein a difference in thermal expansion coefficient between the first insulating layer and the second insulating layer is 8.6 × 10 ⁻⁶ / ° C. or less. 2. The wiring board with a built-in electric element according to claim 1, wherein the first insulating layer contains 30 to 65% by volume of a thermosetting resin and 35 to 70% by volume of an inorganic filler. 3. The wiring board with a built-in electric element according to claim 1, wherein the inorganic filler is at least one selected from SiO ₂ , Al ₂ O ₃ , AlN, and Si ₃ N ₄ . The thermosetting resin in the first insulating layer and the second insulating layer includes at least one selected from a polyphenylene ether-based resin, an epoxy-based resin, and a cyanate-based resin. Wiring board with built-in electrical elements. The wiring board with a built-in electric element according to any one of claims 1 to 4, wherein the electric element comprises a multilayer ceramic capacitor. 7. The wiring according to claim 1, wherein a via-hole conductor filled with metal powder is formed in the first insulating layer and / or the second insulating layer. 8. substrate.

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