JP2008205451A - Thin-film transistor array and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin-film transistor array in which the electrical resistance increase in the electrodes and difficulty of manufacturing are suppressed, while reducing feedthrough of a thin-film transistor which uses interdigital electrodes. <P>SOLUTION: Source/drain electrodes are made into interdigital shape; width of the drain electrode is made shorter than that of the source electrode; and roots of the drain electrode or of source/drain electrodes are made tapered; thereby the electrical resistance increase is suppressed, and the yield is improved for the thin-film transistor array. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a thin film transistor array used for an image display device or the like.

Based on the transistor and integrated circuit technology based on the semiconductor itself, amorphous silicon (a-Si) and polysilicon (poly-Si) thin film transistors (Thin Film Transistors: TFTs) are manufactured on a glass substrate and used in liquid crystal displays. Applied (Non-Patent Document 1). For example, a TFT as shown in FIG. 10 is used. Here, the TFT plays the role of a switch, and when the TFT is turned on by the selection voltage applied to the gate wiring 2 ′, the signal voltage applied to the source wiring 4 ′ is applied to the pixel electrode 8 connected to the drain 5. Write. The written voltage is held in the storage capacitor constituted by the pixel electrode 8 / gate insulating film 3 / capacitor electrode 10.

Here, in the case of a TFT array, the function of the source and drain varies depending on the polarity of the voltage to be written, so the name cannot be determined by the operation. Therefore, for convenience, one is called a source and the other is called a drain, and the names are unified. In the present invention, the one connected to the wiring is called a source, and the one connected to the pixel electrode is called a drain.

In recent years, organic semiconductors and oxide semiconductors have appeared, and it has been shown that TFTs can be manufactured at a low temperature of 200 ° C. or lower, and expectations for flexible displays using plastic substrates are increasing. In addition to the feature of flexibility, it is also expected to be light, hard to break, and thin. Moreover, an inexpensive and large-area display is expected by forming TFTs by printing.

By the way, in order to increase the area of the display, it is necessary not only to pattern the large area but also to increase the on current. When the channel width is W and the channel length is L, the on current is proportional to W / L. When it is desired to obtain a large on-current, comb-type electrodes in which straight comb teeth are alternately arranged are often used as the source / drain electrodes. This is because the comb type has a large W and a small L. Here, the comb-shaped electrode usually has an equal width as shown in FIG.

However, in the case of a comb-type electrode, since the length of the comb and the number of teeth are large, there is a problem that the electrode overlap area between the gate and the drain becomes large and the feedthrough becomes large.

Here, the feedthrough is a phenomenon in which the potential of the pixel changes when the gate potential changes from on to off, and is caused by the capacitance between the gate and the drain.
If the feedthrough is large, the potential of the pixel is deviated from the design value, and display as expected cannot be performed.

On the other hand, if the electrode width is reduced for the purpose of reducing the electrode overlap area, there are problems that the electrical resistance of the electrode increases and that it becomes difficult to produce the electrode.
Edited by Shoichi Matsumoto: “Liquid Crystal Display Technology -Active Matrix LCD-” Industrial Books.

The present invention has been made in view of the state of the related art, and provides a thin film transistor array in which the feedthrough of a thin film transistor using a comb-type electrode is reduced, and the increase in the electrical resistance of the electrode and the difficulty of production are improved. The task is to do.

In order to solve the above-described problem, the invention according to claim 1 is provided on the insulating substrate, at least a gate electrode connected to the gate wiring, a gate insulating film, a source electrode connected to the source wiring, and a pixel electrode. A thin film transistor array in which thin film transistors having a drain electrode connected to the semiconductor layer and a semiconductor layer formed between the source electrode and the drain are arranged in a matrix, wherein the source electrode and the drain electrode are comb-shaped, The thin film transistor array is characterized in that a width of the drain electrode is smaller than a width of the source electrode.

A second aspect of the present invention is the thin film transistor array according to the first aspect, wherein a shape of a connection portion between the drain electrode and the pixel electrode is a tapered shape.

A third aspect of the present invention is the thin film transistor array according to the first or second aspect, wherein a shape of a connection portion between the source electrode and the source wiring is tapered.

The invention described in claim 4 is the thin film transistor array according to any one of claims 1 to 3, wherein the semiconductor is an organic semiconductor or an oxide semiconductor.

A fifth aspect of the present invention is the method of manufacturing a thin film transistor array according to any one of the first to fourth aspects, wherein the source electrode and the drain electrode are formed by reversal printing. It is a manufacturing method.

According to the first aspect of the present invention, by reducing the width of the drain electrode while keeping the width of the source electrode wide, both the increase in electrical resistance and the risk of disconnection during fabrication are kept only on the drain electrode side. be able to. Therefore, increase in electrical resistance can be reduced and yield can be improved.

According to the second aspect of the present invention, since the shape of the connection portion of the drain electrode with the pixel electrode is tapered, the possibility of disconnection at the time of manufacturing the drain electrode can be reduced. Therefore, the yield can be improved.

According to the third aspect of the present invention, the risk of disconnection during the production of the source electrode can be further reduced by making the shape of the connection portion of the source electrode with the source wiring into a tapered shape. Therefore, the yield can be improved.

According to the invention described in claim 4, by using an organic semiconductor or an oxide semiconductor as a semiconductor, a thin film transistor array can be manufactured at a low temperature of 200 ° C. or less, and a heat-sensitive plastic substrate can be used. Thus, a flexible display can be manufactured.

According to the fifth aspect of the present invention, by forming the source / drain electrodes by the reversal printing method, highly accurate patterning can be performed easily and at high speed, and a thin film transistor array with good performance can be easily manufactured.

According to the present invention, first, the source / drain electrode is comb-shaped and the width of the drain electrode is made narrower than the width of the source electrode, thereby suppressing the increase in electric resistance while suppressing the gate-drain capacitance, And the yield was improved. In addition, the shape of the connection portion of the drain electrode with the pixel electrode is tapered, or the shape of the connection portion of the source electrode with the source wiring and the shape of the connection portion of the drain electrode with the drain wiring is tapered. As a result, the yield was further improved. Furthermore, by using an organic semiconductor or an oxide semiconductor as the semiconductor, manufacturing at a low temperature is possible, and a plastic substrate can be used. Furthermore, by forming the source / drain electrodes by the reverse printing method, a highly accurate element can be easily manufactured.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings used below, the scale is not accurately drawn for easy understanding.

An example of a thin film transistor array according to an embodiment of the present invention is shown in FIG. FIG. 3 is a plan view showing one pixel region of a thin film transistor array. That is, the thin film transistor array of the present invention is a pixel array of FIG. 1 arranged in a matrix. As shown in FIG. 1, in the thin film transistor array according to the embodiment of the present invention, the source electrode 4 and the drain electrode 5 are comb-shaped, and the width of the drain electrode 5 is smaller than the width of the source electrode 4. Therefore, the overlapping area of the gate electrode 2 and the drain electrode 5 can be reduced while suppressing an increase in the electrical resistance of the source electrode 4 and a decrease in yield (disconnection during formation).

As a guideline for the electrical resistance of the source electrode 4 and the drain electrode 5, if the electrode width is Ls and Ld, the comb length is w, the thickness t, and the resistivity ρ, ρw / Lst and ρw / Ldt are Can think. That is, the electrical resistance is inversely proportional to the electrode width. For example, if both the width of the source electrode 4 and the drain electrode 5 are halved, the electric resistance is doubled, but if only the width of the drain electrode 5 is halved, the electric resistance is 1.5 times. On the other hand, the overlap between the drain electrode 5 and the gate electrode 2 is ½ times. Further, since the source electrode 4 is thick, it can be easily formed, and a decrease in the yield of the drain electrode 5 (disconnection during formation) is only a concern.

An example of further improved source electrode 4 and drain electrode 5 is shown in FIG. As shown in FIG. 2A, the shape of the connection portion of the drain electrode 5 with the pixel electrode 8 is tapered, so that a decrease in the yield of the drain electrode 5 (disconnection during formation) can be suppressed. Further, the shape of the connection portion of the source electrode 4 to the source wiring 4 'as shown in FIG. 2 (b) may be tapered, or the tapered portion may be curved as shown in FIG. 2 (c).

The number of teeth of the source electrode 4 being one more than the number of the drain electrodes 5 is also effective for reducing the overlapping area of the gate electrode 2 and the drain electrode 5.

The semiconductor layer 6 is formed in a region where the source electrode 4 and the drain electrode 5 are close to each other, and overlaps the gate electrode 2 with the gate insulating film 3 interposed therebetween. The electric charge at the interface between the semiconductor layer 6 and the gate insulating film 3 can be controlled by controlling the potential of the gate electrode 2, and the drain current can be controlled. The element structure may be a bottom gate or a top gate. Moreover, a bottom contact may be sufficient and a top contact may be sufficient. These will be described with reference to FIG. FIG. 3 is a cross-sectional view taken along line A-A ′ of FIG. 1. In the bottom gate / bottom contact (FIG. 3A), the stacking order is the substrate 1, the gate electrode 2, the gate insulating film 3, the source electrode 4 and the drain electrode 5, and the semiconductor layer 6. In the bottom gate / top contact (FIG. 3B), the stacking order is the substrate 1, the gate electrode 2, the gate insulating film 3, the semiconductor layer 6, the source electrode 4, and the drain electrode 5. In the top gate / bottom contact (FIG. 3C), the stacking order is the substrate 1, the source electrode 4 and the drain electrode 5, the semiconductor layer 6, the gate insulating film 3, and the gate electrode 2. In the top gate / top contact (FIG. 3D), the stacking order is the substrate 1, the semiconductor layer 6, the source electrode 4 and the drain electrode 5, the gate insulating film 3, and the gate electrode 2. Needless to say, the gate wiring 2 ′ is provided in the same layer as the gate electrode 2, and the source wiring 4 ′ and the pixel electrode 8 are provided in the same layer as the source electrode 4 and drain electrode 5. Further, the capacitor electrode 10 and the capacitor wiring 10 ′ may be provided in the same layer as the gate electrode 2 or in a different layer. In the case of a bottom gate, the sealing layer 7 may be provided on the semiconductor layer 6.

Further, an interlayer insulating film 9 and an upper pixel electrode 12 may be further provided, and the upper pixel electrode 12 may be connected to the pixel electrode 8. Particularly in the top gate, it is desirable to have the interlayer insulating film 9 and the upper pixel electrode 12.

However, the upper pixel electrode 12 needs to be connected to the pixel electrode 8, and an opening is required in the interlayer insulating film 9 in the bottom gate and in the interlayer insulating film 9 and the gate insulating film 3 in the top gate.

As the semiconductor layer 6, an organic semiconductor or an oxide semiconductor is used. Specifically, organic semiconductors such as polythiophene derivatives, polyphenylene vinylene derivatives, polythienylene vinylene derivatives, polyallylamine derivatives, polyacetylene derivatives, acene derivatives, oligothiophene derivatives, InGaZnO series, ZnGaO series, InZnO series, InO series, GaO Oxide semiconductors such as Sn, SnO, or a mixture thereof can be used. An organic semiconductor can be formed at a low temperature of 200 ° C. or lower by applying and baking a solution by spin coating, die coating, inkjet, or the like, and an oxide semiconductor by sputtering, vapor deposition, laser ablation, or the like.

The organic semiconductor can also be formed at a low temperature of 200 ° C. or less by applying and baking the solution by flexographic printing.

Therefore, plastic can be used as the insulating substrate 1. Specifically, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), polyimide (PI), polyetherimide (PEI), polystyrene (PS), polyvinyl chloride (PVC), polyethylene (PE), polypropylene (PP), nylon (Ny) and the like can be used.

Although the semiconductor layer 6 can operate even when it is formed on the entire surface, patterning as shown in FIGS. 1 and 5 to 8 is preferable because the off-current can be reduced. Whether film formation is performed by spin coating, die coating, sputtering, vapor deposition, laser ablation, etc., followed by patterning using photolithography or a similar method, or printing, mask vapor deposition, etc. that can be performed simultaneously with film formation and patterning. A lift-off method in which a resist pattern is formed in advance and the resist is removed after film formation on the entire surface can be used. Alternatively, in the case of an organic semiconductor, after forming a sealing layer 7 to be described later, etching with O ₂ plasma, N ₂ plasma, Ar plasma or the like is performed using the sealing layer 7 as a mask, or the semiconductor without dissolving the sealing layer 7 is used. Patterning is also possible by a method such as rinsing with a liquid that dissolves the layer 6.

As the gate electrode 2 and the capacitor electrode 10, a metal such as Al, Cr, Au, Ag, Ni, Cu, and Mo, or a transparent conductive film such as ITO can be used. As a manufacturing method, a method of forming by photolithography + etching after vapor deposition or sputter film formation is generally used, but printing methods (screen printing, flexographic printing, gravure printing, offset printing, reverse printing, etc.) can be used. When printing is used, Ag ink, Ni ink, Cu ink, or the like can be used.

As the gate insulating film 3, an organic insulating film such as polyvinylphenol, epoxy, or polyimide, or an inorganic insulating film such as SiO ₂ , SiN, SiON, or Al ₂ O ₃ can be used. As the production method, spin-coating, die-coating, ink-jet or the like can be used in the case of a solvent-soluble organic substance, and sputtering, vapor deposition, laser ablation or the like can be used in other cases.

For example, when patterning is required as in the top gate, patterning is performed by photolithography, etching, lift-off, etc., or a printing method such as ink jet or exposure / development using a photosensitive organic material as the material of the gate insulating film 3. It is possible to pattern directly.

For the source electrode 4, the source wiring 4 ′, the drain electrode 5, and the pixel electrode 8, the same material and the same method as the gate electrode 2 can be used, but inversion printing is particularly optimal.

As the sealing layer 7, a fluorinated resin is suitable. As the production method, screen printing is suitable. As the interlayer insulating film 9, polyvinylphenol, acrylic, epoxy, polyimide, or the like can be used. As a production method, screen printing is suitable, but it may be formed by exposure / development after forming a photosensitive film. As the upper pixel electrode 12, a metal such as Al, Cr, Au, Ag, Ni, or Cu, a transparent conductive film such as ITO, or the like can be used. As a manufacturing method, methods such as photolithography and etching after film formation such as vapor deposition and sputtering are possible, but screen printing of Ag ink, Ni ink, Cu ink, or the like is preferable.

Next, reverse printing, which is a feature of the method for manufacturing a thin film transistor of the present invention, will be described. FIG. 4 shows an outline of reverse printing.

The reverse printing includes a step of forming an ink liquid film 23 on the blanket 21 having ink releasability, a step of bringing the relief plate 24 into contact with the ink liquid film 23 and removing the convex shaped ink, and the blanket 21 And a step of transferring an image pattern onto the substrate 25 by bringing the ink remaining on the substrate 25 into contact with the substrate 25. Usually, the blanket 21 is a cylinder (transfer cylinder) having a silicone resin on the surface, and the relief plate 24 is a glass plate having a negative convex portion of the image pattern.

As the ink to be used, a conductive ink containing metal particles having an average particle diameter of 50 nm or less, an aqueous solvent, and a water-soluble resin is desirable. Ag is preferred as the metal. By firing after printing, a low-resistance electrode is obtained.

5 and 6 show an example of a method for manufacturing the thin film transistor of FIG. A gate electrode 2 and a capacitor electrode 10 are formed on the insulating substrate 1 (FIG. 5A), and a gate insulating film 3 is formed on the entire surface (FIG. 5B). Further, the source electrode 4, the source wiring 4 ', the drain electrode 5, and the pixel electrode 8 are formed by the above inversion printing (FIG. 5C), and the semiconductor layer 6 is formed (FIG. 5D).

  The above is the procedure for the bottom gate / bottom contact. In the case of the bottom gate / top contact, top gate / bottom contact, top gate / top contact, the layer order may be changed.

For example, FIGS. 7 and 8 show the case of bottom gate / top contact, and the step of forming the source electrode 4, the source wiring 4 ′, the drain electrode 5, and the pixel electrode 8 is replaced with the step of forming the semiconductor layer 6. ing.

Further, as described above, the sealing layer 7 (FIG. 6E), the interlayer insulating film 9 (FIG. 6F), and the upper pixel electrode 12 (FIG. 6G) may be formed. .

(Example 1)
An embodiment of the present invention will be described with reference to FIGS. 1, 5, and 6. The device shown in FIG. 1 was fabricated by the steps of FIGS. 5 (a) to 6 (g). First, an Al film having a thickness of 50 nm was formed on the PEN which is the insulating substrate 1 by vapor deposition, and the gate electrode 2 and the capacitor electrode 10 were formed by photolithography and wet etching (FIG. 5A). Next, a polyvinylphenol solution was spin-coated and baked at 150 ° C. to form 1 μm of polyvinylphenol as the gate insulating film 3 (FIG. 5B). Further, as the source electrode 4, the source wiring 4 ′, the drain electrode 5, and the pixel electrode 8, a pattern having a thickness of 50 nm was formed by reversal printing of Ag ink and baking at 180 ° C. (FIG. 5C). The shape of the source electrode 4 and the drain electrode 5 at that time is as shown in FIG. 1. The drain electrode width is 5 μm, the source electrode width is 10 μm, the channel length is 5 μm, and the channel width is 800 μm. According to microscopic observation, the yield of the source electrode was 90% and the yield of the drain electrode was 60%.

Here, the yield is the ratio of the comb whose length is 90% or more of the design value among the number of the combs of the electrode.

Furthermore, the semiconductor layer 6 was formed by spin-coating a polythiophene solution and baking at 100 ° C. (FIG. 5D).

However, the semiconductor layer 6 is not patterned.

Then, CYTOP, which is a fluorinated resin, was screen-printed to form the sealing layer 7 (FIG. 6E).

Thereafter, the semiconductor layer except under the sealing layer was removed by rinsing with xylene (FIG. 6E).

Further, an epoxy resin was screen printed to form an interlayer insulating film 9 (FIG. 6F), and an Ag paste was screen printed to form an upper pixel electrode 12 (FIG. 6G).

An electrophoretic display having a structure in which an electrophoretic display body was sandwiched between the thin film transistor array thus produced and a substrate with a counter electrode was produced. Although there were variations in the amount of drain electrode deficiency, it was confirmed that it operated almost as expected.

Specifically, when a predetermined writing operation (predetermined source voltage, gate voltage, gate pulse width, writing cycle, number of writings) calculated from the characteristics of the electrophoretic display body and the characteristics of the transistor is performed, a defect-free pixel portion is obtained. Confirmed that it works almost as expected.

Also in the following embodiments, “operation as expected” means that the operation is performed with the number of writings as expected under a predetermined writing condition.

(Example 2)
A thin film transistor array similar to that of Example 1 was manufactured except that the shape of the source electrode 4 and the drain electrode 5 was as shown in FIG. Specifically, the width of the drain electrode in contact with the pixel electrode is 25 μm, and the width is constant (5 μm) in a portion separated by 20 μm or more from the contacted portion. According to microscopic observation, the yield of the source electrode was 90%, and the yield of the drain electrode was 90%.

(Example 3)
A thin film transistor array similar to that of Example 1 was produced except that the shapes of the source electrode 4 and the drain electrode 5 were as shown in FIG. Specifically, the width of the portion of the source electrode that is in contact with the source wiring is 20 μm, and the width is constant (10 μm) at a portion that is 5 μm or more away from the contacted portion. According to microscopic observation, the yield of the source electrode was 95%, and the yield of the drain electrode was 90%.

Example 4
A thin film transistor array similar to that in Example 1 was manufactured except that the shapes of the source electrode 4 and the drain electrode 5 were as shown in FIG. Specifically, the portion of the drain electrode that is in contact with the pixel electrode has a tapered shape rounded by an arc having a radius of 10 μm, and the portion of the source electrode that is in contact with the source wiring has a radius of 7.5 μm. According to microscopic observation, the yield of the source electrode was 95%, and the yield of the drain electrode was 90%.

(Example 5)
An embodiment of the present invention will be described with reference to FIGS. 1, 7, and 8. FIG. The device shown in FIG. 1 (however, the drain electrode shape is shown in FIG. 2A) was produced by the steps shown in FIGS. 7A to 8G. First, an Al film having a thickness of 50 nm was formed on the PEN as the insulating substrate 1 by vapor deposition, and the gate electrode 2 and the capacitor electrode 10 were formed by photolithography and wet etching (FIG. 7A). Next, SiN was used as a target, and Ar, O ₂ , and N ₂ were flowed and RF sputtering was performed to form 500 nm of SiON as the gate insulating film 3 (FIG. 7B). Further, RF sputtering was performed by flowing Ar and O ₂ using InGaZnO ₄ as a target, thereby depositing an InGaZnO film having a thickness of 50 nm as the semiconductor layer 6 and patterning by wet etching using photolithography and hydrochloric acid (FIG. 7C). Further, as the source electrode 4, the source wiring 4 ′, the drain electrode 5, and the pixel electrode 8, a pattern having a thickness of 50 nm was formed by reversal printing of Ag ink and baking at 180 ° C. (FIG. 7D). The shape of the source electrode 4 and the drain electrode 5 at that time is as shown in FIG. 2A. The drain electrode width is 5 μm, the source electrode width is 10 μm, the channel length is 5 μm, and the channel width is 800 μm.

Further, the width of the drain electrode in contact with the pixel electrode is 25 μm, and the width is constant (5 μm) in a portion separated by 20 μm or more from the contacted portion.

According to microscopic observation, the yield of the source electrode was 90%, and the yield of the drain electrode was 90%.

Then, CYTOP, which is a fluorinated resin, was screen-printed to form the sealing layer 7 (FIG. 8E). Further, an epoxy resin was screen printed to form an interlayer insulating film 9 (FIG. 8F), and an Ag paste was screen printed to form an upper pixel electrode 12 (FIG. 8G).

An electrophoretic display having a structure in which an electrophoretic display body is sandwiched between the thin film transistor array thus manufactured and a substrate with a counter electrode is manufactured, and it is confirmed that the electrophoretic display operates almost as expected.

(Example 6)
An embodiment of the present invention will be described with reference to FIGS. 1, 5, and 6. The element shown in FIG. 1 (however, the drain electrode shape is FIG. 2 (a)) was produced by the steps of FIG. 5 (a) to FIG. 6 (g). First, an Al film having a thickness of 50 nm was formed on the PEN which is the insulating substrate 1 by vapor deposition, and the gate electrode 2 and the capacitor electrode 10 were formed by photolithography and wet etching (FIG. 5A). Next, a polyvinylphenol solution was spin-coated and baked at 150 ° C. to form 1 μm of polyvinylphenol as the gate insulating film 3 (FIG. 5B). Further, as the source electrode 4, the source wiring 4 ′, the drain electrode 5, and the pixel electrode 8, a pattern having a thickness of 50 nm was formed by reversal printing of Ag ink and baking at 180 ° C. (FIG. 5C). The shape of the source electrode 4 and the drain electrode 5 at that time is as shown in FIG. 2A, the drain electrode width is 5 μm, the source electrode width is 10 μm, the channel length is 5 μm, the channel width is 800 μm, and the pixel electrode of the drain electrode The width in contact with each other is 25 μm, and the width is constant (5 μm) in a portion separated by 20 μm or more from the contacted portion. According to microscopic observation, the yield of the source electrode was 90%, and the yield of the drain electrode was 90%.

Further, the semiconductor layer 6 was formed by flexographic printing of the polythiophene solution and baking at 100 ° C. (FIG. 5D). Then, CYTOP, which is a fluorinated resin, was screen-printed to form the sealing layer 7 (FIG. 6E). Further, an epoxy resin was screen printed to form an interlayer insulating film 9 (FIG. 6F), and an Ag paste was screen printed to form an upper pixel electrode 12 (FIG. 6G).

An electrophoretic display having a structure in which an electrophoretic display body is sandwiched between the thin film transistor array thus manufactured and a substrate with a counter electrode is manufactured, and it is confirmed that the electrophoretic display operates almost as expected.

(Comparative Example 1)
A thin film transistor array similar to that of Example 1 was manufactured except that the shapes of the source electrode 4 and the drain electrode 5 were as shown in FIG. Specifically, the drain electrode width is 5 μm, the source electrode width is 5 μm, the channel length is 5 μm, and the channel width is 800 μm. According to microscopic observation, for example, as shown in FIG. 9B, defects were observed in some electrodes, the yield of the source electrode was 60%, and the yield of the drain electrode was 60%. In FIG. 9B, one of the three source electrodes is missing and one of the two drain electrodes is missing.

(Comparative Example 2)
A thin film transistor array similar to that of Example 1 was manufactured except that the shapes of the source electrode 4 and the drain electrode 5 were as shown in FIG. Specifically, the drain electrode width is 10 μm, the source electrode width is 10 μm, the channel length is 10 μm, and the channel width is 1600 μm. According to microscopic observation, the yield of the source electrode was 90%, and the yield of the drain electrode was 90%.

When an electrophoretic display having a structure in which an electrophoretic display body is sandwiched between a thin film transistor array thus manufactured and a substrate with a counter electrode is manufactured, the feedthrough is large, so that display is not performed 10 times as many times as expected. could not.

It is a top view which shows an example of the thin-film transistor array of this invention. It is a top view which shows the other example of the source / drain electrode shape of the thin-film transistor array of this invention. It is sectional drawing which shows the example of the laminated structure of the thin-film transistor array of FIG. It is explanatory drawing which shows a reverse printing method. It is sectional drawing and a top view which show an example of the manufacturing process of the thin-film transistor of this invention. It is sectional drawing and a top view which show an example of the manufacturing process of the thin-film transistor of this invention. It is sectional drawing and a top view which show another example of the manufacturing process of the thin-film transistor of this invention. It is sectional drawing and a top view which show another example of the manufacturing process of the thin-film transistor of this invention. It is a top view which shows the source / drain electrode shape of the thin-film transistor array which has the conventional comb-type electrode. It is a top view which shows the structure of the conventional thin-film transistor array.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Insulating substrate 2 ... Gate electrode 2 '... Gate wiring 3 ... Gate insulating film 4 ... Source electrode 4' ... Source wiring 5 ... Drain electrode 6 ... Semiconductor layer 7 ... Sealing layer 8 ... Pixel electrode 9 ... Interlayer insulating film 10 ... capacitor electrode 10 '... capacitor wiring 12 ... upper pixel electrode 21 ... blanket 22 ... ink application mechanism 23 ... ink liquid film 24 ... relief printing (removal plate)
25 ... Base material 26 ... Stage

Claims (5)

Formed on an insulating substrate at least between a gate electrode connected to the gate wiring, a gate insulating film, a source electrode connected to the source wiring, a drain electrode connected to the pixel electrode, and between the source electrode and the drain A thin film transistor array in which thin film transistors having a formed semiconductor layer are arranged in a matrix, wherein the source electrode and the drain electrode are comb-shaped, and the width of the drain electrode is smaller than the width of the source electrode. A thin film transistor array. 2. The thin film transistor array according to claim 1, wherein a shape of a connection portion between the drain electrode and the pixel electrode is a tapered shape. 3. The thin film transistor array according to claim 1, wherein a shape of a connection portion of the source electrode with the source wiring is tapered. The thin film transistor array according to claim 1, wherein the semiconductor is an organic semiconductor or an oxide semiconductor. 5. The method of manufacturing a thin film transistor array according to claim 1, wherein the source electrode and the drain electrode are formed by reversal printing. 6.