JP2008262615A - Programming method of reference cell and nonvolatile memory unit using thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a programming method of a reference cell for converging to a desired reference cell current value and setting a cycle margin value optimal to each nonvolatile memory device. <P>SOLUTION: In a memory cell gate voltage VCCR setting step, a predetermined VCCR initial value is given to the gate voltages of a plurality of memory cells. Thereafter, in a reference cell gate voltage VCR setting step, a total value of a predetermined voltage margin and the predetermined VCCR initial value is given to the gate voltage of the reference cell. Thereafter, in a pulse verify loop, the memory cell current value of each of the plurality of memory cells to which the gate voltage of the predetermined VCCR initial value is applied is compared with the reference cell current value of the reference cell to which the gate voltage of the total value is applied. When the difference value between each memory cell current value and each reference current value is within a predetermined allowable value, the program of the reference cell is completed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for programming a reference cell used for erasure verification and program verification, which is a process for determining a memory cell threshold value and reading a memory cell in a nonvolatile memory device such as a flash EEPROM, and a nonvolatile memory using the same The present invention relates to a memory device, and more particularly to an NROM type nonvolatile memory device.

  In recent years, non-volatile memory devices such as flash memory and EEPROM have realized a large-capacity memory array configuration using miniaturized memory cells. In these nonvolatile memory devices, it is required to accurately read data in the memory cells over a wide temperature voltage operation range over the entire large-scale memory. In the read operation and the margin read operation such as program verify and erase verify that are the determination process of the program threshold value and the erase threshold value, the reference signal is used when converting the analog value stored in the memory cell to the digital value. is required. As a device for generating this reference signal, a reference cell having characteristics similar to that of a memory cell is used.

  Generally, a memory cell set in a programmed state or an erased state is set so as to have a margin value with respect to a reference cell at the time of reading. This margin value is subject to threshold drift such as retention loss due to outflow of carriers injected into the memory cell to realize the threshold temperature, voltage fluctuation, program state and erase state of the memory cell. Even so, the read logic value of the memory cell is set so as not to fluctuate.

  In the nonvolatile memory device, by adopting the reference cell method and the differential sense amplifier, the cell current and threshold voltage drift due to the temperature-voltage characteristics of the memory cell are suppressed by the characteristics of the reference cell, and the memory cell The margin loss such as the deterioration of the retention characteristics due to the miniaturization of the substrate is compensated.

  As described above, in the nonvolatile memory device employing the reference cell, it is possible to compensate for the margin loss, and therefore further miniaturization of the memory cell can be promoted in the future.

  In recent years, the main physical structure of a memory cell is changing from a conventionally used floating gate type to an NROM type using a multi-bit ONO film that is easier to miniaturize as a data retention material.

  In the NROM type memory cell, a channel hot electron selective injection state is a program state on the high VT side, and a state in which injected electrons are neutralized by hot holes is an erase state on the low VT side.

  In view of the fact that the data retention material of the NROM type memory cell is an insulator and that the hot hole injection profile does not match the channel hot electron injection profile, the memory cell is in a state immediately after the manufacturing process (hereinafter referred to as a blank state). If the program / erase cycling is executed once, the remaining carriers always remain in the ONO film, and it is impossible to completely return the threshold value of the memory cell to the threshold value in the blank state. It is. This is because the channel hot electron injection process is a process in which holes generated by band-to-band tunneling are accelerated by a drain electric field and injected, and has a steep injection profile near the drain. On the other hand, neutralization of injected electrons is an injection process by hot holes, and has a slow injection profile in view of injection of secondary electrons. For this reason, when program / erase cycling is executed, residual electrons that cannot be neutralized by hot holes accumulate in the center of the channel that is off the drain. Further, the dose amount of holes is a factor that impairs the reliability of the oxide film itself. Therefore, the remaining electrons make it difficult to completely erase the memory cell, and the device reaches the cycling life when the memory cell does not reach the erase level.

  The cycling margin (CM), which is the difference between the threshold value of the blank memory cell and the erase level (EV), is an important parameter that determines the cycling life and retention characteristics of the device. If the memory cell's word line level is lowered to reduce power consumption or to achieve a low erase level to ensure a sufficient read margin for the erase cell, the cycling margin will be reduced and the cycling life will deteriorate. . On the contrary, when the erase level is increased, the read word line level is increased, and further, the program level (PV) is required to be higher in order to secure the read margin of the read cell. A program level that is too high degrades the retention characteristics of the program state. That is, the cycling margin is a parameter that should be managed to an optimum value according to the required specifications of the cycling characteristics and the retention characteristics.

  The NROM type memory cell can constitute a contactless virtual ground array that enables high integration. In this virtual ground array type memory array, a source-side reading method in which a cell current is extracted from the source side of a cell transistor is adopted as a mainstream method. In this source side reading method, an input level close to the ground can be determined with high accuracy.

  Further, as a reference cell programming method, the memory cell current that flows when a fixed reference gate voltage is biased to a blank memory cell transistor is used as a reference cell current, and the threshold value of the reference cell transistor is programmed. Has been done.

The NROM type nonvolatile memory device and the source side reading method are described in, for example, Patent Document 1 and Patent Document 2, and a reference cell programming method based on a blank memory cell is described in, for example, Patent Document 3 and Patent Document 4.
US Pat. No. 6,134,156 US Pat. No. 6,128,226 US Pat. No. 6,064,983 US Pat. No. 6,584,017

  However, in the conventional reference cell programming method, since the value of the reference cell current is directly related to the blank state threshold value of the reference cell transistor, the variation in the reference cell current between chips increases. It is necessary to increase the movable operating point range (dynamic range) of the sense amplifier in accordance with the variation in the reference cell current. However, it is difficult to design a sense amplifier that has a wide dynamic range and can obtain equivalent performance and small offset in the temperature voltage process variation range. In a sense amplifier having an input range close to, it is even more difficult to design a low-area and low-cost design or a high-yield design that can handle all process variations.

  In addition, the lower limit value of the margin window defined by the difference between the program state threshold value and the erase state threshold value of the memory cell transistor is linked to a value irrelevant to the blank state threshold value of the memory cell. Therefore, the cycle margin value cannot be optimally set for each chip.

  As described above, a nonvolatile memory device using a reference cell, particularly an NROM nonvolatile memory device, has a problem of optimization of a reference cell current value between chips and a cycle margin value.

  The present invention has been made paying attention to the above-mentioned problems, and its purpose is to remove the offset voltage of the sense amplifier, to converge to a desired reference cell current value, and to provide an optimum cycle margin value for each chip. It is possible to provide a reference cell programming method to which a low-cost sense amplifier having a narrow movable operation range can be applied and a nonvolatile memory device using the same.

  Specifically, the reference cell programming method according to the first aspect of the present invention is a reference cell programming method in a nonvolatile memory device including a plurality of blank memory cells and a reference cell. Commonly determined between the memory cell gate voltage VCCR setting step for setting a predetermined VCCR initial value determined for each device to be applied to the gate voltages of the plurality of memory cells, and other nonvolatile memory devices A reference cell gate voltage VCR setting step for setting an added value of the predetermined voltage margin and the predetermined VCCR initial value to the gate voltage of the reference cell, and a reference for applying a program pulse to the reference cell Cell program pulse application step and reference of the reference cell A reference cell current verify step for verifying a reference current, and the reference cell program pulse applying step and the reference cell current verify step constitute a pulse verify loop. In the reference cell current verify step, the predetermined VCCR initial step A memory cell current value of each of the plurality of memory cells to which the gate voltage of the value is applied is compared with a reference cell current value of the reference cell to which the gate voltage of the added value is applied; When the difference value between the value and the reference cell current value is within a predetermined allowable value, the program branches from the pulse verify loop to complete the programming of the reference cell.

  According to a second aspect of the present invention, in the reference cell programming method according to the first aspect, the predetermined VCCR initial value is a value correlated with a memory cell current value outside the nonvolatile memory device. To do.

  According to a third aspect of the present invention, in the reference cell programming method according to the first aspect, the predetermined VCCR initial value is a value correlated with a memory cell current value in the nonvolatile memory device. To do.

  According to a fourth aspect of the present invention, the reference cell programming method according to the first aspect further includes a reference cell current test step, and the reference cell programmed in the pulse verify loop in the reference cell current test step. And applying a gate voltage of the added value to the reference cell, and then comparing a reference cell current value of the reference cell with a cell current target value of the reference cell, and a difference value between the reference cell current value and the cell current target value Is within a predetermined tolerance value, the reference cell programming is completed, and when the difference value is larger than the predetermined tolerance value, the predetermined VCCR initial value is decremented by a predetermined increment value, Branching to a pulse verify loop .

  According to a fifth aspect of the present invention, in the reference cell programming method according to the fourth aspect, when the difference value is larger than the predetermined allowable value and the reference cell current value is smaller than the cell target value, The reference cell program is completed as a failure.

  According to a sixth aspect of the present invention, the reference cell programming method according to the first aspect further comprises a reference cell gate voltage search step and a memory cell gate voltage search step, wherein the reference cell gate voltage search step includes: A reference cell gate voltage value at which a difference value between a reference cell current value of the reference cell and a cell current target value of the reference cell is equal to or less than a predetermined allowable value is obtained, and in the memory cell gate voltage search step, the reference cell gate In a state where the reference cell gate voltage value obtained in the voltage search step is applied to the reference cell, the gate voltage value applied to the plurality of memory cells is changed, and the memory cell current value of the memory cells and the memory cell current value are changed. Of reference cell A comparison is made with a reference cell current value, a gate voltage value of a memory cell in which the number of memory cells determined that the memory cell current value is smaller than the reference cell current value is within a predetermined range is obtained, and the memory cell The gate voltage value obtained in the gate voltage search step is set as the predetermined VCCR initial value.

  The invention according to claim 7 is the reference cell programming method according to claim 1, further comprising a high VT memory cell search step and a memory cell gate voltage search step, and in the high VT memory cell search step, With the reference cell gate voltage value set so that the reference cell current value is within a predetermined operating range for the reference cell, the gate voltage values of the plurality of memory cells are changed. The memory cell current value of each of the plurality of memory cells is compared with the reference cell current value of the reference cell, and the number of memory cells determined that the memory cell current value is smaller than the reference cell current value is When it is within a predetermined range, memory cell addresses belonging to the number of memory cells are stored, and the memory In the recell gate voltage search step, a memory in which a difference value between a memory cell current value of each memory cell and a memory cell current target value is equal to or less than a predetermined allowable value with respect to all memory cells having a memory cell address belonging to the number of memory cells. A cell gate voltage value is obtained, and the gate voltage value obtained in the memory cell gate voltage search step is set as the predetermined VCCR initial value.

  According to an eighth aspect of the present invention, there is provided a non-volatile memory device comprising a plurality of memory cells, at least one reference cell array, and a differential sense amplifier, wherein the at least one reference cell array is selected during erase verification. An EV reference cell for verification, an RD reference cell for read operation selected at the time of reading, and a PV reference cell for program verification selected at the time of program verification, the EV reference cell is an operation of erase verification Sometimes, the erase reference cell current is biased by the erase gate voltage value and the RD reference cell is biased by the read gate voltage value and the read reference cell current is passed during the read operation, and the PV reference cell is programmed. Sometimes, A program reference cell current is biased by a program gate voltage value, and the current value of the erase reference cell current, the current value of the read reference cell current, and the current value of the program reference cell current are other nonvolatile memory devices. The gate voltage value is higher in the order of the program gate voltage value, the read gate voltage value, and the erase gate voltage value, and the erase gate voltage value is non-volatile. The value determined for each memory device, and the difference value between the read gate voltage value and the erase gate voltage value, and the program gate voltage value, the read gate voltage value, and the difference value are each other non-volatile. A predetermined value common to the memory device is set.

  According to a ninth aspect of the present invention, in the non-volatile memory device according to the eighth aspect, the predetermined value common to the other non-volatile memory device is the reference cell programming method according to the first aspect. It is set by using.

  According to a tenth aspect of the present invention, there is provided a nonvolatile memory device comprising a plurality of memory cells, a reference cell, and a differential sense amplifier, wherein the reference cell is used for erase verify, read operation and program verify. In the erase verify operation, the reference cell is biased with the read gate voltage value to pass a predetermined reference cell current, and the memory cell is biased with the erase gate voltage value. The reference cell is biased with the read gate voltage value to pass the predetermined reference cell current, and the memory cell is biased with the read gate voltage value. During a program operation, the reference cell is set with the read gate voltage value. Biased and said predetermined The reference cell current is passed, and the memory cell is biased with a program gate voltage value. The current value of the predetermined reference cell current is set to a predetermined value common to other nonvolatile memory devices, and the program The gate voltage value is higher in the order of the gate voltage value, the read gate voltage value, and the erase gate voltage value, and the erase gate voltage value is a value determined for each nonvolatile memory device, and the read gate voltage The difference value between the value and the erase gate voltage value, and the difference value between the program gate voltage value and the read gate voltage value are each set to a predetermined value common to other nonvolatile memory devices. It is characterized by that.

  According to an eleventh aspect of the present invention, in the non-volatile memory device according to the tenth aspect, the predetermined value common to the other non-volatile memory device is the reference cell programming method according to the first aspect. It is set by using.

  A nonvolatile memory device according to a twelfth aspect of the present invention is the nonvolatile memory device according to the eighth aspect, wherein the at least one reference cell array further includes a PVH for high level program operation selected at the time of high level program verification. The PVH reference cell is biased with the program gate voltage value to flow a high level program reference cell current during a high level program verify operation, and the current value of the high level program reference cell current is: It is set to a value smaller than the current value of the program reference cell current.

  According to a thirteenth aspect of the present invention, in the nonvolatile memory device according to the twelfth aspect, the plurality of memory cells are virtual ground arrays having a common drain bit line, and the current of the program reference cell current The difference value between the value and the current value of the high-level program reference cell current is made to correspond to the cell current leak value to the adjacent memory cell.

  The reference cell programming method according to the fourteenth aspect of the invention is a PVH reference cell for high-level program operation and a reference cell programming method for a PV reference cell for program operation, and the PVH reference cell is programmed. A reference cell program step, a physical checker program step for programming a plurality of memory cells provided in the nonvolatile memory device to a physical checker state, and a PV reference cell program step for programming the PV reference cell, In the PVH reference cell programming step, the PVH reference cell is programmed using the reference cell programming method according to claim 1, and in the PV reference cell programming step, Serial using the program process of the reference cell according to claim 1, by carrying out the cell current verification by the gate voltage of the reference cell in the PVH reference cell program steps, characterized in that programming the PV reference cell.

  In the first aspect of the present invention, the reference cell current value can be adjusted to a desired constant value for each nonvolatile memory device, and a common read window margin can be set between the nonvolatile memory devices. Furthermore, the required operating point width of the read sense amplifier can be reduced, and the read window margin from the blank state to the erase state of the memory cell can be made constant between the nonvolatile memory devices.

  In the second and third aspects of the present invention, the VCCR initial value is set in common for each wafer or lot by referring to a PCM value representing the threshold value of a memory cell on the same wafer, or non-volatile. It is possible to set the threshold value by referring to a threshold value obtained by sampling a specific memory cell in the memory device. When the manufacturing process is relatively stable, the VCCR initial value can be set for each nonvolatile memory device more easily.

  In the invention of claim 4, the VCCR initial value of claim 1 can be automatically adapted to the reference cell current of the target. By giving a sufficiently high value to the VCCR initial value and setting an appropriate increment value, it is possible to execute the reference cell programming method in which the reference current is completely controlled.

  In the invention described in claim 5, it is determined whether or not a program pulse can be added to a reference cell (in a nonvolatile memory device using an ONO film such as NROM as a data holding material, a reference cell once programmed is erased. It is known that the retention characteristics of electron injection due to subsequent programming deteriorate due to hole injection due to erasing), and VCCR increment value is improperly large or sensitive. It is possible to determine whether the reference cell is removed from a non-defective product.

  In the invention according to the sixth aspect, as compared with the invention according to the fourth aspect, an iterative process for each VCCR initial value of the pulse verify loop becomes unnecessary. In addition, priority is given to the convergence of the reference current value to the target value, the offset voltage of the sense amplifier is absorbed in the variation of the memory cell current value, and the reference cell program is focused on reducing the required operating point of the sense amplifier. It becomes possible.

  In the invention according to the seventh aspect, as compared with the invention according to the fourth aspect, an iterative process for each VCCR initial value of the pulse verify loop becomes unnecessary. In contrast to the method of programming the reference cell according to claim 6, priority is given to the convergence of the memory cell current value to the target value, and the offset voltage of the sense amplifier is absorbed into the reference cell current value, Emphasis can be placed on the reliability of the memory cell rather than reduction of the required operating point.

  In the inventions according to the eighth and ninth aspects, the gate voltages of the memory cell and the reference cell are common in the operations of read, program verify, and erase verify, and the hardware can be simplified. Further, the reference cell current can be adjusted and fixed for each nonvolatile memory device, and a read window margin common to the nonvolatile memory devices can be set. As a result, the required operating point width of the read sense amplifier can be reduced, and the read window margin from the blank state to the erase state of the memory cell can be made constant between chips.

  According to the tenth and eleventh aspects of the present invention, in each of the program verify and erase verify operations, the reference cell is reduced to one type instead of using two types of gate voltages for the memory cell and the reference cell. Hardware and program costs can be reduced. Further, the reference cell current can be adjusted and fixed for each nonvolatile memory device, and a common read window margin can be set between the nonvolatile memory devices. As a result, the required operating point width of the read sense amplifier can be reduced, and the read window margin from the blank state to the erase state of the memory cell can be made constant between chips.

  In the invention described in claim 12, high level verification can be realized under the same memory cell and reference cell bias conditions as in program verification, the output voltage of the built-in power supply can be kept low, and the nonvolatile memory device It is possible to reduce power consumption and area.

  According to the thirteenth aspect of the present invention, when a memory cell adjacent to a memory cell to be programmed is in an erased state, a cell leaking to the adjacent cell is selectively applied at the time of program verification by applying a high-level verification memory cell. It is possible to program by supplementing the current, that is, to realize the same program state regardless of the presence or absence of the adjacent cell.

  In the invention of the fourteenth aspect, the PVH reference cell is programmed based on the memory cell current when the adjacent cell is in the erased state, and the PV reference cell is programmed based on the memory cell current when the adjacent cell is in the programmed state. The By selecting the PV reference when the neighboring cell is in the programmed state at the time of program verification, and selecting the PVH reference cell when the neighboring cell is in the programmed state, it becomes possible to cancel the influence of the neighboring cell.

  According to the reference cell programming method of the first aspect of the invention, the reference cell current value is adjusted to a desired constant value for each nonvolatile memory device, and a common readout window margin is set between the nonvolatile memory devices. be able to. This makes it possible to reduce the required movable operating point range of the read sense amplifier, facilitates the design of the sense amplifier, improves the yield of the sense amplifier and the characteristics of the sense amplifier, and eliminates the high precision of erasing and programming. Threshold control is possible, and more reliable reading is realized. In addition, the cycle window from the blank state to the erased state of the memory cell can be optimally controlled, the cycling characteristics and the retention characteristics can be easily optimized, and the optimum device conditions (device characteristics can be determined according to market specifications). It is possible to provide a non-volatile memory device that is operated under conditions that make the most of it.

  According to the reference cell programming method of the second and third aspects of the present invention, in addition to the effect of the first aspect, the setting value of the VCCR initial value is a PCM representing the threshold value of the memory cells on the same wafer. It can be determined by referring to the value and making it common for each wafer or lot, or by referring to a threshold value obtained by sampling a specific memory cell in the nonvolatile memory device. When the manufacturing process is relatively stable, the VCCR initial value can be easily set for each nonvolatile memory device, and the reference cell can be programmed at a lower cost.

  According to the reference cell programming method of the fourth aspect, in addition to the effect of the first aspect, the VCCR initial value can be automatically adapted to the target reference cell current. By giving a sufficiently high value to the VCCR initial value and setting an appropriate increment value, it is possible to execute an algorithm in which the reference current is completely controlled.

  According to the reference cell programming method of the fifth aspect of the invention, in addition to the effect of the first aspect, it is determined whether a program pulse can be added to the reference cell, and the increment value of VCCR is inappropriately large. Alternatively, it is possible to determine whether the reference cell is over-programmed due to sensitive programming characteristics and to remove it from a non-defective product and to make the reference cell program more reliable.

  According to the reference cell programming method of the sixth aspect of the invention, in addition to the effect of the first aspect, compared with the reference cell programming method of the fourth aspect, the iterative process for each VCCR initial value of the pulse verify loop is improved. This eliminates the need to speed up the reference cell programming process. In addition, priority is given to the convergence of the reference current value to the target value, and the offset voltage of the sense amplifier is absorbed by variations in the memory cell current value, so the reference cell program is focused on reducing the required operating point of the sense amplifier. Is possible.

  According to the reference cell programming method of the seventh aspect of the invention, in addition to the effect of the first aspect, compared with the reference cell programming method of the fourth aspect, the iterative process for each VCCR initial value of the pulse verify loop is This eliminates the need to speed up the reference cell programming process. Contrary to the programming method of claim 6, the convergence of the target value of the memory cell current value is prioritized and the offset voltage of the sense amplifier is absorbed by the reference cell current value, so that the required operating point of the sense amplifier is reduced. This makes it possible to program the reference cell with more emphasis on the reliability of the memory cell.

  According to the nonvolatile memory device of the eighth and ninth aspects of the invention, the gate voltage of the memory cell and the reference cell is common in the read operation, the program verify operation, and the erase verify operation, and the external power source is used in the reference cell programming process. By preparing the chip, the hardware of the chip can be simplified. Further, the reference cell current can be adjusted and fixed for each nonvolatile memory device, and a read window margin common to the nonvolatile memory devices can be set. As a result, the required operating point width of the read sense amplifier can be reduced, and the read window margin from the blank state to the erase state of the memory cell can be made constant between chips.

  According to the nonvolatile memory device of the tenth and eleventh aspects of the invention, in the program verify operation and the erase verify operation, the reference cell is reduced to one type instead of using two types of gate voltages of the memory cell and the reference cell. Therefore, the hardware and program cost of the reference cell can be reduced. In addition, the reference cell current value can be adjusted and fixed for each nonvolatile memory device, and a common read window margin can be set between the nonvolatile memory devices. As a result, the required operating point width of the read sense amplifier can be reduced, and the read window margin from the blank state to the erase state of the memory cell can be made constant between chips.

  According to the nonvolatile memory device of the twelfth aspect of the present invention, high level verification can be realized under the same memory cell and reference cell bias conditions as program verification, and the output voltage of the built-in power supply can be suppressed low. Thus, it is possible to realize low power consumption and area reduction of the nonvolatile memory device.

  According to the nonvolatile memory device of the thirteenth aspect of the invention, in the virtual ground array, when the memory adjacent to the memory cell to be programmed is in the erased state, the high-level verify memory cell is selectively applied at the program verify time. This makes it possible to program by compensating for the cell current leaking to the adjacent cell, that is, to realize the same program state regardless of the presence or absence of the adjacent cell.

  According to the reference cell programming method of the fourteenth aspect of the present invention, in the virtual ground array, the PVH reference cell is programmed based on the memory cell current when the adjacent cell is in the erased state, and the PV reference cell is programmed in the adjacent cell The memory cell current is programmed with reference to the current. That is, it becomes possible to guarantee the leak current of the adjacent cell in a self-aligned manner for each chip. At the time of program verification, the PV reference is selected when the adjacent cell is in the programmed state, and the PVH reference cell is selected when the adjacent cell is in the programmed state. Therefore, it is possible to easily cancel the influence of the adjacent cell.

  Hereinafter, a reference cell programming method and a nonvolatile memory device using the same according to embodiments of the present invention will be described with reference to the drawings. In addition, embodiment shown below is an example to the last, and this invention is not necessarily limited to these embodiment.

(First embodiment)
FIG. 1 is a schematic configuration diagram of a source-side reading method of a memory cell using a reference cell in a nonvolatile memory device. Hereinafter, the operation of the differential sense amplifier will be described with reference to FIG.

  In the figure, the source of the memory cell 1014 and the source of the reference cell 1012 are connected to the input of the differential sense amplifier 1004 via the SL transistor 1011. Here, the SL transistor 1011 is a bit line selection transistor. Memory cell 1014 is part of a virtual ground array.

  A reference cell gate line 1009 is connected to the gate of the reference cell 1012, and a reference cell gate voltage VCR is applied. A memory cell gate line 1001 is connected to the gate of the memory cell 1014 and a memory cell gate voltage VCCR is applied. The two gate lines 1009 and 1001 constitute a word line of the memory array. The drains of the respective cells 1012 and 1014 are given a bias Vbias by the bit line voltage source 1010 via the SL transistor 1011.

  A reference cell 1012 is connected to the inverting input tref of the differential sense amplifier 1004, and a memory cell 1014 is connected to the normal input cmi. A discharge transistor 1013 is provided from each input tref, cmi to the ground GND, and the inputs tref, cmi of the differential sense amplifier 1004 can be initialized to a ground level at a desired timing.

  The reference cell current Iref of the reference cell 1012 and the memory cell current Icell of the memory cell 1014 are charged from the cell transistor source side by charging the bit line capacitance 1008 of the capacitance value Ctref and the bit line capacitance 1003 of the capacitance value Ccmi, respectively. The line potentials Vdbl (tref) and Vdbl (tref) are detected by the differential sense amplifier 1004. The differential sense amplifier 1004 amplifies a difference between the bit line potential Vdbl (tref) and the bit line potential Vdbl (cmi). The charging operation of the bit line capacitors 1008 and 1003 is started from the fall of the signal φ1 input from the discharge line 1002 of the discharge transistor 1013.

  If the two bit line potentials are “Vdbl (cmi)> Vdbl (tref)”, the differential sense amplifier 1004 determines that the memory cell 1014 is in the erased state (low VT state) and “1”. Output the status. In the opposite case, it is determined that the memory cell 1014 is in the program state (high VT state), and the “0” state is output. The output of the differential sense amplifier 1004 is sampled by the output latch 1005 at the rising timing of the latch signal φ2 from the latch signal line 1007 to determine the sense amplifier output SAO.

  Design the circuit so that the AC characteristics (time constant) of the input tref and the input cmi match more precisely so that the capacitance value of the bit line capacitance 1003 matches the capacitance value of the bit line capacitance 1008. For example, when the memory cell current and the reference cell current are “Icell≈Iref”, the output of the differential sense amplifier 1004 is in a transition state of “1” and “0”. That is, “Icell≈Iref” can be determined by detecting the output transition of the differential sense amplifier 1004.

  Further, when the AC characteristics of the input tref and the input cmi do not match, for example, when “Ctref = K × Ccmi (K> 0)”, the two cell currents become “Icell = K × Iref”. The output of the differential sense amplifier 1004 is in a transition state of “1” and “0”. In the present embodiment, for the sake of simplicity of explanation, the case where “K = 1” is assumed. In the case of “K> 0” or “K> 0”, by replacing with “Icell = K × Iref”, a constant K of which the temperature characteristics of the memory cell current Icell and the reference cell current Iref can be determined to be equal The same effect can be obtained in the range.

  FIG. 2 is a waveform diagram showing operation waveforms in the source side reading method of FIG. Hereinafter, a specific reading operation of the source side reading method will be described with reference to FIG.

  The read operation is started from the rising timing of the gate potential of each of the memory cell 1014, the reference cell 1012, and the SL transistor 1011. At this time, the discharge transistor 1013 is on, and the inputs tref and cmi are initialized to the ground level. When the time t has elapsed and the gate potential has stabilized (t = 0), the discharge transistor 1013 is turned off, the charging of the bit line capacitors Ctref and Ccmi starts, and the bit line potentials Vdbl (tref) and Vdbl (cmi) are It evolves with the passage of time t. When the latch signal φ2 is raised at the integration time (interval) t = Tint, the output of the differential sense amplifier 1004 is sampled. The logic of the sense amplifier output SAO of the differential sense amplifier 1004 is determined by the difference “Vopen = Vdbl (cmi) −Vdbl (tref)” of Vdbl at the integration time (t = Tint).

  The bit line potential Vdbl (tref) at the integration time (t = Tint) determines the operating point input level of the differential sense amplifier 1004. The differential sense amplifier 1004 exhibits constant performance (high gain, high noise rejection, low offset, low drift of these) against temperature / voltage fluctuations and process condition fluctuations near the operating point input level. Is required. In general, characteristic drift causes a read margin loss. Therefore, the read margin requires an extra margin value to compensate for the margin loss.

  Further, the operating point input level of the differential sense amplifier 1004 depends on the reference cell current value Iref and the charge capacity of the bit line capacity 1008 (approximated to be proportional to the reference cell current excluding the offset and inversely proportional to the charge capacity) Can). As an example, the fluctuation of the operating point input level when the present invention is not used is mainly due to variations in the reference cell current value. Under the condition that the bit line potential Vbias is about 2 V, the ground level is several tens to several hundred mV. It is necessary to design the operating point of the differential sense amplifier 1004 in accordance with this dynamic range.

  FIG. 3 is a diagram showing the relationship between the variation in the reference cell current value and the required movable operating point width of the differential sense amplifier.

  As shown in FIG. 4A, when the variation of the reference cell current value Iref for each nonvolatile memory device is large, the fluctuation range of the bit line potential Vdbl at the integration time Tint becomes large, and the differential sense amplifier needs to be larger. An operating point width is required.

  As shown in FIG. 5B, by converging the reference cell current Iref for each nonvolatile memory device to a constant value, the required operating point width of the differential sense amplifier is reduced, so that the temperature voltage range and process variations are reduced. It becomes easy to design an amplifier with suppressed characteristic drift.

  If only the required operating point width of the differential sense amplifier is to be reduced, when the access time is sufficient, variation in the reference cell current value is allowed and the timing of the integration time Tint is set for each nonvolatile memory device. Note that trimming is also possible, but not optimized in terms of the cycle margin described above.

  FIG. 4 is a flowchart showing a processing flow of the reference cell programming method according to the first embodiment of the present invention.

  Hereinafter, a reference cell programming method in the above nonvolatile memory device will be described.

  In the figure, the reference cell programming method of the present embodiment includes a gate voltage setting step for each of the memory cell and the reference cell in the program verify read operation, and a pulse verify loop S102 following the step.

  The gate voltage setting step is a procedure for setting the first program verify condition in the pulse verify loop S102. The memory cell gate voltage VCCR setting step S100 for setting the gate voltage of the memory cell and the gate voltage of the reference cell are set. And a reference cell gate voltage VCR setting step S101 to be set.

  In the memory cell gate voltage VCCR setting step S100, a gate voltage value (predetermined VCCR initial value INIT) to be applied to a blank memory cell at the time of program verification is set.

  FIG. 5 is a diagram showing the relationship between the cell current distribution and the memory cell gate voltage VCCR in the memory cell array.

  In the figure, the memory cell current distribution 150 is a distribution shape when the memory cell gate voltage value VCCR is V1 (@ VCCR = V1), and the memory cell current distribution 151 is when the memory cell gate voltage value VCCR is V2. (@ VCCR = V2) distribution shape. The memory cell current distribution 150 shifts the distribution shape to the low Icell side (left) like the memory cell current distribution 151 by lowering the memory cell gate voltage value VCCR from V1 to V2.

  In FIG. 4, a reference cell gate voltage VCR setting step S101 sets a gate voltage value to be applied to a reference cell to which a program pulse is applied during program verification. Here, the gate voltage VCR is set to an addition value “VCR = INIT + WM” obtained by adding a predetermined voltage margin value WM to the predetermined VCCR initial value INIT. The predetermined voltage margin is a value set in common with other nonvolatile memory devices. In a pulse verify loop S102 described later, the memory cell current Icell (VCCR = INIT) is copied to the reference cell current Iref (VCR = INIT + WM) by the verify operation using the read operation of the differential sense amplifier.

  The pulse verify loop S102 includes a loop of a reference cell program pulse application step S103 and a reference cell current verify step S104.

  In the reference cell program pulse application step S103, in order to gradually control the threshold value of the memory cell, for example, in a channel hot electron program type device, a high voltage between the drain and source is applied as a pulse. Such bias voltage level and pulse width must be small enough to achieve threshold control accuracy.

  In the reference cell current verify step S104, after applying a program pulse to the reference cell, all or some of the memory cells in the blank state among the memory cells to be read of the reference cell being programmed are read. And the reference cell current value are compared.

  Hereinafter, the sequence of the reference cell current verify step S104 will be described.

  First, in memory cell initial address setting step S105, an initial address for scanning a memory cell in a blank state is designated, and reference cell current determination step S106 is executed. In the reference cell current determination step S106, the reference cell current value Iref (VCR = INIT + WM) at the gate potential “VCR = INIT + WM”, the memory cell current value Icell (ADD) of the gate potential “VCCR = INIT”, address “ADD” .. Comparison with VCCR = INIT) is performed by verify reading by the differential sense amplifier described above.

  In the determination of the reference cell current determination step S106, a case where “K × Iref (VCR = INIT + WM) −Icell (ADD.VCCR−INIT) ≦ Δ1 (K = 1, Δ1≈0)” is determined as a path, and other cases Fail.

  When the determination at the reference cell current determination step S106 fails, the process loops to the reference cell program pulse application step S103.

  If the reference cell current determination step S106 is passed, the process branches to the memory cell address setting step S107, and the address of the next blank memory cell is calculated. Here, an increment or decrement is assumed as an address scan algorithm.

  Further, it is determined whether the calculated branch address is within the address range of the memory array or outside the address range in the address range determination step S108. When the scanning of the desired blank memory cell is outside the address range indicating completion, the programming of the reference cell is completed. If the calculated address is within the address range, a branch is made to the reference cell current determination step S106 to loop to check the remaining blank memory cells.

  The memory cell in all blank states is scanned by the memory cell address setting step S107 and the reference cell current determination step S106. When the reference cell current determination step S106 passes through the desired memory cell in the blank state, the programming of the reference cell is completed.

  FIG. 6 is a diagram showing the relationship between the reference cell current and the memory cell current during the reference cell programming operation.

  This figure is a distribution chart of cell currents in a blank state, the horizontal axis is the cell current value, and the vertical axis is the number of memory cells.

  Since the memory cell current distribution 152 has a constant gate bias, the distribution is fixed on the cell current value axis. The reference cell current 153 is an initial value before the program pulse is applied (PC = 0), and is the reference cell current according to the number of times the program pulse is repeatedly applied (as the program pulse count PC increases). The value decreases.

  In the figure, the reference cell current 155 that satisfies “Iref−Icell ≦ Δ1” is reached at a pulse count of 5 (PC = 5). In the threshold determination by the differential sense amplifier, the predetermined allowable value Δ1 is set in the vicinity of “0” if the input offset of the differential sense amplifier is ignored, and the reference cell current 155 is the memory cell current distribution 152 It corresponds to the cell current value at the lower end.

  Therefore, the reference cell current can converge to a constant value by adjusting the word line voltage VCCR = INIT of the memory cell for each nonvolatile memory device and keeping the cell current value at the lower end of the memory cell current distribution constant. it can. Thereby, the movable operating point range of the differential sense amplifier can be kept narrow.

  In addition, regarding the setting of the predetermined VCCR initial value INIT, for example, by referring to the PCM value that represents the threshold value of the memory cell on the same wafer, it can be set to a common value in wafer units or lot units, or non-volatile It can be determined with reference to a threshold value by sampling a specific memory cell in the memory device. This makes it possible to more easily set a predetermined VCCR initial value for each nonvolatile memory device when the manufacturing process is relatively stable, and to realize a reference cell program at a lower cost. it can.

  The window margin WM, which is a predetermined voltage margin of the reference cell, is set to a constant value with other nonvolatile memory devices in order to set an equivalent read margin in all nonvolatile memory devices. This allows setting the read gate voltage VCCR for each nonvolatile memory device. The fluctuation of the gate voltage VCCR for each nonvolatile memory device is about 5 to 10%, and the influence on the generation circuit of the gate line voltage VCCR is not great. In addition, the setting accuracy of the cycling margin can be improved by making the reference cell current constant.

  FIG. 7 is a diagram for explaining the definition of the offset voltage VOFS of the sense amplifier, and FIG. 8 is a diagram for explaining cell current conversion of the offset voltage VOFS of the sense amplifier.

  The offset voltage of the differential sense amplifier applied to the reference cell current will be described below with reference to FIGS.

  The offset voltage VOFS of the differential sense amplifier SA is a differential input potential at which the output voltage SAO is neutral. When the offset voltage VOFS exists for the input cmi and the input tref of the differential sense amplifier SA, when “Vdbl (cmi) ≧ Vdbl (tref) + VOFS”, the sense amplifier output SAO of the differential sense amplifier SA is “ SAO = 1 ”, and it is determined as an erased state. When “Vdbl (cmi) <Vdbl (tref) + VOFS”, the sense amplifier output SAO of the differential sense amplifier SA is “SAO = 0”, and it is determined that the program state.

  The offset voltage VOFS of the differential sense amplifier SA is caused by a systematic offset of the circuit and variations in threshold values of the transistors in the input stage.

  FIG. 8 shows the temporal evolution of the bit line potential at the time when the offset voltage VOFS exists in the differential sense amplifier SA, the application of the program pulse proceeds, and the sense amplifier output SAO changes from the erased state to the programmed state. Has been.

  In the figure, when the offset voltage VOFS is present in the differential sense amplifier SA, the reference cell current Iref is programmed smaller than the target current Icell (VCCR = INIT) by the offset current IOFS. The offset current IOFS is obtained by “IOFS = Ctref × VOFS / Tint” when the bit line capacitance is “Cmbl = Ctref = Ccmi”.

  Conversely, when Icell is programmed with reference to the reference cell current Iref, Icell is programmed larger than Iref by the offset current IOFS, and Icell is programmed to the target current Icell (VCCR = INIT). That is, the offset voltage VOFS of the differential sense amplifier SA is in a state equivalent to being completely canceled by being absorbed by the reference cell current value Iref.

  Assuming that the temperature / power supply voltage characteristics of the memory cell and the reference cell match with respect to the offset cancellation accuracy, drift due to temperature / power supply voltage fluctuations in the offset of the differential sense amplifier SA becomes an issue. However, the range of the reference cell current Iref can be maintained at a constant value as described above, and the movable operation condition of the differential sense amplifier SA may be narrow, an amplifier with a high gain can be configured, and the offset value itself can be reduced. Can withstand temperature and power supply voltage fluctuations.

  As described above, in this embodiment, the reference cell current can be adjusted to a desired constant value for each nonvolatile memory device, and a read window margin common to other nonvolatile memory devices can be set. . This reduces the required movable operating point range of the read differential sense amplifier, facilitates the design of the differential sense amplifier, improves the yield of the differential sense amplifier, and improves the characteristics of the differential sense amplifier. Further, it is possible to perform highly accurate threshold control of the erased state and the programmed state, and to realize more reliable reading. In addition, the cycle window from the blank state to the erased state of the memory cell can be optimally controlled, the cycling characteristics and the retention characteristics can be easily optimized, and the device characteristics can be maximized according to the market specification requirements. In addition, it is possible to provide a non-volatile memory device that is operated under optimum device conditions.

  In the present embodiment, in the reference cell current determination step S106, the memory cell current value and the reference cell current value are compared using the source side read type differential sense amplifier. The same effect can be obtained even when a voltage detection type reading method or a current detection type reading method is used.

(Second Embodiment)
FIG. 9 is a flowchart showing a processing flow of the reference cell programming method according to the second embodiment of the present invention.

  The only difference from the reference cell programming method of the first embodiment described above is that it further includes a reference cell current test step S202. Since other configurations are the same as those of the first embodiment, the description thereof is omitted.

  In the figure, a reference cell current test step S202 and a VCCR decrement step S205 are provided after the pulse verify loop S102. The reference cell programmed in the pulse verify loop S102 is tested for its cell current by the reference cell current test step S202.

  In reference cell current test step S202, the reference cell current is compared with its cell current target value Iref_EXP. In the reference cell current test step S202, when “| Iref (VCR = VCCR + WM) −Iref_EXP | ≦ Δ2” is satisfied, the reference cell program is completed (S203). When “| Iref (VCR = VCCR + WM) −Iref_EXP |> Δ2”, the magnitude relationship between the reference cell current Iref and the cell current target value Iref_EXP is further obtained.

  Then, when “Iref (VCR = VCCR + WM) <Iref_EXP”, the program of the reference cell fails as an overprogram state (S204). In the NROM type nonvolatile memory device, it is important to program the reference cell from the blank state, and it cannot be erased and returned to the blank state. Further, since it is known that the threshold value of the reference cell once erased has a large drift, the program is failed and ended as an overprogrammed state.

  Conversely, when the reference cell is not overprogrammed, that is, when “Iref (VCR = INIT + WM)> Iref_EXP”, the process branches to the VCCR decrement step S205. Thereafter, in the VCCR decrement step S205, the memory cell gate voltage value VCCR is subtracted by the increment value INC, “VCR = VCCR + WM” is updated in the reference cell gate voltage VCR setting step S201, and the process loops to the pulse verify loop 102 again.

  When the mutual conductance of the reference cell is Gm, the increment value INC is sufficiently smaller than “(Iref−Iref_EXP) / Gm”, thereby enabling control of the reference cell current value Iref.

  As described above, according to this embodiment, in the first embodiment described above, the predetermined VCCR initial value INIT is given to the gate voltage of the memory cell and the pulse verify loop S102 is executed. INIT can be automatically adapted to the target reference cell current Iref_EXP. At this time, at the start of programming of the reference cell, it is possible to control the reference current with high accuracy by giving a sufficiently high value to the VCCR initial value INIT and setting an appropriate increment value INC.

  In addition, it is possible to determine whether it is possible to add a program pulse to the reference cell, and it is a good reference cell that is overprogrammed due to an inappropriately large or sensitive program characteristic where the increment INC of the memory cell gate voltage VCCR is inappropriately large. Therefore, the reference cell program can be made more reliable.

  In FIG. 9, the reference cell current test step S202 and the VCCR decrement step S205 are provided separately, but the VCCR decrement step S205 may be provided inside the reference cell current test step S202. Of course.

(Third embodiment)
FIG. 10 is a flowchart showing a processing flow of the reference cell programming method according to the third embodiment of the present invention.

  The difference from the reference cell programming method of the first embodiment described above is that a reference cell gate voltage search step S320 and a memory cell gate voltage search step S312 are further performed before the memory cell gate voltage VCCR setting step S100. It is only a point that has. Since other configurations are the same as those of the first embodiment, the description thereof is omitted. In FIG. 10, only the reference cell gate voltage search step S320 and the memory cell gate voltage search step S312 are shown.

  In the figure, the VCCR initial value INIT is obtained by a sequence including a reference cell gate voltage search step S320 and a memory cell gate voltage search step S312.

  A processing flow in the reference cell gate voltage search step S320 will be described below.

  First, in the reference cell gate voltage initialization step S300, the gate voltage value VCR of the reference cell is set to the minimum voltage value VCR_MIN, and the reference cell current value Iref at that time is measured in the reference cell current measurement step S301. Thereafter, in the reference cell current determination step S302, the measured value Iref and the cell target value Iref_EXP are compared. In the reference cell current determination step S302, the reference cell gate voltage value VCR satisfying “| Iref (VCR) −Iref_EXP) | <Δ3” is output as the VCR set value LOCK.

  If “| Iref (VCR) −Iref_EXP) | ≧ Δ3” is determined in the reference cell current determination step S302, the process branches to the VCR increment step S319 to increment dVCR (> 0) to the gate voltage value VCR. . The incremented gate voltage value VCR is compared with the maximum gate voltage value VCR_MAX in the VCR determination step S318. If the gate voltage value VCR exceeds the maximum value VCR_MAX, the reference program ends in fail (S317). When the gate voltage value VCR is smaller than the maximum value VCR_MAX, the process loops again to the reference current measurement step S301.

  As described above, in the reference cell gate voltage search step S320, the reference cell gate voltage VCR = LOCK at which the reference cell current value Iref becomes the cell target value Iref_EXP is obtained, and the reference cell current value is set to a desired value Iref_EXP.

  The VCR set value LOCK obtained in the reference cell gate voltage search step S320 is taken over by the memory cell gate voltage search step S312. In the memory cell gate voltage search step S312, a predetermined VCCR initial value INIT that can reproduce the reference cell current value Iref_EXP is obtained.

  In the memory cell gate voltage search step S312, the reference cell gate voltage value VCR is fixed to the VCR set value LOCK, and the memory cell in the blank state is read by the differential sense amplifier while scanning the memory cell gate voltage value VCCR, and the program is performed. A gate voltage value VCCR = INIT of a memory cell in which the number of memory cells FBC determined to be in a state (pass expected value) is 1 or more and within FBC_MAX is obtained. In FIG. 6, this is equivalent to fixing the reference cell current 155, moving the memory cell current distribution 152 to the right, and keeping the number of memory cells belonging to Δ1 within 1 or more and FBC_MAX.

  A processing flow in the memory cell gate voltage search step S312 will be described below.

  First, in the VCCR initialization step S304, the memory cell gate voltage value VCCR is set to the maximum value VCCR_MAX. In FBC / ADD initialization step S305, the pass bit number FBC and the memory cell address ADD are set. Next, only when the sense amplifier read step S306 is executed and the read result determination step S307 is passed, the FBC count is incremented in the FBC count up step S308.

  If the address does not match the maximum address ADD_MAX in ADD determination step S309, the address is incremented in ADD increment step S316, and the process loops to the sense amplifier read step S306. If the address matches the maximum address ADD_MAX in the ADD determination step S309, the address scan is completed, and the pass bit number FBC is determined in the FBC determination step S310.

  In the FBC determination step S310, when “0 <FBC ≦ FBC_MAX”, a predetermined VCCR initial value INIT is determined. When “FBC = 0” or “FBC> FBC_MAX”, the set value of the memory cell gate voltage value VCCR is decremented by dVCCR in the VCCR decrement step S315. The decremented gate voltage value VCCR is compared with the lower limit value VCCR_MIN of the memory cell gate voltage value VCCR in the VCCR determination step S314. When “VCCR <VCCR_MIN”, the reference cell program fails. If “VCCR ≧ VCCR_MIN”, loop back to the FBC • ADD initialization step S304, scan the address under the new setting conditions, and count FBC.

  Here, as FBC_MAX is set to a smaller value (> 1), the accuracy of setting the reference cell current value Iref in a later program sequence is improved.

  As described above, in the present embodiment, the predetermined VCCR initial value INIT can be obtained in advance, and compared with the second embodiment described above, the iterative process for each VCCR initial value INIT of the pulse verify loop is performed. This eliminates the need to speed up the reference cell programming process.

  In addition, priority is given to the convergence of the reference cell current value to the target value, the offset voltage of the differential sense amplifier is absorbed in the variation of the memory cell current value, and the reference is focused on reducing the required operating point of the differential sense amplifier. The cell can be programmed.

(Fourth embodiment)
FIG. 11 is a flowchart showing a processing flow of the reference cell programming method according to the fourth embodiment of the present invention.

  The difference from the reference cell programming method of the first embodiment described above is that a high VT memory cell search step S400 and a memory cell gate voltage search step S410 are further provided before the memory cell gate voltage VCCR setting step S100. It is only a point that has. Since other configurations are the same as those of the first embodiment, the description thereof is omitted. In FIG. 10, only the high VT memory cell search step S400 and the memory cell gate voltage search step S410 are shown.

  In the drawing, a predetermined VCCR initial value INIT is determined by a sequence including a high VT memory search step S400 and a memory cell gate voltage search step S410.

  In the high VT memory search step S400, the differential sense amplifier is set to the operating point range by setting the current of the reference cell in the blank state to an appropriate gate voltage value VCR (which allows a relatively wide range of conditions). Set to. Then, the memory cell address group having the highest threshold value in the memory array distribution is extracted from the memory array (memory cell group) by margin reading.

  In the high VT memory search step S400, first, in the VCR initialization step S401, the gate voltage value VCR of the reference cell is set to VCR_INIT. Since this step is only for checking the relative threshold value, the reference cell current is only set in a range in which the differential sense amplifier can be operated, and the current setting accuracy is allowed to some extent. For example, appropriate values such as design values and process representative values can be used.

  When the setting of the reference gate voltage value VCR is completed, in the FBC / ADD / VCCR initialization step S402, the memory cell address ADD and the pass bit number FBC are initialized to “0” and the memory cell gate voltage value VCCR is set to the maximum value. Initialize to VCCR_MAX. Next, only when the sense amplifier read step S403 is executed and the read result determination step S404 passes, the FBC count is incremented in the FBC count-up step S405, and the FBC value is stored in the fail address storage buffer ABUF. The fail address is stored in.

  Thereafter, if the address does not match the maximum address ADD_MAX in ADD determination step S407, the address is incremented in ADD increment step S425, and the process loops to the sense amplifier read step S403. If the address matches the maximum address ADD_MAX in the ADD determination step S407, the address scan is completed, and the pass bit number FBC is determined in the FBC determination step S408.

  In the FBC determination step S408, when “0 <FBC ≦ FBC_MAX”, the address information “ABUF [n], n = 0, 2,... FBC of the FBC memory cells from the high VT side in the memory array. ABUF / FBC data 409 is obtained. When “FBC = 0” or “FBC> FBC_MAX”, the set value of the memory cell gate voltage value VCCR is decremented by dVCCR in the VCCR decrement step S424. The decremented VCCR value is compared with the lower limit value VCCR_MIN of VCCR in the VCCR determination step S423, and when “VCCR <VCCR_MIN”, it becomes the program failure S422 of the reference cell. If “VCCR ≧ VCCR_MIN”, the process loops back to the FBC / ADD / VCCR initialization step S402, scans addresses under the new setting conditions, and executes FBC count and address collection.

  As described above, in the high VT memory search step S400, an arbitrary number of memory cells on the high VT side can be specified.

  Thereafter, in the next memory cell gate voltage search step S410, the memory cell current on the high VT side is set in the vicinity of the desired value Icell_EXP. Here, contrary to the third embodiment, the cell current on the memory cell side is fixed.

  In memory cell gate voltage search step S410, the memory cell gate voltage value VCCR is searched by current measurement. First, in VCCR initialization step S411, the memory cell gate voltage value VCCR is set to the minimum value VCCR_MIN, and the scan is performed on the cell current minimum side. Next, in FBC_T initialization step S412, FBC_T which is an index variable of ABUF is initialized to “0”. In an address generation step S413, a cell address ADD is generated (ABUF [FBC_T]), and in the cell current measurement step S414, the cell current is measured. This measured value is compared with the target current Icell_EXP in the cell current determination step S415.

  In the cell current determination step S415, when “| Icell (VCCR) −Icell_EXP | ≦ Δ4”, the VCCR initial value INIT is determined. Further, when “| Icell (VCCR) −Icell_EXP |> Δ4”, FBC_T is incremented in FBC_T increment step S421, and when “FBC ≦ FBC_T” in FBC_T determination step S420, the process loops back to address generation step S413. When “FBC> FBC_T”, the process branches to the VCCR decrement step S419, the VCCR set value is decreased by dVCCR, and the set VCCR is compared with the minimum value of the memory cell gate voltage value VCCR in the VCCR determination step S418. At this time, if “VCCR <VCCR_MIN”, the reference cell program converges to the program fail step S417. When “VCCR> VCCR_MIN”, the process loops back to the FBC_T initialization step S412 to search for a memory cell under a new VCCR condition. Here, the accuracy of setting the Iref value in the later program sequence increases as FBC_MAX is set to a smaller value (> 1).

  As described above, according to the present embodiment, the iterative process for each VCCR initial value INIT of the pulse verify loop is not required, and the reference cell programming process can be made faster than the second embodiment. Contrary to the third embodiment, priority is given to the convergence of the memory cell current to the target value, the offset voltage of the sense amplifier is absorbed in the reference cell current, and the memory is more effective than the reduction of the required operating point of the sense amplifier. The reference cell can be programmed with emphasis on cell reliability.

(Fifth embodiment)
FIG. 12 is a configuration diagram showing a main configuration of a nonvolatile memory device according to the fifth embodiment of the present invention. The nonvolatile memory device of this embodiment is an example of a nonvolatile memory device to which the above-described reference cell programming method is applied. This figure shows a characteristic structure corresponding to one bit of a read word of the nonvolatile memory device.

  In the figure, the nonvolatile memory device includes a virtual ground array type memory cell array (VGA) 503, a reference cell array 513, and a differential sense amplifier 508 for source side reading. Since the source side reading method is the same as that of the first embodiment, the description thereof is omitted.

  A memory cell array (VGA) 503 is a virtual ground type memory, and shares drain and source bit lines with adjacent memory cells. In the figure, the selected state of the memory cell is shown. The selected memory cell 506 is in a selected state, the voltage value VCCR is biased to the memory cell gate line 505, and the bit line voltage source 500 is connected between the selected bit line (memory cell source) 515 and the selected bit line (memory cell drain) 516. To bit line voltage Vbias is applied. The non-selected memory cell is set to the cut-off state with the voltage of the non-selected memory cell gate line 504 set to the ground potential and the non-selected bit line 502 set to floating.

  The reference cell array 513 includes an EV reference cell 512 for erase verification, an RD reference cell 511 for read operation, and a PV reference cell 510 for program verification. Each reference cell 510, 511, 512 has a common bit line. Each of the reference cells 510, 511, and 512 is selected by applying a desired bias VCR to the selected reference cell gate line 514 and applying a ground potential to the gates of unselected cells.

  In the present embodiment, an example in which the drain is shared is shown as the configuration of the reference cell array 513. In this case, there is a possibility that the threshold interference between the reference cells due to the drain disturb slightly occurs in the memory cell. If the threshold interference between the reference cells due to gate disturb is at a level that does not cause a problem, the word line may be shared and the reference cell may be selected by selecting the source line.

  Further, each reference cell may be arranged in an independent array 510, 511, 512, or cells at diagonal positions on the array may be used so that the drain / source / gate lines are independent.

  In the program verify, erase verify, and read operations of the nonvolatile memory device, the memory cell gate line 505 and the reference cell gate line 514 are connected to bias the voltage VCR having the same potential.

  For each of the EV reference cell 512, the RD reference cell 511, and the PV reference cell 510, the above-described programming method of the reference cell is applied, and the gate lines of the reference cells 512, 511, and 510 are sequentially arranged. With the gate voltage value “VCR = EV”, the gate voltage value “VCR = RD”, and the gate voltage value “VCR = PV” set, each reference current is IEV, IRD, IPV, and It is programmed so that “IEV = IRD = IPV = Icell (VCCR = INIT)”.

  The memory cell in the programmed state by the program verify operation is programmed so that an IPV current flows when PV is applied to the gate voltage. When the read gate voltage RD is applied to the programmed cell, the cell current is reduced by the amount of decrease in the gate potential “PV−RD”. This becomes a read margin of the program cell.

  Similarly, the cell current is increased by “RD−EV” for the erase cell. This creates an erase cell read margin.

  As described above, the margin value of the VT window is preferably set to a constant value for each technology of the memory cell in order to build the reliability of the memory cell.

  Here, the read margin of the erase cell is set to a constant value “EM = RD−EV (> 0)” with another nonvolatile memory device. The read margin of the program cell is set to a constant value “PM = PV−RD (> 0)”. That is, the relationship of “PV> RD> EV” is established. The value of EV is an eigenvalue between the nonvolatile memory devices in order to keep the current value of the reference cell constant with other nonvolatile memory devices. As a result, the values of RD and PV are also unique values between the nonvolatile memory devices.

  As described above, in this embodiment, the gate voltage of the memory cell and the reference cell is common in the read, program verify, and erase verify operations, and the nonvolatile power supply is prepared by preparing an external power supply in the reference cell programming process. The hardware of the memory device can be simplified. Further, the reference cell current can be adjusted and fixed for each nonvolatile memory device, and a read window margin common to other nonvolatile memory devices can be set. As a result, the required operating point width of the read sense amplifier can be reduced, and the read window margin from the blank state to the erased state of the memory cell can be made constant with other nonvolatile memory devices.

(Sixth embodiment)
FIG. 13: is a block diagram which shows the principal part structure of the non-volatile memory device of the 6th Embodiment of this invention. The nonvolatile memory device of this embodiment is an example of a nonvolatile memory device to which the above-described reference cell programming method is applied. This figure shows a characteristic structure corresponding to one bit of a read word of the nonvolatile memory device.

The reference array 513 is different from the nonvolatile memory device of the fifth embodiment described above.
Instead, only a single PV / RD / EV reference cell 600 shared by the program verify, erase verify, and read operations is provided. Since other configurations are the same as those of the fifth embodiment, the description thereof is omitted.

  In the program verify, erase verify, and read operations of the nonvolatile memory device, the gate voltage VCCR of the memory cell gate line 505 is given the gate voltage values of PV, EV, and RD, respectively, and the reference cell gate line 514 has A constant reference cell gate voltage RD is always biased.

  The reference cell programming method described above is applied to the PV, RD, and EV reference cell 600. The reference cell gate line 514 is set with the gate voltage value of “VCR = RD” set to other nonvolatile memory. A reference cell current value “IRD = IIcell (VCCR = INIT)” of a constant value is programmed with the apparatus.

  By the program verify operation, the programmed memory cell is programmed such that an IRD cell current flows with PV applied to the gate voltage. When the read gate voltage RD is applied to the program cell, the cell current is decreased by “PV−RD” corresponding to the decrease in the gate potential. This becomes a read margin of the program cell. Similarly, the cell current is increased by “RD−EV” for the erase cell. This creates an erase cell read margin.

  As described above, the margin value of the VT window is preferably set to a constant value for each technology of the memory cell in order to build the reliability of the memory cell.

  Here, the read margin of the erase cell is set to a constant value “EM = RD−EV (> 0)” with another nonvolatile memory device. The read margin of the program cell is set to a constant value “PM = PV−RD (> 0)”. That is, the relationship of “PV> RD> EV” is established. The value of EV becomes an eigenvalue between the nonvolatile memory devices in order to keep the current value of the reference cell constant with other nonvolatile memory devices. As a result, the values of RD and PV are also unique values between the nonvolatile memory devices.

  As described above, in the present embodiment, in the program verify and erase verify operations, only one type of reference cell needs to be arranged instead of two types of gate voltages applied to the memory cell and the reference cell. The area of the memory device can be reduced, and the hardware cost and program cost of the reference cell can be reduced.

  In addition, the reference cell current can be adjusted and fixed for each nonvolatile memory device, and a read window margin common to other nonvolatile memory devices can be set.

  As a result, the required operating point width of the read sense amplifier can be reduced, and the read window margin from the blank state to the erased state of the memory cell can be made constant with other nonvolatile memory devices.

(Seventh embodiment)
FIG. 14: is a block diagram which shows the principal part structure of the non-volatile memory device of the 7th Embodiment of this invention. The nonvolatile memory device of this embodiment is an example of a nonvolatile memory device to which the above-described reference cell programming method is applied. This figure shows a characteristic structure corresponding to one bit of a read word of the nonvolatile memory device.

  The only difference from the nonvolatile memory device of the fifth embodiment described above is that a PVH reference cell 700 is further provided inside the reference cell array 702. Since other configurations are the same as those of the fifth embodiment, the description thereof is omitted.

  In this embodiment, a high-level verify operation is added to the operations of the nonvolatile memory device in addition to the program verify, erase verify, and read operations. The high-level verify operation is a program verify operation that compensates for an erroneous determination of program verify due to a cell current outflow effect (hereinafter referred to as an adjacent cell effect) at the time of reading inherent to the virtual ground array.

  Hereinafter, the neighbor cell effect will be described.

  FIG. 15 is a configuration diagram showing a memory cell array in a blank state, and FIG. 16 is a configuration diagram showing the memory cell array after physical checker writing.

  In FIG. 15, the gate bias of the selected memory cell 904 biases the adjacent memory cell 908, and part of the memory cell current 905 (current value Icell) is a leakage current 907 (current) to the adjacent memory cell 908 in the blank state or erased state. It leaks by the value Ine). For this reason, the sense amplifier input current 906 (current value Isa), which is a current detected by the sense amplifier, decreases. That is, the current value Isa of the sense amplifier input current 906 is “Isa = Icell−Ine”.

  On the other hand, as shown in FIG. 16, when the memory array is programmed to the physical checker state so that the adjacent memory cell 908 is in the programmed state, the leakage current 907 (current value Ine) is greatly reduced, and the sense amplifier input current Isa is It increases like “Isa = Icell”.

  As described above, the neighbor cell effect is that the current detected by the sense amplifier changes depending on the program state of the neighbor cell. This adjacent cell effect is because when the cell in which the adjacent cell is in the erased state is programmed, the cell current appears to be small due to the leakage current to the adjacent cell, so that the program ends with an insufficient number of program pulses applied, Fewer program injections. When an adjacent cell is programmed, the memory cell current increases, so that the threshold value appears to decrease, and it is predicted that the retention characteristic is deteriorated due to a program margin loss during reading or electron injection at a low dose.

  In FIG. 14, a PVH reference cell 700 is a reference cell used when program verifying a memory cell in which an adjacent cell is in an erased state. The program verify at this time is called high-level verify.

  To realize high-level verification, it is possible to increase the gate potential to the gate voltage value of “VCCR = VCR” during verification, or to lower the potential by independently controlling the gate potential VCR of the reference cell from VCCR. In this embodiment, PV is set similarly to the program verify, and the PVH reference cell is programmed so that the reference cell current becomes “IPV> IPVH”. High-level verification can be realized under the same conditions except that program verification differs from the selected reference cell.

  As described above, according to the present embodiment, high level verification can be realized under the same memory cell and reference cell bias conditions as program verification, and the output voltage of the built-in power supply can be kept low. Thus, the power consumption and area of the nonvolatile memory device can be reduced.

  Further, in the virtual ground array, when the memory adjacent to the memory cell to be programmed is in the erased state, the cell current leaking to the adjacent cell is compensated by selectively applying the high-level verification memory cell during program verification. It is possible to realize the same program state regardless of whether or not there is a neighboring cell.

(Eighth embodiment)
FIG. 17 is a flowchart showing a processing flow of the reference cell programming method according to the eighth embodiment of the present invention. The reference cell programming method of this embodiment is a programming method of programming the PVH reference cell and the PV reference cell of the seventh embodiment.

  In the figure, the reference cell programming method is constituted by a sequence executed in the order of PVH reference cell program step S800, physical checker program step S801, and PV reference cell program step S802.

  In PVH reference cell program step S800, the cell current of the blank memory cell array is used as a reference, that is, based on the cell current of the memory cell affected by the adjacent cell (based on the cell current lost due to the adjacent effect). Program the reference cell current to IPVH.

  In the physical checker program step S801, the reference cells programmed in the PVH reference cell program step S800 are programmed to alternately repeat the programmed memory cells and the blank memory cells in the word line direction. Program to a physical checker state. The program state of this physical checker is the state of FIG.

  Then, in the PV reference cell programming step S802, of the memory cell array programmed in the physical checker, the reference is based on the memory cell current in the blank state, that is, on the basis of the cell current of the memory cell from which the influence of the adjacent effect is eliminated. Program the cell current to IPV.

  Here, since “IPVH <IPV”, if the PVH reference cell is programmed, the threshold value of the memory cell is set higher. This effect works to cancel the threshold drop due to the neighbor cell effect.

  FIG. 18 is a flowchart showing a processing flow in the PVH reference cell program step S800 in the reference cell programming method of the present embodiment.

  In the figure, the process is performed in the same manner as the reference cell programming method of the first embodiment except that a PVH reference cell selection step S803 is added.

  FIG. 19 is a flowchart showing a processing flow in the memory cell physical checker program step S801 in the reference cell programming method of this embodiment.

  In the figure, a memory cell program pulse application step S816 is provided in place of the reference cell program pulse application step, and the algorithm in this step S816 is based on the point that the program pulse is applied to the memory cell instead of the reference, and the address range. Is limited to the range corresponding to the physical checker, and the gate voltage condition in the cell current determination step S818 is changed to “VCCR = VCR”, the reference cell programming method of the first embodiment The process is performed in the same manner as.

  FIG. 20 is a flowchart showing a processing flow in the PV reference cell program step S802 in the reference cell programming method of the present embodiment.

  In the figure, the reference of the first embodiment, except that the PV reference cell selection step S821 is added and the address operation range is limited to the address of the cell in the blank state in the pulse verify loop S815. Processing is performed in the same manner as the cell programming method.

  As described above, according to the present embodiment, in the virtual ground array, the PVH reference cell is programmed based on the memory cell current when the adjacent cell is in the erased state. The PV reference cell is programmed based on the memory cell current when the adjacent cell is in the programmed state. That is, it becomes possible to guarantee the leak current of adjacent cells in a self-aligned manner for each nonvolatile memory device. Thus, at the time of program verification, the PV reference is selected only when the adjacent cell is in the programmed state, and the PVH reference cell is only selected when the adjacent cell is in the programmed state, and the influence of the adjacent cell can be canceled very easily. It becomes possible.

  As described above, the present invention can adjust the reference cell current value to a desired constant value for each nonvolatile memory device and can set a common readout window margin between the nonvolatile memory devices. This is useful as a reference cell programming method and a non-volatile memory device using the same.

It is a schematic block diagram of the memory cell source side read system using the reference cell in the nonvolatile memory device. FIG. 2 is a waveform diagram of operation waveforms in the source side readout method of FIG. 1. FIGS. 7A and 7B are diagrams showing the relationship between the variation in the reference cell current value and the required movable operating point width of the differential sense amplifier. It is a flowchart of the processing flow of the programming method of the reference cell of the 1st Embodiment of this invention. It is the figure which showed the relationship between the cell current distribution in a memory cell array, and the memory cell gate voltage VCCR. FIG. 6 is a diagram showing a relationship between a reference cell current and a memory cell current during a reference cell program operation. It is a figure explaining the definition of offset voltage VOFS of a sense amplifier. It is a figure explaining cell current conversion of offset voltage VOFS of a sense amplifier. It is a flowchart of the processing flow of the programming method of the reference cell of the 2nd Embodiment of this invention. It is a flowchart of the processing flow of the programming method of the reference cell of the 3rd Embodiment of this invention. It is a flowchart of the processing flow of the programming method of the reference cell of the 4th Embodiment of this invention. It is a block diagram of the principal part structure of the non-volatile memory device of the 5th Embodiment of this invention. It is a block diagram of the principal part structure of the non-volatile memory device of the 6th Embodiment of this invention. It is a block diagram of the principal part structure of the non-volatile memory device of the 7th Embodiment of this invention. It is a block diagram of a memory cell array in a blank state. It is a block diagram of the memory cell array after physical checker writing. It is a flowchart of the processing flow of the programming method of the reference cell of the 8th Embodiment of this invention. It is a flowchart of the processing flow in PVH reference cell program step S800 in the programming method of the reference cell. It is a flowchart of the processing flow in memory cell physical checker program step S801 in the programming method of the reference cell. FIG. 7 is a flowchart of a processing flow in a PV reference cell program step S802 in the reference cell programming method.

Explanation of symbols

S100, S200 Memory cell gate voltage VCCR setting step
S101, S201 Reference cell gate voltage VCR setting step
S102 Pulse verify loop
S103 Reference cell program pulse application step
S104 Reference cell current verify step
S105 Memory cell initial address setting step
S106 Reference cell current judgment step
S107 Memory cell address setting step
S108 Address range judgment step
150, 151, 152 Memory cell current distribution
153, 155 Reference cell current
S202 Reference cell current test step
S203 program path
S204 Program Fail
S205 VCCR decrement step
S300 Reference cell gate voltage initialization step
S301 Reference cell current measurement step
S302 Reference cell current judgment step
303 VCR setting value LOCK
S304 VCCR initialization step
S305 FBC / ADD initialization step
S306 Sense amplifier read step
S307 Read result judgment step
S308 FBC count-up step
S309 ADD judgment step
S310 FBC judgment step
311 VCCR initial setting value INIT
S312 Memory cell gate voltage search step
S313 Program Fail
S314 VCCR judgment step
S315 VCCR decrement step
S316 ADD increment step
S317 Program Fail
S318 VCR judgment step
S319 VCR increment step
S320 Reference cell gate voltage search step
S400 High VT memory cell search step
S401 VCR initialization step
S402 FBC / ADD / VCCR initialization step
S403 Sense amplifier read step
S404 Read result judgment step
S405 FBC count-up step
S406 ADD save step
S407 ADD judgment step
S408 FBC judgment step
409 ABUF / FBC data
S410 Memory cell gate voltage search step
S411 VCCR initialization step
S412 FBC_T initialization step
S413 Address generation step
S414 Cell current measurement step
S415 Cell current judgment step
S416 VCCR initial value INIT
S417 Program Fail
S418 VCCR judgment step
S419 VCCR decrement step
S420 FBC_T judgment step
S421 FBC_T increment step
S422 program fail
S423 VCCR judgment step
S424 VCCR decrement step
S425 ADD increment step
500 bit line voltage source
501 Bit line selection gate
502 Unselected bit line
503 Memory cell array (VGA)
504 Unselected memory cell gate line
505 Memory cell gate line
506 Selected memory cell
507 discharge line
508 differential sense amplifier
509 Sense amplifier output
510 Reference cell
511 RD reference cell
512 EV reference cell
513 Reference cell array
514 Reference cell gate line
515 Selected bit line (memory cell source)
516 Selected bit line (memory cell drain)
600 PV / RD / EV reference cell
700 PVH reference cell
701 PV reference cell
702 Reference cell array
S800 PVH reference cell program step
S801 Memory cell physical checker program step
S802 PV reference cell program step
S803 PVH reference cell selection step
S804 Memory cell gate voltage VCCR setting step
S805 Reference cell gate voltage VCR setting step
S806 Pulse verify loop
S807 Reference cell program pulse application step
S808 Reference cell current verification step
S809 Memory cell initial address setting step
S810 Reference cell current judgment step
S811 Memory cell address setting step
S812 Address range judgment step
S813 Reference cell / memory cell gate voltage setting step
S814 Memory cell physical checker initial address setting step
S815 Pulse verify loop
S816 Reference cell program pulse application step
S817 Reference cell current verification step
S818 Cell current judgment step
S819 Memory cell physical checker address setting step
S820 Address range judgment step
S821 PV reference cell selection step
S822 Memory cell gate voltage VCCR setting step
S823 Reference cell gate voltage VCR setting step
S824 Pulse verify loop
S825 Reference cell program pulse application step step
S826 Reference cell current verify step
S827 Memory cell initial address setting step
S828 Reference cell current judgment step
900 Selected bit line (memory cell drain)
901 Unselected bit line
902 Unselected word line (memory cell gate)
903 Selected word line
904 Selected memory cell
905 Memory cell current
906 Sense amplifier input current
907 Adjacent memory cell leakage current
908, 909 Adjacent memory cell
910 Selected bit line (memory cell source)
1000 bit line select gate
1001 Memory cell gate line
1002 discharge line
1003 Memory cell bit line side parasitic capacitance
1004 differential sense amplifier
1005 Output latch
1006 Sense amplifier output
1007 Latch signal line
1008 Parasitic capacitance on the reference cell bit line side
1009 Reference cell gate line
1010 Bit line voltage source

Claims (14)

A method of programming a reference cell in a nonvolatile memory device comprising a plurality of blank memory cells and a reference cell,
A memory cell gate voltage VCCR setting step for setting a predetermined VCCR initial value determined for each nonvolatile memory device to be given to a gate voltage of the plurality of memory cells;
Reference cell gate voltage VCR setting for setting an added value of a predetermined voltage margin determined in common with other nonvolatile memory devices and the predetermined VCCR initial value to the gate voltage of the reference cell Steps,
A reference cell program pulse applying step for applying a program pulse to the reference cell;
A reference cell current verify step for verifying a reference cell current of the reference cell,
The reference cell program pulse applying step and the reference cell current verify step constitute a pulse verify loop,
In the reference cell current verify step,
The memory cell current value of each of the plurality of memory cells to which the gate voltage of the predetermined VCCR initial value is applied is compared with the reference cell current value of the reference cell to which the gate voltage of the added value is applied,
When the difference value between each of the memory cell current values and the reference cell current value is within a predetermined allowable value, the program branches from the pulse verify loop to complete the programming of the reference cell. Reference cell programming method. In the reference cell programming method according to claim 1,
The reference VCCR programming method, wherein the predetermined VCCR initial value is a value correlated with a memory cell current value outside the nonvolatile memory device. In the reference cell programming method according to claim 1,
The predetermined VCCR initial value is a value correlated with a memory cell current value inside the nonvolatile memory device. In the reference cell programming method according to claim 1,
In addition, it has a reference cell current test step,
In the reference cell current test step,
Applying the gate voltage of the added value to a reference cell programmed in the pulse verify loop;
Then, the reference cell current value of the reference cell and the cell current target value of the reference cell are compared,
When the difference value between the reference cell current value and the cell current target value is within a predetermined allowable value, the programming of the reference cell is completed,
When the difference value is larger than the predetermined allowable value, the predetermined VCCR initial value is decremented by a predetermined increment value and branched to the pulse verify loop. In the reference cell programming method according to claim 4,
When the difference value is larger than the predetermined allowable value and the reference cell current value is smaller than the cell target value, the programming of the reference cell is completed as a failure. In the reference cell programming method according to claim 1,
Furthermore, a reference cell gate voltage search step, and a memory cell gate voltage search step,
In the reference cell gate voltage search step,
Obtaining a reference cell gate voltage value at which a difference value between a reference cell current value of the reference cell and a cell current target value of the reference cell is a predetermined allowable value or less;
In the memory cell gate voltage search step,
In a state where the reference cell gate voltage value obtained in the reference cell gate voltage search step is applied to the reference cell, the gate voltage value applied to the plurality of memory cells is changed to change the memory cell of those memory cells. Comparing the current value with the reference cell current value of the reference cell, the gate voltage of the memory cell in which the number of memory cells determined that the memory cell current value is smaller than the reference cell current value is within a predetermined range Find the value
A reference cell programming method, wherein the gate voltage value obtained in the memory cell gate voltage search step is set as the predetermined VCCR initial value. In the reference cell programming method according to claim 1,
Furthermore, a high VT memory cell search step and a memory cell gate voltage search step are provided,
In the high VT memory cell search step,
With the reference cell gate voltage value set so that the reference cell current value is within a predetermined operating range for the reference cell, the gate voltage values of the plurality of memory cells are changed. The memory cell current value of each of the plurality of memory cells is compared with the reference cell current value of the reference cell, and the number of memory cells determined that the memory cell current value is smaller than the reference cell current value is Storing a memory cell address belonging to the number of memory cells when within a predetermined range;
In the memory cell gate voltage search step,
With respect to all memory cells having memory cell addresses belonging to the number of memory cells, a gate voltage value of a memory cell in which a difference value between a memory cell current value of each memory cell and a memory cell current target value is equal to or less than a predetermined allowable value Seeking
A reference cell programming method, wherein the gate voltage value obtained in the memory cell gate voltage search step is set as the predetermined VCCR initial value. A plurality of memory cells;
At least one reference cell array;
With a differential sense amplifier,
The at least one reference cell array includes:
An EV reference cell for erase verification selected at the time of erase verification, an RD reference cell for read operation selected at the time of read, and a PV reference cell for program verification selected at the time of program verification,
The EV reference cell is biased with an erase gate voltage value during an erase verify operation, and allows an erase reference cell current to flow.
The RD reference cell is biased by a read gate voltage value during a read operation and allows a read reference cell current to flow.
The PV reference cell is biased with a program gate voltage value during a program operation, and flows a program reference cell current.
The current value of the erase reference cell current, the current value of the read reference cell current, and the current value of the program reference cell current are set to a predetermined value common to other nonvolatile memory devices,
In order of the program gate voltage value, the read gate voltage value, and the erase gate voltage value, each gate voltage value is high,
The erase gate voltage value is a value determined for each nonvolatile memory device,
The difference value between the read gate voltage value and the erase gate voltage value, and the program gate voltage value, the read gate voltage value, and the difference value are respectively predetermined values that are common to other nonvolatile memory devices. A non-volatile memory device, wherein 9. The nonvolatile memory device according to claim 8, wherein
The non-volatile memory device according to claim 1, wherein the predetermined value common to the other non-volatile memory device is set using the reference cell programming method according to claim 1. A plurality of memory cells;
A reference cell;
With a differential sense amplifier,
The reference cell is used in common during erase verify, read operation, and program verify,
During the erase verify operation, the reference cell is biased with a read gate voltage value to pass a predetermined reference cell current, and the memory cell is biased with an erase gate voltage value.
During a read operation, the reference cell is biased with the read gate voltage value to pass the predetermined reference cell current, and the memory cell is biased with the read gate voltage value,
During the program operation, the reference cell is biased with the read gate voltage value to flow the predetermined reference cell current, and the memory cell is biased with the program gate voltage value.
The current value of the predetermined reference cell current is set to a predetermined value common to other nonvolatile memory devices,
In order of the program gate voltage value, the read gate voltage value, and the erase gate voltage value, each gate voltage value is high,
The erase gate voltage value is a value determined for each nonvolatile memory device,
The difference value between the read gate voltage value and the erase gate voltage value and the difference value between the program gate voltage value and the read gate voltage value are respectively predetermined predetermined values common to other nonvolatile memory devices. A non-volatile memory device characterized by being set to a value. The nonvolatile memory device according to claim 10, wherein
The non-volatile memory device according to claim 1, wherein the predetermined value common to the other non-volatile memory device is set using the reference cell programming method according to claim 1. 9. The nonvolatile memory device according to claim 8, wherein
The at least one reference cell array includes:
Furthermore, it has a PVH reference cell for high-level program operation that is selected during high-level program verification,
The PVH reference cell is biased with the program gate voltage value during a high level program verify operation, and causes a high level program reference cell current to flow.
The non-volatile memory device, wherein a current value of the high-level program reference cell current is set to a value smaller than a current value of the program reference cell current. The nonvolatile memory device according to claim 12, wherein:
The plurality of memory cells are virtual ground arrays having a common drain bit line,
A nonvolatile memory device, wherein a difference value between a current value of the program reference cell current and a current value of the high-level program reference cell current corresponds to a cell current leak value to an adjacent memory cell. A PVH reference cell for high-level program operation and a reference cell programming method for a PV reference cell for program operation,
PVH reference cell programming step for programming the PVH reference cell;
A physical checker program step for programming a plurality of memory cells included in the nonvolatile memory device into a physical checker state;
PV reference cell program step for programming the PV reference cell,
In the PVH reference cell programming step, the PVH reference cell is programmed using the reference cell programming method according to claim 1,
In the PV reference cell programming step, a PV reference cell is programmed by performing cell current verification using the reference cell gate voltage in the PVH reference cell programming step using the reference cell programming method according to claim 1. A reference cell programming method.

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