JP2008244795A - Dynamic range scale circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a dynamic range scale circuit which can solve the problem involved in the conventional dynamic range scale circuit by a small circuit scale by actualizing arithmetic processing using neither a multiplying circuit nor a dividing circuit. <P>SOLUTION: The dynamic range scale circuit has: a maximum output means for outputting a maximum of an absolute value of input data in a predetermined sample period; a constant value judging means; a delay means; a multiplying means for multiplying input data delayed by the delay means by a constant value; and a bit-width converting means, wherein the constant value judging means compares the maximum with a value of power of two, and outputs the value obtained by multiplying the reciprocal number of a minimum value among values of power of two which is equal to or larger than a maximum by a specified value, as a constant value represented as a value of power of two, and the multiplying means multiplies the constant value represented as the value of power of two by the input data delayed by the delay means through bit shift processing. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention extracts only valid bits from a digital signal having a bit width a (a is an integer of 2 or more) and converts it to a digital signal having a bit width b (b is an integer of 2 or more, a ≧ b). It relates to a dynamic range scale circuit that outputs in the same manner.

  The bit width of the digital signal is set so that the maximum amplitude of the signal does not exceed a representable range. Here, the range of values that can be expressed is called the dynamic range.

  When only a desired signal is extracted from a digital signal having a large maximum amplitude including noise or the like by a filter, a digital signal having a small maximum amplitude can be obtained. That is, a digital signal having a small effective bit width can be obtained from a digital signal having a large effective bit width. Assuming that the dynamic range is the same for both, the digital signal whose maximum amplitude has been reduced by the filter increases the number of invalid bits by the amount that the effective bit width has been reduced, and the subsequent processing cost increases. For this reason, a dynamic range scale circuit is arranged at the output stage of the filter, and a process of assigning a smaller dynamic range corresponding to a digital signal having a small effective bit width is performed.

  The “automatic gain control device” of Patent Document 1 describes a dynamic range scale circuit using a division circuit. Here, the input signal level is determined with the maximum sample value during a certain period, and the reciprocal of this maximum sample value is multiplied as a gain coefficient by the sample values of all the input signals that continue during the next period. As a result, a large input signal is multiplied by a small gain coefficient, and a small input signal is multiplied by a large gain coefficient. By adjusting the gain coefficient to be multiplied with the input signal in this way, the dynamic range of the input signal is limited to a certain range.

  FIG. 10 shows a configuration example of a conventional dynamic range scale circuit. In the figure, a dynamic range scale circuit 10 is connected to the output stage of the filter 20. The input unit of the filter 20 is A, the output unit of the filter 20 and the input unit of the dynamic range scale circuit 10 are B, and the output unit of the dynamic range scale circuit 10 is C. FIG. 11 shows the relationship between the waveform of the multi-bit digital data in A, B, and C and the dynamic range.

Waveform A shows a state where the maximum value of the input data is close to the upper limit (2 ^a-1 −1) of the dynamic range. A waveform B shows a state in which noise or the like is removed when the input data of the waveform A passes through the filter 20 and the maximum value of the data is smaller than that of the waveform A. Waveform C shows a state in which the upper limit of the dynamic range is reduced from (2 ^a-1 -1) to (2 ^b-1 -1) by the dynamic range scale circuit 10 and the upper limit of data that can be expressed is lowered.

A series of input data of the dynamic range scale circuit 10 is assumed to be x (i). Here, i is a time-series index. In the dynamic range scale circuit 10, the input data x (i) having the bit width a is obtained from the absolute value circuit 11, the maximum value monitor 12, and the constant value judging circuit 13, and the input data x (i) is inputted to the delay circuit. The signal delayed at 14 is multiplied by the multiplication circuit 15, and the series of output data is defined as y (i). The absolute value circuit 11 calculates and outputs the absolute value | x (i) | of the input data x (i). The maximum value monitor 12 calculates and outputs a maximum value x _m (i) for each absolute value | x (i) | of the M consecutive pieces of input data. Although the maximum value is updated every M samples, the maximum value monitor 12 outputs the maximum value x _m (i) for each sample. The constant value judgment circuit 13 obtains a constant value f _scale (x _m (i)) to be multiplied with the input data by applying the following function.
f _scale (x _m (i)) = (2 ^b−1 −1) / x _m (i) (1)
Here, the maximum value x _m (i) and the constant value f _scale (x _m (i)) have a continuous relationship as shown in FIG. In the dynamic range scale circuit, it is assumed that the digital signal to be corrected for the dynamic range has a certain range of amplitude. Therefore, when the maximum value x _m (i) of the past M samples is equal to or smaller than the predetermined value, the data itself is determined to be invalid, and the constant value f _scale (x _m (i)) is set to zero.

On the other hand, the delay circuit 14 is a shift register having the number of stages for storing M pieces of input data x (i), and outputs delay data x (i−M) obtained by delaying the input data x (i) by M samples. . The multiplication circuit 15 multiplies the delay data x (i−M) and the constant value f _scale (x _m (i)) and outputs the result as output data y (i) having a bit width a. The output data y (i) is input to the bit width converter 16 and b bits on the MSB side of the output data y (i) are extracted as valid bits and output as output data with a bit width b. It is assumed that all digital data is expressed in two's complement.
Japanese Patent Publication No. 7-3950

In the conventional dynamic range scale circuit shown in FIG. 10, a divider circuit is used as the constant value determination circuit 13 for obtaining the constant value f _scale (x _m (i)). Further, the multiplication circuit 15 is necessary for multiplying the constant value f _scale (x _m (i)) by the delay data x (i−M). In general, since the division circuit and the multiplication circuit have a large circuit scale, there has been a problem that the cost becomes high from the viewpoint of occupied area and power consumption when hardware is realized.

  Further, in Patent Document 1, it is pointed out that division is not efficiently performed as a problem of the conventional dynamic range limiting method, and a method of using overflow of addition operation is proposed to solve this. However, it is still necessary to use a lot of multiplication circuits, and the problem that the cost increases from the viewpoint of occupied area and power consumption when hardware is not solved.

  An object of the present invention is to provide a dynamic range scale circuit that realizes arithmetic processing without using a multiplication circuit or a division circuit and can cope with a small circuit scale.

1st invention detects the absolute value of the input data with the 1st bit width which is a time series digital signal, and outputs the maximum value of the absolute value of the input data in a predetermined sample period, Constant value determining means for outputting a constant value having a predetermined relationship with respect to the maximum value, delay means for delaying and outputting input data by a predetermined sample period, input data and constant value delayed by the delay means, And a bit width conversion means for extracting the number of bits specified by the second bit width from the sign bit side of the output of the multiplication means and outputting as a time-series digital signal having the second bit width; In the dynamic range scale circuit having the above, a power value of 2 corresponding to the second bit width is set as a prescribed value, and the constant value determining means and the multiplying means are configured as follows. A specific numerical example is shown in parentheses below with reference to FIG. Here, the specified value is ²⁵ .

Constant value determination means, the maximum value (3/64) and a power of two values (..., 1/2 ^5, 1/2 ^4, 1/2 ^3, ...) by comparing the magnitude of equal to the maximum value The value obtained by multiplying the inverse of the minimum value (2 ⁴ ) in the power of 2 greater than the maximum value by the specified value (2 ⁵ ) is output as a constant value (2 ⁹ ) expressed by the power of 2 It is the structure to do.

  The multiplication means is configured to perform a multiplication process of a constant value represented by a power of 2 and the input data delayed by the delay means by a bit shift process.

According to a second invention, in the same dynamic range scale circuit as in the first invention, a power value of 2 corresponding to the second bit width is set as a specified value, and the constant value judging means and the multiplying means are as follows. Configure. A specific numerical example is shown in parentheses below with reference to FIG. 9 (2). Here, the specified value is ²⁵ .

The constant value judging means calculates the maximum value (1/24 or 3/64), the power of 2 (..., 1/2 ⁵ , 1/2 ⁴ , 1/2 ³ ,...) And the power of 2 The values divided by 3 (..., 1 / (3 * 2 ³ ), 1 / (3 * 2 ² ), ...) are compared, and are powers of 2 that are equal to or greater than the maximum value. large value (1/2 ^4, 1/2 ^3, ...) and 2 of the羃乗value a value obtained by dividing the 3 equal to maximum value greater than the maximum value (1 / (3 * 2 ^3), 1 / (3 * 2 ² ), ...) is multiplied by the reciprocal (3 * 2 ³ or 2 ⁴ ) of the minimum value and the specified value (2 ⁵ ). In this configuration, a constant value (2 ⁹ +2 ⁸ or 2 ⁹ ) expressed as a power value is output.

  The multiplication means is configured to perform multiplication processing of the constant value and the input data delayed by the delay means by bit shift processing and addition processing when the constant value is represented by an addition value of powers of 2. . When the constant value is represented by a power of 2, the multiplication process of the constant value and the input data delayed by the delay means is performed by bit shift processing.

According to a third invention, in the same dynamic range scale circuit as in the first invention, a power value of 2 corresponding to the second bit width is set as a specified value, and the constant value judging means and the multiplying means are as follows. Configure. A specific numerical example is shown in parentheses below with reference to FIG. Here, the specified value is ²⁵ .

Constant value determination means, the maximum value (1/16 or 1/24) and a power of two values (..., 1/2 ^5, 1/2 ^4, 1/2 ^3, ...) and 2 of the羃乗value 3 by multiplying the value (..., 3/2 ^6, 3/2 ^5, ...) and compares the equal or maximum value greater than the maximum value a power of two values (1/2 ^4, 1/2 ( ³ ,...) And the power of 2 multiplied by 3, which is equal to the maximum value or greater than the maximum value (3/2 ⁶ , 3/2 ⁵ ,...) / 16 or 3/64) is a power of 2, a value obtained by multiplying the reciprocal (2 ⁴ ) and the specified value (2 ⁵ ) by a power of 2 (2 ⁹ If the minimum value is a value obtained by multiplying the power of 2 by 3, the reciprocal (3 * 2 ³ ) of the value closest to the maximum value obtained by dividing the power of 2 by ³ and the specified value The value obtained by multiplying (2 ⁵ ) is output as a constant value (2 ⁹ +2 ⁸ ) represented by the sum of powers of 2 .

  The multiplication means is configured to perform multiplication processing of the constant value and the input data delayed by the delay means by bit shift processing and addition processing when the constant value is represented by an addition value of powers of 2. . When the constant value is represented by a power of 2, the multiplication process of the constant value and the input data delayed by the delay means is performed by bit shift processing.

  In the dynamic range scale circuits of the first to third inventions, the specified value may be a power of 2 with an index obtained by subtracting 1 from the second bit width.

  The dynamic range scale circuit of the present invention discretely changes a constant value to be multiplied by input data according to the input data, and the change point is a power value of 2 that is the maximum absolute value of the input data. By setting the value obtained by dividing the product value by 3 to the value obtained by multiplying the power value of 2 by 3, the constant value determination means can be configured by a comparison circuit instead of the subtraction circuit. In particular, the configuration of the comparison circuit can be simplified by making the discrete value a power of 2 or a value obtained by multiplying the power of 2 by 3. In addition, as a constant value to be multiplied with the input data, it can be expressed by a power value of 2 or an addition value of the power values of 2. Therefore, multiplication processing is realized by bit shift or a combination of bit shift and addition processing. can do.

  With the above configuration, it is possible to reduce the circuit scale for dynamic range switching in digital signal processing, and it is possible to realize a dynamic range scale circuit that has both a small occupied area and low power consumption.

(First embodiment)
FIG. 1 shows a first embodiment of a dynamic range scale circuit of the present invention.
The basic configuration of the dynamic range scale circuit of this embodiment is the same as the conventional configuration shown in FIG. That is, the dynamic range scale circuit 10 includes an absolute value circuit 11, a maximum value monitor 12, a constant value determination circuit 13A that uses a comparison circuit instead of a division circuit, a delay circuit 14, and a bit shift circuit that uses a shift register instead of a multiplication circuit. 15A and a bit width converter 16.

The feature of the present embodiment is that the constant value determination circuit 13A is configured by a simple comparison circuit, so that the maximum value x _{m of} the input data (2's complement representation) in which the constant value f _scale (x _m (i)) varies. The discrete value of (i) is a power of 2.

Furthermore, the feature of the present embodiment is that the discrete value of the constant value f _scale (x _m (i)) becomes a power of 2 so that the delay data x (i−M) and the constant value f _scale (x _m ( The multiplication process i)) is realized by a bit shift circuit 15A using a shift register.

FIG. 3 and Table 1 show an example of the relationship between x _m (i) and f _scale (x _m (i)). [S, t] representing the range of x _m (i) is s ≦ x _m (i) ≦ t, and (s, t] is s <x _m (i) ≦ t. A specified value represented by a power of 2 corresponding to the bit width b is ²⁵ .

In the dynamic range scale circuit of the present invention, when the maximum value x _m (i) of the absolute value of the past M sample input data x (i) is equal to or less than a predetermined value as in the conventional configuration, this data itself is used. It is determined that the input data x (i) is invalid, and a constant value f _scale (x _m (i)) to be multiplied with the input data x (i) is set to zero and a multiplication result of zero is output. In the case of Table 1, when the maximum value x _m (i) is 2 ⁻⁶ (1/64) or less, the corresponding constant value f _scale (x _m (i)) is set to zero.

In this embodiment, the discrete value of the maximum value x _m (i) of the input data in which the constant value f _scale (x _m (i)) varies is set to a power of 2, but is this discrete value a power of 2? FIG. 4 shows the difference between the comparison circuits constituting the constant value determination circuit 13A depending on whether or not. Fig. 4 (1) shows the determination process when the discrete value is a power of 2 and the value is 1/4. Fig. 4 (2) shows the determination process when the discrete value is not a power of 2. The determination process when the value is 2/3 is shown.

When x _m (i) expressed in two's complement is represented by a decimal number, a ₇ is a sign bit,
x _m (i) = -a ₇ +2 ^-1 a ₆ +2 ^-2 a ₅ +2 ^-3 a ₄ +2 ^-4 a ₃ +2 ^-5 a ₂ +2 ^-6 a ₁ +2 ^-7 a ₀
It becomes. When x _m (i) is ¼, x _m (i) is less than ¼ or 1 / by a maximum of two comparisons of whether a ₆ is 1 or a ₅ is 1. Whether it is 4 or more can be determined. On the other hand, when x _m (i) is 2/3, up to seven comparison operations are required. It is clear that the number of operations of the latter increases when averaged, and it can be seen that the configuration of the comparison circuit of the constant value determination circuit 13A can be simplified by expressing x _m (i) as a power of 2.

In this embodiment, the bit width a of the input data x (i) in FIG. 1 is 8, the bit width b of the output data y (i) is 6, and the input data x (i) and output data y (i) Each display range is set as follows.
−1 ≦ x (i) ≦ 1-2- ^(a-1)
-2 ^b-1 ≤ y (i) ≤ 2 ^b-1 -1
Here, when the maximum value x _m (i) of the input data x (i) during a certain period is 3/32, 1/16 <3/32 <1/8, so the corresponding constant value f _scale (x _m (i)) is 2 ³ * 2 ⁵ . The output data y (i) of the bit shift circuit 15A for certain input data x (i) = 1/16 during this period is y (i) = (1/16) * 2 ⁸ = 2 ⁴ = 010000 (binary number)
It becomes.

Further, when the maximum absolute value x _m (i) of the input data x (i) during a certain period is 1/8, 1/16 <1/8 ≦ 1/8, so that the corresponding constant value f _scale (x _m (i)) is 2 ³ * 2 ⁵ The output data y (i) of the bit shift circuit 15A for certain input data x (i) = 1/8 during this period is y (i) = (1/8) * 2 ⁸ = 2 ⁵ = 100000 (binary number)
And overflow. In this case, the output data y (i) is the maximum positive value.
2 ⁵ -1 = 0111111
To saturate.

FIG. 2 is a timing chart showing an operation example of the first embodiment. Here, the input data x (i) of the dynamic range scale circuit 10, the maximum value x _m (i) of M samples obtained by the maximum value monitor 12, and the constant value f _scale (x _m ( i)) / 2 ⁵ represents the time change of the output data y (i) / 2 ⁵ of the bit shift circuit 15A. The operation example shown here is the same in the second and third embodiments described below.

(Second Embodiment)
FIG. 5 shows a second embodiment of the dynamic range scale circuit of the present invention.
The configuration of the dynamic range scale circuit of this embodiment is the same as that of the first embodiment shown in FIG. 1, and the dynamic range scale circuit 10 is a comparison circuit in place of the absolute value circuit 11, the maximum value monitor 12, and the division circuit. A constant value determination circuit 13B using a delay circuit 14, a bit shift / addition circuit 15B using a shift register and an addition circuit instead of a multiplication circuit, and a bit width converter 16.

The constant value determination circuit 13B according to the present embodiment converts the discrete value of the maximum value x _m (i) of the input data (2's complement representation) whose constant value f _scale (x _m (i)) changes to a power of 2. The intermediate value is used. The intermediate value of the power of 2 is a value represented by 1 / (3 * 2 ^k-1 ), and the corresponding constant value f _scale (x _m (i)) is 3 * 2 ^k-1 * 2. ^h ,
3 * 2 ^k-1 * 2 ^h = (2 + 1) * 2 ^{k-1 + h} = 2 ^{k + h} +2 ^{k-1 + h}
As shown in the figure, it is transformed into a power value of 2 raised. Here, k and h are integer values, and 2 ^h is a specified value represented by a power of 2 according to the second bit width b.

Further, the feature of the present embodiment is that the constant value f _scale (x _m (i)) is expressed as a power of 2 or an addition value of the power of 2 so that the delay data x (i−M) is constant. The multiplication processing of the numerical value f _scale (x _m (i)) can be realized by a bit shift / addition circuit 15B using a shift register and an addition circuit.

FIG. 6 and Table 2 show an example of the relationship between x _m (i) and f _scale (x _m (i)). [S, t] representing the range of x _m (i) is s ≦ x _m (i) ≦ t, and (s, t] is s <x _m (i) ≦ t. A specified value represented by a power of 2 corresponding to the bit width b is ²⁵ .

In the present embodiment, as shown in FIG. 6, the intermediate value 1 / (2) is a discrete value of the maximum value x _m (i) of the input data whose constant value f _scale (x _m (i)) varies. By increasing 3 * 2 ^k-1 ), the change of the constant value f _scale (x _m (i)) calculated by the constant value determination circuit 13B is smoothed so as to approach the conventional continuous change shown in FIG. I have to. However, as described with reference to FIG. 4 in the first embodiment, the constant value determination circuit 13B can be configured by a comparison circuit, but the configuration is not as simple as that in the first embodiment. The advantage of this embodiment is that a bit shift / adder circuit 15B using a shift register and an adder circuit can be used in place of the conventional multiplier circuit 15.

In the present embodiment, the bit width a of the input data x (i) in FIG. 5 is 8, the bit width b of the output data y (i) is 6, and the input data x (i) and output data y (i). Each display range is set as follows.
−1 ≦ x (i) ≦ 1-2- ^(a-1)
-2 ^b-1 ≤ y (i) ≤ 2 ^b-1 -1
Here, when the maximum value x _m (i) of the input data x (i) during a certain period is 1/32, since 1/48 <1/32 ≦ 1/32, the corresponding constant value f _scale (x _m (i)) is 2 ⁵ * 2 ⁵ . The output data y (i) of the bit shift circuit 15B for certain input data x (i) = 1/64 during this period is y (i) = (1/64) * 2 ¹⁰ = 2 ⁴ = 010000 (binary number)
It becomes.

Further, when the maximum absolute value x _m (i) of the input data x (i) during a certain period is 1/32, since 1/48 <1/32 ≦ 1/32, the corresponding constant value f _scale (x _m (i)) is 2 ⁵ * 2 ⁵ The output data y (i) of the bit shift circuit 15B for some input data x (i) = 1/32 during this period is y (i) = (1/32) * 2 ¹⁰ = 2 ⁵ = 100000 (binary number)
And overflow. In this case, the output data y (i) is the maximum positive value.
2 ⁵ -1 = 0111111
To saturate.

(Third embodiment)
In the third embodiment, the configuration of the comparison circuit constituting the constant value determination circuit 13B in the second embodiment is simplified, and the configuration of the dynamic range scale circuit is the same as that of the second embodiment shown in FIG. It is.

The constant value determination circuit 13B according to the present embodiment converts the discrete value of the maximum value x _m (i) of the input data (2's complement representation) whose constant value f _scale (x _m (i)) changes to a power of 2. The intermediate value is used. The intermediate value of the power of ² is a value represented by 3/2 ^{k + 2} , but the constant value f _scale (x _m (i)) corresponding to this is 3 * 2 as in the second embodiment. ^k-1 * 2 ^h ,
3 * 2 ^k-1 * 2 ^h = (2 + 1) * 2 ^{k-1 + h} = 2 ^{k + s} +2 ^{k-1 + h}
As shown in the figure, it is transformed into a power value of 2 raised. Here, k and h are integer values, and 2 ^h is a specified value represented by a power of 2 according to the second bit width b.

The constant value f _scale (x _m (i)) is expressed as a power of 2 or an addition value of powers of 2 so that the delay data x (i−M) and the constant value f _scale (x _m ( Similar to the second embodiment, the multiplication processing of i)) can be realized by the bit shift / addition circuit 15B using a shift register and an addition circuit.

FIG. 7 and Table 3 show an example of the relationship between x _m (i) and f _scale (x _m (i)). [S, t] representing the range of x _m (i) is s ≦ x _m (i) ≦ t, and (s, t] is s <x _m (i) ≦ t. A specified value represented by a power of 2 corresponding to the bit width b is ²⁵ .

In this embodiment, the discrete value of the maximum value x _m (i) of the input data in which the constant value f _scale (x _m (i)) varies is a power of 2 and its intermediate value 3/2 ^{k + 2.} FIG. 8 shows the difference in the comparison circuit of the constant value determination circuit 13B for determining the intermediate value. FIG. 8 (1) shows determination processing when x _m (i) is 3/4, which is an intermediate value of the power of 2, and FIG. 8 (2) shows that x _m (i) is 2/3. The determination process when

When x _m (i) expressed in two's complement is represented by a decimal number, a ₇ is a sign bit,
x _m (i) = -a ₇ +2 ^-1 a ₆ +2 ^-2 a ₅ +2 ^-3 a ₄ +2 ^-4 a ₃ +2 ^-5 a ₂ +2 ^-6 a ₁ +2 ^-7 a ₀
It becomes. When x _m (i) is an intermediate value 3/4 of the power of 2 (“01100000” in binary notation), a maximum of 2 times a ₆ is 1 and a ₅ is 1 By comparison operation, it can be determined whether x _m (i) is less than 3/4 or more than 3/4. On the other hand, when x _m (i) is 2/3 (“01010101” in binary notation), a maximum of seven comparison operations are required. It is obvious that the number of the latter operations increases when averaged, and by determining x _m (i) by a power of 2 and an intermediate value 3/2 ^{k + 2} of the power of ² , a constant value determination circuit It can be seen that the configuration of the 13B comparison circuit can be simplified.

  In this embodiment, the result of multiplying input data by a constant value may overflow. In this case, the multiplication result is saturated within a range that can be expressed as output data.

Further, the characteristics of the constant value determination circuit 13B in the second and third embodiments are evaluated as follows according to the area surrounded by the characteristic curve and the logarithmic x axis. When the area is determined by the interval 2 ⁻ⁿ , 1] of x _m (i), the second embodiment (FIG. 6) is 7n / 12, whereas n / 2 of the first embodiment (FIG. 3) is The third embodiment (FIG. 7) is 5n / 8,
5n / 8> 7n / 12> n / 2
Therefore, it can be said that the configuration of the third embodiment has the best characteristics among them.

The figure which shows the structural example of the 1st Embodiment of this invention. The figure which shows the operation example of the 1st Embodiment of this invention. The figure which shows the input-output example of the constant value determination circuit 13A of 1st Embodiment. The flowchart which shows the process example of 13 A of constant value determination circuits of 1st Embodiment. The figure which shows the structural example of the 2nd Embodiment of this invention. The figure which shows the input-output example of the constant value determination circuit 13B of 2nd Embodiment. The figure which shows the input-output example of the constant value determination circuit 13B of 3rd Embodiment. The flowchart which shows the process example of the constant value determination circuit 13B of 3rd Embodiment. The figure which shows the constant value determination operation example of the dynamic range scale circuit of this invention. The figure which shows the structural example of the conventional dynamic range scale circuit. The figure which shows the operation example of a dynamic range scale circuit. The figure which shows the input-output example of the conventional constant value determination circuit 13.

Explanation of symbols

10 dynamic range scale circuit 11 absolute value circuit 12 maximum value monitor 13 constant value judgment circuit 13A, 13B constant value judgment circuit (comparison circuit)
14 delay circuit 15 multiplication circuit 15A bit shift circuit 15B bit shift / addition circuit 16 bit width conversion circuit 20 filter

Claims (4)

A maximum value output means for detecting an absolute value of input data having a first bit width which is a time series digital signal and outputting a maximum value of the absolute value of the input data in a predetermined sample period;
Constant value determination means for outputting a constant value having a predetermined relationship with respect to the maximum value;
Delay means for delaying and outputting the input data by the predetermined sample period;
Multiplying means for multiplying the input data delayed by the delay means and the constant value;
A dynamic range scale comprising: a bit width conversion means for extracting the number of bits specified by the second bit width from the sign bit side of the output of the multiplication means and outputting as a time-series digital signal having the second bit width. In the circuit
A power value of 2 corresponding to the second bit width is set as a specified value;
The constant value determining means compares the maximum value with a power value of 2 and compares the reciprocal of the minimum value of 2 power values equal to or greater than the maximum value and the specified value. Is output as the constant value represented by a power of 2;
The dynamic range scale circuit is characterized in that the multiplication means is configured to perform multiplication processing of the constant value represented by a power of 2 and the input data delayed by the delay means by bit shift processing. A maximum value output means for detecting an absolute value of input data having a first bit width which is a time series digital signal and outputting a maximum value of the absolute value of the input data in a predetermined sample period;
Constant value determination means for outputting a constant value having a predetermined relationship with respect to the maximum value;
Delay means for delaying and outputting the input data by the predetermined sample period;
Multiplying means for multiplying the input data delayed by the delay means and the constant value;
A dynamic range scale comprising: a bit width conversion means for extracting the number of bits specified by the second bit width from the sign bit side of the output of the multiplication means and outputting as a time-series digital signal having the second bit width. In the circuit
A power value of 2 corresponding to the second bit width is set as a specified value;
The constant value judging means compares the maximum value with a power value of 2 and a value obtained by dividing the power value of 2 by 3, and is a power value of 2 that is equal to or greater than the maximum value. A value obtained by dividing the value greater than the value and the power value of 2 by 3 and multiplying the prescribed value by the inverse of the minimum value equal to or greater than the maximum value and a power of 2 It is configured to output as the constant value represented by the addition value of the power value or the power value of 2;
When the constant value is expressed by a power of 2, the multiplication means performs a multiplication process of the constant value and the input data delayed by the delay means by a bit shift process, and the constant value is 2 The dynamic value is a configuration in which a multiplication process of the constant value and the input data delayed by the delay means is performed by a bit shift process and an addition process. Range scale circuit. A maximum value output means for detecting an absolute value of input data having a first bit width which is a time series digital signal and outputting a maximum value of the absolute value of the input data in a predetermined sample period;
Constant value determination means for outputting a constant value having a predetermined relationship with respect to the maximum value;
Delay means for delaying and outputting the input data by the predetermined sample period;
Multiplying means for multiplying the input data delayed by the delay means and the constant value;
A dynamic range scale comprising: a bit width conversion means for extracting the number of bits specified by the second bit width from the sign bit side of the output of the multiplication means and outputting as a time-series digital signal having the second bit width. In the circuit
A power value of 2 corresponding to the second bit width is set as a specified value;
The constant value judging means compares the maximum value with a power value of 2 and a value obtained by multiplying the power value of 2 by 3 and is a power value of 2 that is equal to or greater than the maximum value. If the minimum value of the value greater than the value and the power value of 2 multiplied by 3 and equal to the maximum value or greater than the maximum value is a power of 2, the reciprocal and the specified value If the minimum value is a value obtained by multiplying the power value of 2 by 3, the value obtained by dividing the power value of 2 by 3 A value obtained by multiplying the reciprocal of the value closest to the maximum value by the specified value is output as the constant value represented by an addition value of a power of 2;
When the constant value is expressed by a power of 2, the multiplication means performs a multiplication process of the constant value and the input data delayed by the delay means by a bit shift process, and the constant value is 2 The dynamic value is a configuration in which a multiplication process of the constant value and the input data delayed by the delay means is performed by a bit shift process and an addition process. Range scale circuit. In the dynamic range scale circuit according to any one of claims 1 to 3,
The dynamic range scale circuit according to claim 1, wherein the specified value is a power of 2 with an index obtained by subtracting 1 from the second bit width.

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