JP2008134143A - Verification structure and verification method of infrared thermal image array module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an infrared thermal image array module capable of improving the performance and the error detection efficiency of an array sensing module. <P>SOLUTION: Verification of the infrared thermal image array module mainly includes a thermal image module specification design, epitaxial, and optical property verification, and first of all, an epitaxial parameter is calibrated. A single quick-close type sensing component manufacturing process and temperature-changing photoelectric quantity measurement verification are performed, and hereby the epitaxial completes low-temperature temperature change and transformation measurement calibration of the sensing component. A focal plane array manufacturing process and its photoelectric uniformity are verified, and a dark current uniformity test is performed. Adhesion between the focal plane array and a signal reading integrated circuit and a polishing manufacturing process are verified, and indium adhesion is performed between a sensing module and the signal reading integrated circuit, and thereby a photoelectric signal is converted. A thermal image quality integration test verification is performed, and optimum driving, control output parameter analysis and measurement are adjusted. A thermal image array module model is performed continuously, and bonding with a focal plane sensing array is performed by utilizing an indium pillar bonding system, to thereby complete an image sensing array module model. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a kind of infrared thermal image array module. In particular, it relates to a verification structure and verification method of a kind of infrared thermal image array module.

In order to meet the special demands of various image applications, in the selection of array sensing module materials, the optimization of the part structure design, the improvement of image analysis and detection has been the result of high-quality infrared thermal image array modules over the past 10 years. It was a goal in development.
In 2002, Masalkar of Japan (Patent Document 1) submitted the steps to improve the structure of the multiple quantum well manufacturing process in the sensing structure and simplify the manufacturing process. According to this, the detection measurement efficiency of the sensing component can be effectively improved.
In 2004, Jeffrey B. Barton of the US (Patent Document 2) submitted a method for improving the module manufacturing process using a newly designed near-infrared light detection structure for an indium phosphide substrate, and used it for array structure detection. ing.
In 2005, Michael G. Engelmann and others from the US (Patent Document 3) submitted an improved structure to the high-resolution visible light and near-infrared light array image sensor structure of large pixels. In the same year, Frederick E. Koch et al. (Patent Document 4) presented for the first time a thermal image application of a quantum dot infrared focal plane array module structure CMOS signal reading circuit structure.

US20020088943A1 specification US Patent No. 20040061056A1 Specification US Patent 20050104089A1 Specification US Patent No. 20050017176A1

In other words, the development of thermal image modules requires technical personnel from various specialized fields. For example, a complete infrared thermal image array module includes a sensing component array epitaxial and design that requires physics, optoelectronic materials, and materials epitaxial specialists, and an array optical signal reading integrated circuit (ROIC) unit is integrated circuit design, analog Digital electronics specialists are required, thermal display calibration circuits require logic and image circuit design specialists, and system integration specialists are required for best integration of all modules and error detection. However, until now, at the time of integrated technology development, only local performance optimization verification has been performed in individual specialized fields, and a specific infrared image sensing module verification process and its structure manufacturing integration method have not been submitted.
Therefore, the present invention provides a kind of infrared thermal image array module verification for the above problems, not only to improve the traditional thermal image sensing material, heterogeneous joint and image display structure and manufacturing process defects, but also It can be applied to different thermal image sensing materials, heterogeneous bonding and image display structures and manufacturing processes, improving the error detection efficiency in various thermal image array modules and solving the above problems.

  The main object of the present invention is to provide an infrared thermal image array module verification structure and verification method, thereby improving array sensing module performance and error detection efficiency.

  Another object of the present invention is to provide an infrared thermal image array module verification structure and verification method, thereby reducing research and development costs.

That is, the infrared thermal image array module verification structure and verification method includes thermal image module standard design, epitaxial and optical property verification,
First, calibrate the epitaxial parameters,
After passing the verification, the single-type sensing part manufacturing process and temperature-variable photoelectric measurement verification are performed. In fact, the epitaxial has completed the heat-conducting adhesive insulation test, and the coaxial conductor or low-noise signal line is derived from the gold wire, and the temperature is low And through the transformation, measure the dark current, dark electrical resistance, reaction spectrum, detectability calibration,
After passing this verification, verify the focal plane array manufacturing process and its photoelectric uniformity,
If not, go back to thermal image module standard design, epitaxial and optical property verification,
After passing the test, the focal plane array manufacturing process and photoelectric uniformity are verified, and the focal plane array manufacturing process is performed in accordance with the set sensing part standard. After this, select the test area, perform the dark current uniformity test,
After passing this verification, the adhesion and polishing manufacturing process verification of the focal plane array and the signal readout integrated circuit,
If not, go back to thermal image module standard design, epitaxial and optical property verification,
After passing, the focal plane array and the signal readout integrated circuit are bonded and polished, and the manufacturing process is verified. Indium adhesion is performed between the plane sensing module and the signal readout integrated circuit, and the sensing array module converts the photoelectric signal.
After passing this verification, continue the thermal image quality integration test (including optical equipment) verification,
If rejected, return to the verification of the focal plane array manufacturing process and its photoelectric uniformity, and then verify again.After passing, verify the thermal image quality integration test (including optical equipment), Adjust control output parameters, analyze and measure module thermal image quality,
After passing this verification, continue the thermal image array module template,
If it fails, go back to the adhesion and polishing manufacturing process verification of the focal plane array and signal readout integrated circuit, and verify again,
After passing, the thermal image array module template is continuously performed, and the indium column junction method is used to join the focal plane sensing array, and the photocurrent in each array unit is stored in the integration capacitor signal, and the row and column multiplexing is performed. The selector unit sequentially passes through the signal output end, outputs it to the sensor buffer module and the image processing system, performs image signal processing, and completes the image sensing array module template,
Thus, the infrared thermal image array module is characterized in that the performance of the array sensing module can be improved and the time required for verification of the detection module can be shortened.

In the invention of claim 1, waveband detection uses short, medium, and long infrared rays to absorb the waveband,
Sensing module infrared penetration board selects the superiority or inferiority of sensing module quality, affects the infrared penetration rate of waveband reception,
Bottom edge highly doped contact layer affects semiconductor and conductive metal ohmic contact quality,
The infrared absorbing layer is also referred to as the main active layer, the number of cycles affects the light enhancement and quantum efficiency, and the thickness of the intrinsic layer or depletion layer and the magnitude of the intrinsic concentration affect the quantum efficiency and the dark current value of the sensing component. Give,
The failure-inhibiting layer affects the resistance of the sensing component, matching the high injection photocurrent efficiency, the sensing component dark current value, and the activation ability value under the operating temperature,
The top edge high impurity doping contact layer affects the ohmic contact characteristics and photoelectron current output efficiency. The infrared thermal image array module verification structure is characterized by thermal image module standard design, epitaxial and optical property verification.
According to a second aspect of the present invention, in the verification structure of the first aspect, the epitaxial verification epitaxial and high-temperature diffusion equipment is a molecular beam epitaxial method, a metal organic CVD method, or a high-temperature diffusion furnace to manufacture a structural component. The verification structure is characterized by this.
A third aspect of the present invention is the verification structure according to the first aspect, wherein the infrared absorption layer design of the epitaxial verification is a quantum localized structure.
According to a fourth aspect of the present invention, in the verification structure according to the first aspect, the semiconductor substrate material for the epitaxial verification is selected from gallium arsenide, indium phosphide, dichromium trioxide, silicon, silicon carbide, and the doping form is semi-insulating Alternatively, the verification structure is characterized by being n-type.
According to a fifth aspect of the present invention, there is provided the verification structure according to the first aspect, wherein a substrate used for the epitaxial verification is a group IV such as silicon, a group III, such as gallium arsenide, indium phosphide, and the base type sensing material is antimony. The verification structure is characterized by being indium phosphide, mercury cadmium telluride, or indium phosphide.
The invention of claim 6 is the verification structure according to claim 1, wherein the PIN structure of the I-essential layer of the epitaxial verification is formed by using a high temperature diffusion furnace diffusion method, and the P layer diffusion material is arsenic. The verification structure is characterized by being a zinc compound, zinc, and cadmium.
The invention according to claim 7 is the verification structure according to claim 1, wherein the optical physical property verification includes:
The material lamination rate calibration uses the high reflectivity electron firing method or the quartz oscillate frequency test method, and the lamination rate error is set to 0.01 to 0.05 nm.
Cyclic structure perfection inspection measurement uses low-angle twin crystal X-ray interferometer, intense fluorescence test or penetrating electron microscope test. After numerical regression calculation, cycle structure uniformity is> 95%,
Structural crystal quality inspection measurement uses low angle twin crystal X ray incinerator, structural crystal, single crystal and polycrystal uniformity are> 90%,
Polarity and doping concentration calibration uses capacitor voltage verification method, low temperature molding measurement and secondary ion mass spectrometer method, and polarity judgment and doping concentration composition error are> 98% and <0.5E1 times, respectively It is a verification structure.

In the invention of claim 8, the line width error of the single-type sensing component photomask and the actual part manufacturing process is <10%, and the operation temperature error rate at 10 to 300K is <15% at the time of verifying the variable temperature photoelectric measurement, The obtained spectral shape uniformity is> 80%. The infrared thermal image array module verification structure has a single-end sensing component manufacturing process and temperature-variable photoelectric measurement verification.
The invention of claim 9 is the verification structure according to claim 8, wherein the etching water solvent of the verification structure is a weak pH acid solution, hydrogen peroxide: deionized water = 2 to 5: 1 to 2: 5 to 20 The verification structure is characterized by
According to a tenth aspect of the present invention, in the single-end type sensing component manufacturing process and the temperature-variable photoelectric measurement verification according to the eighth aspect, the etching depth is an altitude between the electron-electric tunnel layers generated from the upper part of the component layer structure. The single-type sensing component manufacturing process and temperature-variable photoelectric measurement measurement verification are featured.
According to an eleventh aspect of the present invention, in the verification structure according to the eighth aspect, the contact metal material used by the upper and lower electrode sections of the sensing component is a metal electrode manufactured by thermal evaporation, electron gun warming evaporation, or ion sputtering. The verification structure is characterized by
The invention of claim 12 is the verification structure according to claim 8, wherein the N type of the metal material in the verification structure is palladium / chromium / gold germanium alloy / gold, and the P type is palladium / chromium / gold beryllium alloy or zinc / The verification structure is characterized by being gold.
According to a thirteenth aspect of the present invention, in the verification structure according to the eighth aspect, in the verification structure, in the quick extinguishing manufacturing process, the heating stable temperature and time are 350 to 500 ° C. and 15 to 60 sec, respectively, and the heating temperature gradient is 100 to The verification structure is characterized by 200 ° C / sec.
The invention according to claim 14 is the verification structure according to claim 8, wherein the non-component area of the verification structure is an I-essential layer and can prevent a lateral overflow current.
According to a fifteenth aspect of the present invention, in the single-bottom-type sensing component manufacturing process and the temperature-variable photoelectric measurement verification according to the eighth aspect, the plane type of the single-bottom-type sensing component manufacturing process and the temperature-variable photoelectric measurement measurement verification Define the process, use high-temperature diffusion P-pole, diffusion depth 0.5-5μm, further polish to 0.25-2μm by surface polishing method 1-5μm particle diameter aluminum oxide powder: deionized water = 1: 2-5 ,
The single-bottom sensing component manufacturing process is characterized by the formation of an optimal P-pole region, and the temperature-variable photoelectric measurement verification.
According to a sixteenth aspect of the present invention, in the verification structure according to the eighth aspect, the platform type of the verification structure defines a sensing component area manufacturing process, an etching area is defined using photomask lithography, and the etching area depth is lower than the lower edge height. 1/3 to 1/2 of the doping polarity zone thickness must be exceeded, high temperature diffusion P-polar diffusion depth 0.5 to 5μm, surface polishing method 1-5μm particle diameter aluminum oxide powder: The verification structure is characterized by polishing to 0.25 to 2 μm with ionic water = 1: 2 to 5 to form an optimal P-pole region.
According to a seventeenth aspect of the present invention, in the verification structure according to the eighth aspect, the quantum well sensing component structure manufacturing process of the verification structure defines an etching zone using photomask lithography, and the etching zone depth is a thickness of the lower high doping polar zone. After that, the cycle light fence structure is increased, and the structure is a one-dimensional rod shape, two-dimensional square shape or rhombus shape, and the distance between the light fences and the altitude is 1. The verification structure is characterized by being between -5 μm and 10-500 nm.
The invention of claim 18 is characterized in that the line width error of each unit detection inspection unit uniformity during the focal plane array manufacturing process is <10%, and the total photocurrent uniformity during the optical spectrum reaction is> 75%. Infrared thermal image array module verification structure focal plane array manufacturing process and its photoelectric uniformity verification.

The invention according to claim 19 is the verification structure according to claim 18, wherein the coating polymer layer of the verification structure prevents the surface from receiving exudation of moisture and contaminants from the outside. It is said.
According to the invention of claim 20, the signal sampling and holding unit is stored in an integrating capacitor, that is, with a sensed signal / noise ratio (S / N ratio),
The injection unit injects a charge signal into the integrating capacitor and outputs it to the output end.
Expander module unit expands signal profits,
The row and column multiple selector unit picks up the sensing unit position in turn,
The clock generation control unit controls the reading and signal integration time according to the main clock, and the focal plane array of the infrared thermal image array module verification structure, the signal readout integrated circuit bonding, and the polishing manufacturing process verification.
The invention according to claim 21 is the verification structure according to claim 20, wherein the injection unit is composed of four or more sets of metal oxide semiconductor electric field transistors and one set of integration capacitors.
According to a twenty-second aspect of the present invention, in the verification structure according to the twentieth aspect, the signal readout integrated circuit is converted into a photoelectric signal pickup, and each pixel unit has a set of buffer, direct injection, gate pole change, and capacitor resistance change expansion type. The verification structure is characterized by corresponding to an injection pickup signal integration unit.
According to a twenty-third aspect of the present invention, in the verification structure according to the twenty-first aspect, the adhesive injection step of the verification structure first requires filling an adhesive between the focal plane array module in which the sensing component array and the signal readout integrated circuit are coupled. As a verification structure characterized by protecting the unoccupied part with a photomask, putting the polymer in the polymer adhesive liquid, and waiting for the bubbles to come out from the boundary position between the sensing component array and the signal readout integrated circuit chip Yes.

According to a twenty-fourth aspect of the present invention, the low-temperature vacuum coolable chamber has a focal plane array and a signal readout integrated circuit image chip module and filter, a cold isolation inlet, and an infrared lens joint with the outside, and the sensor buffer module has a focal plane array and a signal readout. Interface drive module between integrated circuit image chip and image processing module,
The image display processing circuit module processes and outputs the image data signal,
The control processor controls the entire command and the output of the image signal, and is connected to the host computer. The infrared heat image array module structure verification structure thermal image integration test and verification including the optical system are performed.
The invention according to claim 25 is the verification structure according to claim 24, wherein the image display processing circuit board includes:
Analog-digital conversion circuit converts analog signal to digital signal,
The output image data signal processing and control circuit outputs image data based on the signal processing and control circuit,
The retractable time pulse generator generates a time pulse signal,
The retractable power supply circuit has a verification structure characterized by providing power to the control processor.
According to a twenty-sixth aspect of the present invention, in the verification structure according to the twenty-fourth aspect, the main clock is supplied to the computer via a virtual device, and the entire control command and the image signal output structure are connected to the bit I in the host computer by the RS232 interface. The verification structure is characterized by the command and I / O function connected to the / F interface card.
In the invention of claim 27, the focal plane array operated at low temperature has an environmental cooler control temperature of 40 to 150K ± 0.5K, an enclosed internal vacuum pressure of 10E-5 to 5E-2torr, and after both-point uniformity image quality compensation The thermal image array module model complete verification of the infrared thermal image array module verification structure is characterized in that the uniformity of the image screen is> 98% and the operation rate of the focal plane array module detection inspection unit is> 95%.

The invention of claim 28 includes thermal image module standard design, epitaxial and optical physical property verification, firstly calibrates the epitaxial parameters, absorbs the wave band using short, medium and long infrared rays in the sense wave band,
The sensing module infrared penetrating board selects the superiority or inferiority of the sensing module's quality, and immediately affects the infrared penetrating rate of receiving wave bands,
The bottom-edge highly doped contact layer affects the contact quality between the semiconductor and the conductive metal ohmic,
The infrared absorbing layer is also referred to as the main active layer, the number of cycles affects the light enhancement and quantum efficiency, and the thickness of the intrinsic layer or depletion layer and the magnitude of the intrinsic concentration affect the quantum efficiency and the dark current value of the sensing component. Give,
The failure-inhibiting layer affects the resistance of the sensing component, matching the high injection photocurrent efficiency, the sensing component dark current value, and the activation ability value under the operating temperature,
The apical high impurity doping contact layer affects ohmic contact characteristics and photocurrent output efficiency,
Single-unit type sensing component manufacturing process and temperature-variable photoelectric measurement measurement verification, actually epitaxial completed heat conduction adhesive insulation test, low temperature temperature-change and transformation test, single-sided sensing component manufacturing process Photomask and real part manufacturing The error of process line width is <10%, the operation temperature error rate at 10-300K is <15% at the time of verification of variable temperature photoelectric measurement, and the obtained spectral form uniformity is> 80%,
The focal plane array manufacturing process and its photoelectric homogeneity are verified, conform to the set sensing component standards, the dark current uniformity test is performed, the focal plane array manufacturing process is performed, the test area is selected, and the dark current uniformity is selected. Test once,
In the focal plane array manufacturing process, the line width error of each unit detection inspection unit uniformity is <10%, and the total photocurrent uniformity during the optical spectrum reaction is> 75%,
Focal plane array and signal readout integrated circuit bonding and polishing manufacturing process verification, indium bonding between the plane sensing module and signal readout integrated circuit, the sensing array module converts the photoelectric signal,
The signal sampling and holding unit is stored in an integrating capacitor, i.e. with a sensed signal / noise ratio (S / N ratio),
The injection unit injects a charge signal into the integrating capacitor and outputs it to the output end.
Expander module unit expands signal profits,
The row and column multiple selector unit picks up the sensing unit position in turn,
The clock generation control unit controls reading and signal integration time with the main clock,
Thermal image quality integration test, verification including optical system, adjust optimal drive and control output parameters, analyze and measure module thermal image quality,
Low-temperature vacuum-coolable chamber is a focal plane array and signal readout integrated circuit image chip module and filter, cold isolation inlet tube, infrared lens joint with the outside,
The sensor buffer module is an interface driving module between the focal plane array, the signal readout integrated circuit image chip and the image processing module.
The image display processing circuit module processes and outputs the image data signal,
Analog-digital conversion circuit converts analog signal to digital signal,
The output image data signal processing and control circuit outputs image data based on the signal processing and control circuit,
The retractable time pulse generator generates a time pulse signal,
The retractable power supply circuit provides power to the control processor,
The control processor controls the entire command and output of the image signal and connects to the host computer. When the image sensing array module template is completed, it joins with the focal plane sensing array using the indium column joining method, and the row and column multiple selector unit. Through the signal output in order, output to the sensor buffer module and the image processing system to perform image signal processing,
The focal plane array for low-temperature operation has an environmental cooler control temperature of 40 to 150K ± 0.5K, and the enclosed internal vacuum pressure is 10E-5 to 5E-2torr. The infrared thermal image array module verification method is characterized in that> 98% and the focal plane array module detection and inspection unit operation rate is> 95%.
The invention of claim 29 is the verification method of claim 28, wherein the epitaxial verification epitaxial and high temperature diffusion equipment of the verification method is selected from a molecular beam epitaxial method, a metal organic CVD method, or a high temperature diffusion furnace. The verification method is characterized by manufacturing.
A thirty-third aspect of the invention is the verification method according to the twenty-eighth aspect, wherein the infrared absorption layer design of the epitaxial verification has a quantum localized structure.
The invention according to claim 31 is the verification method according to claim 28, wherein the semiconductor substrate material for the epitaxial verification is selected from gallium arsenide, indium phosphide, dichromium trioxide, silicon and silicon carbide, and the doping form is semi-insulating. Alternatively, the verification method is characterized by being n-type.
According to a thirty-second aspect of the present invention, there is provided a verification method according to the twenty-eighth aspect, wherein a substrate used for the epitaxial verification is a group IV such as silicon, a group III such as gallium arsenide, indium phosphide, and the base type sensing material is antimony. The verification method is characterized by being indium phosphide, mercury cadmium tellurium, or indium phosphide.
The invention of claim 33 is the verification method according to claim 28, wherein the PIN structure of the I-essential layer of the epitaxial verification is formed by using a high temperature diffusion furnace diffusion method, and the P layer diffusion material is arsenic. The verification method is characterized by being a zinc compound, zinc, and cadmium.
The invention according to claim 34 is the verification method according to claim 28, wherein the optical property verification of the verification method includes:
The material lamination rate calibration uses the high reflectivity electron firing method or the quartz oscillate frequency test method, and the lamination rate error is set to 0.01 to 0.05 nm.
Cycle structure perfection inspection measurement uses low angle twin X ray interferometer, photo-fluorescence test or penetrating electron microscope test. After numerical regression calculation, cycle structure uniformity is> 95%,
Structural crystal quality inspection measurement uses low angle twin crystal X-ray interferometer, structural crystal (single crystal and polycrystal) uniformity is> 90%,
Polarity and doping concentration calibration uses capacitor voltage verification method, low temperature molding measurement and secondary ion mass spectrometer method, and polarity judgment and doping concentration composition error are> 98% and <0.5E1 times, respectively It is a verification method.
The invention of claim 35 is the verification method of claim 28, wherein the etching water solvent of the verification method is a weak pH acid solution, hydrogen peroxide: deionized water = 2 to 5: 1 to 2: 5 to 20 This is a verification method characterized by
A thirty-sixth aspect of the present invention is the verification method according to the twenty-eighth aspect, characterized in that the etching depth of the verification method is an altitude between the electron and electric tunnel layers generated from the upper part of the component layer structure.
According to a thirty-seventh aspect of the present invention, in the verification method according to the twenty-eighth aspect, the contact metal material used by the upper and lower electrode sections of the sensing component is a metal electrode manufactured by thermal evaporation, electron gun heating evaporation, or ion sputtering. The verification method is characterized by
The invention of claim 38 is the verification method according to claim 28, wherein the N type of the metal material is palladium / chromium / gold germanium alloy / gold and the P type is palladium / chromium / gold beryllium alloy or zinc / The verification method is characterized by being gold.
The invention of claim 39 is the verification method according to claim 28, wherein in the verification method, the rapid extinguishing manufacturing process has a heating stable temperature and time of 350 to 500 ° C. and 15 to 60 sec, respectively, and a heating temperature ramp rate of 100 to The verification method is characterized by 200 ° C / sec.

The invention of claim 40 is the verification method according to claim 28, wherein the non-part area of the verification method is an I-essential layer and can prevent a lateral overflow current.
The invention according to claim 41 is the verification method according to claim 28, wherein the plane type of the verification method defines a part area manufacturing process, is used for a high-temperature diffusion P-polar diffusion depth of 0.5 to 5 μm, and a surface polishing method 1 to This is a verification method characterized by polishing to 0.25 to 2 μm with 5 μm particle diameter aluminum oxide powder: deionized water = 1: 2 to 5) to form an optimal P-pole region.
The invention according to claim 42 is the verification method according to claim 28, wherein the platform type of the verification method defines a sensing part area manufacturing process, defines an etching area using photomask lithography, and an etching area depth is lower than the lower edge height. Aluminum oxide powder that must exceed between 1/3 and 1/2 of the doping polarity zone thickness, used for high temperature diffusion P-polar diffusion depth 0.5-5μm, and surface polishing method 1-5μm particle diameter: It is a verification method characterized by polishing to 0.25 to 2 μm with ionic water = 1: 2 to 5 to form an optimal P-pole region.
The invention according to claim 43 is the verification method according to claim 28, wherein the quantum well sensing part structure manufacturing step of the verification method uses photomask lithography to define the etching zone, and the etching zone depth is the thickness of the lower high doping polar zone. After that, the cycle light fence structure is increased, and the structure is a one-dimensional rod shape, two-dimensional square shape or rhombus shape, and the distance between the light fences and the altitude is 1. The verification method is characterized by being between -5 μm and 10-500 nm.
A 44th aspect of the present invention is the verification method according to the 28th aspect, characterized in that the surface of the coating polymer layer of the verification method is subjected to exudation of moisture and contaminants from the outside.
45. The verification method according to claim 28, wherein the injection unit of the verification method is composed of four or more sets of metal oxide semiconductor electric field transistors and a set of integration capacitors. Yes.
According to a 46th aspect of the present invention, in the verification method according to the 28th aspect, the signal readout integrated circuit of the verification method is converted into a photoelectric signal pickup, and each pixel unit has one set of buffer, direct injection, gate pole change, capacitor resistance. The verification method is characterized by corresponding to a conversion expansion type injection pickup signal integration unit.
According to a 47th aspect of the present invention, in the verification method according to the 28th aspect, the adhesive injection step of the verification method needs to be filled with an adhesive between the focal plane array module in which the sensing component array and the signal readout integrated circuit are coupled. It is characterized by detecting the unoccupied portion with a photomask, putting the polymer (Polymer) in the polymerization adhesive liquid, and waiting for the bubbles to come out from the boundary position between the sensing component array and the signal readout integrated circuit chip. As a verification method.
According to a 48th aspect of the present invention, in the verification method according to the 28th aspect, the main clock of the verification method is supplied to the computer via a virtual device, and the entire control command and the image signal output structure are stored in the host computer via the RS232 interface. It is a verification method characterized in that it is connected to the Bit I / F interface card of No. 1 and has a command and I / O function.

The infrared thermal image array module verification structure and verification method of the present invention includes thermal image module standard design, epitaxial and optical physical property verification, and first calibrates epitaxial parameters. In the sensing waveband, short, medium and long infrared rays are used to absorb the waveband.After passing, the single sensor type sensing component manufacturing process and temperature-variable photoelectric measurement verification are performed. Complete transformer measurement calibration. After passing this verification, the focal plane array manufacturing process and its photoelectric uniformity are verified, a dark current uniformity test is performed, and if not, the process returns to thermal image module standard design, epitaxial and optical physical property verification. After passing, the adhesion between the focal plane array and the signal readout integrated circuit and the polishing manufacturing process verification are performed, and indium adhesion is performed between the plane sensing module and the signal readout integrated circuit to convert the photoelectric signal. If it fails, return to the focal plane array manufacturing process and verification of the photoelectric uniformity, and verify again.
After passing, the thermal image quality integration test verification is continued and the optimum drive and control output parameter analysis and measurement are adjusted. If it fails, the process returns to the verification of the adhesion of the focal plane array and the signal readout integrated circuit and the polishing manufacturing process. After the acceptance, the thermal image array module template is continuously performed, and the indium column bonding method is used to join the focal plane sensing array to complete the image sensing array module template.

As shown in FIG. 1, which is a flowchart of the infrared thermal image array module of the present invention, the present invention includes thermal image module standard design, epitaxial and optical physical property verification 10, and first calibrates epitaxial parameters, Absorbs wave bands using short, medium and long infrared rays.
The sensing module infrared penetration substrate 102 selects the superiority or inferiority of the sensing module quality, and immediately affects the penetration rate of infrared rays that receive a wave band.
In the bottom edge highly doped contact layer 104, infrared affects the contact quality between the semiconductor and the conductive metal ohmic.
The infrared absorption layer 106 (also referred to as the number of periods of the main active layer) absorbs the infrared-affected light increase and quantum efficiency.
The essential layer 108 (also referred to as a depletion layer) absorbs the thickness of the infrared rays and the magnitude of the intrinsic concentration, and affects the quantum efficiency and the dark current value of the sensing component.
The failure-inhibiting layer 110 affects the intrinsic resistance of the sensing component, and codes the high injection photocurrent efficiency, the sensing component dark current value, and the activation ability value at the operating temperature.
The top edge highly doped contact layer 112 affects the ohmic contact characteristics and the efficiency of the photocurrent output.

After passing the above verification, the single sensor type sensing component manufacturing process and the variable temperature photoelectric measurement verification 20 are performed.
In fact, Epitaxial has completed adhesion test insulation of heat conductive adhesive, and is derived via gold wire through coaxial wire or low noise signal wire, low temperature change and transformation measurement dark current, dark electrical resistance, reaction spectral, detection sensitivity calibration After passing through this verification, the focal plane array manufacturing process and its photoelectric uniformity verification 30 are performed. If not, the process returns to the thermal image module standard design, epitaxial and optical physical property verification 10 and verification is performed again.
After the acceptance, the focal plane array manufacturing process and its photoelectric uniformity verification 30 are performed, and the focal plane array manufacturing process is performed according to the sensing component standard encoded in the setting. The process performs an array policy according to the single-end type parameter used. After this, a test area is selected and a dark current uniformity test is performed. Subsequently, the selected test area is subjected to a dark current uniformity test, and after passing the verification, the focal plane array, the signal readout integrated circuit adhesion, and the polishing manufacturing process verification 40 are performed. If not, the process returns to the thermal image module standard design, epitaxial and optical physical property verification 10 and verification is performed again.

After passing, the focal plane array, signal readout integrated circuit adhesion and polishing manufacturing process verification 40 are performed, and indium bonding is performed between the plane sensing module and the signal readout integrated circuit for the convenience of the photoelectric conversion of the sensing array module. .
The row sample is held, the circuit unit is enlarged 418, stored in the integrating capacitor 1020, and the sensed signal / noise ratio (S / N ratio) is input to the injection unit 412. The injection unit 412 injects a charge signal into the integrating capacitor 1020 and outputs it to the output terminal.
Amplifier module unit, increased signal profits.
Row 414 and column 416 multi-selector units pick up a sequence of sensing units.
The clock generation control unit 420 controls reading and signal integration time by the main clock 426, and after passing the verification, performs the image integration test (including the optical system) verification 50. In the case of failure, the process returns to the focal plane array manufacturing process and its photoelectric uniformity verification 30 to perform verification again.

After passing, the image integration test (including the optical system) verification 50 is continuously performed, the optimum drive is adjusted, the output parameter is controlled, and the module thermal image quality is analyzed and measured.
Among them, the low-temperature vacuum coolable chamber 502 is a focal plane array, a signal reading integrated circuit image chip module and a filter, a cold isolation inlet tube, and an infrared lens joint with the outside.
The sensor buffer module 524 is an interface driving module between the focal plane array, the signal reading integrated circuit image chip, and the image processing module.
The image display processing circuit module 526 processes and outputs an image data signal.
The control processor 522 controls the entire command and image signal output, and is connected to the host computer.
After passing the verification, the thermal image array module template completion 60 is performed. When the verification is not successful, the process returns to the focal plane array, the signal readout integrated circuit adhesion, and the polishing manufacturing process verification 40, and the verification is performed again.

  After the acceptance, the thermal image array module template completion 60 is continuously performed, and the indium column bonding method is used to join the focal plane sensing array. The photocurrent in each array unit is stored in the integrating capacitor 1020 signal, whereby the column 412 and row 416 multiplexers are sent in sequence to the sensor buffer module 524 via the signal output, and the image signal in the image processing system. Then, the thermal image array module template is completed 60.

  As shown in FIGS. 1 and 2 which are structural diagrams of the present invention, the thermal image module standard design, epitaxial and optical property verification 10 of the present invention is based on the design parameters, and the infrared sensing component in the required thermal image array module. Standard definition of structure. The epitaxial and high-temperature diffusion equipment uses molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or high-temperature diffusion furnace (HTDO) as the manufacturing method for the optimal component structure. . If the infrared absorption layer 106 is designed as a quantum confined structure such as quantum well (Quantum Well) or quantum dot (Quantum Dot) sensing structure operation, it is biased toward the molecular beam epitaxial method or the metal organic CVD method.

  On the other hand, if the sensing structure mainly consists of a bulk type PN or PIN, M is always grown on the N and I layers by molecular beam epitaxy or metal organic CVD, and then diffused at higher temperatures. Use a furnace to diffuse the P layer. The substrate used is Group 4 such as silicon (Si), Group 35 such as GaAs, Inp, etc., and its sensing material, cycle structure and thickness are Si / SizGel-z (z = 0.1 to 0.5, 10 to 40 nm / 1 10 nm, 10-50 cycles), AlxGal-xAs / GaAs (x = 0.1-0.5, 10-40 nm / 1-10 nm, 10-50 cycles), AlxGal-xAs / InyGal-yAs / GaAs (x = 0.1-0.5, y = 0.1 to 0.3, 10 to 40 nm / 1 to 5 nm / 1 to 10 nm, 10 to 50 cycles), the substrate type sensing material is InSb, MCT, Inp, and the PIN of I-essential layer (thickness: 0 to 5 μm) It has a structure, and the P pole is formed using the HTDO diffusion method, and the P pole diffusion material is a ZnAs compound, Zn, Cd, and the depth is 1 to 3 μm.

Before the design sensing component structure is grown by molecular beam epitaxy, metal organic CVD, or high-temperature diffusion furnace (HTDO) epitaxial diffusion machine stand, first, material stacking ratio, cycle structure integrity, structural crystal quality, polarity and doping It is necessary to calibrate epitaxial parameters such as concentration. The above is the process of epitaxial structure design of the sensing component module structure, epitaxial parameter verification and sensing component structure.
After this, a part of the same sensing component epitaxial piece (about 1/4 to 1/5 of the total chip area) is cut out, and the single-end sensing component manufacturing process and photoelectric characteristic measurement verification 20 are performed, mainly the actual epitaxial is completed. Check the photoelectric characteristics and quality difference between the sensing part structure and the design part structure.

  During the manufacturing process of single-end type sensing parts, the photomask entity part manufacturing process line width is <10% error, and when performing temperature-variable photoelectric measurement verification, the operating temperature error from 10 to 300K is <15%, resulting spectrum The uniformity of the morphology is> 80%, and it is a suitable etching water solvent to be adjusted (including weak PH value acid solution: hydrogen peroxide: deionized water = 2 to 5: 1 to 2: 5 to 20). The etching reading is the thickness (about 1 to 10 μm) between the electron-electric hole layers generated in the upper part of the component layer structure layer, and the purpose is to prevent side leakage current. If it is a Planar-type defined part area manufacturing process, use it in the high-temperature diffusion P-pole (diffusion depth 0.5-5 μm), and also use a surface polishing method (1-5 μm particle size aluminum oxide: deionized water) = 1 to 2 to 5), polishing to 0.25 to 2 μm to form an optimal P-pole area. The non-component area is an I-essential layer lateral spreading current, and the photocurrent localization flows from the component main structure layer to the contact electrode region to achieve maximum quantum efficiency.

  Subsequently, plasma enhanced chemical vapor deposition (PECVD) method (substrate temperature is 300 to 500 ° C), photochemical deposition (plasma vapor deposition, PVD) (substrate temperature is 80 to 200 ° C), ion sputtering (generally He (Using an Ar ion blunt gas) or a thermal evaporation plating method to grow silicon oxide (SiOx) or silicon nitride (SiNx). The surface insulating coating layer 116 of the sensing component has a thickness of 50 to 300 nm, and the chemical ion dry method (Reactive Ion Etching, RIE) S is a wet etching method (hydrogen fluoride: deionized water, Buffer HF: DI water = 1-5: 20) defines the semiconductor contact metal section, and if the contact metal material used by the upper 114 and lower 1010 electrode sections of this type is N-type, palladium (Pd) 1-20 nm / chrome ( Cr) 1-20nm / gold Germanium alloy (Au / Ge) 50-300nm / gold (Au) 50-300nm, P-type palladium (Pd) 1-20nm / chrome (Cr) 1-20nm / gold beryllium alloy ( Au / Be) or zinc (Zn) 50 to 300 nm / gold (Au) 50 to 300 nm, and a metal electrode is manufactured using thermal evaporation, electron gun warm evaporation or ion sputtering.

Rapid Thermal Annealing (RTA) manufacturing process forms an optimal ohmic contact between semiconductor and metal. The heating stable temperature and time are 350 to 500 ° C. and 15 to 60 sec, respectively, and the heating temperature ramp rate is 100 to 200 ° C./sec. If defined by the platform (Mesa) sensing component area manufacturing process, the etching area depth is more than 1/3 to 1/2 of the lower high doping polarity area thickness, in addition to using photomask lithography to define the etching area. Must. Other manufacturing processes are the same as those of the planar type.
In the quantum well sensing part structure manufacturing process, a cycleable light fence structure must be added after the platform type sensing part area manufacturing process. Its structure is a one-dimensional rod shape, two-dimensional square shape or rhombus shape, and the distance between light fences and altitude are the same as the etching method between 1-5μm and 10-500nm and the platform type sensing definition area manufacturing process method. The above is the main step of the single-type sensing component manufacturing process, and its purpose is to use this manufacturing process parameter and make it a reference parameter for manufacturing the focal plane array structure.

  After completing the single-unit type sensing component structure, adhere to the test insulation base (aluminum oxide carrier base, etc.) with a heat conductive adhesive, pull out the upper and lower signal ends of the gold wire, put it in a circulating liquid helium low temperature variable temperature vacuum chamber, In addition, the terminal pin signal line is derived from the feedthrough interface through a coaxial conductor or low noise signal line, via low temperature temperature change and transformation measurement, dark current, dark electrical resistance, reaction spectral (by FTIR spectrum analyzer, Incident light source, Fourier spectrum conversion is performed to obtain absorption spectrum distribution, low noise current expander: voltage setting, signal sensitivity and profit increase expansion, detection inspection degree calibration (black body radiation source, FTIR light source intensity calibration) , Phase lock magnifier, synchro-tuning photocurrent conversion control voltage signal reading) If it meets the defined sensing component standards such as signal-to-noise ratio, photoreaction waveband, reactivity, detection inspection degree, dark current, dark differential electrical resistance, etc., 3/4 ~ 4/5 of the same piece sensing epitaxial The chip area is a photomask using an array type.

  In addition, the focal plane array manufacturing process is performed directly, the uniformity line width error of each unit detection inspection unit is <10%, the total photocurrent uniformity during spectral reaction is> 75%, The mold parameters are mainly used for array production. Finally, a dark current uniformity test 13 is added to the component test section, and if the sensing array manufactured using a low energy gap sensing material is indium antimonide or mercury cadmium antimony, plasma and ultraviolet light assists on the sensing array surface. By using a method such as VD or superheated vacuum lamination, a passivation layer (thickness: 50 to 300 nm) such as silicon oxide or silicon nitride, or a spin coating film polymer layer (thickness: 0.5 to 3 μm) is placed on the array layer. Need to grow. The main purpose is to prevent the surface from being exposed to ambient moisture or oozing of contaminants, increasing the moist energy state of the surface, creating a side dark current and affecting the sensing quality.

  Next, as shown in FIG. 3, which is a structural diagram of the present invention, indium pillars 118 (altitude is 3 to 12 μm and the bottom area is smaller than the metal electrode section) grown on the upper and lower metal electrode ends are The signal readout integrated circuit performs indium bonding at the moment of reaching the melting point of the indium column using a heating method (temperature is 90 to 200 ° C.). Subsequently, an adhesive injection solidification process (Polymer polymer material, etc.) is performed to complete a perfect focal plane array and signal readout integrated circuit structure. In the figure, a focal plane array within a set of nxn pixels and a signal readout integrated circuit single structure unit are displayed. The main function of the signal readout integrated circuit is photoelectric signal pickup conversion, and the structure of each pixel unit corresponds to a set of buffer, direct injection, gate pole adjustment, capacitor resistance conversion expansion injection pickup signal integration unit It is. Therefore, by utilizing the degree of support between the focal plane array sensing unit structure and the signal readout integrated well module, the shear stress accumulation caused by polishing is released moderately.

In the adhesive injection process, first, a portion that does not need to be filled with an adhesive between the focal plane array module to which the sensing component array and the signal readout integrated circuit are coupled is protected with a photomask, and the polymer (Polymer) is protected with the polymerization adhesive liquid. insert. It is sufficient if the bubbles do not come out from the boundary position between the sensing component array and the signal readout integrated circuit chip. After being taken out, put it in the culture and dry it in a moisture-proof box. After at least 8 to 12 hours, the protective photomask and the remaining adhesive originally fixed on the focal plane array module chip are removed again with an organic solution such as acetone and trichloromethane.
Finally, as shown in FIG. 4, it is similar to a single-end type sensing chip, and is first fixed on a 68 or 84 pin chip base with a thermally conductive adhesive. Bonding pin connection methods on the base are a focal plane array and a tunnel output end point 70 in a signal readout integrated circuit, a bias and power supply end point 72, a clock end point 74, a chip temperature sensing diode output end point 76, and an output module end point 78. Each of the end points is a sense conversion output signal, a power supply signal, a clock and synchro drive input output I / O signal, a test diode signal, and an operating temperature inspection measurement signal.

  As shown in FIG. 5 which is a block chart of the present invention, after completion, it is placed in a low-temperature vacuum coolable chamber 502 and a clock driving process is first performed by a clock generation module 510. The purpose is to provide a normal working state for the focal plane array module 508 and maintain the output signal in a normal working mode. At this time, using the digital scope, the image analog output terminal in the sensor buffer board module 524 is cut out, and the required output signal standard is confirmed. Before this, the focal plane array at room temperature and the signal readout integrated circuit junction resistance value signal screen will be tested to understand the basic bonding situation. Further, the temperature is set to an appropriate temperature operating range of the infrared thermal image array module waiting for verification. This operating temperature is an absolute Casparian temperature of 40-300K. The temperature stabilizes at this set temperature, and at least 15 minutes later, the bias establishment module 512 adjusts the external module operation bias and switches between absolute values of pressure to be connected across the sensing component, between 10MV and 4V. . Adjustment signal readout Integration time in integrated circuit is adjusted corresponding to between 10μsec and 32msec. The functional ends of the signal conversion inhibition expansion and compensation 504 and the buffer profit increase function 506 are determined based on the post-class expansion and the complementary circuit. All of the above important adjustment parameters are adjusted to the background of the image sensing module sensing monotonous middle temperature zone, and the original image signal is gray level on the display monitor.

  At the same time, the image output end signal is continuously monitored by the scope, and a relatively large dynamic value is displayed with respect to the temperature change. In this image display processing circuit module (Video Processing System) 526, an analog / digital conversion circuit 514, an output image data signal processing and control circuit 516, a flexible type pulse generation circuit 518, and a flexible type power supply circuit 520 are designed. The main clock is also supplied to the computer via the VME bus transmission key, and the entire control command and image signal output structure are also connected to the Bit I / F interface card of the control processor 522 in the host computer via the RS232 interface. Perform the / O function. Subsequently, an infrared optical lens is further installed at the focal length position of the sensing module (F # is 1.5 to 3.5), and the thermal image integration test (including the optical system) 50 performs fine adjustment of parameters. Finally, image signal linearity compensation is performed at two points, low temperature and high temperature, and the uniformity of the dynamic image is calibrated.

Next, as shown in FIG. 6 which is a three-dimensional view of the present invention, after the completion of the image adjustment process, the focal plane array of the focal plane sensing array and the signal readout integrated circuit module are connected to the sensing module during the production of the infrared thermal image array module. After confirming that the infrared light signal 802 can be received by the back contact zone 804, the read circuit chip 808 of the signal readout integrated circuit is connected to the indium column junction type and the sensing array by the photocurrent input terminal 806 on the signal readout integrated circuit. A signal stored in the integrating capacitor 1020 by the photocurrent in each array unit by the focal plane array junction is sequentially sent to the sensor buffer plate module 524 and the image display processing circuit via the signal output terminal 814 by the column 810 and the row multiplexer 812. It is sent into the module 526 to perform processes such as image signal processing.
The control temperature of the focal plane array environmental cooler for low-temperature operation is 40 to 150K ± 0.5K, and the enclosed internal vacuum pressure is 10E-5 to 5E-2torr. The uniformity of the image screen after the image quality compensation for both points is> 98%, the operation rate of the EPA module detection inspection unit is> 95%, and finally, a set of image module templates 60 is completed.

It is a flowchart of the infrared thermal image array module of this invention. It is a structural diagram of the infrared thermal image array module of the present invention. It is a structural diagram of the infrared thermal image array module of the present invention. It is a top view of the infrared thermal image array module of this invention. It is a block chart of the infrared thermal image array module of this invention. It is a three-dimensional view of the infrared thermal image array module of the present invention.

Explanation of symbols

10 Thermal image module standard design, epitaxial and optical physical property verification 20 Single sensor type manufacturing process and variable temperature photoelectric measurement verification 30 Focal plane array manufacturing process and photoelectric homogeneity verification 40 Focal plane array and signal readout integrated circuit adhesion and polishing Manufacturing process verification 50 Image integration test (including optical system) verification 60 Thermal image array module template completion 102 Sensing module infrared penetrating substrate 104 Bottom edge high doping contact layer 106 Infrared absorption layer 108 Essential layer 110 Failure inhibition layer 112 Top edge height Miscellaneous doping contact layer 114 Upper electrode section 116 Sensing component surface insulation coating layer 118 Indium pillar 1010 Lower electrode section 1012 Possible output to P-MOSFET transistor 1014 P-MOSFET transistor switching output and installation 1016 Sensing component adjustment and P -The MOSFET transistor can be biased 1018 Is installed again in the P-MOSFET transistor 1020 Integration capacitor 1022 Select possible end point 1024 Inject pressure into end point 1026 Install end point again 1028 Negative end point 1030 Signal output end 412 Injection unit 414 Row multiplexer 416 Column multiplexer 418 Row sample 420 Clock generation control unit 424 Line clock 426 Main clock 428 Row selection port 2110 Column port is re-installed 2111 Column selection port 2112 Column port is re-installed 2113 A tunnel output end 2114 B tunnel output End 70 tunnel output end point 72 bias and power supply end point 74 clock end point 76 chip temperature sensing diode output end point 78 output module end point 502 low temperature vacuum coolable chamber 524 sensor buffer plate module 504 Compensation 506 Buffer Increase Function 508 Focal Plane Array Module 510 Clock Generation Module 512 Bias Pressure Establishing Module 526 Image Display Processing Circuit Module 514 Analog-to-Digital Conversion Circuit 516 Output Image Data Signal Processing and Control Circuit 518 Random Time Pulse Generation Circuit 520 Random Power Supply circuit 522 Control processor 524 Sensor buffer module 802 Infrared light signal incident 804 Sensing module backside contact zone 806 Photocurrent input terminal 808 on signal readout integrated circuit Signal readout integrated circuit reader circuit chip 810 Column multiplexer (multiplexing) Communication device)
812 row multiplexer 814 signal output terminal

Claims (48)

Wave band detection uses short, medium and long infrared rays to absorb wave bands,
Sensing module infrared penetration board selects the superiority or inferiority of sensing module quality, affects the infrared penetration rate of waveband reception,
Bottom edge highly doped contact layer affects semiconductor and conductive metal ohmic contact quality,
The infrared absorbing layer is also referred to as the main active layer, the number of cycles affects the light enhancement and quantum efficiency, and the thickness of the intrinsic layer or depletion layer and the magnitude of the intrinsic concentration affect the quantum efficiency and the dark current value of the sensing component. Give,
The failure-inhibiting layer affects the resistance of the sensing component, matching the high injection photocurrent efficiency, the sensing component dark current value, and the activation ability value under the operating temperature,
Thermal image module standard design, epitaxial and optical properties verification of infrared thermal image array module verification structure, characterized in that the top high impurity doping contact layer affects ohmic contact characteristics and photocurrent output efficiency.   2. The verification structure according to claim 1, wherein the epitaxial verification epitaxial and high-temperature diffusion equipment is a molecular beam epitaxial method, a metal organic CVD method, or a high-temperature diffusion furnace to manufacture a structural component. .   The verification structure according to claim 1, wherein the infrared absorption layer design for the epitaxial verification is a quantum localized structure.   2. The verification structure according to claim 1, wherein the semiconductor substrate material for the epitaxial verification is selected from gallium arsenide, indium phosphide, dichromium trioxide, silicon, and silicon carbide, and the doping form is semi-insulating or n-type. Feature verification structure.   2. The verification structure according to claim 1, wherein a substrate used for the epitaxial verification is a group IV such as silicon, a group III such as gallium arsenide, indium phosphide, and the base type sensing material is indium antimonide, mercury cadmium telluride, A verification structure characterized by being indium phosphide.   2. The verification structure according to claim 1, wherein the PIN structure of the I-essential layer of the epitaxial verification is formed using a high temperature diffusion furnace diffusion method, and the P layer diffusion material is composed of a zinc arsenide compound, zinc, and cadmium. A verification structure characterized by being. The verification structure according to claim 1, wherein the optical physical property verification includes:
The material lamination rate calibration uses the high reflectivity electron firing method or the quartz oscillate frequency test method, and the lamination rate error is set to 0.01 to 0.05 nm.
Cyclic structure perfection inspection measurement uses low-angle twin crystal X-ray interferometer, intense fluorescence test or penetrating electron microscope test. After numerical regression calculation, cycle structure uniformity is> 95%,
Structural crystal quality inspection measurement uses low angle twin crystal X ray incinerator, structural crystal, single crystal and polycrystal uniformity are> 90%,
Polarity and doping concentration calibration uses capacitor voltage verification method, low temperature molding measurement and secondary ion mass spectrometer method, and polarity judgment and doping concentration composition error are> 98% and <0.5E1 times, respectively Validation structure.   Single-type sensing part photomask and solid part manufacturing process line width error is <10%, operation temperature error rate at 10-300K is <15% at the time of variable temperature photoelectric measurement verification, and the obtained spectral shape uniformity is Single-infrared sensing component manufacturing process and temperature-variable photoelectric measurement verification of infrared thermal image array module verification structure characterized by> 80%.   9. The verification structure according to claim 8, wherein the etching water solvent of the verification structure is a weak PH acid solution, and hydrogen peroxide: deionized water = 2 to 5: 1 to 2: 5 to 20. Validation structure.   9. The single-end type sensing component manufacturing process according to claim 8 and variable temperature photoelectric quantity measurement verification, wherein the etching depth is an altitude between the electron-to-electric layer generated from the upper part of the component layer structure. Component manufacturing process and variable temperature photoelectric measurement verification.   9. The verification structure according to claim 8, wherein the contact metal material used by the upper and lower electrode sections of the sensing part is a metal electrode manufactured by thermal evaporation, electron gun warm deposition or ion sputtering.   9. The verification structure according to claim 8, wherein the N type of the metal material is palladium / chromium / gold germanium alloy / gold and the P type is palladium / chromium / gold beryllium alloy or zinc / gold. Verification structure to be   9. The verification structure according to claim 8, wherein in the verification structure, the rapid extinguishing manufacturing process has a heating stable temperature and time of 350 to 500 ° C. and 15 to 60 sec, respectively, and a heating temperature gradient is 100 to 200 ° C./sec. A verification structure characterized by   9. The verification structure according to claim 8, wherein the non-component area of the verification structure is an I-essential layer and can prevent a lateral overflow current. 9. The single-type sensing component manufacturing process and the variable photoelectric measurement measurement verification according to claim 8, wherein the plane type of the single-type sensing component manufacturing process and the variable photoelectric measurement measurement verification defines a component area manufacturing process, and high-temperature diffusion Used for P-electrode, diffusion depth 0.5-5μm, surface polishing method 1-5μm particle diameter aluminum oxide powder: deionized water = 1: 2-5, polished to 0.25-2μm,
Single sensor type manufacturing process and variable temperature photoelectric measurement verification characterized by forming the optimal P-pole area.   9. The verification structure of claim 8, wherein the platform type of the verification structure defines a sensing component area manufacturing process, defines an etching area using photomask lithography, and the etching area depth is 1 / th of the lower high doping polarity area thickness. Between 3 and 1/2 must be exceeded, high-temperature diffusion P-extreme diffusion depth 0.5-5μm, surface polishing method 1-5μm particle diameter aluminum oxide powder: deionized water = 1: 2 ~ 5. Verification structure characterized by polishing to 0.25-2μm to form the optimal P-pole area.   9. The verification structure according to claim 8, wherein the quantum well sensing component structure manufacturing process of the verification structure defines an etching zone using photomask lithography, and the etching zone depth is 1/3 to 1/1 / th of the lower high doping polarity zone thickness. After that, the cycle light fence structure is increased, and the structure is one-dimensional rod-shaped or two-dimensional square or rhombus shape, the distance between the light fence and the altitude is between 1 ~ 5μm and 10 ~ 500nm A verification structure characterized by   Infrared thermal image array module verification, characterized in that the line width error of each unit detection inspection unit uniformity during the focal plane array manufacturing process is <10% and the total photocurrent uniformity during photospectral reaction is> 75% The focal plane array manufacturing process of the structure and its photoelectric uniformity verification.   19. The verification structure according to claim 18, wherein the film polymer layer of the verification structure prevents the surface from being exposed to moisture and / or contaminants from the outside. The signal sampling and holding unit is stored in an integrating capacitor, i.e. with a sensed signal / noise ratio (S / N ratio),
The injection unit injects a charge signal into the integrating capacitor and outputs it to the output end.
Expander module unit expands signal profits,
The row and column multiple selector unit picks up the sensing unit position in turn,
The clock generation control unit controls the reading and signal integration time by the main clock, the focal plane array of the infrared thermal image array module verification structure, the signal readout integrated circuit bonding and polishing manufacturing process verification.   21. The verification structure according to claim 20, wherein the injection unit is composed of four or more sets of metal oxide semiconductor electric field transistors and a set of integration capacitors.   21. The verification structure according to claim 20, wherein said signal readout integrated circuit performs photoelectric signal pickup conversion, and each pixel unit corresponds to one set of buffer, direct injection, gate pole modulation, capacitor resistance conversion expansion injection pickup signal integration unit. A verification structure characterized by   21. The verification structure according to claim 20, wherein the adhesive injection step of the verification structure first protects a portion that does not need to be filled with adhesive between the focal plane array module in which the sensing component array and the signal readout integrated circuit are coupled by a photomask. And verifying that the polymer is put in a polymer adhesive solution and waiting for bubbles to come out from the boundary position between the sensing component array and the signal readout integrated circuit chip. Low-temperature vacuum-coolable chamber is a focal plane array and signal readout integrated circuit image chip module and filter, cold isolation inlet tube, infrared lens joint with the outside,
The sensor buffer module is an interface driving module between the focal plane array, the signal readout integrated circuit image chip and the image processing module.
The image display processing circuit module processes and outputs the image data signal,
The control processor controls the entire command and the output of the image signal, and is connected to the host computer. The infrared image array module structure verification structure thermal image integration test, verification including the optical system. The verification structure according to claim 24, wherein the image display processing circuit board includes:
Analog-digital conversion circuit converts analog signal to digital signal,
The output image data signal processing and control circuit outputs image data based on the signal processing and control circuit,
The retractable time pulse generator generates a time pulse signal,
A verifiable power supply circuit provides a power supply to the control processor.   25. The verification structure according to claim 24, wherein the main clock is supplied to a computer through a virtual device, and the entire control command and image signal output structure are connected to a Bit I / F interface card in a host computer by an RS232 interface. Verification structure characterized by command and I / O functions.   The low temperature operation focal plane array has an environmental cooler control temperature of 40-150K ± 0.5K, and the enclosed internal vacuum pressure is 10E-5-5E-2torr. Thermal image array module template completion verification of infrared thermal image array module verification structure characterized by> 98% and focal plane array module detection and inspection unit operation rate> 95%. Including thermal image module standard design, epitaxial and optical physical property verification, first calibrate the epitaxial parameters, absorb the wave band using short, medium and long infrared in the sense wave band,
The sensing module infrared penetrating board selects the superiority or inferiority of the sensing module's quality, and immediately affects the infrared penetrating rate of receiving wave bands,
The bottom-edge highly doped contact layer affects the contact quality between the semiconductor and the conductive metal ohmic,
The infrared absorbing layer is also referred to as the main active layer, the number of cycles affects the light enhancement and quantum efficiency, and the thickness of the intrinsic layer or depletion layer and the magnitude of the intrinsic concentration affect the quantum efficiency and the dark current value of the sensing component. Give,
The failure-inhibiting layer affects the resistance of the sensing component, matching the high injection photocurrent efficiency, the sensing component dark current value, and the activation ability value under the operating temperature,
The apical high impurity doping contact layer affects ohmic contact characteristics and photocurrent output efficiency,
Single-unit type sensing component manufacturing process and temperature-variable photoelectric measurement measurement verification, actually epitaxial completed heat conduction adhesive insulation test, low temperature temperature-change and transformation test, single-sided sensing component manufacturing process Photomask and real part manufacturing The error of process line width is <10%, the operation temperature error rate at 10-300K is <15% at the time of verification of variable temperature photoelectric measurement, and the obtained spectral form uniformity is> 80%,
The focal plane array manufacturing process and its photoelectric homogeneity are verified, conform to the set sensing component standards, the dark current uniformity test is performed, the focal plane array manufacturing process is performed, the test area is selected, and the dark current uniformity is selected. Test once,
In the focal plane array manufacturing process, the line width error of each unit detection inspection unit uniformity is <10%, and the total photocurrent uniformity during the optical spectrum reaction is> 75%,
Focal plane array and signal readout integrated circuit bonding and polishing manufacturing process verification, indium bonding between the plane sensing module and signal readout integrated circuit, the sensing array module converts the photoelectric signal,
The signal sampling and holding unit is stored in an integrating capacitor, i.e. with a sensed signal / noise ratio (S / N ratio),
The injection unit injects a charge signal into the integrating capacitor and outputs it to the output end.
Expander module unit expands signal profits,
The row and column multiple selector unit picks up the sensing unit position in turn,
The clock generation control unit controls reading and signal integration time with the main clock,
Thermal image quality integration test, verification including optical system, adjust optimal drive and control output parameters, analyze and measure module thermal image quality,
Low-temperature vacuum-coolable chamber is a focal plane array and signal readout integrated circuit image chip module and filter, cold isolation inlet tube, infrared lens joint with the outside,
The sensor buffer module is an interface driving module between the focal plane array, the signal readout integrated circuit image chip and the image processing module.
The image display processing circuit module processes and outputs the image data signal,
Analog-digital conversion circuit converts analog signal to digital signal,
The output image data signal processing and control circuit outputs image data based on the signal processing and control circuit,
The retractable time pulse generator generates a time pulse signal,
The retractable power supply circuit provides power to the control processor,
The control processor controls the entire command and output of the image signal and connects to the host computer. When the image sensing array module template is completed, it joins with the focal plane sensing array using the indium column joining method, and the row and column multiple selector unit. Through the signal output in order, output to the sensor buffer module and the image processing system to perform image signal processing,
The focal plane array for low-temperature operation has an environmental cooler control temperature of 40 to 150K ± 0.5K, and the enclosed internal vacuum pressure is 10E-5 to 5E-2torr. Infrared thermal image array module verification method characterized in that> 98% and focal plane array module detection and inspection unit operation rate is> 95%.   29. The verification method according to claim 28, wherein the epitaxial verification epitaxial and high-temperature diffusion equipment of the verification method selects a molecular beam epitaxial method, a metal organic CVD method, or a high-temperature diffusion furnace to manufacture a structural component. Verification method to do.   29. The verification method according to claim 28, wherein the infrared absorption layer design of the epitaxial verification is a quantum localized structure.   29. The verification method according to claim 28, wherein the semiconductor substrate material for the epitaxial verification is selected from gallium arsenide, indium phosphide, dichromium trioxide, silicon and silicon carbide, and the doping form is semi-insulating or n-type. Feature verification method.   29. The verification method according to claim 28, wherein a substrate used for the epitaxial verification is a group 4 such as silicon, a group 35 such as gallium arsenide, indium phosphide, and the base type sensing material is indium antimonide, mercury cadmium telluride, A verification method characterized by being indium phosphide.   29. The verification method according to claim 28, wherein the PIN structure of the I-essential layer of the epitaxial verification is formed using a high temperature diffusion furnace diffusion method, and the P layer diffusion material is composed of a zinc arsenide compound, zinc, and cadmium. A verification method characterized by being. The verification method according to claim 28, wherein the optical property verification of the verification method includes:
The material lamination rate calibration uses the high reflectivity electron firing method or the quartz oscillate frequency test method, and the lamination rate error is set to 0.01 to 0.05 nm.
Cyclic structure perfection inspection measurement uses low-angle twin crystal X-ray interferometer, intense fluorescence test or penetrating electron microscope test. After numerical regression calculation, cycle structure uniformity is> 95%,
Structural crystal quality inspection measurement uses low angle twin crystal X-ray interferometer, structural crystal (single crystal and polycrystal) uniformity is> 90%,
Polarity and doping concentration calibration uses capacitor voltage verification method, low temperature molding measurement and secondary ion mass spectrometer method, and polarity judgment and doping concentration composition error are> 98% and <0.5E1 times, respectively Method of verification.   29. The verification method according to claim 28, wherein the etching water solvent of the verification method is a weak pH acid solution, and hydrogen peroxide: deionized water = 2-5: 1-2: 5-20. Method of verification.   29. The verification method according to claim 28, wherein an etching depth of the verification method is an altitude between the electron-electric tunnel layers generated from an upper part of the component layer structure.   29. The verification method according to claim 28, wherein the contact metal material used by the upper and lower electrode sections of the sensing component is a metal electrode manufactured by thermal vapor deposition, electron gun warm vapor deposition, or ion sputtering.   29. The verification method according to claim 28, wherein the N type of the metal material is palladium / chromium / gold germanium alloy / gold and the P type is palladium / chromium / gold beryllium alloy or zinc / gold. Verification method to do.   29. The verification method according to claim 28, wherein in the verification method, the rapid extinguishing manufacturing process has a heating stable temperature and time of 350 to 500 ° C. and 15 to 60 sec, respectively, and a heating temperature gradient is 100 to 200 ° C./sec. A verification method characterized by   29. The verification method according to claim 28, wherein the non-component area of the verification method is an I-essential layer and can prevent a lateral overflow current.   29. The verification method according to claim 28, wherein the plane type of the verification method defines a part area manufacturing process, is used for a high temperature diffusion P-polar diffusion depth of 0.5 to 5 [mu] m, and a surface polishing method is 1 to 5 [mu] m particle diameter aluminum oxide powder. : Deionized water = 1: 2 to 5), polishing to 0.25 to 2 μm to form an optimal P-pole area.   29. The verification method according to claim 28, wherein the platform type of the verification method defines a sensing component area manufacturing process, defines an etching area using photomask lithography, and the etching area depth is 1 / th of the lower high doping polarity area thickness. Between 3 and 1/2 must be exceeded, high-temperature diffusion P-extreme diffusion depth 0.5 to 5 μm, surface polishing method 1 to 5 μm particle diameter aluminum oxide powder: deionized water = 1: 2 to 5. A verification method characterized by polishing to 0.25 to 2 μm to form an optimal P-pole area.   29. The verification method according to claim 28, wherein the quantum well sensing component structure manufacturing step of the verification method defines an etching zone using photomask lithography, and the etching zone depth is 1/3 to 1/1 of the thickness of the lower high doping polarity zone. After that, the cycle light fence structure is increased, and the structure is one-dimensional rod-shaped or two-dimensional square or rhombus shape, the distance between the light fence and the altitude is between 1 ~ 5μm and 10 ~ 500nm The verification method characterized by being.   29. The verification method according to claim 28, wherein a surface of the film polymer layer of the verification method is subjected to external moisture and oozing of contaminants.   29. The verification method according to claim 28, wherein the injection unit of the verification method is composed of four or more sets of metal oxide semiconductor electric field transistors and one set of integration capacitors.   29. The verification method according to claim 28, wherein the signal readout integrated circuit of the verification method performs photoelectric signal pickup conversion, and each pixel unit has a set of buffer, direct injection, gate pole change, capacitor resistance change expansion injection pickup signal integration. A verification method characterized by corresponding to a unit.   29. The verification method according to claim 28, wherein the adhesive injection step of the verification method first protects a portion that does not need to be filled with adhesive between the focal plane array module in which the sensing component array and the signal readout integrated circuit are coupled by a photomask. Then, a verification method is characterized in that a polymer is put in a polymer adhesive solution, and waiting until bubbles do not come out from the boundary position between the sensing component array and the signal readout integrated circuit chip.   29. The verification method according to claim 28, wherein a main clock of the verification method is supplied to a computer via a virtual device, and the entire control command and image signal output structure are in a bit I / F interface card in the host computer by an RS232 interface. A verification method characterized in that the command and I / O function are connected to the system.

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