JP2008186245A - Reception device and reception control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reception device and a reception control method capable of saving system power by stopping the supply of power to an RFIC. <P>SOLUTION: Control is performed so that when a report information signal is not received during standby, the supply of power to the RFIC part 12 is stopped, whereas when report information is received during standby, the supply of power to the RFIC part 12 is performed. Once the supply of power to the RFIC part 12 is started, control data retained in an EEPROM 24 is output to an SI2 (data input) signal line. The control data output to the SI2 (data input) signal line is output to a latch circuit (serial/parallel conversion circuit) 41 via an SO (data sending) signal line and stored in a register 42 when an SW 1 and an SW 2 are off and an SW 3 is on. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a receiving apparatus that performs an intermittent receiving operation and a reception control method in the receiving apparatus.

In a portable terminal device such as a cellular phone, when not receiving a notification information signal during standby (intermittent reception), the LSI standby mode or shutdown mode provided by each semiconductor manufacturer is used, and the functions of the LSI specifications are further provided. The system has been used to save power (for example, see Patent Document 1). In addition, for parts that hold control data related to system control, do not turn off the power, always use power supply, and supply power only to parts that do not need to hold data. Power saving is also achieved by stopping the operation. Also, with respect to RFIC (Radio Frequency Integrated Circuit) used in the transmitting / receiving unit of a mobile phone, when not receiving a broadcast information signal at the time of standby, only when using an RFIC of a type that does not hold control data internally, The power supply is also stopped. The RFIC is a general term for various RF control components (IC components) used in the transmission / reception unit of the mobile phone.
JP 2006-211439 A

  However, in the case of using an RFIC of a type that holds control data inside, processing for stopping power supply to the RFIC is not performed. Even for this type of RFIC, it is desirable on the system to stop the power supply to save power as much as possible. However, if the RFIC power supply is stopped to reduce power consumption, all control data Disappears, and when power is supplied to the RFIC again upon reception of the broadcast information signal during standby, there is a problem that the control data cannot be restored to the state before the power supply is stopped.

  The present invention has been made in view of such problems, and an object of the present invention is to stop the power supply to the RFIC and use the system when the RFIC of the type that holds the control data is used. It is an object of the present invention to provide a receiving apparatus and a receiving control method that can reduce power consumption.

  In order to achieve the above object, the present invention provides a receiving apparatus comprising: a receiving means for receiving a signal from a counterpart communication apparatus; and a signal processing means for processing a signal received by the receiving means. Control data output means for outputting control data required for reception of data, and first control data for outputting the control data from the control data output means when the power source is changed from the OFF state to the ON state. A data output control means; a first control data holding means provided in the receiving means for holding the control data output from the control data output means; and the output from the control data output means. A second control data holding means for holding control data at a location different from that of the first control data holding means; and a power supply to the receiving means when the intermittent reception is stopped. Power control means for controlling to supply power to the receiving means at the time of reception in intermittent reception, and for control held in the second control data holding means at the time of reception in intermittent reception And a second control data output control means for outputting the data to the first control data holding means.

  The first control data output control means preferably stops the output of the control data from the control data output means at the time of reception in intermittent reception, and the second control data holding means A non-volatile memory is preferred.

  According to another aspect of the present invention, there is provided a reception control method in a receiving apparatus including a receiving means for receiving a signal from a counterpart communication apparatus and a signal processing means for processing a signal received by the receiving means. A control data output step for outputting the control data required for reception by the receiving means from the signal processing means side when the signal is turned ON, and a first step for holding the output control data in the receiving means. 1 control data holding step, and second control data for holding the control data output from the signal processing means side at a location different from the location held in the first control data holding step When the holding step and intermittent reception are stopped, power supply to the reception unit is stopped, and during reception during intermittent reception, power supply to the reception unit is stopped. Power control step for performing control, and at the time of reception in intermittent reception, the step of outputting the control data held in the second control data holding step to the receiving means, and the output to the receiving means And holding the control data in the receiving means.

  Even if the control data disappears due to the stop of the power supply to the RFIC, the present invention stops the power supply of the control data when the power is supplied again to the RFIC when the broadcast information signal is received at the standby time. Since it is possible to return to the previous state, it is possible to stop the power supply to the RFIC when the broadcast information signal at the time of standby is not received, and the power saving of the system can be achieved.

  Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a system configuration diagram showing a receiving apparatus of the present invention. In the present embodiment, a mobile phone will be described as an example of a receiving device. In FIG. 1, the mobile phone includes an RFIC unit (reception unit) 12 that transmits and receives signals to and from a partner communication device via an antenna 11, and an ASIC unit 17 that processes signals transmitted and received by the RFIC unit 12. . The ASIC unit 17 includes a baseband unit 13 that performs signal modulation / demodulation, a CPU 15, and an SPI (Serial Peripheral Interface) control unit (control data output unit) that outputs control data required for transmission / reception of the RFIC unit 12. 16 is provided.

  In addition, the RFIC unit 12 includes an RF control unit 31, a 4-channel analog-digital converter (4CHAN ADC) 32, a PLL digital-analog converter (PLL DAC) 33, and an SPI control unit 16 when the power is on. And a control register (first control data holding means) 34 for holding the control data output from.

  Further, the mobile phone shown in FIG. 1 further stores an EEPROM (Electrically Erasable Programmable Read Only Memory) (second control data holding means) 24 that holds control data output from the SPI control unit 16 and a program. Memory 25, a liquid crystal display (LCD) 14, a codec unit 18 that performs AD and DA conversion of audio signals, a telephone speaker 22, a telephone microphone 23, and user input information to the CPU 15. A key input unit 19 is provided.

  An SPI (Serial Peripheral Interface) is used as an interface between the control register 34 of the RFIC unit 12, the ASIC unit 17, and the EEPROM 24. The 4-channel analog-digital converter 32 and the PLL digital-analog converter 33 also use SPI as their interfaces. A parallel interface may be used, but the SPI is effective when the transfer amount is small.

  As a power control means, the CPU 15 stops power supply to the RFIC unit 12 when receiving no notification information signal during standby (when intermittent reception is stopped), and when receiving notification information during standby (intermittent). At the time of reception), control is performed so that power is supplied to the RFIC unit 12. In addition, as the first control data output control means, the CPU 15 outputs the control data from the SPI control unit 16 when the power source is switched from the OFF state to the ON state, and the second control data. As the output control means, the control data held in the EEPROM 24 is output to the control register 34 at the time of reception in intermittent reception.

  FIG. 2 is a diagram illustrating an external connection configuration example of the RFIC unit, the ASIC unit, and the EEPROM. The RFIC unit 12 includes a control register 34 including a latch circuit 41 (a circuit corresponding to a “serial / parallel conversion circuit”) and a register 42. Communication between the ASIC unit 17, the RFIC unit 12, and the EEPROM 24 includes an SCLK (clock) signal, an SO (data transmission) signal, an SI (data input) signal, a CS / (chip select) signal, and a GPIO (General Purpose I / O). O: General purpose input / output) signal is used.

  In FIG. 2, when power is supplied to the RFIC unit 12, SW2 is ON, and control data is transferred from the SPI control unit 16 to the latch circuit 41 and the EEPROM 24 via the SO (data transmission) signal line. Then, the control data is stored in the register 42 and the EEPROM 24. If the power supply to the RFIC unit 12 is stopped when the intermittent reception is stopped, the control data stored in the register 42 disappears. When power supply to the RFIC unit 12 is started during intermittent reception, the control data held in the EEPROM 24 is output to the SI2 (data input) signal line. The control data output to the SI2 (data input) signal line is output to the latch circuit 41 via the SO (data transmission) signal line and stored in the register 42 when SW1 and SW2 are OFF and SW3 is ON. Is done. SW1 and SW2 are turned OFF in order to reliably avoid collision between the data output from the SPI control unit 16 of the ASIC unit 17 and the register 42 of the RFIC unit 12 and the control data output from the EEPROM 24. is there.

  FIG. 3 is a diagram illustrating another external connection configuration example of the RFIC unit, the ASIC unit, and the EEPROM. CNTL (control) signal (R (read) / W (write) identification signal (GPIO (General Purpose I / O: general purpose input / output) by software) or SPI control unit control output signal) from the SPI control unit 16 Good))) controls the control data signal output from the register 42 and the EEPROM 24. The CNTL (control) signal is normally “Low”, but becomes “High” when the control data is output from the EEPROM 24. In FIG. 3, when power is supplied to the RFIC unit 12, SW2 is turned on, and control data is output from the SPI control unit 16 to the latch circuit 41 and the EEPROM 24 via the SO (data transmission) signal line. Then, control data is stored in the register 42 and the EEPROM 24. If the power supply to the RFIC unit 12 is stopped when the intermittent reception is stopped, the control data stored in the register 42 disappears. When power supply to the RFIC unit 12 is started during intermittent reception, SW1 is turned on, SW2 is turned off, and when the CNTL (control) signal becomes “High”, data output from the register 42 is stopped. At the same time, the control data held in the EEPROM 24 is output to the SI (data input) signal line. The control data output to the SI (data input) signal line is output to the latch circuit 41 via the SO (data transmission) signal line and stored in the register 42 because SW1 is ON. The reason why SW2 is turned off is to reliably avoid collision between the data output from the SPI control unit 16 of the ASIC unit 17 and the control data output from the EEPROM 24.

  FIG. 4 is a block diagram around the SPI control unit. The SPI control unit 16 is connected to the CPU 15 by using an AHB (Advanced High-performance Bus) interface 20. SW1 and SW2 are signal switching units that switch between an SO (data transmission) signal and an SI (data input) signal. The CPU 15 controls the signal switching units SW1 and SW2 via the SPI control unit 16. The CNTL (control) signal and the SI2 (data input) signal may be GPIO signals. FIG. 5 is a diagram illustrating an example of a circuit on the data input / output side of the SPI control unit.

  In FIGS. 2 and 3 described above, the external connection configuration example in the case where the EEPROM is provided outside the RFIC unit has been described, but the EEPROM may be incorporated in the RFIC unit. FIG. 6 is a diagram showing an external connection configuration example of an RFIC unit and an ASIC unit when using an RFIC unit including an EEPROM having a serial I / F, and FIG. 7 is an RFIC unit including an EEPROM. It is a figure which shows an example of this circuit.

  In FIG. 6, in a state where power is supplied to the RFIC unit 12, a signal line from the SPI control unit 16 is selected in the multiplexer (MUX) 45, and control data is sent from the SPI control unit 16 to SO (data transmission). The data is output to the register 42 and the EEPROM 24 via the signal line, and the control data is stored in the register 42 and the EEPROM 24. If the power supply to the RFIC unit 12 is stopped when the intermittent reception is stopped, the control data stored in the register 42 disappears. When power supply to the RFIC unit 12 is started at the time of intermittent reception, a WAKE UP signal is output from the SPI control unit 16 to the RF control unit 31 and the multiplexer (MUX) 45. When receiving the WAKE UP signal, the RF control unit 31 controls the multiplexer (MUX) 46 so as to select the signal line from the EEPROM 24. The multiplexer (MUX) 45 selects a signal line from the SI (data input) signal line according to the WAKE UP signal. Therefore, at the time of reception in intermittent reception, the control data held in the EEPROM 24 is output to the SI (data input) signal line via the multiplexer (MUX) 46 and SO (data transmission) via the multiplexer (MUX) 45. ) The signal is output to the signal line and stored in the register 42. 6 and 7 describe the RFIC unit with built-in EEPROM, it is of course possible to transmit and receive data within the RFIC unit. In that case, processing and control are managed by the RF control unit, and automatic return is performed by a command signal.

  FIG. 8 is a diagram illustrating an external connection configuration example of the ASIC unit and the EEPROM when the EEPROM is not used. The ASIC unit 17 includes a register 49 that holds control data therein. When the supply of power to the RFIC unit 12 is started at the time of reception in intermittent reception when the control data stored in the register 42 disappears because the power supply to the RFIC unit 12 is stopped, the WAKE UP signal or In response to the WAKE UP command, the control data held in the register 49 of the ASIC unit 17 is stored in the register 42 via the SO (data transmission) signal line. In this way, batch transfer is executed.

  As described above, according to the present invention, even when the control data disappears due to the stop of the power supply to the RFIC, when the broadcast information signal is received at the time of standby, when the power is supplied again to the RFIC, the control data Can be restored to the state before the power supply is stopped, the power supply to the RFIC can be stopped when the broadcast information signal is not received at the standby time, and the power consumption of the system can be reduced.

It is a system block diagram which shows the receiver of this invention. It is a figure which shows the external connection structural example of RFIC part, ASIC part, and EEPROM. It is a figure which shows the other external connection structural example of RFIC part, ASIC part, and EEPROM. It is a block diagram around an SPI control unit. It is a figure which shows an example of the circuit by the side of the data input / output of an SPI control part. It is a figure which shows the external connection structural example of RFIC part and ASIC part which incorporated EEPROM. It is a figure which shows an example of the circuit of the RFIC part which incorporates EEPROM. It is a figure which shows the example of an external connection structure of an ASIC part and EEPROM when not using EEPROM.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Antenna 12 RFIC part 13 Baseband part 14 Liquid crystal display part 15 CPU
16 SPI control unit 17 ASIC unit 18 Codec unit 19 Key input unit 20 AHB interface 22 Speaker 23 Microphone 24 EEPROM
31 RF controller 32 4-channel analog-digital converter 33 PLL digital-analog converter 34 Control register 41 Latch circuit 42, 49 Register 45, 46 Multiplexer

Claims (4)

In a receiving apparatus comprising a receiving means for receiving a signal from a counterpart communication apparatus and a signal processing means for processing a signal received by the receiving means,
Control data output means for outputting control data required for reception by the receiving means;
A first control data output control means for outputting the control data from the control data output means when the power source is changed from the OFF state to the ON state;
A first control data holding means provided in the receiving means for holding control data output from the control data output means;
Second control data holding means for holding the control data output from the control data output means at a location different from the first control data holding means;
Power control means for controlling power supply to the receiving means at the time of stoppage in intermittent reception, and power supply to the receiving means at the time of reception in intermittent reception;
Second control data output control means for outputting the control data held in the second control data holding means to the first control data holding means at the time of reception in intermittent reception;
A receiving apparatus comprising:   The receiving apparatus according to claim 1, wherein the first control data output control means stops output of the control data from the control data output means at the time of reception in intermittent reception.   The receiving apparatus according to claim 1, wherein the second control data holding unit is a nonvolatile memory. In a reception control method in a receiving device comprising: a receiving unit that receives a signal from a counterpart communication device; and a signal processing unit that processes a signal received by the receiving unit.
A control data output step for outputting control data required for reception by the receiving means from the signal processing means side when the power source is turned off;
A first control data holding step for holding the output control data in the receiving means;
A second control data holding step for holding the control data output from the signal processing means side at a location different from the location held at the first control data holding step;
A power control step for controlling power supply to the reception unit at the time of stoppage in intermittent reception, and to perform power supply to the reception unit at the time of reception in intermittent reception;
At the time of reception in intermittent reception, outputting the control data held in the second control data holding step to the receiving means;
Holding the control data output to the receiving means in the receiving means.

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