JP2009003655A - Portable electronic equipment and power-supply circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve both a request for power saving and a request for a consecutive operation of a circuit part which is operative independently of a CPU, in portable electronic equipment or a power supply circuit which is driven by a battery. <P>SOLUTION: The portable electronic equipment 1 includes: a circuit part (sub-processing part) 6 which can be operated independently of a CPU 5 during a period from its start to its stop by the CPU 5; and a control circuit 4 which receives clock signals from a temperature compensation clock signal oscillator 3 and controls the supply of the clock signals to the CPU 5 and the circuit part 6. The control circuit 4 has a register 4a which is rewritten by the CPU 5, a terminal T1 which outputs a clock signal CLK1 to the CPU 5, and a terminal T2 which outputs a clock signal CLK2 to the circuit part 6. When the contents of the register are altered, the outputting states of the terminals T1 and T2 are altered. When the CPU 5 moves to a sleep mode, the CPU 5 stops only the supply of the CLK1 if the circuit part 6 is in an operative state, and stops the supply of the CLK1 and CLK2 if the circuit part 6 is not in an operative state. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention includes a central processing unit (hereinafter abbreviated as “CPU”) that receives power from a battery, and a sub-processing unit that can be operated independently from the CPU until it is started and stopped by the CPU. The present invention relates to a portable electronic device and a power supply circuit.

  When a temperature-compensated crystal oscillator is used as a clock signal supply source to the CPU, which is the control center of the device, the output signal waveform is a sine wave. A control IC is used for output.

  In addition, battery-powered portable electronic devices require power reduction measures when long-time continuous operation is required, and the CPU needs to operate in a sleep mode unless necessary. In order to make the battery last longer, the CPU has a sleep mode, and power saving is realized by stopping the operation clock by shifting to the mode. For example, in a device having a foldable or flip housing, the CPU sleeps when the user closes the housing or when the user has not operated the device for a predetermined time or longer. The mode is switched to power saving control.

By the way, in a mobile phone or the like, there is a device equipped with an application that realizes a function that can be used without using the communication function inherent in the device (for example, a music playback function, a television video display function, a radio sound output function, etc.) is increasing. Taking the music playback function as an example, the device has a dedicated circuit (sub-processing unit such as a sound source IC) that performs audio signal processing, and outputs it from the control IC described above in order to supply a clock signal necessary for its operation. The clock signal supply line is divided into two, and the operation clock signal is sent from the control IC to the CPU and the dedicated circuit via each supply line. A so-called branch connection configuration for supplying operation clock signals branched to a plurality of circuit units (processing units) is disclosed in, for example, Patent Document 1.
JP 2002-9613 A

  By the way, the music playback function or the like is often used by the user as needed regardless of the outgoing / incoming function of the apparatus main body.

  However, when power saving is prioritized and the CPU shifts to the sleep mode and the supply of the clock signal to the CPU is stopped, the supply of the clock signal to the sound source IC is also stopped at the same time. Cannot perform music playback. That is, in the configuration in which the clock signal from the control IC is branched and supplied to the CPU and the sound source IC as described above, the clock signal cannot be supplied to only one of the CPU or the sound source IC to operate. When the clock signal supply is stopped, the clock signal supply to the sound source IC is also stopped. In other words, the CPU cannot be shifted to the sleep mode during music reproduction, and the clock signal is unnecessarily supplied to the CPU. This cannot meet the demand for power saving.

  An object of the present invention is to achieve both a request for power saving and a request for continued operation of a sub-processing unit operable independently of a CPU in a battery-driven portable electronic device or a power supply circuit.

  A portable electronic device according to the present invention includes a central processing unit driven by a battery as a power source, and a sub-processing unit operable independently of the central processing unit until the central processing unit is activated and stopped by the central processing unit And a control circuit that receives the clock signal supplied from the clock signal oscillator and controls the supply of the clock signal to the central processing unit and the sub-processing unit. The control circuit includes a register rewritten by the central processing unit, a first clock signal output terminal for outputting a first clock signal to the central processing unit, and a second clock signal for outputting the second clock signal to the sub-processing unit. A second clock signal output terminal is provided, and when the contents of the register are changed, the output state of the first clock signal output terminal or the output state of the second clock signal output terminal is changed. It has become. The central processing unit rewrites the contents of the register and stops only the supply of the first clock signal when the sub processing unit is in an operating state when shifting to the sleep mode. When the sub-processing unit is not in the operating state, the contents of the register are rewritten to stop the supply of the first clock signal and the second clock signal.

  In controlling whether to supply the first clock signal and the second clock signal, the register holds a plurality of bit states, and the control circuit controls the first clock signal according to the plurality of bit states. It is preferable to have a logic circuit that changes the output state of the output terminal or the output state of the second clock signal output terminal.

  When the sub processor is an audio signal processing integrated circuit, the audio signal processing can be continued in a state where the CPU is operated in the sleep mode.

  After the control circuit buffers the output signal of the temperature compensated clock signal oscillator, the first clock signal and the second clock signal are respectively supplied to the first clock signal output terminal and the second clock signal output terminal. Preferably, the buffering is performed while the supply of the first clock signal and the second clock signal is not stopped.

  The control circuit is preferably provided on a power supply circuit, that is, a power supply circuit that is connected to a battery and controls power supply to the central processing unit and the sub-processing unit. When shifting to the sleep mode, the power supply voltage supplied to the central processing unit is changed for the sleep mode.

  When the present invention is applied to a power supply control IC or the like, the present invention includes a central processing unit that is driven by a battery as a power source, and the central processing unit that is activated and stopped by the central processing unit. Used in a portable electronic device having an independently operable sub-processing unit and a clock signal oscillator, and controls power supply from the battery to the central processing unit and the sub-processing unit, and the central processing unit A power supply circuit that uses a supply voltage for the central processing unit for the sleep mode when shifting to the sleep mode, and receives the clock signal supplied from the clock signal oscillator and receives the central processing unit and the sub-processing. A control circuit for controlling supply of a clock signal to the unit. The control circuit includes a register rewritten by the central processing unit, a first clock signal output terminal for outputting a first clock signal to the central processing unit, and a second clock signal for outputting the second clock signal to the sub-processing unit. A second clock signal output terminal is provided, and when the contents of the register are changed, the output state of the first clock signal output terminal or the output state of the second clock signal output terminal is changed. The register is configured to stop the supply of the first clock signal by the central processing unit when the sub processing unit is in an operating state when the central processing unit shifts to the sleep mode. The contents of the register are rewritten so that the supply of the first clock signal and the second clock signal is stopped by the central processing section when the sub-processing section is not in an operating state.

  According to the present invention, in the portable electronic device or its power supply circuit, it is possible to satisfy both a request for power saving and a request for continued operation of the sub-processing unit operable independently of the CPU.

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 4.

  FIG. 1 is a block diagram showing a basic configuration of a portable electronic device according to the present invention. The portable electronic device 1 includes a battery 2, a temperature compensated clock signal oscillator 3, a control circuit 4, a CPU 5, a first circuit unit 6, and a second circuit unit 7 (one or both of the circuit units correspond to the sub-processing unit). ).

  The temperature-compensated clock signal oscillator 3 is provided for generating a clock signal necessary for the operation of the CPU 5, the circuit units 6 and 7, and the output signal is transmitted to the control circuit 4.

  The control circuit 4 is a circuit that receives the clock signal supplied from the temperature compensation clock signal oscillator 3 and controls the supply of the clock signal to the CPU 5 and the circuit units 6 and 7.

  The CPU 5 is, for example, a control center that controls the entire device, is driven by the battery 2 as a power source, and has at least one sleep mode for power saving control. Note that the concept of “sleep mode” is not limited to a state in which the operation of the circuit unit is temporarily suspended, but is also actively used for the purpose of waiting for a transition to a specific operation state, a transitional state, or power saving. In particular, a state in which all or part of the circuit operation is stopped or restricted is included. The first circuit unit 6 is a circuit unit that can be operated independently from the CPU 5 until it is activated and stopped by the CPU 5. For example, the first circuit unit 6 is an integrated circuit for audio signal processing such as a sound source IC or a television broadcast. An integrated circuit for video signal reception and signal processing for signal processing may be mentioned.

  The second circuit unit 7 is not essential in the implementation of the present invention, and is a circuit unit for realizing various functions excluding the CPU 5 and the first circuit unit 6. For example, in the case of a mobile phone, the second circuit unit 7 is a radio signal processing integrated circuit for realizing a communication processing function.

  The control circuit 4 includes a register 4a, a logic circuit 4b, and a clock signal control unit 4c.

  The contents of the register 4a are rewritten by the CPU 5, and a clock signal controlled in accordance with this is output to the CPU 5, the circuit unit 6, and the like. That is, the control circuit 4 includes a first clock signal output terminal T1 for outputting the first clock signal CLK1 to the CPU 5, and a second clock signal for outputting the second clock signal CLK2 to the first circuit unit 6. When the contents of the register 4a are changed, the output state of the first clock signal output terminal T1 or the output state of the second clock signal output terminal T2 is changed. . Note that the register 4a can hold a plurality of bit states, an option for supplying only one of the first clock signal CLK1 and the second clock signal CLK2, or an option for supplying both, or supply of both clock signals. It is possible to select an option to stop the operation.

  The logic circuit 4b is provided to change the output state of the first clock signal output terminal T1 or the output state of the second clock signal output terminal T2 in accordance with a plurality of bit states held in the register 4a.

  The clock signal control unit 4c receives the output signal of the temperature compensated clock signal oscillator 3, performs clock buffering, etc., and controls the output of the first clock signal CLK1 and the second clock signal CLK2 in accordance with instructions from the logic circuit 4b.

  In the portable electronic device 1 having the above configuration, the CPU 5 rewrites the contents of the register 4a of the control circuit 4 when the first circuit unit 6 is in the operating state when shifting to the sleep mode. Then, only the supply of the first clock signal CLK1 to the CPU 5 is stopped. Thereby, the operation of the first circuit section 6 can be continued even after the transition to the sleep mode. When the CPU 5 shifts to the sleep mode, the first clock signal CLK1 and the second clock signal CLK2 are supplied by rewriting the contents of the register 4a when the first circuit unit 6 is not in the operating state. Stop. As a result, the CPU 5 operates in the sleep mode and the operation of the first circuit unit 6 is stopped, thereby further obtaining a power saving effect.

  The above-described control can be easily extended to a configuration having three or more circuit units including the CPU 5. For example, as shown by a broken signal line in FIG. 1, the clock signal CLK3 output from the clock signal control unit 4c is configured to be supplied from the clock signal output terminal T3 to the second circuit unit 7, and the register 4a. The processing content of the logic circuit 4b may be changed by a program by increasing the number of bits held in the program. When the CPU 5 shifts to the sleep mode, if the first circuit unit 6 or the second circuit unit 7 is in the operating state, the CPU 5 rewrites the contents of the register 4a of the control circuit 4 to thereby change the first clock to the CPU 5 Only the supply of the signal CLK1 is stopped. Further, the CPU 5 stops the supply of the clock signals CLK1, CLK2, and CLK3 by rewriting the contents of the register 4a when the first circuit portion 6 and the second circuit portion 7 are not in the operating state.

  FIG. 2 is a block diagram showing an example of a circuit configuration to which the present invention is applied. Each clock signal is supplied to a necessary device by using the output of the clock buffer 8c in the power supply control IC 8 as a plurality of signal systems. In this example, the power supply control IC 8 corresponds to the control circuit 4, and the sound source IC 9 corresponds to the first circuit unit 6.

  The power supply control IC 8 includes a register 8a, a logic circuit 8b, a clock buffer 8c, a first level shift circuit 8d1, a second level shift circuit 8d2, and a sleep mode control unit 8e.

  The temperature-compensated clock signal oscillator (crystal oscillator) 3 outputs a sine wave signal having a predetermined frequency to the clock buffer 8c.

  The clock buffer 8 c is provided for buffering the output signal of the temperature compensated clock signal oscillator 3. That is, since the sine wave output from the temperature compensated clock signal oscillator 3 cannot be supplied to the CPU 5 or the sound source IC 9 as it is, it is shaped into a rectangular wave (CLK) via the clock buffer 8c. A plurality of level shift circuits are provided in the power supply control IC 8 so that a plurality of clock signals (CLK1, CLK2) can be output. That is, a rectangular wave signal (CLK1) having a predetermined amplitude is obtained using the first level shift circuit 8d1, and the signal is supplied to the CPU 5. Similarly, a rectangular wave signal (CLK2) having a predetermined amplitude is obtained using the second level shift circuit 8d2, and this signal is supplied to the sound source IC9.

  In this example, the output terminal of the first level shift circuit 8d1 corresponds to the first clock signal output terminal T1, and the output terminal of the second level shift circuit 8d2 corresponds to the second clock signal output terminal T2. The clock buffer 8c buffers the output signal of the temperature compensated clock signal oscillator 3, and then supplies the first clock signal CLK1 to the first clock signal output terminal via the first level shift circuit 8d1, and the second level. The second clock signal CLK2 is supplied to the second clock signal output terminal via the shift circuit 8d2. In other words, the circuit unit configured by the clock buffer 8c, the first level shift circuit 8d1, and the second level shift circuit 8d2 corresponds to the clock signal control unit 4c.

  For example, 4-bit data is written to the register 8a by bus access from the CPU 5, and this is referred to by the logic circuit 8b. A control signal (see “CLK_BUFFER_EN” in FIG. 2) from the sleep mode control unit 5a in the CPU 5 is input to the logic circuit 8b, and an output signal determined according to this control signal is input to the clock buffer 8c, the first level. The data is sent to the shift circuit 8d1 and the second level shift circuit 8d2, respectively. These output signals are signals indicated by “EN” in FIG. 2, that is, signals for enabling or disabling the operation of the circuit unit. The control signal from the sleep mode control unit 5a is also sent to the sleep mode control unit 8e in the power supply control IC 8, thereby performing power saving control of the IC.

  FIG. 3 is a block diagram illustrating a configuration example of a main part related to the control of the clock signal supply by the power supply control IC 8. In this example, the logic circuit 8b includes the first logic unit 8b1, the second logic unit 8b2, and the third logic unit. 8b3.

  Of the 4-bit information in the register 8a, for example, lower 2 bits of information are referred to by the first logic unit 8b1, and upper 2 bits of information are referred to by the second logic unit 8b2.

  A control signal (CLK_BUFFER_EN) from the sleep mode control unit 5a in the CPU 5 is supplied to each of the first logic unit 8b1 and the second logic unit 8b2. Then, the output signal (EN) of the first logic unit 8b1 is sent to the first level shift circuit 8d1, and the output signal (EN) of the second logic unit 8b2 is sent to the second level shift circuit 8d2.

  Table 1 below illustrates the input / output states related to the logic units 8b1 and 8b2. “Bit 1” indicates one bit value in the upper or lower two bits, and “Bit 0” indicates the other bit value. Indicates.

  In the operation specification of this example, when the value of Bit1 is “0”, the logic value output from each logic unit is determined according to the logic value indicated by the control signal (CLK_BUFFER_EN). That is, the logical value indicated by the control signal is reflected as it is as the logical value output by each logic unit (thus, the value of Bit0 has no meaning). For example, when the control signal (CLK_BUFFER_EN) is a high level signal, the circuit is enabled by an enable signal sent to the level shift circuit 8d1, and the output signal (CLK) of the clock buffer 8c is subjected to level shift processing. It is output as the clock signal CLK1.

  When the value of Bit 1 is “1”, the logic value output by each logic unit is determined according to the value of Bit 0 regardless of the logic value indicated by the control signal (CLK_BUFFER_EN). In this example, the output signal of the level shift circuit is forcibly stopped when the value of Bit 0 is “0”, and the signal of the level shift circuit is forcibly stopped when the value of Bit 0 is “1”. Is output.

  As described above, the output control of the clock signal can be realized by the exclusive control using the register 8a in the power supply control IC 8 and the control signal (CLK_BUFFER_EN) together. At this time, since the control signal to the first level shift circuit 8d1 and the second level shift circuit 8d2 can be generated based on the common control signal (CLK_BUFFER_EN), it is necessary to increase the number of control lines for each output system of the clock signal. Absent.

  In this example, the clock signal is output by selectively using at least three states (that is, a state in which the value of Bit 1 is “0” and a state in which the upper or lower 2-bit value is “10” or “11”). However, the present invention is not limited to this, and the output states of the two level shift circuits can be controlled by 2-bit information. For example, in the case of a 2-bit value “11”, two level shift circuits are enabled and both circuits output a clock signal. In the case of a 2-bit value “10”, “01”, one level shift circuit In the case where only the circuit is enabled and the circuit outputs a clock signal and the 2-bit value is “00”, the two level shift circuits are disabled and both circuits do not output the clock signal. That is, four states are necessary for enabling / disabling the two level shift circuits.

  The first logic unit 8b1 and the second logic unit 8b2 send signals to the third logic unit 8b3 for generating a control signal for the clock buffer 8c. For example, the output of the third logic unit 8b3 is determined according to the logic states shown in Table 2 below, and the clock buffer 8c is in an operating state while the supply of the first clock signal CLK1 and the second clock signal CLK2 is not stopped. Clock buffering is performed.

  “OFF” in the table indicates a circuit stop state (or a state in which no signal is output), and “ON” indicates an operation state of the circuit (or a state in which a signal can be output), and the first level shift circuit 8d1. When at least one of the second level shift circuit 8d2 is "ON", the clock buffer 8c is operated by a signal (enable signal) sent from the third logic unit 8b3 to the clock buffer 8c, and the first level shift circuit 8d1 When both the second level shift circuit 8d2 and the second level shift circuit 8d2 are "OFF", the operation of the clock buffer 8c is stopped by a signal (disable signal) sent from the third logic unit 8b3 to the clock buffer 8c. As can be seen by replacing “OFF” with the logical value “0” and “ON” with the logical value “1”, the correspondence relationship of the sum (OR) operation in the positive logic is established, and such a simple logic Since it can be handled by elements, the design burden is reduced.

  As described above, in this example, the clock buffer 8c and the level shift circuits 8d1 and 8d2 are not simply subjected to binary control according to the control signal (CLK_BUFFER_EN), but according to the contents of the register 8a in the power control IC 8 8b controls whether or not a clock signal is supplied. That is, by incorporating the logic shown in the above table 1 in the logic circuit 8b, only one of the clock signals CLK1 and CLK2 is supplied exclusively to the CPU 5 or the sound source IC 9 corresponding to them, and both clock signals Control of stopping the output of CLK1 and CLK2 is possible. Then, by incorporating the logic shown in Table 2 in the logic circuit 8b, when one or both of the clock signals CLK1 and CLK2 are supplied to the CPU 5 or the sound source IC 9 corresponding to them, the clock buffer The clock buffer 8c can be stopped when the output of both the clock signals CLK1 and CLK2 is stopped.

  In this example, a control circuit for controlling the clock signal supply to the CPU 5 and the sound source IC 9 is provided on the power supply control IC 8. That is, this control circuit is provided on a power supply circuit that controls power supply to a circuit unit that is connected to the battery 2 and controlled independently of the CPU 5. Then, when the CPU 5 shifts to the sleep mode, the power supply voltage supplied to the CPU 5 is changed for the sleep mode. Such a transition process to the sleep mode is executed, for example, when the user closes the apparatus housing or when the user does not perform an operation for a predetermined time or longer, and thus the CPU 5 Even when operating in the sleep state, the supply of the clock signal from the power supply control IC 8 to the sound source IC 9 is continued, so that the music reproduction (background reproduction) function is guaranteed.

  FIG. 4 is a block diagram showing an application example to a mobile phone device. The mobile phone device 10 includes a control unit 11 using a CPU 5, a communication unit 12, a processing unit 13 that processes information communicated by the communication unit 12, and a power supply circuit unit 14 connected to the battery 2. ing. The battery 2 is, for example, a lithium ion secondary battery. The communication unit 12 includes a main antenna 12a that communicates with an external device in a predetermined use frequency band, and a communication processing unit 12b that performs signal processing such as modulation processing or demodulation processing. Receive the supply. The processing unit 13 includes an operation key group 13a, a camera module 13b, a display 13c, a memory 13d, an audio processing unit 13e, an image processing unit 13f, a microphone (audio input unit) 13g, and a speaker (audio output unit) 13h. The sound source IC 9 is provided in the sound processing unit 13e. The power supply circuit unit 14 transforms the power supply voltage supplied from the battery 2 to a predetermined voltage value, and then supplies it to the control unit 11, the communication unit 12, and the processing unit 13. The power supply circuit unit 14 is provided with the power supply control IC 8, and a clock signal is supplied to the CPU 5 of the control unit 11, the sound source IC 9 in the processing unit 13, and the like.

  According to the configuration described above, the following advantages can be obtained.

  By incorporating a plurality of level shift circuits (8d1, 8d2) in the power supply control IC 8, it is not necessary to have an external level shift circuit, which is effective in deleting the number of parts.

  In addition, by rewriting the contents of the register 8a in the power supply control IC 8, it becomes possible to control the output of the clock signal regardless of the control signal (CLK_BUFFER_EN).

  In the conventional configuration, when only the sound source IC 9 is desired to operate, the CPU 5 and the power supply control IC 8 do not enter the sleep mode and the current consumption increases. As a result, the sound source IC 9 cannot achieve long-time reproduction. Only the sound source IC 9 can be operated after shifting to the sleep mode. Further, since the control signal (CLK_BUFFER_EN) can be set to a low level, it is not necessary to individually set each block in the IC to the power saving mode in order to reduce the current consumption of the CPU 5 and the power supply control IC 8, and the software can be changed. I don't need it. That is, instead of realizing a pseudo power saving mode by changing the software, the CPU 5 and the power supply control IC 8 operate completely in the sleep mode, so that the current consumption can be reduced as much as possible.

  Further, by applying exclusive control in the logic circuit 8b in the power supply control IC 8, it is possible to create a forced off state of the clock buffer 8c and the level shift circuits 8d1 and 8d2. For example, even if the control signal (CLK_BUFFER_EN) is a high level signal, the supply of the clock signal to the sound source IC 9 can be stopped, so that the current consumption can be reduced.

It is a block diagram which shows the basic composition of the portable electronic device by this invention. It is a block diagram which shows an example of the circuit structure to which this invention is applied. It is a block diagram which shows the structural example of the principal part regarding control of the clock signal supply by power supply control IC. It is a block diagram which shows the example of application to a mobile telephone apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Portable electronic device 2 Battery 3 Temperature compensation clock signal oscillator 4 Control circuit 4a Register 4b Logic circuit 5 Central processing part 6 Circuit part (sub-processing part)
8a register 8b logic circuit 8c clock buffer T1 first clock signal output terminal CLK1 first clock signal T2 second clock signal output terminal CLK2 second clock signal

Claims (6)

A central processing unit driven by a battery as a power source;
A sub-processing unit that can be operated independently from the central processing unit until it is started and stopped by the central processing unit,
A control circuit that receives a clock signal supplied from a clock signal oscillator and controls supply of the clock signal to the central processing unit and the sub-processing unit, and
The control circuit includes a register rewritten by the central processing unit, a first clock signal output terminal for outputting a first clock signal to the central processing unit, and a second clock signal for outputting the second clock signal to the sub-processing unit. A second clock signal output terminal, and when the contents of the register are changed, the output state of the first clock signal output terminal or the output state of the second clock signal output terminal is changed;
The central processing unit rewrites the contents of the register to stop only the supply of the first clock signal when the sub processing unit is in an operating state when shifting to the sleep mode, and stops the supply of the first clock signal. When the unit is not in an operating state, the contents of the register are rewritten to stop the supply of the first clock signal and the second clock signal.   The register holds a plurality of bit states, and the control circuit changes the output state of the first clock signal output terminal or the output state of the second clock signal output terminal according to the plurality of bit states. The portable electronic device according to claim 1, further comprising a circuit.   The portable electronic device according to claim 1, wherein the sub-processing unit is an integrated circuit for audio signal processing.   The control circuit buffers the output signal of the temperature-compensated clock signal oscillator and then outputs the first clock signal and the second clock signal to the first clock signal output terminal and the second clock signal output terminal, respectively. 4. The clock buffer for supplying the first clock signal and the second clock signal, wherein the buffering is performed while the supply of the first clock signal and the second clock signal is not stopped. 5. The portable electronic device described in 1.   The control circuit is provided on a power supply circuit that is connected to the battery and controls power supply to the central processing unit and the sub processing unit, and when the central processing unit shifts to a sleep mode. The portable electronic device according to any one of claims 1 to 4, wherein a power supply voltage supplied to the central processing unit is changed for a sleep mode. A mobile phone having a central processing unit driven by a battery as a power source, a sub-processing unit operable by the central processing unit until it is stopped and operated, and a clock signal oscillator Used in a type electronic device to control power supply from the battery to the central processing unit and the sub processing unit, and when the central processing unit shifts to a sleep mode, the supply voltage to the central processing unit is set to sleep. A power supply circuit for mode,
A control circuit that receives a clock signal supplied from the clock signal oscillator and controls supply of the clock signal to the central processing unit and the sub-processing unit;
The control circuit includes:
A register rewritten by the central processing unit, a first clock signal output terminal for outputting a first clock signal to the central processing unit, and a second clock signal output for outputting a second clock signal to the sub-processing unit And when the contents of the register are changed, the output state of the first clock signal output terminal or the output state of the second clock signal output terminal is changed,
The register is
When the central processing unit shifts to the sleep mode, the contents of the register are rewritten so that only the supply of the first clock signal is stopped by the central processing unit when the sub processing unit is in an operating state. In addition, when the sub-processing unit is not in an operating state, the contents of the register are rewritten by the central processing unit so that the supply of the first clock signal and the second clock signal is stopped.
A power supply circuit.

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