JP2008016163A - Memory device and memory read error detection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory device which has resistance to an error in general such as a timing error and a software error, and is guaranteed in reading a cell value correctly, and a memory read error detection method. <P>SOLUTION: The memory device is equipped with one or a plurality of memory cells (CL) arranged over rows and columns; a word line prepared in each row (WD); a complimentary bit line pair (BL1, BL2) comprising mutually-complementary first second bit lines prepared in each column; and a matching comparison circuit (CM) which carries out the matching comparison of the output of the complimentary bit line pair. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a memory device and a memory read error detection method.

  A semiconductor memory used as a RAM is a micro component, so it is vulnerable to disturbances such as heat and radiation, and an error may occur. Since a memory error causes a system down, an error countermeasure technique is important. As a conventional technique for dealing with errors, there is an error code correction technique (see, for example, Patent Document 1). However, this prior art is aimed at detecting the inversion of the bit stored in the memory cell, and is ineffective against the following error during reading.

In order to read the value correctly from the semiconductor memory, it is necessary to send each control signal at the correct timing. Conventional RAMs are not resistant to timing errors caused by heat, manufacturing variations, dynamic voltages, operating frequency changes, and the like. This timing is precisely designed using CAD or the like, but due to the recent effects of device miniaturization and processor power saving, it has become difficult to secure a margin with only design measures. . In addition, control signals flowing through address lines, bit lines, and the like may be inverted due to disturbances (soft errors) such as cosmic rays.
Japanese Patent Laid-Open No. 10-334697

  Therefore, the present invention provides a memory device that is resistant to all possible memory read errors such as timing errors and soft errors, and is guaranteed to correctly read the cell value, and a memory read error detection method. For the purpose.

In order to solve the above-described problems, a memory device according to a first invention
One or more memory cells arranged across rows and columns;
A word line provided in each row;
A pair of complementary bit lines provided in each column, the first bit line and the second bit line being complementary to each other;
A coincidence comparison circuit for comparing and comparing the outputs of the complementary bit line pairs;
With
The memory cell array can be read and written by the word line and the complementary bit line pair.

The memory device according to the second invention is
A first sense amplifier coupled to the first bit line constituting the complementary bit line pair;
A second sense amplifier coupled to the second bit line constituting the complementary bit line pair;
The coincidence comparison circuit compares the output from the first sense amplifier with the output from the second sense amplifier;
It is characterized by that.

A memory device according to a third invention is
The coincidence comparison circuit comprises an exclusive OR gate.

As described above, the solution of the present invention has been described as an apparatus, but the present invention can be realized as a method substantially corresponding to these, and the scope of the present invention also includes these. I want you to understand.
For example, the memory read error detection method according to the fourth aspect of the present invention realized as a method is as follows:
A memory read error detection method for detecting an error that occurs during reading of a memory cell array,
A read step of complementing the bit line pair by reading values to the first and second bit lines from different ends of the memory cells that complementarily hold the values;
The output of the first sense amplifier and the output of the second sense amplifier are compared and matched (that is, if the outputs of the complementary bit line pair do not match, it is determined as normal, and if they match, it is determined as an error) An error detection step for detecting the occurrence of a read error based on the calculation result;
It is a method including.

  According to the present invention, a pair of bit lines coupled to each row of one cell or cell array is complemented, and two sense amplifiers respectively coupled to two bit lines constituting the bit line pair are provided. It is possible to provide a memory device capable of detecting a read error with a simple configuration in which the amplifier output is subjected to a coincidence comparison operation. There are various errors such as timing errors and soft errors as read errors, and it is possible to provide a memory device and an error detection technique that are resistant to all errors that may occur at the time of reading. In particular, the timing error can be detected only by the operating frequency without using a relatively slow clock frequency, and the cost effectiveness and practicality are improved. The register, cache memory, and main storage device configured with such error-resistant memory can realize high reliability and high efficiency of the computer and improve availability.

  In order to help understand the principle of the present invention, FIG. 4 shows a schematic diagram of a two-rail RAM cell as a conventional example. As shown in the figure, the cell CL is coupled to the decoder DC by the word line WD. The cell CL is coupled to the precharge circuit PC via the complementary bit lines BL1 and BL2. The cell CL is composed of access transistors T1 and T2, load transistors T3 and T4, and driver transistors T5 and T6. The central four transistors T3 to T6 store a 1-bit value. Alternatively, it can be said that one bit is held by six gates of six transistors. The held values Q1 and Q2 are set to complementary values (complementary). For convenience of explanation and drawing, a 1-bit cell is shown. However, when one address holds 1-byte data, the same mechanism is arranged in a horizontal direction. Data of different addresses are arranged in the vertical direction, and the entire RAM is in a lattice shape to constitute a memory cell array including a large number of cells CL.

  The precharge circuit PC is activated and both bit lines BL1 and BL2 are set to a high value. Next, the decoder (decode circuit) DC decodes the input address, and among the plurality of word lines, only the word line WD corresponding to the address is set high. When the access gate of the corresponding cell CL is activated by this set and the holding value Q is 0, the charge of the bit line BL1 is released by the driver transistor, and the potential approaches a low value. Since this change is gentle, the sense amplifier AMP is used to shorten the access time. When the sense amplifier drive signal SAE becomes high, the sense amplifier AMP reads the bit line potential and outputs the read result.

  In the prior art, redundant bits such as parity and ECC added to improve the reliability of the memory can be detected and repaired if they are errors such as cell holding data or bit line inversion. . However, timing errors such as the word line being asserted before the precharge circuit completes the precharge circuit or the sense amplifier turning on before a sufficient time elapses are likely to be multi-bit errors. It cannot be effectively dealt with by bits. In addition, it is not effective against disturbance of the control line in which the word line is inverted by the disturbance.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing a basic configuration of a memory device according to the present invention. A description of the same configuration as the conventional configuration in FIG. 4 is omitted, and only the differences will be described. As shown in the figure, the memory device according to the present invention includes a first sense amplifier AMP1 coupled to a bit line BL1 having a complementary set value and a bit line BL2 having a complementary set value. A second sense amplifier AMP2 to be coupled; That is, each sense amplifier handles a single bit. Receiving the sense amplifier drive signal SAE, the sense amplifiers AMP1 and AMP2 supply the read numerical result read from each bit line to the coincidence comparison circuit CM.

  That is, two separate sense amplifiers are used to extract the values of two complementary bit lines, respectively, and check whether the values are inverted. If the value held in the cell is correctly read, the values of the two bit lines are inverted as (0, 1) or (1, 0). As an example of a timing error, a timing error such as turning on a word line before precharging is sufficient results in (0, 0), and sensing before the bit line potential changes sufficiently. A timing error such as turning on the amplifier gives a result such as (1, 1). When a plurality of cells having different values are read due to disturbance to the word line, the value becomes (0, 0). When a plurality of cells having the same value are read, they are not detected as an error. However, the value read in this case is a correct value and there is no problem in execution. In this way, since the complementary bit line pair feature is used in which the values match if there is any error, it is possible to detect general read errors.

  As described above, there are two bit line read numerical results, but if they are normal, they are complementary numerical values (that is, if one is 0, the other is 1). As a circuit that can be used for the coincidence comparison circuit, for example, there is an XOR circuit, and the XOR circuit performs an exclusive OR operation on these two numerical values and outputs the operation result as an error signal. If the error signal is 1 (when the value is inverted), it is normal. If it is 0 (when the value is not inverted), it is determined that some error such as a timing error or soft error has occurred. The system can be recovered by performing post error processing such as retrying the reading operation of the hold value Q1 or Q2. The technique of the present invention is resistant to all errors including timing errors. An error that cannot be detected by this technique is a case where two errors occur at the same time and both of the complementary bit line pairs are inverted at the same time. However, there is very little chance for such an error to occur. Therefore, practically sufficient error resistance can be obtained by the technique of the present invention.

  FIG. 2 is a schematic diagram for explaining a cell array structure in which many cells shown in FIG. 1 are arranged. As shown in the figure, the memory device addresses one cell of a cell array composed of many cells CL by a row decoder DCR, a column decoder DCC, a column selector SEL, and the like. A general memory device is configured as such a memory cell array.

  FIG. 3 is a flowchart for explaining the processing of the memory read error detection method according to the present invention. As shown in the figure, in step ST1, one word line is asserted and an attempt is made to read the value held in the cell. First, two complementary bit line pairs of the cell are set to the same value (1, 1, Initializing to 1) and reading the value held in the cell after the initialization, the bit line pair is complemented as (1,0). Next, in step S3, the first and second sense amplifiers read the complementary bit line pair values and supply them to the coincidence comparison circuit CM. In step ST5, the numerical values supplied from the sense amplifiers are compared and compared (ST7). If the numerical values do not match, the process ends as normal. If they match, the process proceeds to step ST9, error processing (rereading is attempted, etc.) is performed, and the process is terminated.

  Although the present invention has been described based on the drawings and examples, it should be noted that those skilled in the art can easily make various modifications and corrections based on the present disclosure. Therefore, it should be noted that these variations and modifications are included in the scope of the present invention. For example, functions included in each member, each means, each step, etc. can be rearranged so as not to be logically contradictory, and a plurality of means, steps, etc. can be combined or divided into one. Is possible.

1 is a circuit diagram showing a basic configuration of a memory device according to the present invention. It is the schematic explaining the cell array structure which arranged many cells shown in FIG. It is a flowchart explaining the process of the memory read error detection method by this invention. It is a schematic diagram of a conventional two-rail RAM cell.

Explanation of symbols

AMP, AMP1, AMP2 Sense amplifiers BL1, BL2 Bit line WD Word line CL Cell DC decoder DCC Column decoder SEL Column selector DCR Row decoder PC Precharge circuit Q1, Q2 Holding value SAE Sense amplifier drive signal T1, T2 Access transistor T3 T4 Load transistor T5, T6 Driver transistor CM Match comparison circuit

Claims (4)

One or more memory cells arranged across rows and columns;
A word line provided in each row;
A pair of complementary bit lines provided in each column, the first bit line and the second bit line being complementary to each other;
A coincidence comparison circuit for comparing and comparing the outputs of the complementary bit line pairs;
A memory device comprising: The memory device according to claim 1,
A first sense amplifier coupled to the first bit line constituting the complementary bit line pair;
A second sense amplifier coupled to the second bit line constituting the complementary bit line pair;
The coincidence comparison circuit compares the output from the first sense amplifier with the output from the second sense amplifier;
A memory device. The memory device according to claim 1 or 2,
The coincidence comparison circuit comprises an exclusive OR gate;
A memory device. A memory read error detection method for detecting an error that occurs during reading of a memory cell array,
A read step of complementing the bit line pair by reading values to the first and second bit lines from different ends of the memory cells that complementarily hold the values;
An error detection step of comparing the output of the first sense amplifier with the output of the second sense amplifier and detecting the occurrence of a read error based on the calculation result;
A memory read error detection method including:

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