JP2008004726A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the contact resistance of an ohmic electrode provided on the rear-surface side of a silicon carbide bulk substrate, in a semiconductor element having the silicon carbide bulk substrate. <P>SOLUTION: The semiconductor element 700 has a first conductivity-type silicon carbide bulk substrate 1 having a principal surface 1p and a rear surface 1r; and has a first conductivity-type high concentration impurity epitaxial layer 3 which is formed on the rear surface 1r of the silicon carbide bulk substrate 1, and contains the impurity with a concentration higher than the one of the silicon carbide bulk substrate 1. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  2. Description of the Related Art Semiconductor elements (power devices) that have a high breakdown voltage and can flow a large current are used in various fields. Conventionally, Si power devices using silicon (Si) semiconductors have been the mainstream, but in recent years, SiC power devices using silicon carbide (SiC) semiconductors have been developed for the purpose of reducing power device loss. ing. The “SiC” semiconductor refers to a semiconductor in which silicon (Si) and carbon (C) are combined at a component ratio of 1: 1. Generally, a small amount of C represented by “Si: C” (for example, several percent or less) The included Si semiconductor is a material having different physical and chemical properties.

  The SiC semiconductor is a semiconductor material having a larger band gap than the Si semiconductor, and has a dielectric breakdown electric field that is one digit higher than that of the Si semiconductor. Therefore, in a PN junction or a Schottky junction using a SiC semiconductor, the reverse breakdown voltage can be maintained even if the depletion layer formed in the SiC semiconductor layer is thinner than the depletion layer in the junction using the Si semiconductor. Therefore, when the SiC semiconductor is used, the thickness of the device can be reduced and the doping concentration can be increased, so that the on-resistance can be reduced, and a power device with high breakdown voltage and low loss can be realized.

  The SiC power device is formed using a low-resistance SiC bulk substrate, and many of them have a so-called vertical structure in which current flows in a direction perpendicular to the SiC bulk substrate.

  Taking a vertical PN diode as an example, a high resistance epitaxial layer for maintaining a withstand voltage is formed on the main surface of the SiC bulk substrate, and a PN junction and an ohmic electrode are formed on the high resistance epitaxial layer. ing. On the other hand, a back electrode is formed on the back surface of the SiC bulk substrate. Further, a vertical MOSFET will be described as an example. A high resistance epitaxial layer is formed on the main surface of the SiC bulk substrate, and a MOSFET portion including a channel and a source electrode are formed on the high resistance epitaxial layer. . On the other hand, a drain electrode is formed on the back surface of the SiC bulk substrate.

  In the present specification, the term “SiC bulk substrate” refers to a single crystal substrate obtained by cutting and polishing single crystal SiC produced by a modified Lely method or sublimation method to a predetermined size. . Further, using the above example, in the SiC bulk substrate, a surface on which element components such as a high-resistance epitaxial layer, a PN junction, a channel region, and a source electrode constituting a device are formed is a “main surface”. The opposite surface, that is, the surface on which only the electrodes are basically formed is referred to as a “back surface”.

  As described with respect to the vertical PN diode and the vertical MOSFET, in the SiC power device having the vertical structure, electrodes are provided on the main surface side and the back surface side of the SiC bulk substrate, respectively. In the following description, regardless of the function of the power device, an electrode provided on the main surface side of the SiC bulk substrate is referred to as an “upper electrode”, and an electrode provided on the back surface side is referred to as a “lower electrode” to distinguish them.

  In order to further reduce the power loss of such a SiC power device, it is necessary to keep the on-resistance along the current path small in a state in which a current flows through the SiC power device (on state). As one means for suppressing the on-resistance, it is conceivable to reduce the contact resistance of the lower electrode provided on the back side of the SiC bulk substrate. The lower electrode is usually provided in contact with the back surface of the SiC bulk substrate. However, since the impurity concentration of the SiC bulk substrate is low, the contact resistance between the lower electrode and the back surface of the SiC bulk substrate increases, and the power This is because it is one of the factors that increase the power loss of the device.

If the impurity concentration of the SiC bulk substrate is increased, the impurity concentration in the vicinity of the back surface of the SiC bulk substrate is also increased, so that the contact resistance can be reduced. However, the higher the impurity concentration, the lower the crystallinity of the SiC bulk substrate, causing more defects in the high resistance epitaxial layer formed on the SiC bulk substrate. Therefore, when a device is manufactured using a SiC bulk substrate having a high impurity concentration, a leakage current increases due to defects generated in the high resistance epitaxial layer, and high characteristics cannot be obtained. Therefore, the impurity concentration of the commercially available SiC bulk substrate is suppressed to about 5 × 10 ¹⁸ cm ⁻³ or less.

  On the other hand, Patent Document 1 by the present applicant discloses a technique for increasing the impurity concentration in the vicinity of the back surface of the SiC bulk substrate by implanting impurity ions into the back surface of the SiC bulk substrate.

  8A and 8B are process cross-sectional views for explaining the technique disclosed in Patent Document 1. FIG. First, as shown in FIG. 8A, impurity ions 113 are implanted into the back surface 111r of the SiC bulk substrate 111, and then activation annealing is performed to form the impurity doped layer 112. Next, as shown in FIG. 8B, an active layer 114 is formed on the main surface 111p of the SiC bulk substrate 111 by epitaxial growth. Thereafter, although not shown, a diffusion region is formed in the active layer 114. An upper electrode is provided on the active layer 114, and a lower electrode is provided on the impurity doped layer 112.

According to the above technique, the impurity concentration in the vicinity of the back surface 111r of the SiC bulk substrate 111 can be increased by providing the impurity doped layer 112 containing impurities at a high concentration, so that the bottom electrode and the back surface 111r of the silicon carbide bulk substrate 111 can be increased. Can be reduced.
JP 2003-86816 A

  However, the inventors of the present application have examined the technique disclosed in Patent Document 1 and found that there are the following two problems.

  First, in order to more reliably reduce the contact resistance, the impurity doped layer 112 formed on the SiC bulk substrate 111 preferably has a sufficient thickness (for example, 1 μm or more). However, it is difficult to form the impurity doped layer 112 by ion implantation. Second, since the impurity doped layer 112 is formed by ion implantation, the impurity concentration in the impurity doped layer 112 has a distribution in the depth direction, and as a result, the contact resistance varies among products. There is.

  First, the first problem will be described.

  When manufacturing a device using the SiC bulk substrate 111 on which the impurity doped layer 112 is formed, by sacrificial oxidation for surface cleaning, and when manufacturing a MOSFET, a gate insulating film is formed. By the gate oxidation, the surface portion of the impurity doped layer 112 is oxidized to form a thermal oxide film. At this time, the impurity doped layer 112 becomes thinner according to the thickness of the thermal oxide film to be formed. As calculated from the density of SiC and the density of the thermal oxide film, when a thermal oxide film having a thickness t is formed, the thickness of the impurity doped layer 112 decreases by 0.46 × t. In particular, when a 4H—SiC or 6H—SiC substrate is used as the SiC bulk substrate 111, the impurity doped layer 112 is formed on the C surface of such a substrate, and the active layer 114 is formed on the Si surface, Since the thermal oxidation rate is 5 to 10 times higher than the thermal oxidation rate on the Si surface, a thicker oxide film is formed in the impurity doped layer 112, and the thickness of the impurity doped layer 112 is accordingly increased. Decrease significantly. For example, when a thermal oxide film having a thickness of several tens of nm is formed on the surface (Si surface) of the active layer 114, a thermal oxide film having a thickness of several hundreds of nm is formed on the surface (C surface) of the impurity doped layer 112. As a result, the thickness of the impurity doped layer 112 is greatly reduced.

  Furthermore, when forming a lower electrode on the back surface of the SiC bulk substrate 111 and adopting a Post Deposition Annealing (PDA) method in order to obtain good ohmic characteristics, the thickness of the impurity doped layer 112 is further reduced. When the PDA method is used, the lower electrode can be formed by depositing a conductor such as nickel (thickness: for example, several tens of nm) on the impurity-doped layer 112 and then performing annealing at about 1000 ° C. By this annealing, nickel is silicided and nickel silicide is formed at the interface between the impurity doped layer 112 and the conductor, so that an ohmic junction is formed between the impurity doped layer 112 and the lower electrode. At this time, since silicon carbide in the impurity doped layer 112 is consumed for silicidation, the impurity doped layer 112 is further thinned. Typically, the thickness of the impurity doped layer 112 is reduced by approximately the same as the thickness of the deposited nickel.

  This will be described more specifically by taking a process of manufacturing a vertical MOSFET as an example. When the Si surface of the SiC bulk substrate 111 is used as the main surface 111p, if a gate oxide film having a thickness of 80 nm is formed on the surface (Si surface) of the active layer 1114 formed on the main surface 111p of the SiC bulk substrate 111, impurities A thermal oxide film having a thickness of 800 nm is formed on the surface (C surface) of the doped layer 112. Thereby, the thickness of the impurity doped layer 112 is reduced by about 370 nm. Further, when the lower electrode (drain electrode) is formed by using the PDA method described above, the impurity doped layer 112 becomes thinner. For example, when a drain electrode is formed by depositing nickel having a thickness of 100 to 200 nm on the impurity doped layer 112 and then annealing at about 1000 ° C., the thickness of the impurity doped layer 112 is reduced by about 100 to 200 nm. To do. Accordingly, in this example, the formation of the gate oxide film and the drain electrode reduces the thickness of the impurity doped layer 112 in total from 470 nm to 570 nm.

  Therefore, in order to reliably reduce the contact resistance, it is necessary that the thickness of the impurity doped layer 112 formed by ion implantation is sufficiently larger than a decrease (amount of reduction) in the device manufacturing process. In the example of the vertical MOSFET described above, the thickness of the impurity doped layer 112 needs to be at least 600 nm, preferably 1 μm or more.

  However, it is difficult to form the impurity doped layer 112 having such a thickness by ordinary ion implantation. The reason for this will be described below.

The inventors of the present application determined the range of each ion when nitrogen ions (N ⁺ ) or phosphorus ions (P ⁺ ) are implanted into the silicon carbide bulk substrate by simulation, and the results are shown in FIG. . The horizontal axis of the graph shown in FIG. 9 represents ion energy during ion implantation, and the vertical axis represents ion implantation depth. Normally, the acceleration energy of an ion implantation facility used in the device manufacturing process is 400 keV or less, but as can be seen from FIG. 9, when such an ion implantation facility is used, nitrogen ions are more than 600 nm and phosphorus ions are more than 400 nm. Cannot be injected into deep areas. Accordingly, the impurity doped layer 112 thicker than 600 nm cannot be formed when nitrogen ions are implanted, and 400 nm thicker than 400 nm when phosphorous ions are implanted.

  On the other hand, in Patent Document 1, an impurity doped layer 112 having a thickness of, for example, about 3 μm is formed by performing ion implantation with high energy of MeV level. Such high energy injection requires a considerably large facility and increases the manufacturing cost, so that it is difficult to apply it to a mass production process.

  Next, the second problem will be described.

  In order to reduce the contact resistance using the technique of Patent Document 1, the impurity doped layer 112 after the thickness is reduced in the device manufacturing process is in the vicinity of the surface (that is, in the vicinity of the surface on which the lower electrode is formed). It is necessary to have a high impurity concentration. If the impurity concentration in the impurity doped layer 112 is constant in the depth direction, the impurity concentration in the vicinity of the surface where the lower electrode is formed is constant regardless of the amount of reduction in the device manufacturing process. Can be reduced. However, the impurity concentration profile of the impurity doped layer 112 formed by ion implantation generally follows a Gaussian distribution. For this reason, it is necessary to adjust the depth at which the impurity concentration profile has a peak when the impurity doped layer 112 is formed in consideration of the amount of reduction. However, the amount of reduction in the impurity doped layer 112 is likely to vary depending on various factors, and also varies depending on the type of device and the manufacturing method. Therefore, depending on the reduction amount of the impurity doped layer 112, a predetermined high impurity concentration may not be obtained on the surface of the impurity doped layer 112 where the lower electrode is formed. In addition, when the amount of reduction is varied, the impurity concentration in the vicinity of the surface where the lower electrode is formed in the impurity doped layer 112 varies greatly. As a result, the contact resistance varies, and the reliability may be lowered.

FIG. 10 is a graph showing a concentration profile of nitrogen ions in the depth direction when nitrogen ions are implanted into the silicon carbide layer at an energy of 500 keV and a dose of 1 × 10 ¹⁴ cm ⁻² . The horizontal axis of the graph shown in FIG. 10 represents the depth from the surface of the silicon carbide layer, and the vertical axis represents the concentration of nitrogen ions. From this graph, it can be seen that the concentration profile of nitrogen ions has a peak in the vicinity of 600 nm, and when the depth deviates from 600 nm to 100 nm, the concentration of nitrogen ions decreases by an order of magnitude.

  In the manufacturing process of the vertical MOSFET described above, the thickness of the impurity doped layer 112 is reduced by, for example, about 470 nm to 570 nm. If the amount of reduction is about 600 nm, the thickness near the surface of the impurity doped layer 112 after the reduction is reduced. Since the impurity concentration is close to the peak value, the contact resistance between the impurity doped layer 112 and the lower electrode can be greatly reduced. On the other hand, if the reduction amount varies by about 100 nm, the contact resistance may not be sufficiently reduced.

  Patent Document 1 discloses performing so-called multi-stage implantation in which ion implantation is performed a plurality of times while changing acceleration energy in order to suppress variation in contact resistance caused by impurity ion concentration profiles. However, in order to perform multi-stage injection at a high dose, the injection process becomes complicated, and the time spent for the injection process increases significantly, so that it is difficult to apply to a mass production process. Furthermore, even if multi-stage implantation is performed, the concentration profile of impurity ions is not completely uniform in the depth direction, and has a plurality of peaks corresponding to each ion implantation, so that variations in contact resistance due to the concentration profile are completely eliminated. It is difficult to suppress.

  As described above, in the prior art, it is difficult to reduce the contact resistance between the electrode provided on the back surface 111r of the SiC bulk substrate 111 and the SiC bulk substrate 111 by a process suitable for mass production.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to reduce the contact resistance of an ohmic electrode provided on the back side of a SiC bulk substrate in a semiconductor element including the SiC bulk substrate. The purpose is to lower the power loss than before.

  A semiconductor element of the present invention is a first conductivity type silicon carbide bulk substrate having a main surface and a back surface, and a first impurity formed on the back surface of the silicon carbide bulk substrate and containing impurities at a higher concentration than the silicon carbide bulk substrate. A conductive type high concentration impurity epitaxial layer.

  In a preferred embodiment, the semiconductor device further includes a first-conductivity-type low-concentration impurity epitaxial layer formed on a main surface of the silicon carbide bulk substrate and containing impurities at a lower concentration than the silicon carbide bulk substrate.

  You may further provide the upper electrode provided in the main surface of the said silicon carbide bulk substrate, and the lower electrode electrically connected to the said silicon carbide bulk substrate through the said high concentration impurity epitaxial layer.

The impurity concentration in the high-concentration impurity epitaxial layer is preferably 1 × 10 ¹⁹ cm ⁻³ or more.

  In a preferred embodiment, the impurity concentration in the high-concentration impurity epitaxial layer is substantially constant in the depth direction.

  The back surface of the silicon carbide bulk substrate may be a carbon surface. Alternatively, the back surface of the silicon carbide bulk substrate may be a silicon surface.

  The semiconductor element may be a vertical MOSFET. Alternatively, the semiconductor element may be a vertical PN diode. Alternatively, the semiconductor element may be a vertical Schottky diode.

  A semiconductor substrate of the present invention is formed on a first conductivity type silicon carbide bulk substrate and a first conductivity type high-concentration formed on a first surface of the silicon carbide bulk substrate and containing impurities at a higher concentration than the silicon carbide bulk substrate. A concentration impurity epitaxial layer.

  In a preferred embodiment, the silicon carbide bulk substrate further includes a low-concentration impurity epitaxial layer provided on a second surface opposite to the first surface and containing impurities at a lower concentration than the silicon carbide bulk substrate.

  In a preferred embodiment, the high-concentration impurity epitaxial layer has a thickness of 300 nm or more.

The impurity concentration in the high-concentration impurity epitaxial layer is preferably 1 × 10 ¹⁹ cm ⁻³ or more.

  In a preferred embodiment, the impurity concentration in the high-concentration impurity epitaxial layer is substantially constant in the depth direction.

  The first surface of the silicon carbide bulk substrate may be a carbon surface. Alternatively, the first surface of the silicon carbide bulk substrate may be a silicon surface.

  A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including a silicon carbide bulk substrate of a first conductivity type having a main surface and a back surface, and (a) at a concentration lower than that of the silicon carbide bulk substrate. A first conductivity type low concentration impurity epitaxial layer containing impurities is formed on the main surface, and a first conductivity type high concentration impurity epitaxial layer containing impurities at a higher concentration than the silicon carbide bulk substrate is formed on the back surface. And (b) forming an electrode in contact with the high-concentration impurity epitaxial layer on the back surface of the silicon carbide bulk substrate.

  In a preferred embodiment, the step (a) includes (a1) a step of forming the high-concentration impurity epitaxial layer on the back surface of the silicon carbide bulk substrate, and (a2) a main surface of the silicon carbide bulk substrate. Forming the low-concentration impurity epitaxial layer.

  The step (a2) is preferably performed after the step (a1).

  The step (a) includes a step of forming a protective film on the main surface of the silicon carbide bulk substrate before the step (a1), and between the step (a1) and the step (a2). The method may further include a step of removing the protective film from the silicon carbide bulk substrate.

  The step (a) may further include a step of planarizing a main surface of the silicon carbide bulk substrate between the step (a1) and the step (a2).

  According to the method of manufacturing a semiconductor substrate of the present invention, a first conductivity type high concentration impurity epitaxial layer containing impurities at a higher concentration than the silicon carbide bulk substrate is formed on the first surface of the first conductivity type silicon carbide bulk substrate. The process of carrying out is included.

  According to the present invention, in a semiconductor device including a SiC bulk substrate, the contact resistance of an electrode provided on the back surface side of the SiC bulk substrate can be reduced by providing the high concentration impurity epitaxial layer on the back surface of the SiC bulk substrate. Therefore, the power loss can be made lower than before.

  Further, according to the present invention, the semiconductor element as described above can be manufactured by a simple process suitable for mass production.

  The semiconductor element of the present invention is characterized in that a high-concentration impurity epitaxial layer containing impurities at a higher concentration than the SiC bulk substrate is formed on the back surface of the SiC bulk substrate.

  The “semiconductor element” in the present specification only needs to include at least one element formed using a semiconductor layer, and other than these elements such as a vertical MOSFET, JFET, Schottky diode, and PN diode, these elements. A wide range of devices including:

  According to the present invention, since the high-concentration impurity epitaxial layer is formed on the back surface of the SiC bulk substrate, the contact resistance of the lower electrode provided on the back surface side of the SiC bulk substrate can be reduced.

  As described above with reference to FIG. 8, the impurity doped layer 112 having a sufficient thickness cannot be formed with the conventional technique disclosed in Patent Document 1 (first problem). As a result, there is a problem that the contact resistance varies (second problem).

  In contrast, in the present invention, a high-concentration impurity epitaxial layer having a desired thickness can be easily formed on the back surface of the SiC bulk substrate by controlling conditions such as the growth time during epitaxial growth. Therefore, even if the thickness of the high-concentration impurity epitaxial layer decreases in the device manufacturing process, the contact resistance can be reliably reduced.

  In the present invention, the impurity concentration profile of the high concentration impurity epitaxial layer can be made substantially uniform in the depth direction. Here, “the impurity concentration profile is substantially uniform in the depth direction” means that the impurity concentration profile in the depth direction of the high concentration impurity layer 3 does not have a peak like the impurity concentration profile by ion implantation. It means within ± 10% of the set value of impurity concentration, typically within ± 5% of the set value. When such a high-concentration impurity epitaxial layer is formed, even if the high-concentration impurity epitaxial layer is reduced in the device manufacturing process, the surface of the high-concentration impurity layer after the reduction (that is, the surface on which the lower electrode is formed) is reduced. Impurity concentration can be made substantially constant. Therefore, it is advantageous because the contact resistance can be stably reduced regardless of the reduction amount. Furthermore, even if the amount of reduction varies, it is possible to prevent variation in contact resistance.

  On the other hand, the inventors of the present application have studied a process for manufacturing the above-described semiconductor element, and found that there is a new problem that was not found in the technique of Patent Document 1. In general, when a device is formed using a SiC bulk substrate, an epitaxial layer is formed on the main surface of the SiC bulk substrate. In the semiconductor element, an epitaxial layer is also formed on the back surface of the SiC bulk substrate. Conventionally, the epitaxial layer was not formed on the both surfaces (main surface and back surface) of the SiC bulk substrate as described above, but it was not recognized. However, the epitaxial layer was also formed on the back surface of the SiC bulk substrate. When trying to form, there is a problem that the epitaxial layer on the main surface side is adversely affected and the device characteristics are deteriorated. This problem will be described in detail later. Further, when one epitaxial layer is formed and then the other epitaxial layer is formed, there is also a problem that surface roughness occurs in the previously formed epitaxial layer, thereby deteriorating device characteristics. Furthermore, in the case of a SiC bulk substrate having a hexagonal crystal structure (4H, 6H), it is necessary to epitaxially grow SiC not only on the Si surface but also on the C surface, but the process conditions for epitaxial growth on the C surface are optimized. There is also the problem that it is difficult to do.

  The inventors of the present invention overcome the above-mentioned process problems by original ideas and can further reduce the contact resistance by actively utilizing the surface roughness generated in the previously formed epitaxial layer. I found it. This will be described in detail later.

(First embodiment)
Hereinafter, a semiconductor substrate according to a first embodiment of the present invention will be described with reference to the drawings. 1A and 1B are schematic cross-sectional views showing the semiconductor substrate of this embodiment, respectively. The “semiconductor substrate” in this specification refers to a substrate that is formed using a semiconductor bulk substrate and is used for forming a semiconductor element, such as an epitaxial substrate having an epitaxial layer formed on the surface of the semiconductor bulk substrate. A wide range of substrates obtained by performing some kind of processing on the semiconductor bulk substrate is included.

  As shown in FIG. 1A, a semiconductor substrate 100 includes a first conductivity type (for example, n-type) bulk substrate 1 containing SiC, and a high-concentration impurity layer 3 formed on the surface 1r of the bulk substrate 1 by epitaxial growth. And. The high-concentration impurity layer 3 has the same conductivity type (for example, n-type) as the bulk substrate 1 and contains impurities at a higher concentration than the bulk substrate 1.

  As described above, since the semiconductor substrate 100 includes the high concentration impurity layer 3, an ohmic electrode is provided on the high concentration impurity layer 3 when a vertical semiconductor element is formed using the semiconductor substrate 100. The contact resistance of the ohmic electrode can be reduced.

  In this embodiment, since epitaxial growth is used, the high concentration impurity layer 3 thicker than the impurity doped layer 112 in Patent Document 1 can be formed by controlling the growth time. Further, the impurity concentration profile can be made substantially uniform in the depth direction. Therefore, the impurity concentration in the vicinity of the surface of the high-concentration impurity layer 3 is substantially equal to the design value (typically within ± 5% of the design value) regardless of the reduction amount of the high-concentration impurity layer 3 in the process of manufacturing the SiC device ), The contact resistance can be more reliably reduced. Furthermore, variations in contact resistance between products are suppressed, and reliability can be improved.

  The thickness of the high-concentration impurity layer 3 is not particularly limited, but is set to be larger than the amount of reduction due to a thermal oxidation process or an electrode formation process when a device is formed using the semiconductor substrate 100. When a 4H—SiC or 6H—SiC substrate is used as the bulk substrate 1 and the high concentration impurity layer 3 is formed on the C surface of such a substrate, the thermal oxidation rate on the C surface is higher than that of the Si surface. The amount of loss due to the oxidation process increases. Therefore, in such a case, the thickness of the high concentration impurity layer 3 is preferably 1 μm or more, more preferably 1.2 μm or more. On the other hand, when the high-concentration impurity layer 3 is formed on the Si surface of the 4H—SiC or 6H—SiC substrate, the amount of loss due to the thermal oxidation process can be kept small, and the thickness of the high-concentration impurity layer 3 is, for example, 300 nm. It is sufficient if it is above, preferably 500 nm or more. In addition, in the case where the high concentration impurity layer 3 is formed on either the C surface or the Si surface, the thickness of the high concentration impurity layer 3 is such that at least about 100 nm to 200 nm remains, except for the amount of loss due to thermal oxidation or silicide. It is preferable to set the length. The same applies to the second to fourth embodiments.

The impurity concentration of the high-concentration impurity layer 3 is not particularly limited as long as it is higher than that of the bulk substrate 1. However, it is preferable that the impurity concentration is 10 times or more the impurity concentration of the bulk substrate 1 because the contact resistance can be improved more effectively. When an SiC bulk substrate having an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ is used as the bulk substrate 1, the impurity concentration of the high concentration impurity layer 3 is 1 × 10 ¹⁹ cm ⁻³ or more, more preferably 1 × 10 ²⁰ cm ^−3. If it is above, since an ohmic electrode can be formed with respect to the SiC surface containing impurities at a concentration higher by one digit or more than the surface 1r of the bulk substrate 1, the contact resistance can be greatly reduced. On the other hand, the impurity concentration of the high concentration impurity layer 3 is preferably set to about 5 × 10 ²⁰ cm ⁻³ or less. The same applies to the second to fourth embodiments.

  The high concentration impurity layer 3 may not have a substantially uniform impurity concentration profile in the depth direction. For example, if the amount of reduction in the device manufacturing process is taken into account, the effect of reducing contact resistance can be obtained if it is adjusted to have a high impurity concentration in a predetermined region (for example, a region having a depth of 500 nm to 1 μm). It is done. In such a case, it is preferable that the impurity concentration in the predetermined region is sufficiently high and substantially constant in the depth direction because the contact resistance can be more reliably reduced.

  The high concentration impurity layer 3 is formed on one surface of the bulk substrate 1. When a 4H—SiC or 6H—SiC substrate is used as the bulk substrate 1, the high concentration impurity layer 3 is preferably formed on the C plane. For example, Materials Science Forum Vols. As described in 383-393 (2002) pp165-170, an epitaxial layer containing impurities at a higher concentration can be more easily formed on the C plane than on the Si plane. Therefore, when the high concentration impurity layer 3 is formed on the C plane, the impurity concentration in the high concentration impurity layer 3 can be increased, and the contact resistance can be further reduced.

  On the other hand, when the high-concentration impurity layer 3 is formed on the Si surface, the thermal oxidation rate of the Si surface is smaller than that of the C-plane, so that the amount of reduction by the thermal oxidation process of the high-concentration impurity layer 3 can be reduced. There is an advantage that the thickness of 3 can be reduced.

  The configuration of the semiconductor substrate in the present embodiment is not limited to the configuration shown in FIG. For example, an epitaxial substrate having an epitaxial layer on both sides of the bulk substrate 1 may be used. With reference to FIG. 1B, the structure of the substrate with epi in this embodiment will be described.

As illustrated, the semiconductor substrate 200 further includes an epitaxial layer 5 containing impurities at a lower concentration than the bulk substrate 1 on the surface 1p of the bulk substrate 1 opposite to the surface 1r where the high concentration impurity layer 3 is formed. ing. The epitaxial layer 5 has a function of ensuring the off breakdown voltage of the vertical power device formed on the semiconductor substrate 200. The impurity concentration in the epitaxial layer 5 is, for example, 5 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁶ cm ⁻³ or less. Moreover, the thickness of the epitaxial layer 5 is 10 micrometers or more and 15 micrometers or less, for example.

  The high-concentration impurity layer 3 in the semiconductor substrates 100 and 200 is preferably in contact with the surface 1r of the bulk substrate 1 as shown in the figure, but another layer (for example, carbonized) is interposed between the high-concentration impurity layer 3 and the bulk substrate 1. A silicon epitaxial layer or the like may be provided.

  Next, a method for manufacturing the semiconductor substrate of the present embodiment will be described with reference to the drawings. Here, a method for manufacturing the semiconductor substrate 200 shown in FIG. 1B will be described as an example.

First, as shown in FIG. 2A, a bulk substrate 1 containing silicon carbide is prepared. As the bulk substrate 1, for example, a 4H—SiC substrate (conductivity type: n-type, impurity concentration: 1 × 10 ¹⁸ cm ⁻³ ) is used. One of the surfaces 1r and 1p of the bulk substrate 1 is a Si surface in which only silicon atoms are exposed, and the other is a C surface in which only carbon atoms are exposed. The bulk substrate 1 is an off-cut substrate in which the Si surface has an off angle of 8 degrees from the (0001) to the <112-0> (112 bar 0) direction. In this embodiment, since epitaxial growth is performed on both surfaces 1p and 1r of the bulk substrate 1, it is preferable to polish both surfaces 1p and 1r of the bulk substrate 1 so that their surface roughness is approximately the same.

  After the bulk substrate 1 as described above is washed using sulfuric acid / hydrogen peroxide, ammonia / hydrogen peroxide, hydrofluoric acid, etc., as shown in FIG. 2 (b), on the surface (here, C surface) 1r of the bulk substrate 1, The high concentration impurity layer 3 is epitaxially grown by the CVD method. Thereby, the semiconductor substrate 100 is obtained.

For the formation of the high-concentration impurity layer 3, a vertical CVD furnace disclosed in Patent Document 1 can be used. In this embodiment, monosilane (SiH ₄ ) and propane (C ₃ H ₈ ) are used as source gases, hydrogen is used as a carrier gas, and nitrogen is used as an n-type dopant gas.

A method for forming the high-concentration impurity layer 3 will be specifically described. First, the bulk substrate 1 is placed on the susceptor in the chamber in the vertical CVD furnace so that the surface 1r on which the high-concentration impurity layer 3 is to be formed becomes the front surface, and the degree of vacuum in the chamber is 10 ⁻⁶ Pa or less. Reduce pressure until Thereafter, hydrogen as a carrier gas is supplied to the chamber at a flow rate of 2 L / min, for example, and the bulk substrate 1 is heated to a growth temperature (for example, 1600 ° C.) by a high-frequency heating method while keeping the pressure in the chamber at 1 atm. When the temperature of the bulk substrate 1 reaches the growth temperature, silane and propane as source gases and nitrogen as a dopant gas are supplied into the chamber. Here, silane and propane are supplied at a flow rate of 10 mL / min and 1 mL / min, respectively, and nitrogen as a dopant gas is supplied at a flow rate of 10 mL / min. For the process conditions for epitaxial growth on the C-plane, see, for example, Materials Science Forum Vols. 483-485 (2005) pp 92-96 and Materials Science Forum Vols. 389-393 (2002) pp 165-170. In this way, the high concentration impurity layer 3 is formed. The thickness of the formed high concentration impurity layer 3 is, for example, 1 μm, and the impurity concentration is, for example, 1 × 10 ¹⁹ cm ⁻³ .

  Next, as shown in FIG. 2 (c), the bulk substrate 1 installed on the susceptor in the chamber is turned over so that the surface (here, Si surface) 1p of the bulk substrate 1 is turned up, and the CVD method is applied. Thus, the epitaxial layer 5 containing impurities at a lower concentration than the bulk substrate 1 is formed on the surface 1p. Thereby, the semiconductor substrate 200 is obtained.

  The types of CVD furnaces and gases (such as source gas, carrier gas and n-type dopant gas) used for forming the epitaxial layer 5 may be the same as those described above with reference to FIG. . Suitable growth conditions differ depending on whether the surface 1p of the bulk substrate on which the epitaxial layer 5 is to be formed is a C plane or a Si plane. Here, since epitaxial growth is performed on the Si surface of the bulk substrate 1, for example, the C / Si ratio in the source gas is adjusted to be about 0.3.

A specific method for forming the epitaxial layer 5 will be described. First, after reducing the pressure in the chamber to a vacuum of 10 ⁻⁶ Pa or less, hydrogen gas as a carrier gas is supplied to the chamber at a flow rate of 2 L / min, for example, while maintaining the pressure in the chamber at 1 atm, The bulk substrate 1 is heated to a growth temperature (for example, 1600 ° C.) by a heating method. When the temperature of the bulk substrate 1 reaches the growth temperature, silane and propane as raw material gases are supplied to the chamber at flow rates of 10 mL / min and 1 mL / min, respectively, and nitrogen gas as a dopant gas is supplied at a flow rate of 3 mL / min. Supply. In this way, the epitaxial layer 5 is formed. The thickness of the obtained epitaxial layer 5 is, for example, 15 μm, and the impurity concentration is lower than the impurity concentration of the bulk substrate 1, for example, 5 × 10 ¹⁵ cm ⁻³ .

  In the above method, the thickness of the high-concentration impurity layer 3 is 1 μm, but it is possible to form a thicker high-concentration impurity layer 3 by extending the growth time in epitaxial growth. As described above, in this embodiment, since it is not restricted by the acceleration energy of ions as in the case of forming by ion implantation, depending on the configuration of the semiconductor element to be manufactured and the manufacturing process of the semiconductor element, high-concentration impurities The thickness of the layer 3 can be arbitrarily set.

  In the above method, the bulk substrate 1 having both surfaces polished is used, but the bulk substrate 1 having only one surface polished may be used. In this case, it is preferable that the epitaxial layer 5 is formed on the polished surface, that is, the surface having a smaller surface roughness, and the high concentration impurity layer 3 is formed on the opposite surface. In many cases, only an ohmic electrode is formed on the high-concentration impurity layer 3, whereas a diffusion region, a gate structure, or the like is formed on the surface of the epitaxial layer 5. Because it is required.

  Further, the process conditions such as the type, flow rate, and growth temperature of the source gas when forming the high-concentration impurity layer 3 and the epitaxial layer 5 are not limited to the above-described conditions, and are appropriately selected.

  The order in which the epitaxial layer 5 and the high concentration impurity layer 3 are formed is not particularly limited. However, when the epitaxial layer 5 is formed after the high concentration impurity layer 3 as in the above method, there are the following advantages.

  In the step shown in FIG. 2C, when the epitaxial layer 5 is grown on the surface (for example, Si surface) 1p of the bulk substrate 1 using a CVD furnace, the surface (for example, C surface) 1r on the opposite side of the bulk substrate 1 is grown. Since the surface 3r of the formed high-concentration impurity layer 3 is in contact with the susceptor of the CVD furnace, it becomes a high temperature of 1600 ° C. in a state where the source gas is not supplied. For this reason, carbon or silicon is sublimated from the surface 3r to cause surface roughness. As a result, the surface roughness Ra of the high concentration impurity layer 3 in the semiconductor substrate 200 is, for example, not less than 10 nm and not more than 100 nm. In addition, "surface roughness Ra" in this specification is defined by arithmetic average roughness Ra standardized by JISB0601-1994.

  When a semiconductor element is formed using the semiconductor substrate 200, an electrode is formed by depositing a conductive material such as Ni on the high-concentration impurity layer 3 and performing PDA as necessary. At this time, if the high-concentration impurity layer 3 has such surface roughness, the resistance between the high-concentration impurity layer 3 and the electrode formed thereon can be greatly reduced. As described above, according to the above method, when the epitaxial layers are sequentially formed on both surfaces of the bulk substrate 1, the on-resistance in the semiconductor element can be further reduced by utilizing the surface roughness generated in the previously formed epitaxial layer.

  By the way, the present inventors have found that there are the following process problems when an epitaxial layer is formed on both sides of a bulk substrate. This problem will be described with reference to FIGS.

  In the step shown in FIG. 2B, when the high concentration impurity layer 3 is epitaxially grown on the surface 1r of the bulk substrate 1 in the chamber of the CVD furnace, the opposite surface 1p of the bulk substrate 1 is in contact with the susceptor in the chamber. ing. Accordingly, the surface 1p of the bulk substrate 1 becomes high temperature (1600 ° C.) in a state where the source gas is not supplied, so that carbon or silicon is sublimated to cause surface roughness, or substances from the susceptor adhere to the surface 1p. Surface roughening and contamination may occur. When epitaxial growth is performed by the method described with reference to FIG. 2C on the surface 1p on which such surface roughness or contamination occurs, the crystallinity of the obtained epitaxial layer 5 is the above surface roughness or contamination. There is a risk of lowering due to. If, for example, a vertical MOSFET is manufactured using such an epitaxial layer 5, there is a possibility that device characteristics such as a breakdown voltage of a gate insulating film or a channel mobility may be deteriorated.

  Therefore, in order to prevent the device characteristics from being deteriorated due to the surface roughness or contamination of the surface 1p of the bulk substrate 1, the surface 1p of the bulk substrate 1 is subjected to planarization before the epitaxial layer 5 is formed. You may suppress the crystallinity fall of the epitaxial layer 5 formed on it. Hereinafter, it demonstrates concretely, referring drawings.

  3A to 3C are process cross-sectional views for explaining another method for manufacturing a semiconductor substrate in the present embodiment. For simplicity, the same components as those of the semiconductor substrates 100 and 200 are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 3A, a high-concentration impurity layer 3 is formed by epitaxial growth on a surface (here, C-plane) 1r in a bulk substrate 1 containing silicon carbide. As the bulk substrate 1, the 4H—SiC substrate described with reference to FIG. The high concentration impurity layer 3 is formed using a CVD furnace in the same manner as described above with reference to FIGS. 2 (a) and 2 (b). By this step, the high concentration impurity layer 3 is formed, and on the surface (here, Si surface) 1p ′ opposite to the surface 1r on the bulk substrate 1 where the high concentration impurity layer 3 is formed, as shown in the figure. Surface roughness and contamination occur.

  Next, as shown in FIG. 3B, the surface 1p ′ on which surface roughness or contamination has occurred is planarized using CMP (chemical mechanical polishing), and the surface roughness Ra is reduced to about 0.1 nm. 1p ″ is obtained. As the CMP slurry, for example, a slurry of colloidal silica or chromium oxide can be used. The surface roughness Ra of the planarized surface 1p ″ is not particularly limited, but is preferably 0.1 nm or less. After the CMP, the surface 1p '' of the bulk substrate 1 is cleaned so that there is no slurry remaining. In this way, the semiconductor substrate 300 is obtained.

  Thereafter, as shown in FIG. 3 (c), the semiconductor substrate 300 is placed on the susceptor in the chamber of the CVD furnace so that the flattened surface 1p ″ becomes the surface, and the epitaxial layer is formed on the surface 1p ″. 5 is formed. The method for forming the epitaxial layer 5 is the same as the method described with reference to FIG. Thereby, the semiconductor substrate (substrate with epi) 400 is obtained.

  According to this method, when the high-concentration impurity layer 3 is epitaxially grown on the surface (for example, C surface) 1r of the bulk substrate 1, surface roughness or contamination occurs on the opposite surface (for example, Si surface) 1p of the bulk substrate 1. Even in this case, it is possible to suppress the deterioration of device characteristics due to such surface roughness and contamination.

  Alternatively, a high concentration impurity layer is formed on the surface 1r of the bulk substrate 1 in a state where the surface 1p of the bulk substrate 1 is covered with a protective film in order to prevent deterioration of device characteristics due to surface roughness or contamination on the surface 1p of the bulk substrate 1. 3 can also be epitaxially grown. Hereinafter, it demonstrates concretely, referring drawings.

  4A to 4D are process cross-sectional views for explaining another method for manufacturing a semiconductor substrate in the present embodiment. For simplicity, the same components as those of the semiconductor substrates 100 and 200 are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 4A, a protective film 4 is formed on a surface (here, Si surface) 1p opposite to a surface on which a high concentration impurity layer is to be formed in a bulk substrate 1 containing silicon carbide. To do. Here, a carbon film having a thickness of 0.1 μm is formed as the protective film 4 by sputtering. Although the thickness of the protective film 4 is not specifically limited, For example, it is 0.05 micrometer or more, Preferably it is 0.1 micrometer or more.

  The protective film 4 is preferably formed of a material that can withstand the growth temperature (for example, 1600 ° C.) in the epitaxial growth of silicon carbide, and is not limited to the carbon film. As a material of the protective film 4, for example, aluminum nitride or tantalum carbide may be used. Here, the protective film 4 is formed by sputtering, but CVD may be used instead.

Next, as shown in FIG. 4B, the bulk substrate 1 on which the protective film 4 is formed is placed on the susceptor of the CVD furnace so that the surface 1r on which the high concentration impurity layer is to be formed is exposed. The concentration impurity layer 3 is epitaxially grown. The conditions such as the type, flow rate, and growth temperature of the source gas when performing epitaxial growth are the same as those described above with reference to FIG. The thickness of the obtained high concentration impurity layer 3 is preferably 1 μm or more, and the concentration of the n-type impurity (nitrogen) is preferably 1 × 10 ¹⁹ cm ⁻³ or more.

  Thereafter, as shown in FIG. 4C, the protective film 4 is removed from the bulk substrate 1 to obtain a semiconductor substrate 500. Although the removal method of the protective film 4 is not specifically limited, For example, it is preferable to carry out by exposing to the hydrogen gas, keeping the bulk substrate 1 at high temperature.

A method for removing the protective film 4 will be described more specifically. First, the bulk substrate 1 is placed on the susceptor in the chamber of the CVD furnace so that the surface 1p on which the protective film 4 is formed becomes the front. Next, after reducing the pressure in the chamber to 10 ⁻⁶ Pa or less, hydrogen is supplied to the chamber at a flow rate of, for example, 2 L / min, and the pressure in the chamber is maintained at 1 atm, and the bulk is formed by a high-frequency heating method. The substrate 1 is heated to 1600 ° C., for example. As a result, carbon, which is the material of the protective film 4, reacts with hydrogen to become hydrocarbons, which are detached from the surface 1 p of the bulk substrate 1. In this way, the protective film 4 can be removed almost completely without damaging the surface 1p of the bulk substrate 1. According to this method, since the protective film 4 can be removed using a CVD furnace, the protective film 4 is removed while the bulk substrate 1 is installed in the CVD furnace, and the subsequent formation of the epitaxial layer 5 is performed. Is advantageous because it can be carried out continuously.

  Subsequently, as shown in FIG. 4D, the epitaxial layer 5 is formed on the surface 1p of the bulk substrate 1 in a state where the semiconductor substrate 500 is left on the susceptor without being taken out of the CVD furnace. The formation conditions of the epitaxial layer 5 are the same as those described above with reference to FIG. In this way, a semiconductor substrate 600 which is an epitaxial substrate is obtained.

  According to this method, when the high-concentration impurity layer 3 is epitaxially grown on the surface (for example, C surface) 1r of the bulk substrate 1, the opposite surface (for example, Si surface) 1p in the bulk substrate 1 is covered with the protective film 4. Therefore, it is possible to prevent surface roughness and contamination from occurring on the surface 1p of the bulk substrate 1. Accordingly, since the epitaxial layer 5 having excellent crystallinity can be formed on the surface 1p of the bulk substrate 1, high device characteristics can be obtained.

(Second Embodiment)
Hereinafter, a semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings. The semiconductor element of this embodiment is a vertical PN diode formed using a SiC bulk substrate. A PN junction or an ohmic electrode is formed on the main surface side of the SiC bulk substrate, and a high-side is formed on the back surface side. A back electrode electrically connected to the bulk substrate through a concentration impurity layer is formed.

  A method for manufacturing the semiconductor device of this embodiment will be described. 5A to 5K are process cross-sectional views illustrating the method for manufacturing a semiconductor element of this embodiment. For simplicity, the same components as those of the semiconductor substrates 100 and 200 are denoted by the same reference numerals, and description thereof is omitted.

As shown in FIG. 5A, the semiconductor substrate 100 is obtained by epitaxially growing the high-concentration impurity layer 3 on the surface 1r of the bulk substrate 1 containing silicon carbide. In the present embodiment, the 4H—SiC substrate described with reference to FIG. 2A is used as the bulk substrate 1, and the C surface of the 4H—SiC substrate is defined as the surface 1r. The semiconductor substrate 100 in the present embodiment is manufactured by a method similar to the method described above with reference to FIGS. The thickness of the high concentration impurity layer 3 is 1 μm or more (for example, 1.1 μm), and the concentration of the n-type impurity is 1 × 10 ¹⁹ cm ⁻³ or more (for example, 2 × 10 ¹⁹ cm ⁻³ ).

Next, as shown in FIG. 5B, the epitaxial layer 5 is formed on the surface (Si surface) 1 p opposite to the surface 1 r on which the high-concentration impurity layer 3 is formed in the bulk substrate 1. The method for forming the epitaxial layer 5 is the same as that described above with reference to FIG. The epitaxial layer 5 becomes an active layer constituting an active region of the PN diode, and has a function of ensuring an off breakdown voltage of the PN diode. For example, when a PN diode having a withstand voltage of 1000 V is manufactured, the thickness of the epitaxial layer 5 is set to 10 μm to 15 μm, and the impurity concentration is set to 5 × 10 ¹⁵ cm ^{−3 to} 1 × 10 ¹⁶ cm ⁻³ .

  Thereafter, as shown in FIG. 5C, a P-type well region, a field limiting ring serving as a termination structure, and a P-type contact region are respectively defined on the surface of the epitaxial layer 5 by using an ion implantation method. Injection layers 7 ′, 9 ′, 11 ′ are formed.

A method for forming these injection layers 7 ′, 9 ′, and 11 ′ will be specifically described. First, P-type impurities (here, Al) are ion-implanted into the epitaxial layer 5 to form implantation layers 7 ′ and 9 ′ that respectively define a P-type well region and a field limiting ring (first implantation step). ). The implantation layer 9 ′ that defines the field limiting ring is arranged on the surface of the epitaxial layer 5 so as to surround the implantation layer 7 ′ that defines the P-type well region. Here, as the first injection process, four-stage multi-stage injection is performed with four types of acceleration voltages selected from the range of 30 keV to 350 keV. The total dose in the multi-stage implantation is about 1 × 10 ¹⁴ cm ⁻² . Subsequently, an injection layer 11 ′ for defining a P-type contact region is formed inside the injection layer 7 ′ for defining a P-type well region (second implantation step). The implantation layer 11 ′ that defines the P-type contact region contains P-type impurities at a higher concentration than the implantation layer 7 ′ that defines the P-type well region, and is more than the implantation layer 7 ′ that defines the P-type well region. shallow. Here, as the second implantation step, three-stage implantation is performed with three types of acceleration voltages selected from the range of 30 keV to 150 keV. The total dose in multistage implantation is about 1 × 10 ¹⁵ cm ⁻² . Both the first and second implantation steps are performed at a high temperature of 500 ° C. In the case of ion implantation for silicon carbide, if the crystallinity of silicon carbide collapses during implantation, the crystallinity does not recover even if high-temperature annealing is performed after the implantation. It is because it can maintain.

After the first and second implantation steps, annealing is performed for 30 minutes at a temperature of 1700 ° C. in an inert atmosphere such as argon to activate Al ions. Thereby, as shown in FIG. 5D, the implantation layers 7 ′, 9 ′, and 11 ′ become the P-type well region 7, the field limiting ring 9, and the P-type contact region 11, respectively. The depths of the obtained P-type well region 7 and field limiting ring 9 are about 0.4 μm, and the impurity concentration is about 2 × 10 ¹⁸ cm ⁻³ . The depth of the P-type contact region 11 is about 0.2 μm, and the impurity concentration is about 5 × 10 ¹⁹ cm ⁻³ .

  As a result of the above implantation process, damaged layers are formed on the surfaces of the epitaxial layer 5 and the high-concentration impurity layer 3. In order to remove the damaged layers, thermal oxidation treatment (first thermal oxidation treatment) is performed on these surfaces. Do. As a result, as shown in FIG. 5E, the surfaces of the epitaxial layer 5 and the high concentration impurity layer 3 are oxidized to form sacrificial oxide films 13 and 15. In the present embodiment, the first thermal oxidation treatment is performed in a dry oxygen atmosphere at a temperature of 1200 ° C. for 3 hours using a thermal oxidation furnace. By such thermal oxidation treatment, a sacrificial oxide film 13 having a thickness of about 80 nm is formed on the surface of the epitaxial layer 5 that is the Si surface, and a sacrificial layer having a thickness of about 800 nm is formed on the surface of the high concentration impurity layer 3 that is the C surface. Oxide films 15 are formed respectively.

  Subsequently, as shown in FIG. 5F, the sacrificial oxide films 13 and 15 are removed. The sacrificial oxide films 13 and 15 can be removed by performing wet etching for 30 minutes using, for example, 10: 1 buffered hydrofluoric acid as an etching solution.

  As described above, when a thermal oxide film having a thickness t is formed on the SiC surface, the thickness of consumed SiC is 0.46 × t. Therefore, the thickness of the high-concentration impurity layer 3 after removing the sacrificial oxide film 15 is reduced by about 400 nm compared to before the sacrificial oxide film 15 is formed.

  Next, as shown in FIG. 5G, the epitaxial layer 5 and the high-concentration impurity layer 3 are subjected to thermal oxidation treatment (second thermal oxidation treatment), and the surface of these layers 5 and 3 is subjected to surface protection. As the films, new oxide films 17 and 19 are formed. In the present embodiment, the second thermal oxidation treatment is performed in a dry oxygen atmosphere at a temperature of 1200 ° C. for 3 hours using a thermal oxidation furnace. By such thermal oxidation treatment, an oxide film 17 having a thickness of 80 nm is formed on the surface of the epitaxial layer 5, and an oxide film 19 having a thickness of 800 nm is formed on the surface of the high concentration impurity layer 3.

  In order to form the oxide film 19, the thickness of the high-concentration impurity layer 3 is further reduced by about 400 nm. Therefore, the thickness of the high concentration impurity layer 3 is reduced by about 800 nm in total by the first and second thermal oxidation treatments.

  Thereafter, as shown in FIG. 5H, after removing a part of the oxide film 17 located on the P-type contact region 11, an ohmic electrode 21 in contact with the P-type contact region 11 is formed.

  The ohmic electrode 21 can be formed using, for example, a lift-off method. First, a resist layer (not shown) is formed on a predetermined region in the oxide film 17 by known photolithography. Thereafter, wet etching is performed using buffered hydrofluoric acid as an etchant, and a portion of the oxide film 17 not covered with the resist layer is removed. As a result, the surface of the P-type contact region 11 is exposed. Subsequently, a nickel film having a thickness of, for example, 100 nm is deposited on the exposed surface of the P-type contact region 11 and the resist layer by EB vapor deposition. Thereafter, by removing the resist layer, the nickel film is patterned (lift-off method), and the ohmic electrode 21 is formed.

  Subsequently, as shown in FIG. 5I, a back electrode 23 in contact with the high-concentration impurity layer 3 is formed on the back side of the bulk substrate 1.

  A method for forming the back electrode 23 will be described. First, in order to protect the surface on the main surface side of the bulk substrate 1, a photoresist (not shown) is applied. In this state, the oxide film 19 formed on the back side of the bulk substrate 1 is removed to expose the high concentration impurity layer 3. The oxide film 19 can be removed by etching for 30 minutes using buffered hydrofluoric acid as an etchant. On the high-concentration impurity layer 3 exposed by etching, for example, nickel having a thickness of about 200 nm is deposited by EB vapor deposition. Thereafter, the photoresist for protecting the surface on the main surface side of the bulk substrate 1 is removed, followed by annealing for about 2 minutes at a temperature of about 1000 ° C. in an inert atmosphere such as argon. In this way, the back electrode 23 is obtained.

  By the annealing, nickel silicide is formed at the interface between the back electrode 23 and the high-concentration impurity layer 3, so that good ohmic characteristics can be obtained. The formation of nickel silicide consumes the high concentration impurity layer 3 having the same thickness (200 nm) as the deposited nickel, so the thickness of the high concentration impurity layer 3 is further reduced by about 200 nm, for example, 100 nm or more. 500 nm or less. By this annealing, nickel silicide is also formed at the interface between the ohmic electrode 21 and the P-type contact region 11.

  Thereafter, an interlayer insulating film 25 is formed so as to cover the ohmic electrode 21 and the oxide film 17 as shown in FIG. The interlayer insulating film 25 is formed by depositing an insulating material such as silicon oxide by a plasma CVD method. The thickness of the interlayer insulating film 25 is, for example, about 1 μm.

  Next, as shown in FIG. 5 (k), a contact hole reaching the ohmic electrode 21 is formed in the interlayer insulating film 25 using a known dry etching technique, and then an electrode is formed inside the contact hole and on the interlayer insulating film 25. A pad 27 is provided. The electrode pad 27 forms a conductive film (thickness: 3 μm, for example) by depositing a conductive material such as aluminum on the inside of the contact hole and on the entire surface of the interlayer insulating film 25, and the conductive film is publicly known. It can be formed by patterning using a photolithography technique and an etching technique. In this way, the semiconductor element 700 is obtained.

  The semiconductor element 700 obtained by the above method has a PN junction composed of the N-type epitaxial layer 5, the P-type well region 7 and the P-type contact region 11 on the main surface side of the bulk substrate 1. . In addition, an ohmic electrode 21 that is in ohmic contact with the P-type contact region 11 is provided. On the other hand, a high concentration impurity layer 3 and a back electrode 23 electrically connected to the bulk substrate 1 through the high concentration impurity layer 3 are provided on the back surface side of the bulk substrate 1. Since the back electrode 23 is in contact with the high-concentration impurity layer 3 having an impurity concentration higher than that of the bulk substrate 1, the contact resistance can be reduced as compared with the conventional configuration in contact with the back surface 1r of the bulk substrate 1.

  According to the present embodiment, since the high concentration impurity layer 3 is formed by epitaxial growth, the thickness of the high concentration impurity layer 3 can be easily controlled by adjusting the growth time. Therefore, there is an advantage that the high-concentration impurity layer 3 having a sufficient thickness can be formed in accordance with the thermal oxidation process performed in the process of forming the PN diode.

  More specifically, in the above method, two thermal oxidation treatments (first and second thermal oxidation treatments) are performed for surface cleaning and surface protection of the epitaxial layer 5 serving as an active layer. In any thermal oxidation treatment, a thermal oxide film having a thickness of 80 nm is formed on the surface of the epitaxial layer 5 that is the Si surface. At this time, the surface of the high-concentration impurity layer 3 that is the C surface has a thickness of A thermal oxide film having a thickness of 800 nm is formed. Therefore, when the thickness of the high-concentration impurity layer 3 consumed by these thermal oxidation processes is combined, the thickness is at least about 700 nm (for example, about 800 nm). Therefore, the thickness of the high concentration impurity layer 3 formed by epitaxial growth is preferably at least 700 nm or more. In addition, when performing PDA when forming the back surface electrode 23, since the high concentration impurity layer 3 about 100-200 nm thick is consumed for silicidation of the electrically-conductive material (nickel etc.) which comprises the back surface electrode 23, The thickness of the high-concentration impurity layer 3 formed by epitaxial growth is preferably 900 nm or more, for example. More preferably, it is 1 micrometer or more, More preferably, it is 1.1 micrometers or more.

  Here, considering the case where the impurity doped layer 112 is formed by ion implantation into the bulk substrate 1 as in Patent Document 1, in order to obtain the impurity doped layer 112 having a thickness of 700 nm or more, an extremely high acceleration voltage is necessary. It becomes. From the graph shown in FIG. 9, even if nitrogen is selected as an implantation seed for performing deeper implantation, the acceleration voltage required for ion implantation is 600 keV. The acceleration voltage of an ion implantation facility usually used in the manufacture of semiconductor elements is 500 keV or less, and in order to perform ion implantation at an acceleration voltage of 600 keV, a special large-sized facility is required, resulting in an increase in manufacturing cost.

  On the other hand, in the present embodiment, it is advantageous that the high concentration impurity layer 3 having a thickness of 700 nm or more can be easily formed by lengthening the growth time for epitaxial growth.

  In this embodiment, since the high concentration impurity layer 3 is formed by epitaxial growth, the impurity concentration profile of the high concentration impurity layer 3 is substantially uniform in the depth direction. Therefore, even if the amount of reduction in the high concentration impurity layer 3 in the process of forming the semiconductor element 700 varies, the impurity concentration in the vicinity of the surface in contact with the back electrode 23 in the high concentration impurity layer 3 of the obtained semiconductor element 700 is constant. . Therefore, variation in on-resistance between products is reduced, and reliability can be improved.

  The manufacturing method of the present embodiment is not limited to the method described with reference to FIGS. As described with reference to FIG. 3B, after the high-concentration impurity layer 3 is formed on the surface 1r of the bulk substrate 1, a planarization process may be performed on the surface 1p of the bulk substrate 1. FIG. As described with reference to (b), the high-concentration impurity layer 3 may be formed on the surface 1r of the bulk substrate 1 in a state where the protective film is formed on the surface 1p of the bulk substrate 1. Thereby, since a high quality epitaxial layer (active layer) 5 can be formed on the surface 1p of the bulk substrate 1, device characteristics can be improved.

  Moreover, in the said method, although Si surface in the bulk substrate 1 was used as a main surface, it is good also considering C surface as a main surface. In that case, since the high-concentration impurity layer 3 is formed on the Si surface, the amount of reduction due to the thermal oxidation treatment is smaller than that formed on the C surface. Therefore, the thickness of the high concentration impurity layer 3 to be epitaxially grown can be reduced.

(Third embodiment)
Hereinafter, a semiconductor device according to a third embodiment of the present invention will be described with reference to the drawings. The semiconductor element of the present embodiment is a vertical Schottky diode formed using a SiC bulk substrate. A Schottky electrode is formed on the main surface side of the SiC bulk substrate, and a high-concentration impurity is formed on the back surface side. It has a structure in which a back electrode electrically connected to the SiC bulk substrate through a layer is formed.

  The semiconductor element of this embodiment can be manufactured by the following method, for example. 6A to 6J are process cross-sectional views illustrating the method for manufacturing a semiconductor element of this embodiment. For simplicity, the same components as those of the semiconductor substrates 100 and 200 are denoted by the same reference numerals, and description thereof is omitted. In the method described below, unlike the above-described second embodiment, the C surface of the bulk substrate 1 is used as the main surface, and the high concentration impurity layer 3 is formed on the Si surface.

  First, as shown in FIG. 6A, a semiconductor substrate 100 'is obtained by epitaxially growing a high concentration impurity layer 3 on a surface (here, Si surface) 1r of a bulk substrate 1 containing silicon carbide. As the bulk substrate 1, the 4H—SiC substrate described with reference to FIG. Here, in order to perform epitaxial growth on both surfaces 1r and 1p of the bulk substrate 1, it is preferable to polish both surfaces 1r and 1p of the bulk substrate 1 so that their surface roughness is approximately the same. For the formation of the high-concentration impurity layer 3, the same CVD furnace or source gas as the method described in FIG. 2B can be used. However, in this embodiment, the epitaxial growth is performed on the Si surface of the bulk substrate 1. Suitable process conditions are different.

A specific method for forming the high concentration impurity layer 3 will be described. First, the bulk substrate 1 is washed with sulfuric acid / hydrogen peroxide, hydrofluoric acid, or the like, and then placed on a susceptor provided in the chamber of the CVD furnace so that the surface 1r becomes front. Next, the pressure in the chamber is reduced to a vacuum level of 10 ⁻⁶ Pa or less. Thereafter, hydrogen gas as a carrier gas is supplied to the chamber at a flow rate of 2 L / min, for example, and the bulk substrate 1 is heated to a growth temperature (for example, 1600 ° C.) by a high-frequency heating method while keeping the pressure in the chamber at 1 atm. . When the temperature of the bulk substrate 1 reaches the growth temperature, silane and propane, which are raw material gases, and nitrogen, which is a dopant gas, are supplied to the chamber. The flow rates of silane and propane are preferably adjusted so that the C / Si ratio is about 0.3, and are, for example, 3 mL / min and 2 mL / min, respectively. The flow rate of nitrogen as the dopant gas is, for example, 10 mL / min.

The thickness of the high-concentration impurity layer 3 thus formed is 300 nm or more (for example, 400 nm), and the impurity concentration of the high-concentration impurity layer 3 is 1 × 10 ¹⁹ cm ⁻³ (for example, 2 × 10 ¹⁹ cm ^−3). ).

  Next, as shown in FIG. 6B, the bulk substrate 1 installed on the susceptor in the chamber is turned over, and the surface of the bulk substrate 1 opposite to the surface 1r on which the high-concentration impurity layer 3 is formed (here, (C plane) 1p is set to be the front, and the epitaxial layer 5 is formed on the surface 1p of the bulk substrate 1. The method for forming the epitaxial layer 5 is the same as the method described above with reference to FIG. 2C, but in this embodiment, the epitaxial layer 5 is formed on the C-plane of the bulk substrate 1, and therefore suitable process conditions are used. Is different.

A specific method for forming the epitaxial layer 5 will be described. First, after reducing the pressure in the chamber to a vacuum of 10 ⁻⁶ Pa or less, hydrogen gas as a carrier gas is supplied to the chamber at a flow rate of 2 L / min, for example, while maintaining the pressure in the chamber at 1 atm, The bulk substrate 1 is heated to a growth temperature (for example, 1600 ° C.) by a heating method. When the temperature of the bulk substrate 1 reaches the growth temperature, silane and propane, which are raw material gases, and nitrogen gas, which is a dopant gas, are supplied to the chamber. The flow rates of silane and propane are, for example, 10 mL / min and 1 mL / min, respectively. The flow rate of the nitrogen gas that is the dopant gas is, for example, 0.1 mL / min. In this way, the epitaxial layer 5 is obtained.

The epitaxial layer 5 becomes an active layer constituting the active region of the Schottky diode, and has a function of ensuring the off breakdown voltage of the Schottky diode. For example, when a Schottky diode having a withstand voltage of 1000 V is manufactured, the thickness of the epitaxial layer 5 is set to 10 μm to 15 μm and the impurity concentration is set to 5 × 10 ¹⁵ cm ^{−3 to} 1 × 10 ¹⁶ cm ⁻³ .

Thereafter, as shown in FIG. 6C, a guard ring 31 serving as a termination structure is formed around the region of the surface of the epitaxial layer 5 where a Schottky electrode is to be formed, using an ion implantation method. . In the present embodiment, a P-type impurity (here, boron) is ion-implanted into the epitaxial layer 5 at an acceleration voltage of 30 kV. The dose is 1 × 10 ¹⁵ cm ⁻² . After the ion implantation, activation annealing is performed for 30 minutes at a temperature of 1700 ° C. in an inert atmosphere such as argon to obtain a P-type guard ring 31. The obtained guard ring 31 has an impurity concentration of 2 × 10 ²⁰ cm ⁻³ and a depth of 0.08 μm.

  As a result of the above implantation process, damaged layers are formed on the surfaces of the epitaxial layer 5 and the high-concentration impurity layer 3. In order to remove the damaged layers, thermal oxidation treatment (first thermal oxidation treatment) is performed on these surfaces. Do. Thereby, as shown in FIG. 6D, the surfaces of the epitaxial layer 5 and the high-concentration impurity layer 3 are oxidized to form sacrificial oxide films 33 and 35. In the present embodiment, the first thermal oxidation treatment is performed in a dry oxygen atmosphere at a temperature of 1200 ° C. for 0.5 hours using a thermal oxidation furnace. By such a thermal oxidation process, a sacrificial oxide film 33 having a thickness of about 80 nm is formed on the surface of the epitaxial layer 5 which is the C plane. On the other hand, since the surface of the high-concentration impurity layer 3 that is the Si surface has a low thermal oxidation rate, a sacrificial oxide film (thickness: about 8 nm, for example) 35 thinner than the sacrificial oxide film 33 is formed.

  Subsequently, as shown in FIG. 6E, the sacrificial oxide films 33 and 35 are removed by performing wet etching for about 10 minutes using, for example, 10: 1 buffered hydrofluoric acid as an etching solution.

  Next, as shown in FIG. 6 (f), thermal oxidation treatment (second thermal oxidation treatment) is performed on the epitaxial layer 5 and the high concentration impurity layer 3, and surface protection is performed on the surfaces of these layers 5 and 3. New oxide films 37 and 39 are formed as films. In the present embodiment, the second thermal oxidation treatment is performed in a dry oxygen atmosphere at a temperature of 1200 ° C. for 0.5 hours using a thermal oxidation furnace. By such thermal oxidation treatment, an oxide film 37 having a thickness of 80 nm is formed on the surface of the epitaxial layer 5, and an oxide film 39 having a thickness of about 8 nm is formed on the surface of the high-concentration impurity layer 3.

  In the first and second thermal oxidation processes described above, the surface portion of the high-concentration impurity layer 3 is consumed to form the sacrificial oxide film 35 and the oxide film 39. In the present embodiment, since the thicknesses of these oxide films 35 and 39 are both about 8 nm, the thickness of the high-concentration impurity layer 3 consumed is about 7 nm (0.46 × 8 (nm) in total. ) + 0.46 × 8 (nm)).

  Subsequently, as shown in FIG. 6G, a back electrode 41 in contact with the high concentration impurity layer 3 is formed on the back side of the bulk substrate 1.

  The back electrode 41 can be formed by the following method, for example. First, in order to protect the main surface side surface of the bulk substrate 1, a photoresist (not shown) is applied to the main surface side surface. In this state, the oxide film 39 formed on the back surface side of the bulk substrate 1 is removed to expose the high concentration impurity layer 3. The oxide film 39 can be removed by etching for 3 minutes using buffered hydrofluoric acid as an etchant. On the high-concentration impurity layer 3 exposed by etching, for example, nickel (thickness: about 200 nm) is deposited by EB vapor deposition. Thereafter, the photoresist for protecting the surface on the main surface side is removed, and then annealing is performed at a temperature of about 1000 ° C. for about 2 minutes in an inert atmosphere such as argon. Thereby, nickel and Si in the high concentration impurity layer 3 react to form nickel silicide (not shown). In this way, the back electrode 41 is obtained.

  Since nickel silicide is formed at the interface between the back electrode 41 and the high concentration impurity layer 3, good ohmic characteristics can be realized. It should be noted that the formation of nickel silicide further consumes the high-concentration impurity layer 3 having the same thickness (200 nm) as the deposited nickel.

  Thereafter, as shown in FIG. 6H, a part of the oxide film 37 is removed, and a Schottky electrode 43 in contact with the epitaxial layer 5 is formed. Schottky electrode 43 is provided in contact with the region surrounded by guard ring 31 on the surface of epitaxial layer 5 and the inner edge of the surface of guard ring 31.

  The Schottky electrode 43 can be formed by the following method, for example. First, a resist layer (not shown) is formed on a predetermined region in the oxide film 37 by known photolithography. Thereafter, wet etching is performed using buffered hydrofluoric acid as an etchant, and a portion of the oxide film 37 not covered with the resist layer is removed. As a result, the surface of the epitaxial layer 5 is exposed. Subsequently, a nickel film having a thickness of 100 nm is deposited on the exposed surface of the epitaxial layer 5 and the resist layer by EB vapor deposition. Thereafter, by removing the resist layer, the nickel film is patterned (lift-off method), and the Schottky electrode 43 is formed. In this embodiment, in order to enhance the adhesion between the Schottky electrode 43 and the epitaxial layer 5, after removing the resist layer, annealing is performed at a temperature of about 400 ° C. for 30 minutes in an inert atmosphere such as argon. I do. Here, the Schottky electrode 43 is formed using nickel, but the material of the Schottky electrode 43 is not particularly limited, and may be titanium, for example.

  Next, as illustrated in FIG. 6I, an interlayer insulating film 45 is formed so as to cover the Schottky electrode 43. The interlayer insulating film 45 can be formed by depositing an insulating material such as silicon oxide using a CVD method. The thickness of the interlayer insulating film 45 is, for example, about 1 μm.

  Subsequently, as shown in FIG. 6J, a contact hole reaching the Schottky electrode 43 is formed in the interlayer insulating film 45 by using a known dry etching technique, and then inside the contact hole and on the interlayer insulating film 45. An electrode pad 47 is provided on the substrate. The electrode pad 47 is formed by depositing a conductive material such as aluminum on the inside of the contact hole and the entire surface of the interlayer insulating film 45 to form a conductive film (thickness: 3 μm, for example). It can be formed by patterning using a lithography technique and an etching technique. In this way, the semiconductor element 800 is obtained.

  In the semiconductor element 800 obtained by the above method, the back electrode 41 is electrically connected to the bulk substrate 1 through the high concentration impurity layer 3. Therefore, the contact resistance can be reduced as compared with the conventional configuration in which the back electrode 41 and the back surface of the bulk substrate 1 are in contact with each other.

  In the above method, unlike the embodiment described above, the high concentration impurity layer 3 is formed on the Si surface of the bulk substrate 1 and the epitaxial layer 5 is formed on the C surface. Therefore, the thickness of the oxide films 35 and 39 formed on the surface of the high-concentration impurity layer 3 by the first and second thermal oxidation treatments is 1 / th that of the oxide films 33 and 37 formed on the surface of the epitaxial layer 5. It is suppressed to about 10. Therefore, since the thickness of the high concentration impurity layer 3 consumed by forming the oxide films 35 and 39 can be reduced, the thickness of the high concentration impurity layer 3 formed on the bulk substrate 1 by epitaxial growth can be reduced.

  Specifically, the total thickness of the high-concentration impurity layer 3 consumed by the first and second thermal oxidation treatments and the formation of the back electrode 41 is about 207 nm. Therefore, the thickness of the high concentration impurity layer 3 formed by epitaxial growth is preferably 300 nm or more, more preferably 400 nm or more. Thereby, the on-resistance between the back electrode 23 and the bulk substrate 1 can be reduced more reliably.

  The high concentration impurity layer 3 in the present embodiment is formed by epitaxial growth, and the impurity concentration profile is substantially uniform in the depth direction. Therefore, even if the reduction amount of the high concentration impurity layer 3 in the process of forming the semiconductor element 800 varies, the impurity concentration in the vicinity of the surface in contact with the back electrode 23 in the high concentration impurity layer 3 of the obtained semiconductor element 800 is constant. . Therefore, variation in on-resistance between products is reduced, so that reliability can be improved.

  The manufacturing method of the present embodiment is not limited to the method described with reference to FIGS. As described with reference to FIG. 3B, after the high-concentration impurity layer 3 is formed on the surface 1r of the bulk substrate 1, a planarization process may be performed on the surface 1p of the bulk substrate 1. FIG. As described with reference to (b), the high-concentration impurity layer 3 may be formed on the surface 1r of the bulk substrate 1 in a state where the protective film is formed on the surface 1p of the bulk substrate 1. Thereby, since a high quality epitaxial layer (active layer) 5 can be formed on the surface 1p of the bulk substrate 1, device characteristics can be improved.

  In the present embodiment, the C plane of the bulk substrate 1 is used as the main surface, but a Schottky diode may be configured using the Si surface as the main surface. In that case, since the high-concentration impurity layer 3 is formed on the C-plane, it is necessary to make the high-concentration impurity layer 3 to be epitaxially grown thick (for example, 1 μm or more) in consideration of the amount of reduction due to thermal oxidation treatment or the like.

(Fourth embodiment)
Hereinafter, a semiconductor device according to a fourth embodiment of the present invention will be described with reference to the drawings. The semiconductor element of this embodiment is a vertical MOSFET formed using a SiC bulk substrate, and a MOSFET portion including a channel that is turned on and off by a gate, a source electrode, and the like are formed on the main surface side of the SiC bulk substrate. On the back surface side, a drain electrode electrically connected to the SiC bulk substrate through a high concentration impurity layer is formed.

  A method for manufacturing the semiconductor device of this embodiment will be described. 7A to 7K are process cross-sectional views illustrating the method for manufacturing a semiconductor element of this embodiment. For simplicity, the same components as those of the semiconductor substrates 100 and 200 are denoted by the same reference numerals, and description thereof is omitted.

As shown in FIG. 7A, the semiconductor substrate 100 is obtained by epitaxially growing the high-concentration impurity layer 3 on the surface 1r of the bulk substrate 1 containing silicon carbide. In the present embodiment, the 4H—SiC substrate described with reference to FIG. 2A is used as the bulk substrate 1, and the Si surface of the 4H—SiC substrate is defined as the surface 1r. The high-concentration impurity layer 3 is produced by a method similar to the method described above with reference to FIG. The thickness of the high-concentration impurity layer 3 is 1 μm or more (for example, 1.2 μm), and the n-type impurity concentration is 1 × 10 ¹⁹ cm ⁻³ or more (for example, 2 × 10 ¹⁹ cm ⁻³ ).

Next, as shown in FIG. 7B, the epitaxial layer 5 is formed on the second surface (namely, Si surface) 1 p opposite to the first surface 1 r in the bulk substrate 1. The method for forming the epitaxial layer 5 is the same as that described above with reference to FIG. The epitaxial layer 5 becomes an active layer constituting the active region of the MOSFET and has a function of ensuring the off-breakdown voltage of the MOSFET. For example, when manufacturing a MOSFET having a withstand voltage of 1000 V, the thickness of the epitaxial layer 5 is set to 10 μm to 15 μm and the impurity concentration is set to 5 × 10 ¹⁵ cm ^{−3 to} 1 × 10 ¹⁶ cm ⁻³ .

  Thereafter, as shown in FIG. 7C, an implantation layer for defining a field limiting ring, a P-type well region, a source region, and a P-type contact region on the surface of the epitaxial layer 5 by using an ion implantation method. 51 ', 52', 53 ', 55' are formed.

A method of forming these injection layers 51 ′, 52 ′, 53 ′, and 55 ′ will be specifically described. First, a P-type impurity (for example, Al) is ion-implanted into the epitaxial layer 5 to form implantation layers 51 ′ and 52 ′ that respectively define a field limiting ring and a plurality of P-type well regions (first implantation). Process). The implantation layer 51 ′ defining the field limiting ring is disposed on the surface of the epitaxial layer 5 so as to surround the implantation layer 52 ′ defining the P-type well region. Here, as the first injection process, four-stage multi-stage injection is performed with four types of acceleration voltages selected from the range of 30 keV to 350 keV. The total dose in the multi-stage implantation is about 1 × 10 ¹⁴ cm ⁻² . Subsequently, an implantation layer 55 ′ for defining a P-type contact region is formed inside the implantation layer 52 ′ for defining a P-type well region by ion implantation (second implantation step). The implantation layer 55 ′ that defines the P-type contact region contains P-type impurities at a higher concentration than the implantation layer 52 ′ that defines the P-type well region, and is more than the implantation layer 52 ′ that defines the P-type well region. shallow. Here, as the second implantation step, three-stage implantation is performed with three types of acceleration voltages selected from the range of 30 keV to 150 keV. The total dose in multistage implantation is about 1 × 10 ¹⁵ cm ⁻² . Similarly, N-type impurities (for example, nitrogen) are ion-implanted (third implantation) in order to form an implantation layer 53 ′ defining an N-type source region inside an implantation layer 52 ′ defining a P-type well region. Process). Here, as the third injection step, four-stage multi-step injection is performed with four types of acceleration voltages selected from the range of 30 keV to 180 keV. The total dose in multi-stage implantation is about 1.7 × 10 ¹⁵ cm ⁻² .

  The first, second, and third implantation steps are all performed at a high temperature of 500 ° C. In the case of ion implantation for silicon carbide, if the crystallinity of silicon carbide collapses during implantation, the crystallinity does not recover even if high-temperature annealing is performed after the implantation. It is because it can maintain.

After the first, second, and third implantation steps, annealing is performed for 30 minutes at a temperature of 1700 ° C. in an inert atmosphere such as argon to activate Al ions and nitrogen ions. As a result, as shown in FIG. 7D, the implantation layers 51 ′, 52 ′, 53 ′, and 55 ′ include the field limiting ring 51, the P-type well region 52, the source region 53, and the P-type contact, respectively. It becomes area 55. The obtained field limiting ring 51 and P-type well region 52 have a depth of about 0.4 μm and an impurity concentration of about 2 × 10 ¹⁸ cm ⁻³ .

  As a result of the above implantation process, damaged layers are formed on the surfaces of the epitaxial layer 5 and the high-concentration impurity layer 3. In order to remove the damaged layers, thermal oxidation treatment (first thermal oxidation treatment) is performed on these surfaces. Do. Thereby, as shown in FIG. 7E, the surfaces of the epitaxial layer 5 and the high concentration impurity layer 3 are oxidized to form sacrificial oxide films 57 and 59. In the present embodiment, the first thermal oxidation treatment is performed in a dry oxygen atmosphere at a temperature of 1200 ° C. for 3 hours using a thermal oxidation furnace. By such thermal oxidation treatment, a sacrificial oxide film 57 having a thickness of about 80 nm is formed on the surface of the epitaxial layer 5 that is the Si surface, and the thickness of the high concentration impurity layer 3 that is the C surface is A sacrificial oxide film 59 having a thickness of about 800 nm is formed.

  Subsequently, as shown in FIG. 7F, the sacrificial oxide films 57 and 59 are removed by performing wet etching for about 30 minutes using, for example, 10: 1 buffered hydrofluoric acid as an etching solution.

  Next, as shown in FIG. 7G, a thermal oxidation process (second thermal oxidation process) is performed to form a new oxide film 61 as a surface protective film on the surface of the epitaxial layer 5. At this time, an oxide film 63 is also formed on the surface of the high concentration impurity layer 3. The second thermal oxidation treatment in this embodiment is performed at a temperature of 1200 ° C. for 3 hours in a dry oxygen atmosphere using a thermal oxidation furnace. When thermal oxidation treatment is performed under such conditions, an oxide film 61 having a thickness of 80 nm is formed on the surface of the epitaxial layer 5 and an oxide film 63 having a thickness of 800 nm is formed on the surface of the high-concentration impurity layer 3. Is done.

  In the first and second thermal oxidation processes described above, SiC is consumed on the surface portion of the high-concentration impurity layer 3 in order to form the sacrificial oxide film 59 and the oxide film 63. In the present embodiment, since the thicknesses of these oxide films 59 and 63 are both about 800 nm, the thickness of the high-concentration impurity layer 3 consumed is about 800 nm (0.46 × 800 (nm) in total. ) + 0.46 × 800 (nm)).

Thereafter, a gate electrode 65 is formed on the oxide film 61 as shown in FIG. The gate electrode 65 is disposed so as to cover a portion to be a channel in the epitaxial layer 5. The gate electrode 65 is formed using, for example, N-type polycrystalline silicon doped with an N-type impurity at a high concentration. Specifically, polycrystalline silicon containing phosphorus at a concentration of 7 × 10 ²⁰ cm ⁻³ is deposited on the oxide film 61 to form a polycrystalline silicon film having a thickness of, for example, 400 nm. Thereafter, the gate electrode 65 is formed by patterning the polycrystalline silicon film using known photolithography and dry etching.

  Subsequently, as shown in FIG. 7I, an interlayer insulating film 67 and a source electrode 69 are formed.

  The interlayer insulating film 67 is formed by depositing an insulating material such as silicon oxide on the oxide film 61 and the gate electrode 65 by plasma CVD, for example. The thickness of the interlayer insulating film 67 is, for example, about 1 μm.

  The source electrode 69 is formed inside a contact hole provided in the interlayer insulating film 67 and forms an ohmic junction with a part of the N-type source region 53 and the P-type contact region 55. Such a source electrode 69 is formed as follows, for example. First, a contact hole reaching a part of the N-type source region 53 and the P-type contact region 55 is formed in the interlayer insulating film 67 by using known photolithography and dry etching. Subsequently, after depositing nickel (thickness: 100 nm, for example) inside the contact hole and on the interlayer insulating film 67, RTA (Rapid Thermal Annealing) is performed at a temperature of 600 ° C. to carbonize the nickel deposited inside the contact hole. React with silicon. Thereby, the source electrode 69 is obtained. Next, unreacted nickel deposited on the interlayer insulating film 67 is removed by wet etching. Thereafter, by applying RTA for 2 minutes at a temperature of 1000 ° C., good ohmic characteristics can be obtained between the source electrode 69 and the N-type source region 53 and the P-type contact region 55.

  Next, as shown in FIG. 7J, an electrode pad 71 electrically connected to the source electrode 69 is provided. The electrode pad 71 forms a conductive film (thickness: for example, 3 μm) by depositing a conductive material such as aluminum inside the contact hole of the interlayer insulating film 67 and on the interlayer insulating film 67 by, for example, EB vapor deposition. It can be formed by patterning this conductive film using photolithography technique and etching technique.

  Thereafter, as shown in FIG. 7 (k), a drain electrode 73 in contact with the high-concentration impurity layer 3 is formed on the back surface side of the bulk substrate 1. In this way, the semiconductor element 900 is obtained.

  The drain electrode 73 can be formed by the following method, for example. First, the oxide film 63 formed on the back surface side of the bulk substrate 1 is removed to expose the high concentration impurity layer 3. The oxide film 63 can be removed by performing wet etching for 30 minutes using buffered hydrofluoric acid. For example, nickel (thickness: about 100 nm) is deposited on the high-concentration impurity layer 3 exposed by etching by EB vapor deposition. Thereafter, in order to obtain good ohmic characteristics, annealing is performed for about 2 minutes at a temperature of about 1000 ° C. in an inert atmosphere such as argon as necessary to obtain the drain electrode 73. When the annealing is performed, the high-concentration impurity layer 3 having a thickness (100 nm) comparable to the deposited nickel is consumed.

  In the semiconductor element 900 obtained by the above method, the drain electrode 73 is electrically connected to the bulk substrate 1 through the high concentration impurity layer 3. Therefore, the contact resistance can be reduced as compared with the conventional configuration in which the drain electrode 73 and the back surface of the bulk substrate 1 are in contact with each other.

  According to the present embodiment, since the high concentration impurity layer 3 is formed by epitaxial growth, the thickness of the high concentration impurity layer 3 can be easily controlled by adjusting the growth time. Therefore, there is an advantage that a high-concentration impurity layer 3 having a sufficient thickness can be formed according to a thermal oxidation process or an electrode formation process performed when manufacturing the MOSFET. In the above method, the thickness of the high-concentration impurity layer 3 consumed by the two thermal oxidation processes (first and second thermal oxidation processes) is at least about 700 nm (for example, 800 nm). Therefore, the thickness of the high concentration impurity layer 3 formed by epitaxial growth is preferably at least 700 nm or more. When PDA is performed when forming the drain electrode 73, the high-concentration impurity layer 3 is further consumed. Therefore, the thickness of the high-concentration impurity layer 3 formed by epitaxial growth is preferably 900 nm or more, for example. . More preferably, it is 1 micrometer or more, More preferably, it is 1.1 micrometers or more. Thereby, the on-resistance between the drain electrode 73 and the bulk substrate 1 can be reduced more reliably.

  Further, the impurity concentration profile of the high concentration impurity layer 3 formed by epitaxial growth is substantially uniform in the depth direction. Therefore, even if the reduction amount of the high concentration impurity layer 3 in the process of forming the semiconductor element 900 varies, the impurity concentration in the vicinity of the surface in contact with the drain electrode 73 in the high concentration impurity layer 3 of the obtained semiconductor element 900 is constant. . Accordingly, variation in on-resistance between products can be suppressed, and reliability can be improved.

  The manufacturing method of the present embodiment is not limited to the method described with reference to FIGS. In the above method, the Si surface of the bulk substrate 1 is used as the main surface, but the C surface may be used as the main surface. Further, as described with reference to FIG. 3B, after the high-concentration impurity layer 3 is formed on the surface 1r of the bulk substrate 1, the surface 1p of the bulk substrate 1 may be planarized, As described with reference to FIG. 4B, the high-concentration impurity layer 3 may be formed on the surface 1r of the bulk substrate 1 in a state where the protective film is formed on the surface 1p of the bulk substrate 1. Thereby, since a high quality epitaxial layer (active layer) 5 can be formed on the surface 1p of the bulk substrate 1, device characteristics can be improved.

  According to the present invention, in a semiconductor element provided with a SiC bulk substrate, the contact resistance of an electrode provided on the back side of the SiC bulk substrate can be reduced, so that the power loss can be kept small. Further, according to the present invention, the semiconductor element as described above can be manufactured by a simple process suitable for mass production.

  The present invention can be widely applied to vertical semiconductor elements such as vertical PN diodes, vertical Schottky diodes, and vertical MOSFETs formed using a SiC bulk substrate, and devices including such semiconductor elements.

(A) And (b) is a cross-sectional schematic diagram which respectively shows the semiconductor substrate of 1st Embodiment by this invention. (A)-(c) is process sectional drawing for demonstrating the method to manufacture the semiconductor substrate of 1st Embodiment by this invention. (A)-(c) is process sectional drawing for demonstrating the other method of manufacturing the semiconductor substrate of 1st Embodiment by this invention. (A)-(d) is process sectional drawing for demonstrating the further another method of manufacturing the semiconductor substrate of 1st Embodiment by this invention. (A)-(k) is process sectional drawing for demonstrating the method to manufacture the semiconductor element of 2nd Embodiment by this invention. (A)-(j) is process sectional drawing for demonstrating the method to manufacture the semiconductor element of 3rd Embodiment by this invention. (A)-(k) is process sectional drawing for demonstrating the method to manufacture the semiconductor element of the 4th Embodiment by this invention. (A) And (b) is sectional process drawing for demonstrating the manufacturing method of the conventional semiconductor substrate. It is a graph showing the relationship between the ion energy and implantation depth at the time of implanting nitrogen or phosphorus ions into a silicon carbide bulk substrate. It is a graph which shows the density | concentration profile of the nitrogen ion in the depth direction of a silicon carbide layer when nitrogen ion is inject | poured with respect to the silicon carbide layer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Bulk substrate 1r, 1p Bulk substrate surface 3 High-concentration impurity layer 4 Protective film 5 Epitaxial layer 7, 52 P-type well region 9, 51 Field limiting ring 11, 55 P-type contact region 13, 15, 17, 19, 33, 35, 37, 39, 57, 59, 61, 63 Oxide film 21 Ohmic electrode 23, 41 Back electrode 25, 45, 67 Interlayer insulating film 27, 47, 71 Electrode pad 31 Guard ring 43 Schottky electrode 53 Source region 65 Gate electrode 69 Source electrode 73 Drain electrode 100, 100 ′, 200, 300, 400, 500, 600 Semiconductor substrate 700, 800, 900 Semiconductor element

Claims (23)

A first conductivity type silicon carbide bulk substrate having a main surface and a back surface;
A semiconductor device comprising: a first conductivity type high concentration impurity epitaxial layer formed on a back surface of the silicon carbide bulk substrate and containing impurities at a higher concentration than the silicon carbide bulk substrate.   2. The semiconductor device according to claim 1, further comprising a first-conductivity-type low-concentration impurity epitaxial layer formed on a main surface of the silicon carbide bulk substrate and containing impurities at a lower concentration than the silicon carbide bulk substrate. An upper electrode provided on a main surface of the silicon carbide bulk substrate;
The semiconductor element according to claim 1, further comprising: a lower electrode electrically connected to the silicon carbide bulk substrate through the high-concentration impurity epitaxial layer. 4. The semiconductor element according to claim 1, wherein an impurity concentration in the high-concentration impurity epitaxial layer is 1 × 10 ¹⁹ cm ⁻³ or more.   The semiconductor element according to claim 1, wherein an impurity concentration in the high-concentration impurity epitaxial layer is substantially constant in a depth direction.   The semiconductor element according to claim 1, wherein a back surface of the silicon carbide bulk substrate is a carbon surface.   The semiconductor element according to claim 1, wherein a back surface of the silicon carbide bulk substrate is a silicon surface.   The semiconductor element according to claim 1, wherein the semiconductor element is a vertical MOSFET.   The semiconductor element according to claim 1, wherein the semiconductor element is a vertical PN diode.   The semiconductor device according to claim 1, wherein the semiconductor device is a vertical Schottky diode. A silicon carbide bulk substrate of a first conductivity type;
A semiconductor substrate comprising: a first conductivity type high concentration impurity epitaxial layer formed on a first surface of the silicon carbide bulk substrate and containing impurities at a higher concentration than the silicon carbide bulk substrate.   The semiconductor according to claim 11, further comprising a low-concentration impurity epitaxial layer provided on a second surface opposite to the first surface in the silicon carbide bulk substrate and containing impurities at a lower concentration than the silicon carbide bulk substrate. substrate.   The semiconductor substrate according to claim 11 or 12, wherein a thickness of the high-concentration impurity epitaxial layer is 300 nm or more. The semiconductor substrate according to claim 11, wherein an impurity concentration in the high-concentration impurity epitaxial layer is 1 × 10 ¹⁹ cm ⁻³ or more.   The semiconductor substrate according to claim 11, wherein an impurity concentration in the high-concentration impurity epitaxial layer is substantially constant in a depth direction.   The semiconductor substrate according to claim 11, wherein the first surface of the silicon carbide bulk substrate is a carbon surface.   The semiconductor substrate according to claim 11, wherein the first surface of the silicon carbide bulk substrate is a silicon surface. A method of manufacturing a semiconductor device comprising a silicon carbide bulk substrate of a first conductivity type having a main surface and a back surface,
(A) A first conductivity type low-concentration impurity epitaxial layer containing impurities at a lower concentration than the silicon carbide bulk substrate is formed on the main surface, and the first conductivity type contains impurities at a higher concentration than the silicon carbide bulk substrate. Preparing a silicon carbide bulk substrate having a conductive type high-concentration impurity epitaxial layer formed on the back surface;
(B) forming an electrode in contact with the high-concentration impurity epitaxial layer on the back surface of the silicon carbide bulk substrate. The step (a)
(A1) forming the high-concentration impurity epitaxial layer on the back surface of the silicon carbide bulk substrate;
The method for manufacturing a semiconductor device according to claim 18, further comprising: (a2) forming the low-concentration impurity epitaxial layer on a main surface of the silicon carbide bulk substrate.   The method for manufacturing a semiconductor device according to claim 19, wherein the step (a2) is performed after the step (a1).   The step (a) includes a step of forming a protective film on the main surface of the silicon carbide bulk substrate before the step (a1), and between the step (a1) and the step (a2). 21. The method of manufacturing a semiconductor element according to claim 20, further comprising a step of removing the protective film from the silicon carbide bulk substrate.   21. The method of manufacturing a semiconductor element according to claim 20, wherein the step (a) further includes a step of planarizing a main surface of the silicon carbide bulk substrate between the step (a1) and the step (a2). . A method of manufacturing a semiconductor substrate, comprising: forming a first conductivity type high concentration impurity epitaxial layer containing impurities at a higher concentration than the silicon carbide bulk substrate on a first surface of the first conductivity type silicon carbide bulk substrate. .

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