JP2008091013A - Non-volatile memory device including local control gate on a plurality of isolated well regions and related method and system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a byte-variable type non-volatile memory device and a system having a high cell array efficiency. <P>SOLUTION: A non-volatile integrated circuit memory device includes a semiconductor substrate having first and second electrically isolated wells of the same conductivity type. A first plurality of non-volatile memory cell transistors are mounted on the first well, and a second plurality of non-volatile memory cell transistors are mounted on the second well. A local control gate line is electrically coupled with the first and second pluralities of non-volatile memory cell transistors, and a group selection transistor is electrically coupled between the local control gate line and a global control gate line. More particularly, the group selection transistor is configured to electrically couple and decouple the local control gate line and the global control gate line in response to a group selection gate signal applied to a gate of the group selection transistor. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to electronic memory devices, and more particularly to non-volatile memory devices and related systems and methods.

  Advanced EEPROM technology is used to implement system-on-chip (SOC) functionality. SOC technology requires an EEPROM that operates with high operating performance, fast access, low voltage and low power with an advanced CMOS process. Typically, non-volatile memory includes flash memory for code storage and EEPROM for data storage. EEPROM requires very high durability and byte variability to the extent that more than a million erase / program operations are performed.

  Generally, the byte variable EEPROM is based on a floating gate tunnel oxide (FLOTOX) cell, and uses FN (Fowler Nordheim) tunneling for both write and erase operations. Each cell includes a tunneling region, a high voltage (HV) select transistor, and a separate high voltage select transistor on the drain side. FLOTOX memory provides low power operation and high durability, but has a relatively large cell size.

The memory structure is described in “Device Architecture And Reliability Aspects of A Novel 1.22 um ² EEPROM Cell In 0.18 um Node For Embedded Applications (Micro 72)” by Tao. And is included as a reference for the present invention. The EEPROM structure published by Tao improves scalability while providing characteristics such as byte variability, high durability, and low power operation. More specifically, the EEPROM structure published by Tao is based on a 2T-FN-NOR cell.

  Other memory structures are discussed in Imamiya's US Pat. No. 5,099,059 “Nonvolatile Semiconductor Memory Device” and are included as a reference to the present invention. According to the content discussed in the Imamiya patent, a non-volatile semiconductor device includes a memory cell array (eg, a NAND memory cell), a row decoder for selecting and operating a word line, and a memory selected via a bit line. It includes a sense amplifier / latch circuit for exchanging data with the cell. The memory cell array is divided into blocks in the word line direction. Each block is formed in a well formed individually in the semiconductor substrate. Each word line operated by the row decoder is continuously controlled by a control transistor formed in a boundary region between blocks. Turning off the control transistor allows data to be erased simultaneously in blocks.

Despite the memory structures described above, there is always a need for improved memory structures and methods.
US registered patent No. US6031763 specification

  The present invention has been made in view of the above-described problems, and an object thereof is to provide a byte variable nonvolatile memory device and system having high cell array efficiency.

  Another object of the present invention is to provide a memory cell array structure capable of reducing the chip size, and a memory device and system including the memory cell array.

  To achieve the above object, an electronic system according to the present invention includes a semiconductor substrate including electrically isolated first and second wells having the same conductivity, and a plurality of first nonvolatiles on the first well. A plurality of second nonvolatile memory cell transistors on the second well, a local control gate line electrically connected to the plurality of first and second nonvolatile memory cell transistors, A group selection transistor electrically connected between a local gate line and a global control gate line, wherein the group selection transistor is responsive to a group selection gate signal applied to a gate of the group selection transistor. Local control gate line and global control gate line It is set so as to electrically interrupt the.

  In some embodiments, the electrically isolated first and second wells have a first conductivity, and the semiconductor substrate includes a well having a second conductivity different from the first conductivity, A group select transistor is on the well having the second conductivity. The electrically isolated first and second wells having the same conductivity include electrically isolated first and second p-type wells, and the second conductivity well is n. The group selection transistor includes a PMOS well selection transistor.

  As an embodiment, the well having the second conductivity is between the electrically isolated first and second wells having the first conductivity, and the first having the first conductivity. The well is between the well having the second conductivity and the second well having the first conductivity.

  In one embodiment, the electrically isolated first and second wells include electrically isolated first and second p-type wells. The electronic system according to the present invention further includes a controller connected to the first and second wells having the first conductivity, connected to the global control gate line, and connected to a gate of the group selection transistor. The controller simultaneously applies different first and second electrical biases to the electrically isolated first and second wells having the first conductivity, and the electrically separated first and second wells. And applying a turn-on signal to the gate of the group selection transistor while applying the first and second electrical biases to the second well, and passing the local control gate line and the plurality of the plurality of the plurality of wells through the group selection transistor. The first and second memory cell transistors are transmitted from the global control gate line. By applying the same control signal, the programmed state of the plurality of first memory cell transistors is erased while maintaining the programmed state of the plurality of second memory cell transistors. The The controller receives address information from an input / output bus during a read operation, and at least one of the plurality of first and / or second nonvolatile memory cell transistors according to the address information during the read operation. Data transmitted from one is set to be provided to the input / output bus. The electronic system according to the present invention further includes a processor coupled to the input / output bus, the processor generating the address information during the read operation, and the address information via the input / output bus. The data is provided to the controller, and the data is transmitted from the controller via the input / output bus.

  In one embodiment, the controller receives address information and data from the input / output bus during a write operation, and includes a plurality of first and / or second nonvolatile memory cell transistors specified by the address information. The electronic system according to the present invention further includes a processor coupled to the input / output bus, and the processor is configured to write the address information during the write operation. And generating the data, and providing the address information and the data to the controller via the input / output bus. The plurality of first nonvolatile memory cell transistors include eight nonvolatile memory cell transistors, the plurality of second nonvolatile memory cell transistors include eight nonvolatile memory cell transistors, and the group selection transistor Includes a byte select transistor.

  The non-volatile integrated circuit memory device according to the present invention includes a plurality of first and second non-volatile memory cell transistors respectively formed on electrically isolated first and second wells having the same conductivity. The method of operating comprises: applying different first and second electrical biases to electrically isolated first and second wells having the same conductivity; and the electrically isolated first and second wells. By applying the same control gate signal to the plurality of first and second memory cell transistors while applying the first and second electrical biases to the second well, the plurality of second memory cell transistors Erasing the programmed state of the plurality of first memory cell transistors while maintaining the programmed state.

  As an embodiment, the electrically isolated first and second wells include electrically isolated first and second p-type wells, and the operation method according to the present invention further includes a read operation. A step of transmitting address information from an input / output bus; and, in the read operation, data input from the plurality of first and / or second nonvolatile memory cell transistors according to the address information Providing to the bus before transmitting the address information from the input / output bus, and transmitting the address information transmitted from a processor to the input / output bus. And after the data is provided to the bus, the data is transmitted from the input / output bus during the read operation.

  As an embodiment, an operation method according to the present invention includes a step of transmitting address information and data from an input / output bus during a write operation, and the plurality of first and / or second nonvolatiles specified by the address information. Writing the data to at least one of the memory cell transistors, and the address information and the data transmitted from the input / output bus before the address information and the data are transmitted from the processor. The method further includes transmitting information and the data to the input / output bus. The plurality of first memory cell transistors include eight nonvolatile memory cell transistors, the plurality of second memory cell transistors include eight nonvolatile memory cell transistors, and the group selection transistor includes a byte selection transistor. Includes a select transistor.

  According to another aspect of the present invention, there is provided an electronic system including a semiconductor substrate including electrically isolated first and second wells having the same conductivity, and respective nonvolatile memory cells on the first well. A plurality of first non-volatile memory cells including non-volatile memory cell transistors coupled in series between word select and sector select transistors, and each word select and each non-volatile memory cell on the second well A plurality of second non-volatile memory cells including non-volatile memory cell transistors connected in series between the sector selection transistors, and a plurality of first bits connected to the respective sector selection transistors of the plurality of first memory cells. A plurality of second bits coupled to a line and a sector select transistor of each of the plurality of second memory cells. A line, a local control gate line electrically connected to the plurality of first and second memory cell transistors, and a signal applied to the gate connected between the local control gate line and the global control gate line. And a group selection transistor configured to electrically connect the local control gate line and the global control gate line, and the word selection and sector selection transistors of the plurality of first and second nonvolatile memory cells. A row decoder connected to the global control gate line, and the first and second wells electrically separated from each other, the plurality of first and second bit lines, and the group selection gate line. A column decoder, And a controller coupled to the column decoder, wherein the controller causes the column decoder to apply a different electrical bias to the first and second wells and to program the plurality of second memory cell transistors. The group selection is performed while the different electrical bias is applied to the first and second wells so as to erase the programmed state of the plurality of first memory cell transistors while maintaining the selected state. A transistor is set to provide the same control gate signal transmitted from the global control gate line to the nonvolatile memory cell transistors of the plurality of first and second nonvolatile memory cells through the local gate line. The

  In some embodiments, the electrically isolated first and second wells have a first conductivity, and the semiconductor substrate includes a well having a second conductivity different from the first conductivity, The group selection transistor is on the well having the second conductivity, and the electrically isolated first and second wells having the same conductivity are electrically isolated first and second p-types. The well having the second conductivity includes an n-type well, and the group selection transistor includes a PMOS group selection transistor. The well having the second conductivity is between the electrically isolated first and second wells having the first conductivity, and the first well having the first conductivity is the It is formed between the well having the second conductivity and the second well having the first conductivity.

  In one embodiment, the electrically isolated first and second wells include electrically isolated first and second p-type wells, and the plurality of first nonvolatile memory cell transistors includes eight A non-volatile memory cell transistor, wherein the plurality of second non-volatile memory cell transistors includes eight non-volatile memory cell transistors, the group selection transistor includes a byte selection transistor, and the controller performs a read operation. Address information is transmitted from the input / output bus to the input / output bus, and data transmitted from the first and / or second nonvolatile memory cell transistors is provided to the input / output bus according to the address information during the read operation. The electronic system according to the present invention is configured to generate the address information and the input / output bus Providing the address information to the controller via, during the read operation, further comprising a processor that is configured so as to transmit the data via the output bus from said controller.

  In one embodiment, the controller receives address information and data from the input / output bus during a write operation, and includes a plurality of first and / or second nonvolatile memory cell transistors specified by the address information. The electronic system according to the present invention is connected to the input / output bus, generates the address information and the data during the write operation, and is configured to write the data to at least one of the input / output bus. And further includes a processor configured to provide the address information and the data to the controller via the controller.

  The electronic system according to the present invention includes a plurality of first and second nonvolatile memory cell transistors, a local control gate line electrically connected to the plurality of first and second nonvolatile memory cell transistors, A controller coupled to the local control gate line, wherein the controller maintains the programmed state of the plurality of second non-volatile memory cell transistors during the erase operation. The programmed state of the plurality of first nonvolatile memory cell transistors connected is set to be erased.

  As an embodiment, the electronic system according to the present invention further includes a semiconductor substrate including electrically isolated first and second wells having the same conductivity, and the plurality of first nonvolatile memory cell transistors includes the first nonvolatile memory cell transistor. The plurality of second nonvolatile memory cell transistors are on the first well, and the plurality of second nonvolatile memory cell transistors are on the second well. The electronic system according to the present invention simultaneously applies different first and second electrical biases to the first and second wells having the first conductivity and being electrically separated during the erase operation. Set to do.

  In one embodiment, the electrically isolated first and second wells include electrically isolated first and second p-type wells, and the plurality of first nonvolatile memory cell transistors includes eight nonvolatile memory cells. The plurality of second nonvolatile memory cell transistors include eight nonvolatile memory cell transistors, and the group selection transistor includes a byte selection transistor.

  According to the present invention, the cell array efficiency of the nonvolatile memory device can be improved and the chip size can be reduced.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the invention can be implemented in numerous other forms and should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the layer and region sizes and relative sizes are emphasized for clarity. The same reference numbers indicate the same components.

  A nonvolatile memory device 100 according to the present embodiment shown in FIG. 1 includes a memory cell array 10, a row decoder 30, a column decoder 40, a data input / output circuit 50, an input / output buffer 60, a controller 70, and a voltage generator 80. Row address X-ADD and column address Y-ADD for read, write, and / or erase operations are provided from controller 70 to row decoder 30 and column decoder 40. The voltage generator 80 generates different voltage levels used for read, write and erase operations.

  The input / output circuit 50 includes a write driver 52 and a sense amplifier 54. The write driver 52 performs write and erase operations on the memory cell selected by the row address X-ADD and the column address Y-ADD under the control of the controller 70. The sense amplifier 54 performs a read operation on the memory cell selected by the row address X-ADD and the column address Y-ADD.

  For example, during a read operation, a memory address including a row address X-ADD and a column address Y-ADD and designating a memory cell to be read is transmitted from the input / output bus to the input / output buffer 60 and provided to the controller 70. . The controller 70 provides the row address X-ADD to the row decoder 30 and the column address Y-ADD to the column decoder 40 so that the appropriate voltage level transmitted from the voltage generator 80 is provided to the memory cell array 10. . The sense amplifier 54 reads data stored in the memory cell designated by the address, and the read data is provided from the sense amplifier 54 to the input / output buffer 60 and from the input / output buffer 60 to the input / output bus.

  During a write operation, a memory address including a row address X-ADD and a column address Y-ADD and specifying a memory cell into which data is written is transmitted from the input / output bus to the input / output buffer 60 and provided to the controller 70. The Data to be written is also transmitted from the input / output bus to the input / output buffer 60 and provided to the write driver 52. The controller 70 provides the row address X-ADD to the row decoder 30 and the column address Y-ADD to the column decoder 40 so that the appropriate voltage level transmitted from the voltage generator 80 is provided to the memory cell array 10. . The write driver 52 writes data to the designated memory cell.

  During the erase operation, the memory address including the row address X-ADD and the column address Y-ADD and specifying the memory cell from which data is erased is transmitted from the input / output bus to the input / output buffer 60 and provided to the controller 70. Is done. The controller 70 sends the row address X-ADD to the row decoder 30, and the appropriate voltage level transmitted from the voltage generator 80 is transmitted to the memory cell array 10 to erase the memory cell specified by the address. A column address Y-ADD is provided to the column decoder 40.

  The nonvolatile memory device 100 of FIG. 1 can be used as the nonvolatile memory device 100 (for example, a nonvolatile flash memory device) in the electronic system 500 of the present embodiment illustrated in FIG. More specifically, the electronic system 500 includes an input / output bus 501 electrically connected to the input / output buffer 60 of the nonvolatile memory device 100 of FIG. The electronic system 500 also includes an encryption circuit 510, a logic circuit 520, a digital signal processor (DSP) 530, a main processor 540, an SRAM 550, and / or an input / output circuit 590. For example, the nonvolatile memory device 100 performs a read, write, and / or erase operation according to an instruction / address transmitted from the main processor 540 via the input / output bus 501.

  Although the components of the electronic system 500 are illustrated in FIG. 2 as an embodiment, not all the components of FIG. 2 are required by all embodiments of the present invention, but are illustrated in FIG. None of the components can be included. For example, the electronic system 500 may be a wireless communication device such as a wireless telephone, a wireless PDA, or a wireless pocket computer. The nonvolatile memory device 100 can be used to store operation codes, recognition information, serial numbers, contact information (eg, name, address, telephone number, email address, etc.), profile information, and the like. . Thus, the RF circuit 580 can provide wireless communication according to a long-range communication standard (cellular radiotelephone standard), a short-range communication standard (Bluetooth standard), and / or a Wi-Fi standard. In a wireless communication device, the individual input / output circuit 590 may be omitted, or wired or otherwise coupled to another computer device (eg, a personal / laptop computer for data transmission). be able to.

  According to another embodiment of the present invention, the electronic system 500 may be a flash memory card system controlled by an external host directly connected to the input / output bus 501. For example, the input / output bus 501 is integrated with a connector that provides a removable physical connection with an external host such as a digital camera, digital video recorder / player, digital audio recorder / player, wireless telephone, and the like. In the flash memory card system, the non-volatile memory device 100 of the electronic system 500 includes a digital photograph, digital video, digital audio, wireless telephone data (eg, wireless telephone recognition information, serial number, contact information, PDA, pocket computer, etc.), It is configured to store operation codes, profile information, and the like. In this case, since the electronic system 500 is controlled by an external host electrically and physically connected to the input / output bus 501, the configuration such as the RF circuit 580, the input / output circuit 590, and / or the main processor 540 is omitted. To do.

  As described above, the nonvolatile memory device 100 of FIG. 1 includes the controller 70 separated from the row decoder 30, the column decoder 40, the data input / output circuit 50, the input / output buffer 60, and / or the voltage generator 80. Defined. However, the controller 70 is defined to include one or more components of the row decoder 30, the column decoder 40, the data input / output circuit 50, the input / output buffer 60, and / or the voltage generator 80. Can do. For example, the controller 70 can be defined to include a row decoder 30, a column decoder 40, a data input / output circuit 50, an input / output buffer 60, and a voltage generator 80. A cell array according to various embodiments of the present invention will be described in detail with reference to FIGS. 3A, 3B, and 5A to 6B.

  3A is a circuit diagram showing a memory cell array 10a according to an embodiment of the present invention, and FIG. 3B is a sectional view taken along the section line AB of the memory cell array of FIG. 3A. As shown in FIGS. 3A and 3B, the memory cell array 10 a of the nonvolatile integrated circuit includes first and second p-type wells 11 and 12 that are electrically separated by a high-voltage n-type well 15. The nonvolatile memory cell transistor T1 is formed on the p-type wells 11 and 12 together with the word line selection transistor T2, and the byte selection transistor T3 is formed on the high-voltage n-type well 15. Electrical isolation is provided by forming p-type wells 11, 12 in n-type well BNW. The gates of the sector selection transistors T4 on the p-type well are connected to sector selection gate lines SSG1 and SSG2, respectively. The area of the quadrangle 17 illustrated by the dotted line in FIG. 3B corresponds to the dark area shaded by the section line AB in FIG. 3A.

  As shown in FIG. 3A, 8 bytes of the nonvolatile memory cell transistor T1 and each word line select transistor T2 are formed in the p-type wells 11 and 12, respectively. The control gate of each nonvolatile memory cell transistor T1 of the same byte of the nonvolatile memory cell transistor T1 is connected to the same local control gate line LCG, and each of the nonvolatile memory cell transistors T1 in the same p-type well. Are connected to different local control gate lines LCG. However, each local control gate line LCG is connected to a byte of nonvolatile memory cell transistor T1 in at least two different p-type wells. The gate of each word selection transistor T2 in one row is connected to each word line WL1, WL2, WL3, or WL4, and the gate of each byte selection transistor T3 is connected to each byte selection gate line BSG. The gates of the sector selection transistors T4 are connected to the sector selection gate lines SSG1 or SSG2. Each word select transistor T2 is electrically connected between the nonvolatile memory cell transistor T1 and each common source line CS1, CS2, CS3, or CS4. Each sector selection transistor T4 is connected to one of the common source / drain and bit lines L_BL1 to L_BL16 and R_BL1 to R_BL16 of adjacent memory cell transistors T1 located in different rows of the same sector.

  The connection between the byte of the non-volatile memory cell transistor T1 in the different p-type wells 11, 12 and one identical local control gate line LCG is illustrated in detail in the cross-sectional view of FIG. 3B. The first bytes of the nonvolatile memory cell transistors T1a to T1h are formed on the p-type well 11, and the second bytes of the nonvolatile memory cell transistors T1i to T1p are formed on the p-type well 12. , 12 are electrically isolated. The same local control gate line LCG12 is provided to all the nonvolatile memory cell transistors T1a to T1h and T1i to T1p, and the local control gate line LCG12 is connected to the global control gate line GCG1 via the respective byte selection transistors T3. Connected to Other bytes of the nonvolatile memory cell transistor on the p-type well 11 are connected to a separate local control gate line LCG11 separated from the local control gate line LCG12, and other bytes of the nonvolatile memory cell transistor on the p-type well 12 are connected. Are connected to a separate local control gate line LCG13 separated from the local control gate line LCG12. Although not shown in FIGS. 3A and 3B, the local control gate lines LCG11 to LCG13 are connected to the same global control gate line GCG1 using byte selection transistors that are individually controlled. Accordingly, one or more local control gate lines LCG11 to LCG13 are connected to the global control gate line GCG1 while the connection between the other local control gate lines LCG11 to LCG13 and the global control gate line GCG1 is cut off. be able to.

According to the embodiment of the present invention shown in FIG. 3A, one byte (for example, eight transistors) of nonvolatile memory cell transistors in the same p-type well is connected to the local control gate line. However, according to other embodiments of the present invention, other numbers of non-volatile memory cell transistors can be connected to the local control gate line. For example, each local control gate line can be coupled to 4, 6, or 32 non-volatile memory cell transistor groups in the same p-type well. Although not all the components of the nonvolatile memory cell transistor T1 are separately displayed, each nonvolatile memory cell transistor T1 has a tunnel insulating layer (for example, a tunnel oxide layer) on the channel region of the p-type well. A floating gate (eg, a floating polysilicon gate) and / or a charge trap layer (eg, a silicon nitride layer) on the tunnel insulating layer, an insulating layer on the floating gate / charge trap layer, and a respective control gate on the insulating layer including. The structure of the non-volatile memory cell transistor is described in “Device Architecture And Reliability Aspects of A Novel 1.22 um ² EEPROM Cell In 0.18 um Node For Embedded Applications (Micro41)” published by Tao. ) "And is included as a reference to the present invention.

  The memory cell array 10a shown in FIGS. 3A and 3B can be used as the memory cell array 10 shown in FIG. When the memory cell array 10a of FIGS. 3A and 3B is used as the memory cell array 10 of FIG. 1, the word lines WL1 to WL4, the common source lines CS1 to CS4, the sector selection gate lines SSG1 and SSG2, and the global control gate lines GCG1 to GCG1. Each GCG 4 is coupled to and / or controlled by a row decoder 30. The biases of the byte selection gate line BSG, the bit lines L_BL1 to L_BL16, R_BL1 to R_BL16, and the p-type wells 11 and 12 are connected to the column decoder 40 and / or controlled by the column decoder 40, respectively. The bias of the n-type well BNW is directly connected to the voltage generator 80. FIG. 4 is a table showing signals used for write, erase, and read operations according to an embodiment of the present invention. Hereinafter, the write, erase and read operations for the memory cell array 10a used in the memory device 100 of FIG. 1 will be described in detail with reference to the table of FIG.

  As an embodiment, a write operation for the memory cell transistors T1a to T1h in the p-type well 11 and connected to the local control gate line LCG12 will be described with reference to the write signal in FIG. At the start of the write operation, address information including the row address X-ADD and the column address Y-ADD and data to be written are transmitted to the input / output buffer 60. The address information is provided to the controller 70, which provides the row address X-ADD to the row decoder 30 and the column address Y-ADD to the column decoder 40. The data to be written is provided to the write driver 52.

  As shown in FIG. 4, the row decoder 30 includes common source lines CS1 to CS4 (see CS in FIG. 4), word lines selected and non-selected by the row address X-ADD from the write signal transmitted from the voltage generator 80, This is transmitted to lines WL1 to WL4 (see WL in FIG. 4), sector selection gate lines SSG1 and SSG2 (see SSG in FIG. 4), and global control gate lines GCG1 to GCG4 (see CG in FIG. 4). As shown in FIG. 4, the column decoder 40 and the write driver 52 are bit lines L_BL1 to L_BL16, R_BL1 to R_BL16 (FIG. 4) in which the write signal transmitted from the voltage generator 80 is selected and deselected by the column address Y-ADD. 4 BL), byte select gate line BSG, and p-type wells 11 and 12 (see I-PW in FIG. 4). The voltage generator 80 directly applies an appropriate bias to the n-type well BNW.

  When writing data to the memory cell transistors T1a to T1h, the row decoder 30 applies “10V” to the selected global control gate line GCG1 and “0V” to the unselected global control gate lines GCG2 to GCG4. Then, “1V” is applied to the selected sector selection gate line SSG1, and “−5V” is applied to the unselected sector selection gate line SSG2. The column decoder 40 applies “0V” to the unselected bit lines L_BL1 to L_BL8 and R_BL1 to R_BL16, and applies “0V” to the unselected byte selection gate line BSG between the p-type wells 11 and 12. Then, “10V” is applied to the selected byte selection gate line on the left side of the p-type well 11 and the right side of the p-type well 12, and “−5V” is applied to the selected p-type well 11 and the non-selected state is selected. “0 V” is applied to the p-type well 12. The column decoder 40 applies “−5V” or “0V” to the bit lines L_BL9 to L_BL16 selected by the data transmitted for writing. Since different bias voltages are provided to the selected p-type well 11 and the non-selected p-type well 12, data is not written to the memory cell transistors T1i to T1p connected to the local control gate line LCG12, Data is written in the memory cell transistors T1a to T1h connected to the control gate line LCG12.

  Although not shown in FIGS. 3A and 3B, the local control gate line LCG11 is connected to the global control gate line GCG1 through the byte selection transistor on the left side of the p-type well 11, and the local control gate line LCG13 is connected to the p-type well 11. It is connected to the global control gate line GCG1 through a byte select transistor on the right side of the mold well 12. The non-selected byte selection transistors connected to the local control gate lines LCG11 and LCG13 operate in accordance with the non-selected byte selection gate lines on the left side of the p-type well 11 and the right side of the p-type well 12, respectively. . By individually controlling the unselected local control gate line LCG11 and the selected local control gate line LCG12 for each byte of memory cell transistors in the same row and the same p-type well 11, local Data is written to the selected bytes of the memory cell transistors T1a to T1h connected to the local control gate line LCG12 without affecting the data of the non-selected bytes of the memory cell transistors connected to the control gate line LCG11. .

  As an embodiment, an operation of erasing data of the memory cell transistors T1a to T1h connected to the local control gate line LCG12 and existing in the p-type well 11 will be described with reference to the erase signal of FIG. At the start of the erase operation, address information including the row address X-ADD and the column address Y-ADD is transmitted to the input / output buffer 60. The address information is provided to the controller 70, which provides the row address X-ADD to the row decoder 30 and the column address Y-ADD to the column decoder 40.

  As shown in FIG. 4, the row decoder 30 includes common source lines CS1 to CS4 (refer to CS in FIG. 4) in which the erase signal transmitted from the voltage generator 80 is selected and non-selected by the row address X-ADD, word This is transmitted to lines WL1 to WL4 (see WL in FIG. 4), sector selection gate lines SSG1 and SSG2 (see SSG in FIG. 4), and global control gate lines GCG1 to GCG4 (see CG in FIG. 4). As shown in FIG. 4, the column decoder 40 and the write driver 52 are bit lines L_BL1 to L_BL16, R_BL1 to R_BL16 (FIG. 4) in which the erase signal transmitted from the voltage generator 80 is selected and deselected by the column address Y-ADD. 4 BL), byte select gate line BSG, and p-type wells 11 and 12 (see I-PW in FIG. 4). The voltage generator 80 directly applies an appropriate bias to the n-type well BNW.

  When erasing the data in the memory cell transistors T1a to T1h, the row decoder 30 sets “−5V” to the selected global control gate line GCG1 and “6V” to the unselected global control gate lines GCG2 to GCG4. Apply. The column decoder 40 sets “−8V” to the selected byte selection gate line BSG between the p-type wells 11 and 12, and the unselected byte selection on the left side of the p-type well 11 and the right side of the p-type well 12. “6V” is applied to the gate line, and 1 “0V” is applied to the selected p-type well 11 and “6V” is applied to the non-selected p-type well 12. By providing different bias voltages to the selected p-type well 11 and the non-selected p-type well 12, data is not erased from the memory cell transistors T1i to T1p connected to the local control gate line LCG12. Data is erased from the memory cell transistors T1a to T1h connected to the local control gate line LCG12.

  As described above, the local control gate line LCG11 is connected to the global control gate line GCG1 through the byte selection transistor on the left side of the p-type well 11, and the local control gate line LCG13 is selected on the right side of the p-type well 12. The transistor is connected to the global control gate line GCG1 through a transistor. The non-selected byte selection transistors connected to the local control gate lines LCG11 and LCG13 operate in accordance with the non-selected byte selection gate lines on the left side of the p-type well 11 and the right side of the p-type well 12, respectively. . By individually controlling the unselected local control gate line LCG11 and the selected local control gate line LCG12 for each byte of memory cell transistors in the same row and the same p-type well 11, local Data is erased from the selected bytes of the memory cell transistors T1a to T1h connected to the local control gate line LCG12 without affecting the data of the non-selected bytes of the memory cell transistors connected to the control gate line LCG11. The

  As an embodiment, an operation of reading data from the memory cell transistors T1a to T1h connected to the local control gate line LCG12 and in the p-type well 11 will be described with reference to the read signal of FIG. At the start of the reading operation, address information including the row address X-ADD and the column address Y-ADD is transmitted to the input / output buffer 60. The address information is provided to the controller 70, which provides the row address X-ADD to the row decoder 30 and the column address Y-ADD to the column decoder 40.

  As shown in FIG. 4, the row decoder 30 includes common source lines CS1 to CS4 (see CS in FIG. 4), word lines selected and non-selected by the row address X-ADD from the read signal transmitted from the voltage generator 80, This is transmitted to lines WL1 to WL4 (see WL in FIG. 4), sector selection gate lines SSG1 and SSG2 (see SSG in FIG. 4), and global control gate lines GCG1 to GCG4 (see CG in FIG. 4). The column decoder includes bit lines L_BL1 to L_BL16, R_BL1 to R_BL16 (see BL in FIG. 4), a byte selection gate line BSG, and a p-type well 11, which are selected and unselected from the read signal transmitted from the voltage generator 80. 12 (see I-PW in FIG. 4). The voltage generator 80 directly applies an appropriate bias to the n-type well BNW.

  When reading data from the memory cell transistors T1a to T1h, the row decoder 30 applies “1V” to the selected global control gate line GCG1 and “0V” to the unselected global control gate lines GCG2 to GCG4. The power supply voltage Vdd is applied to the selected sector selection gate line SSG1, and “0V” is applied to the unselected sector selection gate line SSG2, the power supply voltage Vdd is applied to the selected word line WL1, and the non-selected “0V” is applied to the word lines WL2 to WL4. The column decoder 40 applies “0.5V” to the selected bit lines L_BL9 to L_BL16, and applies “0V” to the unselected bit lines L_BL1 to L_BL8, so that the selected between the p-type wells 11 and 12 is applied. “0V” is applied to the selected byte select gate line BSG, and “1V” is applied to the non-selected byte select gate lines on the left side of the p-type well 11 and the right side of the p-type well 12, and the selected and unselected p “0 V” is applied to the mold wells 11 and 12. In order to read data from the selected memory cell transistors T1a to T1h, the voltages of the selected bit lines L_BL9 to L_BL16 are sensed by the sense amplifier 50, and the read data is provided as an output from the input / output buffer 60.

  FIG. 5A is a circuit diagram showing a memory cell array 10b according to an embodiment of the present invention, and FIG. 5B is a sectional view taken along the section line CD of the memory cell array of FIG. 5A. As shown in FIGS. 5A and 5B, the memory cell array 10b of the nonvolatile integrated circuit includes a semiconductor substrate 203 including p-type wells 211, 212, 221, and 222 that are electrically isolated in an n-type well BNW. The nonvolatile memory cell transistor T1 is formed on the p-type wells 211, 212, 221, and 222 together with the word selection transistor T2, and the byte selection transistors T3 and T5 are formed on the high-voltage n-type well 25. The gates of the sector selection transistors T4 on the p-type wells 211, 212, 221, and 222 are connected to sector selection gate lines SSG1 and SSG2, respectively. The regions of the rectangles 27 and 28 illustrated by the dotted lines in FIG. 5B correspond to the dark regions 27 and 28 shaded by the section line CD in FIG. 5A.

  As shown in FIG. 5A, 4 bytes of the nonvolatile memory cell transistor T1 and each word selection transistor T2 are formed in each p-type well 211, 212, 221, 222. The control gates of the nonvolatile memory cell transistors T1 of the same byte of the nonvolatile memory cell transistor T1 are connected to the same local control gate line LCG, and the nonvolatile memory cell transistors T1 in the same p-type well are connected. Are connected to a different local control gate line LCG. However, each local control gate line LCG is connected to a byte of nonvolatile memory cell transistor T1 in at least two different p-type wells. For example, referring to FIGS. 5A and 5B, the local control gate line LCG11 is connected to the first byte of the memory cell transistor T1 in the p-type well 212 and the second byte of the memory cell transistor T1 in the p-type well 211. The The local control gate line LCG21 is connected to the first byte of the memory cell transistor T1 in the p-type well 221 and the second byte of the memory cell transistor T1 in the p-type well 222.

  The gate of each word selection transistor T2 in one row is connected to the respective word line WL1, WL2, WL3, or WL4, and the gate of each byte selection transistor T3 is connected to the local selection gate line LSG1, and each byte selection. The gate of the transistor T5 is connected to the local selection gate line LSG2, and the gate of each sector selection transistor T4 is connected to the respective sector selection gate line SSG1 or SSG2. Each word select transistor T2 is electrically connected between the nonvolatile memory cell transistor T1 and the respective common source line CS1, CS2, CS3 or CS4. Each sector selection transistor T4 is connected between an adjacent memory cell transistor T1 in a different row of the same sector and one of bit lines BL1a to BL8a, BL1b to BL8b, BL1c to BL8c, BL1d to BL8d. The connection between the different p-type well 211, 212 or the byte of the non-volatile memory cell transistor T1 in the different p-type well 221, 222 and the same local control gate line LCG is illustrated in detail in the cross-sectional view of FIG. 5B. ing. In the electrically isolated p-type wells 211 and 212, the local control gate line LCG11 is connected to the gates of the first bytes of the nonvolatile memory cell transistors T1a ′ to T1h ′ on the p-type well 211 and the p-type well 212. The nonvolatile memory cell transistors T1i ′ to T1p ′ are connected to the gates of the second bytes. Similarly, in the electrically isolated p-type wells 221 and 222, the local control gate line LCG21 is connected to the first byte gate and the p-type well of the nonvolatile memory cell transistors T1a ″ to T1h ″ on the p-type well 221. The non-volatile memory cell transistors T1i ″ to T1p ″ on 222 are connected to the gates of the second bytes. The local control gate line LCG11 is connected to the global control gate line GCG1 via each byte selection transistor T3, and the local control gate line LCG21 is connected to the global control gate line GCG1 via each byte selection transistor T5. Is done. Therefore, while one of the local control gate lines LCG11 and LCG12 is disconnected from the global control gate line GCG1, one of the local control gate lines LCG11 and LCG12 is connected to the global control gate line GCG1. be able to.

According to the embodiment of the present invention shown in FIGS. 5A and 5B, a byte (eg, eight transistors) of a non-volatile memory cell transistor is coupled to a local control gate line. However, according to other embodiments of the present invention, other numbers of memory cell transistors may be coupled to the local control gate line. For example, each local control gate line can be connected to 4, 6, or 32 non-volatile memory cell transistor groups on the same p-type well. Although not all the components of the nonvolatile memory cell transistor T1 are individually displayed, each nonvolatile memory cell transistor T1 has a tunnel insulating layer (for example, a tunnel oxide layer) on the channel region of the respective p-type well. ), A floating gate (eg, a floating polysilicon gate) and / or a charge trap layer (eg, a silicon nitride layer) on the tunnel insulating layer, an insulating layer (eg, a silicon oxide layer) on the floating gate / charge trap layer, and Each control gate on the insulating layer is included. The structure of the non-volatile memory cell transistor is described in “Device Architecture And Reliability Aspects of A Novel 1.22 um ² EEPROM Cell In 0.18 um Node For Embedded Applications” ) And is included as a reference to the present invention.

  The memory cell array 10b shown in FIGS. 5A and 5B can be used as the memory cell array 10 shown in FIG. When the memory cell array 10b of FIGS. 5A and 5B is used as the memory cell array 10 of FIG. 1, the word lines WL1 to WL4, the common source lines CS1 to CS4, the sector selection gate lines SSG1 and SSG2, and the global control gate lines GCG1 to GCG1. Each GCG 4 is coupled to and / or controlled by a row decoder 30. Local selection gate lines LSG1, LSG2, bit lines BL1a to BL8a, BL1b to BL8b, BL1c to BL8c, BL1d to BL8d, and biases PW1 to PW4 of the p-type wells 211, 212, 221, and 222 are connected to the column decoder 40, respectively. And / or controlled by the column decoder 40. The bias BNW of the n-type well 25 is directly connected to the voltage generator 80. The signals of FIG. 4 are used for write, erase, and read operations for a memory device including the memory cell array 10b of FIGS. 5A and 5B according to an embodiment of the present invention. Hereinafter, the write, erase, and read operations for the memory cell array 10b used in the memory device 100 of FIG. 1 will be described in detail with reference to the table of FIG.

  As an embodiment, an operation of writing data to the memory cell transistors T1a 'to T1h' in the p-type well 211 and connected to the local control gate line LCG11 will be described with reference to the write signal in FIG. At the start of the write operation, address information including the row address X-ADD and the column address Y-ADD and data to be written are transmitted to the input / output buffer 60. The address information is provided to the controller 70, which provides the row address X-ADD to the row decoder 30 and the column address Y-ADD to the column decoder 40. The data to be written is provided to the write driver 52.

  As shown in FIG. 4, the row decoder 30 includes common source lines CS1 to CS4 (see CS in FIG. 4), word lines selected and non-selected by the row address X-ADD from the write signal transmitted from the voltage generator 80, This is transmitted to lines WL1 to WL4 (see WL in FIG. 4), sector selection gate lines SSG1 and SSG2 (see SSG in FIG. 4), and global control gate lines GCG1 to GCG4 (see CG in FIG. 4). As shown in FIG. 4, the column decoder 40 and the write driver 52 are bit lines BL1a to BL8a, BL1b to BL8b, and BL1c, which are selected and non-selected by the column address Y-ADD, from the write signal transmitted from the voltage generator 80. ˜BL8c, BL1d˜BL8d (see BL in FIG. 4), local selection gate lines LSG1, LSG2 (see LSG in FIG. 4), and signal lines PW1 to PW4 (see FIG. 4) of the p-type wells 211, 212, 221, 222 I-PW reference). The voltage generator 80 directly applies a suitable BNW bias BNW to the signal line of the n-type well 25.

  When writing data to the memory cell transistors T1a ′ to T1h ′, the row decoder 30 sets “10V” to the selected global control gate line GCG1 and “0V” to the unselected global control gate lines GCG2 to GCG4. Then, “1V” is applied to the selected sector selection gate line SSG1, and “−5V” is applied to the unselected sector selection gate line SSG2. The column decoder 40 applies “0V” to the unselected BL1b to BL8b, BL1c to BL8c, BL1d to BL8d, “0V” to the selected local selection gate line LSG1, and the unselected local selection gate. “10 V” is applied to the line LSG 2, “−5 V” is applied to the selected p-type well 211, and “0 V” is applied to the non-selected p-type wells 212, 221 and 222. Then, the column decoder 40 applies “−5V” or “0V” to the bit lines LBL1a to BL8a selected by the transmitted written data. By applying different bias voltages to the selected p-type well 211 and the non-selected p-type well 212, data is written to the memory cell transistors T1i ′ to T1p ′ connected to the local control gate line LCG11. First, data is written in the memory cell transistors T1a ′ to T1h ′ connected to the local control gate line LCG11.

  As an embodiment, an operation of erasing data of the memory cell transistors T1a 'to T1h' connected to the local control gate line LCG11 and in the p-type well 211 will be described with reference to the erase signal of FIG. At the start of the erase operation, address information including the row address X-ADD and the column address Y-ADD is transmitted to the input / output buffer 60. The address information is provided to the controller 70, which provides the row address X-ADD to the row decoder 30 and the column address Y-ADD to the column decoder 40.

  As shown in FIG. 4, the row decoder 30 includes common source lines CS1 to CS4 (refer to CS in FIG. 4) in which the erase signal transmitted from the voltage generator 80 is selected and non-selected by the row address X-ADD, word This is transmitted to lines WL1 to WL4 (see WL in FIG. 4), sector selection gate lines SSG1 and SSG2 (see SSG in FIG. 4), and global control gate lines GCG1 to GCG4 (see CG in FIG. 4). As shown in FIG. 4, the column decoder 40 and the write driver 52 are bit lines BL1a to BL8a, BL1b to BL8b, and BL1c, which are selected and non-selected by the column address Y-ADD, from the erase signal transmitted from the voltage generator 80. ˜BL8c, BL1d˜BL8d (see BL in FIG. 4), local selection gate lines LSG1, LSG2 (see LSG in FIG. 4), and signal lines PW1 to PW4 connected to the p-type wells 211, 212, 221, 222 ( (See I-PW in FIG. 4). The voltage generator 80 directly applies an appropriate bias BNW to the n-type well 25.

  When erasing the data in the memory cell transistors T1a ′ to T1h ′, the row decoder 30 sets “−5V” to the selected global control gate line GCG1, and “6V to the unselected global control gate lines GCG2 to GCG4. "Is applied. The column decoder 40 applies “−8 V” to the selected local selection gate line LSG 1, applies “6 V” to the unselected local selection gate line LSG 2, and applies “10 V” to the selected p-type well 211. , And “6V” is applied to the non-selected p-type wells 212, 221, 222. By providing different bias voltages to the selected p-type well 211 and the non-selected p-type well 212, data can be erased from the memory cell transistors T1i ′ to T1p ′ connected to the local control gate line LCG11. First, data is erased from the memory cell transistors T1a ′ to T1h ′ connected to the local control gate line LCG11.

  As an embodiment, an operation of reading data from the memory cell transistors T1a ′ to T1h ′ connected to the local control gate line LCG11 and in the p-type well 211 will be described with reference to the read signal of FIG. At the start of the reading operation, address information including the row address X-ADD and the column address Y-ADD is transmitted to the input / output buffer 60. The address information is provided to the controller 70, which provides the row address X-ADD to the row decoder 30 and the column address Y-ADD to the column decoder 40.

  As shown in FIG. 4, the row decoder 30 includes common source lines CS1 to CS4 (see CS in FIG. 4), word lines selected and non-selected by the row address X-ADD from the read signal transmitted from the voltage generator 80, This is transmitted to lines WL1 to WL4 (see WL in FIG. 4), sector selection gate lines SSG1 and SSG2 (see SSG in FIG. 4), and global control gate lines GCG1 to GCG4 (see CG in FIG. 4). As shown in FIG. 4, the column decoder 40 includes bit lines BL1a to BL8a, BL1b to BL8b, BL1c to BL8c, and BL1d in which the read signal transmitted from the voltage generator 80 is selected and deselected by the column address Y-ADD. ˜BL8d (see BL in FIG. 4), local selection gate lines LSG1, LSG2 (see LSG in FIG. 4), and signal lines PW1 to PW4 (I in FIG. 4) connected to the p-type wells 211, 212, 221, 222. -See PW). The voltage generator 80 directly applies an appropriate bias to the n-type well BNW.

  When reading data from the memory cell transistors T1a ′ to T1h ′, the row decoder 30 sets “1V” to the selected global control gate line GCG1 and “0V” to the unselected global control gate lines GCG2 to GCG4. Apply the power supply voltage Vdd to the selected sector selection gate line SSG1, apply "0V" to the unselected sector selection gate line SSG2, apply the power supply voltage Vdd to the selected word line WL1, and unselect “0V” is applied to the word lines WL2 to WL4. The column decoder 40 applies "0.5V" to the selected bit lines BL1a to BL8a, and applies "0V" to the non-selected bit lines BL1b to BL8b, BL1c to BL8c, BL1d to BL8d. "0V" is applied to the local selection gate line LSG1, "1V" is applied to the unselected local selection gate line, and "0V" is applied to the selected and unselected p-type wells 211, 212, 221, and 222. To do. In order to read data from the selected memory cell transistors T1a 'to T1h', the voltages of the selected BL1a to BL8a are sensed by the sense amplifier 50, and the read data is provided as an output from the input / output buffer 60.

  6A and 6B are diagrams showing a cross-sectional portion of a memory cell according to another embodiment of the present invention. More specifically, FIGS. 6A and 6B show the p-type wells 211, 212, 221, 222 connected to the same control gate line LCG11 or LCG12, and the nonvolatile memory cell transistors T1 in the same row. 5B illustrates an embodiment of the memory cell array 10b of FIG. 5A extended to include a plurality of bytes. In FIG. 6A and FIG. 6B, the regions of the rectangles 27 ′ and 28 ′ illustrated by dotted lines correspond to the dark regions 27 and 28 shaded by the section line CD in FIG. 5A.

  As shown in FIGS. 6A and 6B, the memory cell transistor bytes LB11 to LB1N are formed on the p-type well 211 ′, and the memory cell transistor bytes LBK1 to LBKN are formed on the p-type well 212 ′. The bytes LB11 to LB1N and LBK1 to LBKN are connected to the same local control gate line LCG11. Similarly, the bytes RB11 to RB1N of the memory cell transistor T1 are formed on the p-type well 221 ′, and the bytes RBK1 to RBKN of the memory cell transistor T1 are formed on the p-type well 222 ′, and the bytes RB11 to RB1N, RBK1 to RBKN is connected to the same local control gate line LCG21. The local control gate line LCG11 is connected to the global control gate line GCG1 through the byte selection transistor T3, and the local control gate line LCG21 is connected to the global control gate line GCG1 through the byte selection transistor T5.

  In the memory cell array 10b of FIG. 5A including the row structure of FIGS. 6A and 6B, the memory write, erase, and read operations are performed in the same manner as described with reference to FIG. During the write operation, by applying different bias voltages to the p-type wells 211 ′ and 212 ′, data is not written to the memory cell transistors LB11 and / or LB1N in the p-type well 211 ′, and the p-type well 212 ′. Data is written into the memory cell transistors of the bytes LBK1 and / or LBKN. Therefore, the write operation to the memory cell transistors of different bytes in the different p-type wells connected to the same local control gate line is selectively performed. During the erase operation, by applying a different bias to the p-type wells 211 ′ and 212 ′, the data of the memory cell transistors LB11 and / or LB1N in the p-type well 211 ′ is not erased, and the p-type well 212 ′. The data in the memory cell transistors in the bytes LBK1 and / or LBKN is erased. Therefore, the erase operation is selectively performed on the memory cell transistors of different bytes connected to the same local control gate line and in different p-type wells.

  The above-described preferred embodiments of the present invention are disclosed for the purpose of illustration, and those having ordinary knowledge in the technical field to which the present invention pertains depart from the technical idea of the present invention. Various substitutions, modifications, and alterations are possible within the scope of not being included, and such substitutions, alterations, and the like belong to the scope of the claims.

1 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the present invention. 1 is a block diagram illustrating an electronic system including a nonvolatile memory device according to an embodiment of the present invention. 1 is a circuit diagram showing a memory cell array according to an embodiment of the present invention. 3B is a cross-sectional view taken along the line AB of the section line of the memory cell array of FIG. 3A. 4 is a table showing signals used for write, erase, and read operations according to an embodiment of the present invention. 1 is a circuit diagram showing a memory cell array according to an embodiment of the present invention. FIG. 5B is a cross-sectional view taken along line CD of the section line of the memory cell array of FIG. It is a figure which shows the part of the cross section of the memory cell which concerns on other embodiment of this invention. It is a figure which shows the part of the cross section of the memory cell which concerns on other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Memory cell array 10a Memory cell array 10b Memory cell array 11, 12 P type well 15 High voltage n type well 25 High voltage n type well 30 Row decoder 40 Column decoder 50 Data input / output circuit 52 Write driver 54 Sense amplifier 60 Input / output buffer 70 Controller 80 Voltage generator 100 Nonvolatile memory device 203 Semiconductor substrate 211, 212, 221, 222 p-type well 500 Electronic system 501 I / O bus 510 Encryption circuit 520 Logic circuit 530 Digital signal processor (DSP)
540 main processor 550 SRAM
560 DRAM
570 ROM
580 RF circuit 590 I / O circuit T1 Non-volatile memory cell transistor T2 Word line selection transistor T3, T5 Byte selection transistor T4 Sector selection transistor BNW n-type well SSG Sector selection gate line LCG Local control gate line WL Word line BSG Byte selection gate line CS Common source line GCG Global control gate line LSG Local selection gate line BL Bit line PW p-type well signal line

Claims (35)

A semiconductor substrate including electrically isolated first and second wells having the same conductivity;
A plurality of first nonvolatile memory cell transistors on the first well;
A plurality of second nonvolatile memory cell transistors on the second well;
A local control gate line electrically connected to the plurality of first and second nonvolatile memory cell transistors;
A group selection transistor electrically connected between the local gate line and the global control gate line,
The group selection transistor is set to electrically connect the local control gate line and the global control gate line according to a group selection gate signal applied to a gate of the group selection transistor. Electronic system.   The electrically isolated first and second wells have a first conductivity, the semiconductor substrate includes a well having a second conductivity different from the first conductivity, and the group selection transistor has The electronic system according to claim 1, wherein the electronic system is on the well having the second conductivity.   The electrically isolated first and second wells having the same conductivity include first and second p-type wells that are electrically isolated, and the well having the second conductivity is an n-type well. The electronic system of claim 2, wherein the group selection transistor includes a PMOS group selection transistor.   3. The electronic system of claim 2, wherein the well having the second conductivity is between the electrically isolated first and second wells having the first conductivity.   The electronic system according to claim 2, wherein the first well having the first conductivity is between the well having the second conductivity and the second well having the first conductivity. .   The electronic system according to claim 1, wherein the electrically isolated first and second wells include electrically isolated first and second p-type wells. A controller coupled to the first and second wells having the first conductivity, coupled to the global control gate line, and coupled to a gate of the group selection transistor;
The controller simultaneously applies different first and second electrical biases to the electrically isolated first and second wells having the first conductivity, and the electrically separated first and second wells. And applying a turn-on signal to the gate of the group selection transistor while applying the first and second electrical biases to the second well, and passing through the group selection transistor through the local control gate line and the plurality of the plurality of wells. By applying the same control signal transmitted from the global control gate line to the first and second memory cell transistors, the plurality of second memory cell transistors can be maintained while maintaining the programmed state. Set to erase the programmed state of the first memory cell transistor. Electronic system according to claim 1, wherein the.   The controller receives address information from an input / output bus during a read operation, and at least one of the plurality of first and / or second nonvolatile memory cell transistors according to the address information during the read operation. The electronic system according to claim 7, wherein the electronic system is set to provide data transmitted from one to the input / output bus. A processor coupled to the input / output bus;
The processor generates the address information during the read operation;
Providing the address information to the controller via the input / output bus;
9. The electronic system according to claim 8, wherein the electronic system is set so that the data is transmitted from the controller via the input / output bus.   The controller receives address information and data from the input / output bus during a write operation, and at least one of the plurality of first and / or second nonvolatile memory cell transistors specified by the address information. The electronic system according to claim 7, wherein the electronic system is set to write the data. A processor coupled to the input / output bus;
The processor is configured to generate the address information and the data during the write operation and to provide the address information and the data to the controller via the input / output bus. Item 11. The electronic system according to Item 10.   The plurality of first nonvolatile memory cell transistors include eight nonvolatile memory cell transistors, the plurality of second nonvolatile memory cell transistors include eight nonvolatile memory cell transistors, and the group selection transistor includes a byte selection transistor. The electronic system according to claim 1, comprising a selection transistor. An operation method of a nonvolatile integrated circuit memory device including a plurality of first and second nonvolatile memory cell transistors formed on electrically isolated first and second wells having the same conductivity, respectively. ,
Applying different first and second electrical biases to electrically isolated first and second wells having the same conductivity;
By applying the same control gate signal to the plurality of first and second memory cell transistors while applying the first and second electrical biases to the electrically separated first and second wells. And erasing the programmed states of the plurality of first memory cell transistors while maintaining the programmed states of the plurality of second memory cell transistors.   The method of claim 13, wherein the electrically isolated first and second wells include electrically isolated first and second p-type wells. A step of receiving address information from the input / output bus during a read operation;
Providing the data transmitted from the plurality of first and / or second nonvolatile memory cell transistors to the input / output bus according to the address information during the read operation. The operation method according to claim 13. Before the step of transmitting the address information from the input / output bus,
Transmitting the address information transmitted from the processor to the input / output bus;
The method according to claim 15, further comprising the step of transmitting the data from the input / output bus during the read operation after providing the data to the input / output bus. A step of transmitting address information and data from an input / output bus during a write operation;
The method of claim 13, further comprising: writing the data to at least one of the plurality of first and / or second nonvolatile memory cell transistors specified by the address information. How it works.   The method further comprises the step of transmitting the address information and the data transmitted from the processor to the input / output bus before the step of transmitting the address information and the data from the input / output bus. Item 18. The operation method according to Item 17.   The plurality of first memory cell transistors include eight nonvolatile memory cell transistors, the plurality of second memory cell transistors include eight nonvolatile memory cell transistors, and the group selection transistor is a byte selection transistor. The method according to claim 13, further comprising: A semiconductor substrate including electrically isolated first and second wells having the same conductivity;
A plurality of first non-volatile memory cells including non-volatile memory cell transistors, each non-volatile memory cell connected in series between a respective word select and sector select transistor on the first well;
A plurality of second non-volatile memory cells, each including a non-volatile memory cell transistor connected in series between a respective word select and sector select transistor on the second well;
A plurality of first bit lines coupled to respective sector select transistors of the plurality of first memory cells;
A plurality of second bit lines connected to respective sector selection transistors of the plurality of second memory cells;
A local control gate line electrically connected to the plurality of first and second memory cell transistors;
A group selection transistor connected between the local control gate line and the global control gate line and set to electrically connect the local control gate line and the global control gate line according to a signal applied to the gate. When,
A row decoder coupled to the word selection and sector selection transistors of the plurality of first and second nonvolatile memory cells and coupled to the global control gate line;
A column decoder coupled to the electrically isolated first and second wells, the plurality of first and second bit lines, and the group selection gate line;
A controller coupled to the row and column decoder,
The controller causes the column decoder to apply different electrical biases to the first and second wells and maintains the programmed states of the plurality of second memory cell transistors. While the different electrical biases are applied to the first and second wells to erase the programmed state of the memory cell transistors, the group select transistors are connected to the plurality of second through the local gate lines. An electronic system configured to provide the same control gate signal transmitted from the global control gate line to the nonvolatile memory cell transistors of the first and second nonvolatile memory cells.   The electrically isolated first and second wells have a first conductivity, the semiconductor substrate includes a well having a second conductivity different from the first conductivity, and the group selection transistor has 21. The electronic system of claim 20, wherein the electronic system is on a well having the second conductivity.   The electrically isolated first and second wells having the same conductivity include first and second p-type wells that are electrically isolated, and the well having the second conductivity is an n-type well. The electronic system of claim 21, wherein the group selection transistor comprises a PMOS group selection transistor.   22. The electronic system of claim 21, wherein the well having the second conductivity is between the electrically isolated first and second wells having the first conductivity.   The first well having the first conductivity is formed between the well having the second conductivity and the second well having the first conductivity. Electronic systems.   21. The electronic system of claim 20, wherein the electrically isolated first and second wells include electrically isolated first and second p-type wells.   The plurality of first nonvolatile memory cell transistors include eight nonvolatile memory cell transistors, and the plurality of second nonvolatile memory cell transistors include eight nonvolatile memory cell transistors, and the group selection transistor 21. The electronic system of claim 20, comprising a byte select transistor.   The controller receives address information from an input / output bus during a read operation, and is transmitted from the plurality of first and / or second nonvolatile memory cell transistors according to the address information during the read operation. 21. The electronic system of claim 20, wherein the electronic system is configured to provide data to the input / output bus.   The address information is generated, the address information is provided to the controller via the input / output bus, and the data is transmitted from the controller via the input / output bus during the reading operation. 28. The electronic system of claim 27, further comprising a processor.   The controller receives address information and data from the input / output bus during a write operation, and at least one of the plurality of first and / or second nonvolatile memory cell transistors specified by the address information. 21. The electronic system of claim 20, wherein the electronic system is set to write the data.   A processor coupled to the input / output bus and configured to generate the address information and the data during the write operation and to provide the address information and the data to the controller via the input / output bus; 30. The electronic system of claim 29, further comprising: A plurality of first and second nonvolatile memory cell transistors;
A local control gate line electrically connected to the plurality of first and second nonvolatile memory cell transistors;
A controller coupled to the local control gate line,
The controller may program the plurality of first nonvolatile memory cell transistors connected to the local control gate line while maintaining a programmed state of the plurality of second nonvolatile memory cell transistors during an erase operation. An electronic system, wherein the electronic system is set to erase the recorded state. A semiconductor substrate including electrically isolated first and second wells having the same conductivity;
32. The electronic system of claim 31, wherein the plurality of first nonvolatile memory cell transistors are on the first well and the plurality of second nonvolatile memory cell transistors are on the second well. .   In the erase operation, the first and second electrical biases having the first conductivity and different from the electrically separated first and second wells are set to be simultaneously applied. 33. The electronic system according to claim 32, characterized in that   32. The electronic system of claim 31, wherein the electrically isolated first and second wells include electrically isolated first and second p-type wells.   The plurality of first nonvolatile memory cell transistors include eight nonvolatile memory cell transistors, the plurality of second nonvolatile memory cell transistors include eight nonvolatile memory cell transistors, and the group selection transistor includes a byte selection transistor. 32. The electronic system of claim 31, comprising a selection transistor.

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