JP2008083137A - Driving method of plasma display panel - Google Patents

Abstract

Even a plasma display panel having a large display screen size displays an image with good quality.
A field period includes a plurality of subfields each having an initialization period, an address period, and a sustain period, and a ramp waveform voltage is applied to a scan electrode in an initialization period of at least one subfield of the plurality of subfields. An initializing period portion for applying an initializing discharge by applying, and an abnormal charge erasing portion for applying a downward ramp waveform voltage after applying a plurality of rectangular waveforms to the scan electrodes are provided.
[Selection] Figure 4

Description

  The present invention relates to a method for driving a plasma display panel.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of pairs of display electrodes made up of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other, and a dielectric layer and a protective layer are formed so as to cover the display electrodes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of partition walls formed in parallel to the data electrodes on each of the dielectric layers. A phosphor layer is formed on the side surface of the partition wall. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode and the data electrode are three-dimensionally crossed and sealed, and a discharge gas is sealed in the internal discharge space. Here, a discharge cell is formed at a portion where the display electrode and the data electrode face each other. In the panel having such a configuration, ultraviolet light is generated by gas discharge in each discharge cell, and phosphors of RGB colors are excited and emitted by the ultraviolet light to perform color display.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields. In addition, among the subfield methods, Patent Document 1 discloses a novel driving method in which light emission not related to gradation display is reduced as much as possible to suppress an increase in black luminance and an contrast ratio is improved.

  The driving method will be briefly described below. Each subfield has an initialization period, an address period, and a sustain period. Also, during the initialization period, all cell initialization operations for performing initialization discharge for all discharge cells that perform image display, or selectively for discharge cells that have undergone sustain discharge in the immediately preceding subfield, are performed. One of the selective initialization operations for performing the initialization discharge is performed.

  In the initialization period in which all cell initialization operations are performed, all discharge cells perform initialization discharge all at once, and the wall charge history for individual previous discharge cells is erased. Form a charge. In addition, it has a function of generating priming (priming for discharge = excited particles) for reducing the discharge delay and stably generating the address discharge. In the subsequent address period, a scan pulse is sequentially applied to the scan electrodes, and an address pulse corresponding to an image signal to be displayed is applied to the data electrodes, so that an address discharge is selectively generated between the scan electrodes and the data electrodes. Then, selective wall charge formation is performed. In the sustain period, a predetermined number of sustain pulses corresponding to the luminance weight are applied between the scan electrodes and the sustain electrodes, and the discharge cells in which the wall charges are formed by the address discharge are selectively discharged to emit light.

As described above, in order to display an image correctly, it is important to surely perform selective address discharge in the address period. To that end, it is necessary to reliably perform an initialization operation to prepare for the address operation. Is important.
JP 2000-242224 A

  In the all-cell initialization period, it is necessary to generate an initialization discharge with the scan electrode as the anode and the sustain electrode and the data electrode as the cathode, but the data electrode is coated with a phosphor with a small electron emission coefficient. For this reason, the discharge delay of the discharge using the data electrode as a cathode increases, and the initialization discharge may become unstable. When the initialization discharge becomes unstable, the subsequent address discharge and sustain discharge also become unstable, and there is a possibility that the image display quality may be deteriorated, such as discharge cells that should not emit light.

  In recent years, a panel having a large display screen size has been developed to meet the demand for a large screen display device. In such a panel, in order to generate a uniform discharge over the entire screen, a driving voltage applied to the panel is applied. Tend to be higher. When the drive voltage is increased, discharge is likely to occur, and a discharge cell having a slight wall charge abnormality may generate a sustain discharge regardless of the image signal, which may deteriorate image display quality.

  The present invention has been made in view of these problems, and an object of the present invention is to provide a panel driving method capable of displaying an image with good quality even if the panel has a large display screen size.

  The present invention relates to a panel driving method in which discharge cells are formed at intersections of scan electrodes, sustain electrodes, and data electrodes, and a plurality of sub-fields in which one field period has an initialization period, an address period, and a sustain period An initialization period unit configured to perform an initializing discharge by applying a ramp waveform voltage to the scan electrode in an initialization period of at least one subfield of the plurality of subfields, and a plurality of rectangular waveforms on the scan electrode. An abnormal charge erasing unit that applies a downward ramp waveform voltage after application is provided. By this method, it is possible to provide a panel driving method capable of displaying an image with good quality even if the panel has a large display screen size.

  Further, the initialization period part of the present invention includes a first half of an initialization period in which an upward ramp waveform voltage is applied to the scan electrode to perform a first initialization discharge using the scan electrode as an anode and a sustain electrode and a data electrode as a cathode; There may be provided a second half of an initialization period in which a second ramp discharge voltage is applied to the scan electrode to perform a second setup discharge using the scan electrode as a cathode and the sustain electrode and the data electrode as an anode. By this method, it is possible to suppress the increase in black luminance and improve the contrast ratio.

  ADVANTAGE OF THE INVENTION According to this invention, even if it is a panel with a big display screen size, the drive method of the panel which can display an image with favorable quality can be provided.

  Hereinafter, a panel driving method according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is a perspective view showing a main part of a panel used in the embodiment of the present invention. The panel 1 is configured such that a glass front substrate 2 and a back substrate 3 are disposed to face each other and a discharge space is formed therebetween. On the front substrate 2, a plurality of scanning electrodes 4 and sustaining electrodes 5 constituting display electrodes are formed in parallel with each other. A dielectric layer 6 is formed so as to cover the scan electrode 4 and the sustain electrode 5, and a protective layer 7 is formed on the dielectric layer 6. The protective layer 7 is preferably made of a material having a large secondary electron emission coefficient and high sputtering resistance in order to generate a stable discharge, and an MgO thin film is used in the embodiment of the present invention. A plurality of data electrodes 9 covered with an insulator layer 8 are provided on the back substrate 3, and a grid-like partition wall 10 is provided on the insulator layer 8 between the data electrodes 9. A phosphor layer 11 is provided on the surface of the insulator layer 8 and the side surfaces of the partition walls 10. The front substrate 2 and the rear substrate 3 are arranged to face each other in the direction in which the scan electrodes 4 and the sustain electrodes 5 and the data electrodes 9 intersect, and in the discharge space formed between them, for example, neon And a mixed gas of xenon.

  FIG. 2 is an electrode array diagram of the panel according to the embodiment of the present invention. The n scan electrodes SCN1 to SCNn (scan electrode 4 in FIG. 1) and n sustain electrodes SUS1 to SUSn (sustain electrode 5 in FIG. 1) that are long in the row direction are alternately arranged, and m scan electrodes that are long in the column direction are arranged. Data electrodes D1 to Dm (data electrode 9 in FIG. 1) are arranged. A discharge cell is formed at the intersection of one pair of scan electrode SCNi and sustain electrode SUSi (i = 1 to n) and one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. m × n are formed.

  FIG. 3 is a configuration diagram of a plasma display apparatus using the panel driving method according to the embodiment of the present invention. The plasma display device includes a panel 1, a data electrode drive circuit 12, a scan electrode drive circuit 13, a sustain electrode drive circuit 14, a timing generation circuit 15, an AD (analog / digital) converter 18, a scan number conversion unit 19, and a subfield. A conversion unit 20 and a power supply circuit (not shown) are provided.

  In FIG. 3, the image signal sig is input to the AD converter 18. The horizontal synchronization signal H and the vertical synchronization signal V are input to the timing generation circuit 15, the AD converter 18, the scanning number conversion unit 19, and the subfield conversion unit 20. The AD converter 18 converts the image signal sig into digital signal image data, and outputs the image data to the scanning number conversion unit 19. The scanning number conversion unit 19 converts the image data into image data corresponding to the number of pixels of the panel 1 and outputs the image data to the subfield conversion unit 20. The subfield conversion unit 20 divides the image data of each pixel into a plurality of bits corresponding to a plurality of subfields, and outputs the image data for each subfield to the data electrode driving circuit 12. The data electrode driving circuit 12 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm.

  The timing generation circuit 15 generates a timing signal based on the horizontal synchronization signal H and the vertical synchronization signal V, and outputs the timing signal to the scan electrode drive circuit 13 and the sustain electrode drive circuit 14, respectively. Scan electrode drive circuit 13 supplies a drive waveform to scan electrodes SCN1 to SCNn based on the timing signal, and sustain electrode drive circuit 14 supplies a drive waveform to sustain electrodes SUS1 to SUSn based on the timing signal.

  Next, a driving waveform for driving the panel and its operation will be described. In the embodiment of the present invention, it is assumed that one field period is composed of ten subfields (first SF, second SF,..., Tenth SF) having an initialization period, an address period, and a sustain period. To do.

  FIG. 4 is a drive waveform diagram applied to each electrode of the panel according to the embodiment of the present invention, and is a subfield having an initialization period for performing the all-cell initialization operation (hereinafter abbreviated as “all-cell initialization subfield”). And a driving waveform diagram for a subfield having an initialization period for performing a selective initialization operation (hereinafter abbreviated as “selective initialization subfield”). FIG. 4 shows the first SF as an all-cell initializing subfield and the second SF as a selective initializing subfield for explanation.

  First, the drive waveform and operation of the all-cell initialization subfield will be described. The all-cell initialization period is divided into two periods, an initialization period part and an abnormal charge erasing part as follows, and the initialization period part is further divided into a first half of the initialization period and a second half of the initialization period. To do.

  In the first half of the initialization period, sustain electrodes SUS1 to SUSn and data electrodes D1 to Dm are held at 0 (V), and a discharge start voltage from voltage Vp (V) that is equal to or lower than the discharge start voltage with respect to scan electrodes SCN1 to SCNn. An upward ramp waveform voltage that gently rises toward a voltage Vr (V) that exceeds V is applied. Then, a weak first initialization discharge is generated with scan electrodes SCN1 to SCNn as anodes and sustain electrodes SUS1 to SUSn and data electrodes D1 to Dm as cathodes. Thus, the first weak initializing discharge is generated in all the discharge cells, the negative wall voltage is stored on the scan electrodes SCN1 to SCNn, and the positive wall on the sustain electrodes SUS1 to SUSn and the data electrodes D1 to Dm. Stores voltage. Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the phosphor layer, the protective layer, and the like.

  In the latter half of the initialization period, sustain electrodes SUS1 to SUSn are maintained at positive voltage Vh (V), and the downward slope waveform gradually decreases from voltage Vg (V) to voltage Va (V) at scan electrodes SCN1 to SCNn. Apply voltage. Then, in all the discharge cells, a second weak initializing discharge is generated with scan electrodes SCN1 to SCNn as cathodes and sustain electrodes SUS1 to SUSn and data electrodes D1 to Dm as anodes. Then, the wall voltage on scan electrodes SCN1 to SCNn and the wall voltage on sustain electrodes SUS1 to SUSn are weakened, and the wall voltage on data electrodes D1 to Dm is also adjusted to a value suitable for the write operation. As described above, the initialization operation in the all-cell initialization subfield is an all-cell initialization operation in which initialization discharge is performed in all discharge cells. Since the initializing discharge is weak, the luminance accompanying the initializing discharge is low, and the contrast ratio can be improved by suppressing an increase in black luminance.

  In the abnormal charge erasing unit in the initialization period, the sustain electrodes SUS1 to SUSn are returned to 0 (V) again. Then, after applying positive voltage Vm (V) less than the discharge start voltage as the first rectangular waveform to scan electrodes SCN1 to SCNn, negative voltage Va (V) is applied as the second rectangular waveform, Further, a positive voltage Vm (V) is applied as a third rectangular waveform, and then a ramp waveform voltage that gently falls toward the voltage Va (V) is applied. During this time, discharge does not occur in the discharge cells that have performed stable initialization discharge, and the wall voltage also maintains the state of the latter half of the initialization period. However, for a discharge cell in which a positive excess wall voltage is accumulated on scan electrode SCNi, if voltage Vm (V) is applied as first rectangular waveform to scan electrodes SCN1 to SCNn, the discharge start voltage is exceeded. Discharge occurs and the wall voltage on scan electrode SCNi is inverted. Then, when the second rectangular waveform is applied, a discharge is generated again and the wall voltage is reversed. After that, when the third rectangular waveform is further applied, a third discharge is generated. These series of discharges not only accumulate negative wall voltages on scan electrodes SCN1 to SCNn, but also accumulate positive wall voltages on sustain electrodes SUS1 to SUSn and data electrodes D1 to Dm. The wall voltage on scan electrodes SCN1 to SCNn and the wall voltage on sustain electrodes SUS1 to SUSn are weakened by the gradually decreasing ramp waveform voltage, and the wall voltage on data electrodes D1 to Dm is also adjusted to a value suitable for the write operation. Is done. In this way, after applying a plurality of rectangular waveforms to scan electrodes SCN1 to SCNn, a downward ramp waveform voltage is applied to generate a plurality of discharges for the discharge cells that have accumulated excessive wall voltage. Eliminate excess wall voltage. Since the wall voltage of these discharge cells is adjusted to a wall voltage suitable for the address operation, it can be operated normally after the subsequent address period. In this embodiment, the pulse widths of the first rectangular waveform and the third rectangular waveform are set to about 6 μs, and the pulse width of the second rectangular waveform is set to about 3 μs. It is desirable to set the optimum value according to the characteristics of

  In the subsequent address period, scan electrodes SCN1 to SCNn are temporarily held at Vs (V). Next, a positive address pulse voltage Vw (V) is applied to the data electrode Dk (k = 1 to m) of the discharge cell to be displayed in the first row among the data electrodes D1 to Dm, and the first row. Scan pulse voltage Vb (V) is applied to scan electrode SCN1. At this time, the voltage at the intersection of the data electrode Dk and the scan electrode SCN1 is obtained by adding the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SCN1 to the externally applied voltage (Vw−Vb) (V). The discharge start voltage is exceeded. Then, an address discharge occurs between data electrode Dk and scan electrode SCN1 and between sustain electrode SUS1 and scan electrode SCN1, and a positive wall voltage is accumulated on scan electrode SCN1 of this discharge cell, and on sustain electrode SUS1. And a negative wall voltage is also accumulated on the data electrode Dk. In this manner, an address operation is performed in which address discharge is caused in the discharge cells to be displayed in the first row and wall voltage is accumulated on each electrode. On the other hand, since the voltage at the intersection of the data electrode to which the positive address pulse voltage Vw (V) is not applied and the scan electrode SCN1 does not exceed the discharge start voltage, the address discharge does not occur. In addition, since the discharge cell that has caused a discharge in the abnormal charge erasing portion in the initialization period has also erased the wall voltage on the data electrode, no address discharge occurs. The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, first, sustain electrodes SUS1 to SUSn are returned to 0 (V), and positive sustain pulse voltage Vm (V) is applied to scan electrodes SCN1 to SCNn. At this time, in the discharge cell in which the address discharge has occurred, the voltage between scan electrode SCNi and sustain electrode SUSi is equal to sustain pulse voltage Vm (V) as the wall voltage on scan electrode SCNi and sustain electrode SUSi. The magnitude is added and exceeds the discharge start voltage. Then, a sustain discharge occurs between scan electrode SCNi and sustain electrode SUSi, a negative wall voltage is accumulated on scan electrode SCNi, and a positive wall voltage is accumulated on sustain electrode SUSi. At this time, a positive wall voltage is also accumulated on the data electrode Dk. In the discharge cells where no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage state at the end of the initialization period is maintained. Subsequently, scan electrodes SCN1 to SCNn are returned to 0 (V), and positive sustain pulse voltage Vm (V) is applied to sustain electrodes SUS1 to SUSn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage between the sustain electrode SUSi and the scan electrode SCNi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUSi and the scan electrode SCNi. Negative wall voltage is accumulated on sustain electrode SUSi, and positive wall voltage is accumulated on scan electrode SCNi. Thereafter, similarly, by applying sustain pulses alternately to scan electrodes SCN1 to SCNn and sustain electrodes SUS1 to SUSn, the sustain discharge is continuously performed in the discharge cells in which the address discharge is generated in the address period. At the end of the sustain period, a so-called narrow pulse is applied between scan electrodes SCN1 to SCNn and sustain electrodes SUS1 to SUSn to leave positive wall charges on data electrode Dk, and scan electrode SCN1. ˜SCNn and the wall voltage on sustain electrodes SUS1 to SUSn are erased. Thus, the maintenance operation in the maintenance period is completed.

  Next, the drive waveform and operation of the selective initialization subfield will be described.

  In the initialization period, sustain electrodes SUS1 to SUSn are held at Vh (V), data electrodes D1 to Dm are held at 0 (V), and scan electrodes SCN1 to SCNn are moved from Vq (V) to Va (V). Apply a descending ramp waveform voltage that gradually falls. Then, in the discharge cell in which the sustain discharge is performed in the sustain period of the previous subfield, a weak initializing discharge is generated, the wall voltage on scan electrode SCNi and sustain electrode SUSi is weakened, and the wall voltage on data electrode Dk is reduced. Is also adjusted to a value suitable for the write operation. On the other hand, the discharge cells in which the address discharge and the sustain discharge were not performed in the previous subfield are not discharged, and the wall charge state at the end of the initialization period of the previous subfield is maintained as it is. As described above, the initializing operation in the selective initializing subfield is a selective initializing operation in which initializing discharge is performed in the discharge cells that have undergone sustain discharge in the previous subfield.

  The address period and the sustain period are the same as the address period and the sustain period of the all-cell initialization subfield, and thus description thereof is omitted. In this way, by combining the all-cell initializing subfield and the selective initializing subfield, it is possible to reduce light emission not related to gradation display as much as possible, suppress an increase in black luminance, and improve a contrast ratio.

  Here, the reason why the abnormal charge erasing unit is provided in the all-cell initialization period will be described. In the first half of the initialization period, when a gradually increasing ramp waveform voltage is applied to the scan electrodes SCN1 to SCNn, usually the weak initialization using the scan electrodes SCN1 to SCNn as the anode and the sustain electrodes SUS1 to SUSn as the cathode Discharge occurs. However, the initialization discharge may be greatly delayed due to insufficient priming. Then, when the discharge is generated, the discharge start voltage is greatly exceeded, so that the discharge is not weak and a strong discharge is generated. Or the strong discharge which uses the data electrodes D1-Dm as a cathode will generate | occur | produce in advance. Then, excessive negative wall charges are accumulated on scan electrodes SCN1 to SCNn. Then, in the latter half of the initialization period, strong discharge is generated again while applying a downward ramp waveform voltage to scan electrodes SCN1 to SCNn, and excessive positive wall charges are accumulated on scan electrodes SCN1 to SCNn. Become.

  Alternatively, the address discharge generated in the address period of the subfield before the all-cell initialization subfield is weak, the wall voltage to be accumulated on the scan electrode, the sustain electrode, or the data electrode is insufficient, and the sustain discharge is generated in the sustain period. Abnormal wall charges remain in the discharge cells that could not be generated. Even if the address discharge itself is performed normally, abnormal wall charges may remain even if the wall voltage accumulated on the scan electrode, the sustain electrode or the data electrode decreases for some reason. . Then, if a sustain pulse is applied without eliminating the excessive wall voltage due to such an abnormal wall charge, a sustain discharge occurs during the sustain period. This tendency is particularly strong in a panel having a large display screen size and a high sustain pulse voltage applied to the panel in order to generate a uniform discharge over the entire screen.

  However, in the present embodiment, an abnormal charge erasing unit is provided in the all-cell initializing period, and a plurality of rectangular waveforms are sequentially applied to scan electrodes SCN1 to SCNn, so that a plurality of discharge cells accumulate excessive wall voltages. A strong discharge is generated. Thereafter, a gradually decreasing ramp waveform voltage is applied to weaken the wall voltage on scan electrodes SCN1 to SCNn and the wall voltage on sustain electrodes SUS1 to SUSn, and the wall voltage on data electrodes D1 to Dm is also used for the write operation. It is adjusted to an appropriate value. Therefore, even if a discharge cell in which abnormal wall charges are accumulated for some reason is generated, it can be operated normally after the subsequent address period.

  The reason for applying a plurality of rectangular waveforms in the abnormal charge erasing portion in the all-cell initializing period before applying the ramp waveform voltage that gently falls to scan electrodes SCN1 to SCNn is as follows. In general, the magnitude of the wall voltage due to abnormal wall charges accumulated in the discharge cell is considered to take various values. However, when a plurality of rectangular waveforms are applied to such discharge cells having various values of wall voltage to repeatedly generate a discharge, there is a characteristic of convergence to one of the two wall voltages. FIG. 5 is a diagram schematically showing a discharge state when a plurality of pulses are applied to discharge cells having various wall charges.

  FIG. 5A shows the case of a discharge cell having a very large wall voltage. In the first discharge, a very strong discharge occurs because a large wall voltage is added to the rectangular waveform voltage. Since the wall voltage formed by this discharge is not as great as the initial wall voltage, the second discharge is weaker than the first discharge, but is still a strong discharge. Since the wall voltage formed by the second discharge is slightly smaller than the wall voltage formed by the first discharge, but is almost the same magnitude, the third discharge is slightly weaker than the second discharge. However, the discharges are almost the same size. Thereafter, the same is repeated to converge to a discharge having a certain intensity, and the formed wall voltage value also converges to a certain value.

  FIG. 5B shows a discharge cell having a slightly smaller wall charge. In the first discharge, since the wall voltage is not so high, the generated discharge is not so strong. However, when the wall voltage formed by this discharge is larger than the initial wall voltage, the second discharge is stronger than the first discharge. Since the wall voltage formed by the second discharge is slightly higher than the wall voltage formed by the first discharge, the third discharge is slightly stronger than the second discharge. Thereafter, the same is repeated to grow to a discharge having a certain intensity, and the accumulated wall voltage converges to a certain value. The magnitude of the wall charge that converges at this time is the same as the value shown in FIG.

  FIG. 5C shows a discharge cell having a smaller wall charge. The first discharge is weak because the wall voltage is small. Then, the wall voltage formed by this discharge also becomes small, but when this value is smaller than the initial wall charge, the second discharge becomes even weaker than the first discharge. Since the wall voltage formed by the second discharge is even smaller than the wall voltage formed by the first discharge, the third discharge is even weaker than the second discharge or no discharge occurs. In this case, the discharge does not last and the wall charges are erased.

  As described above, it is considered that the magnitude of the wall voltage due to abnormal wall charges accumulated in the discharge cell takes various values. It is difficult to eliminate these wall voltages that take various values all at once. However, in the present embodiment, an abnormal charge erasing unit is provided in the all-cell initializing period, and a plurality of rectangular waveforms are sequentially applied to scan electrodes SCN1 to SCNn, thereby causing discharge with excessive wall voltage due to abnormal wall charges. Multiple strong discharges are generated in the cell to eliminate excess wall voltage or converge to a constant value. After that, for the discharge cells in which the gradually decreasing ramp waveform voltage is applied and the wall voltage is converged to a constant value, the wall voltage on the scan electrodes SCN1 to SCNn and the wall on the sustain electrodes SUS1 to SUSn. The wall voltage on the data electrodes D1 to Dm can be adjusted to a value suitable for the write operation by decreasing the voltage.

  In the above description, the number of rectangular waveforms applied to the scan electrodes SCN1 to SCNn in the abnormal charge erasing portion in the all-cell initialization period is set to 3, but the present invention only needs to have a plurality of rectangular waveforms. For example, the number of rectangular waveforms may be set to 5.

  In the present embodiment, one field period is composed of 10 subfields, and the first SF is described as an all-cell initializing subfield and the second SF as a selective initializing subfield. However, the number of subfields is the above value. It is not limited to. Further, the subfield configuration is not limited to the above, and each of a plurality of subfields constituting one field period may be set to either an all-cell initializing subfield or a selective initializing subfield. In that case, as described in the present embodiment, it is desirable to provide an abnormal charge erasing portion in the initialization period of the all-cell initialization subfield.

  Further, the specific numerical values used in the present embodiment are merely examples, and it is desirable to appropriately set the values appropriately according to the characteristics of the panel, the specifications of the plasma display device, and the like.

  The panel driving method of the present invention is useful as a plasma display panel or the like used in a large-screen image display device because an image can be displayed with good quality even if the panel has a large display screen size.

The perspective view which shows the principal part of the panel used for embodiment of this invention Panel arrangement diagram of panel according to the embodiment of the present invention Configuration diagram of plasma display device using the panel driving method Drive waveform diagram applied to each electrode of the panel A diagram schematically showing the state of discharge when multiple pulses are applied to a discharge cell with various wall charges

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Panel 2 Front substrate 3 Back substrate 4 Scan electrode 5 Sustain electrode 9 Data electrode 12 Data electrode drive circuit 13 Scan electrode drive circuit 14 Sustain electrode drive circuit 15 Timing generation circuit 18 AD converter 19 Scan number conversion part 20 Subfield conversion part

Claims (2)

A method for driving a plasma display panel in which discharge cells are formed at intersections of scan electrodes, sustain electrodes, and data electrodes,
One field period is composed of a plurality of subfields having an initialization period, an address period, and a sustain period,
In an initialization period of at least one subfield of the plurality of subfields,
An initializing period portion for applying an initial discharge by applying a ramp waveform voltage to the scan electrode;
A method for driving a plasma display panel, comprising: an abnormal charge erasing unit that applies a downward ramp waveform voltage after applying a plurality of rectangular waveforms to the scan electrode. The initialization period section includes an initial period of an initialization period in which an upward ramp waveform voltage is applied to the scan electrode to perform a first initialization discharge using the scan electrode as an anode and the sustain electrode and the data electrode as a cathode. And a second half of an initializing period in which a second ramp waveform voltage is applied to the scan electrode to perform a second initializing discharge using the scan electrode as a cathode and the sustain electrode and the data electrode as an anode. The method for driving a plasma display panel according to claim 1.

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