JP2005301013A - Method for driving plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for driving a plasma display panel which suppresses increase in the luminance of black and reduces the writing period, while securing stable writing operation. <P>SOLUTION: One field period is constituted of a plurality of sub-fields, having an initialization period, a write period and a maintenance period, and during the initialization period of each sub-field, either the whole cell initialization operation or selective initialization operation is performed; and the time for generating write discharge of the head sub-field constituting one field is set long and the time for making write discharge of the sub-field generated for performing the selective initialization operation is set shorter than or equal to that for making write discharge of the preceding sub-field generated. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for driving a plasma display panel and an image display device using the plasma display panel.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of pairs of display electrodes made up of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other, and a dielectric layer and a protective layer are formed so as to cover the display electrodes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs formed on the back side in parallel with the data electrodes. A phosphor layer is formed on the side surface of the partition wall. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode and the data electrode are three-dimensionally crossed and sealed, and a discharge gas is sealed in the internal discharge space. Here, a discharge cell is formed at a portion where the display electrode and the data electrode face each other. In the panel having such a configuration, ultraviolet light is generated by gas discharge in each discharge cell, and phosphors of RGB colors are excited and emitted by the ultraviolet light to perform color display.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields. Also, among the subfield methods, Patent Document 1 discloses a novel driving method in which light emission not related to gradation expression is reduced as much as possible to suppress the increase in black luminance and the contrast ratio is improved.

  The subfield method will be briefly described below. Each subfield has an initialization period, an address period, and a sustain period. In addition, the initializing period is an initializing operation for all the cells that perform initializing discharge for all the discharge cells that perform image display, or selectively for the discharge cells that have undergone sustain discharge in the immediately preceding subfield. One of the selective initializing operations for causing the igniting discharge is performed.

  First, during the all-cell initialization period, all discharge cells perform an initializing discharge all at once, erasing the wall charge history for each previous discharge cell, and forming the wall charge necessary for the subsequent address operation. To do. In addition, it has a function of generating priming (priming for discharge = excited particles) for reducing discharge delay and generating address discharge stably. In the subsequent address period, a scan pulse is sequentially applied to the scan electrodes, and an address pulse corresponding to an image signal to be displayed is applied to the data electrodes, thereby selectively causing an address discharge between the scan electrodes and the data electrodes. , Selective wall charge formation. In the sustain period, a predetermined number of sustain pulses corresponding to the luminance weight are applied between the scan electrodes and the sustain electrodes, and the discharge cells in which the wall charges are formed by the address discharge are selectively discharged to emit light.

Thus, in order to display an image correctly, it is important to reliably perform selective address discharge in the address period. However, due to restrictions on the circuit configuration, a high voltage cannot be used for the address pulse, There are many factors that increase the discharge delay with respect to the address discharge, such as the fact that the phosphor layer formed on the substrate makes it difficult for the discharge to occur. Therefore, priming for generating the address discharge stably is very important.
JP 2000-242224 A

  However, since the priming generated by the discharge rapidly decreases with time, the priming generated by the initialization discharge is insufficient for the address discharge after a long time has elapsed from the initialization discharge, and the discharge delay becomes large. Therefore, there has been a problem that the writing time is set long in order to perform the writing operation stably, and as a result, the time spent in the writing period becomes too long.

  Further, the number of discharge cells increases with the recent high definition of the panel, and the time required for the address period tends to become longer. Furthermore, a driving method for increasing the number of subfields in order to improve image display quality, such as improvement of a moving image pseudo contour, has been studied, and a shortening of a writing period is increasingly required in the future.

  The panel driving method of the present invention has been made in view of the above problems, and provides a panel driving method that suppresses an increase in black luminance and shortens the writing period while guaranteeing a stable writing operation. For the purpose.

  The panel driving method of the present invention is a panel driving method in which discharge cells are formed at intersections of scan electrodes, sustain electrodes, and data electrodes, and an initializing discharge is generated in the discharge cells during one field period. It is composed of a plurality of subfields having an initializing period, an address period for generating an address discharge in the discharge cells, and a sustain period for generating a sustain discharge for causing the discharge cells to emit light with a predetermined luminance weight. In the initializing period, initializing discharge is selectively performed on all cells initializing operation for generating initializing discharge on all discharge cells that perform image display or on discharge cells that have generated sustain discharge in the immediately preceding subfield. When any of the selective initialization operations to be generated is performed to generate the address discharge in the subfield where the selective initialization operation is performed Characterized in that set shorter than or equal to the time for generating the address discharge of the immediately preceding subfield is. With this driving method, it is possible to provide a driving method of a plasma display panel that suppresses an increase in black luminance and shortens the writing period while guaranteeing a stable writing operation.

  Further, the panel driving method of the present invention is configured to perform multi-gradation display by controlling to emit or not emit light in each sustain period of a plurality of subfields, perform selective initialization, and emit light. It is desirable that the selection initialization is performed immediately before the subfield so that the gray level where two or more subfields that do not emit light are not continuous is obtained. This driving method can further stabilize the writing operation.

  In the panel driving method of the present invention, the first subfield constituting one field is a subfield having the smallest luminance weight in the sustain period, and the subsequent subfield is a subfield having the luminance weight in the respective sustain period immediately before. It is desirable that the subfield be greater than or equal to the luminance weight of the field. By this driving method, the time difference between the subfields constituting one field can be set small.

  According to the present invention, it is possible to provide a method for driving a plasma display panel that suppresses an increase in black luminance and shortens an address period while guaranteeing a stable address operation.

  Hereinafter, a panel driving method according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a perspective view showing a main part of a panel used in Embodiment 1 of the present invention. The panel 1 is configured such that a glass front substrate 2 and a rear substrate 3 are arranged to face each other and a discharge space is formed therebetween. On the front substrate 2, a plurality of scanning electrodes 4 and sustaining electrodes 5 constituting display electrodes are formed in parallel with each other. A dielectric layer 6 is formed so as to cover the scan electrode 4 and the sustain electrode 5, and a protective layer 7 is formed on the dielectric layer 6. A plurality of data electrodes 9 covered with an insulating layer 8 are provided on the back substrate 3, and a partition wall 10 is provided in parallel with the data electrodes 9 on the insulating layer 8 between the data electrodes 9. Yes. A phosphor layer 11 is provided on the surface of the insulator layer 8 and the side surfaces of the partition walls 10. The front substrate 2 and the rear substrate 3 are arranged to face each other in the direction in which the scan electrode 4 and the sustain electrode 5 intersect with the data electrode 9, and in the discharge space formed between them, for example, neon And a mixed gas of xenon.

  FIG. 2 is an electrode array diagram of the panel used in Embodiment 1 of the present invention. N scan electrodes SCN1 to SCNn (scan electrode 4 in FIG. 1) and n sustain electrodes SUS1 to SUSn (sustain electrode 5 in FIG. 1) are alternately arranged in the row direction, and m data electrodes in the column direction. D1 to Dm (data electrodes 9 in FIG. 1) are arranged. A discharge cell is formed at a portion where a pair of scan electrode SCNi and sustain electrode SUSi (i = 1 to n) and one data electrode Dj (j = 1 to m) intersect, and the discharge cell is in the discharge space. M × n are formed.

  FIG. 3 is a configuration diagram of a plasma display device using the panel driving method according to the first embodiment of the present invention. The plasma display device includes a panel 1, a data electrode drive circuit 12, a scan electrode drive circuit 13, a sustain electrode drive circuit 14, a timing generation circuit 15, an AD (analog / digital) converter 18, a scan number conversion unit 19, and a subfield. A conversion unit 20 and a power supply circuit (not shown) are provided.

  In FIG. 3, the image signal sig is input to the AD converter 18. Further, the horizontal synchronizing signal H and the vertical synchronizing signal V are given to the timing generation circuit 15, the AD converter 18, the scanning number conversion unit 19, and the subfield conversion unit 20. The AD converter 18 converts the image signal sig into digital image data, and supplies the image data to the scanning number conversion unit 19. The scanning number conversion unit 19 converts the image data into image data corresponding to the number of pixels of the panel 1 and supplies the image data to the subfield conversion unit 20. The subfield conversion unit 20 divides the image data of each pixel into a plurality of bits corresponding to a plurality of subfields, and outputs the image data for each subfield to the data electrode driving circuit 12. The data electrode drive circuit 12 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes.

  Timing generating circuit 15 generates a timing signal based on horizontal synchronizing signal H and vertical synchronizing signal V, and supplies the timing signal to scan electrode driving circuit 13 and sustain electrode driving circuit 14, respectively. Scan electrode drive circuit 13 supplies a drive waveform to scan electrodes SCN1 to SCNn based on the timing signal, and sustain electrode drive circuit 14 supplies a drive waveform to sustain electrodes SUS1 to SUSn based on the timing signal.

  Next, a method for driving the panel will be described. In the first embodiment, one field is divided into 10 subfields (SF1, SF2,..., SF10), and each subfield is (1, 2, 3, 6, 11, 18, 30, 44). , 60, 80). In this way, the luminance weight is configured to increase in the rear subfield. That is, the first subfield constituting one field is a subfield having the smallest luminance weight in the sustain period, and the subsequent subfield is a subfield in which the luminance weight in each sustain period is larger than the luminance weight of the immediately preceding subfield. It is. At this time, it may be set equal to the luminance weight of the immediately preceding subfield.

  FIG. 4 is a diagram showing combinations of display gradations and subfields that emit light to express the gradations. Here, the subfield indicated by “1” is a subfield that emits light, and the subfield indicated by “0” is a subfield that does not emit light. 4A shows gradation values from “0” to “64”, FIG. 4B shows gradation values from “65” to “128”, and FIG. 4C shows gradation values “129”. From FIG. 4 to FIG. 193, FIG. 4D shows the range of gradation values from “194” to “255”.

  A characteristic point in FIG. 4 is that, except for the first SF, there is no display floor so that two or more non-light-emitting subfields (hereinafter abbreviated as “intermediate non-light-emitting subfield”) preceding the light-emitting subfield are not continuous. The key is the key selected. The reason for the exception of the first SF is that the initialization of the first SF is all-cell initialization as will be described later. In other words, the gray scale used for image display is limited to a gray scale in which two or more subfields for selective initialization and non-light emission do not continue immediately before the subfield for selective initialization and light emission.

  Next, a driving waveform for driving the panel and its operation will be described. FIG. 5 is a drive waveform diagram applied to each electrode of the panel according to Embodiment 1 of the present invention, and FIG. 6 is a configuration diagram of subfields constituting one field. Here, the initialization operation of the first SF is an all-cell initialization operation, and the initialization operation after the second SF is a selective initialization operation.

  In the initializing period of the first SF, the data electrodes D1 to Dm and the sustain electrodes SUS1 to SUSn are held at 0 (V), and rise toward the voltage Vr (V) exceeding the discharge start voltage with respect to the scan electrodes SCN1 to SCNn. Apply the ramp voltage. Thereafter, sustain electrodes SUS1 to SUSn are maintained at positive voltage Vh (V), and a ramp voltage that decreases toward voltage Va (V) is applied to scan electrodes SCN1 to SCNn. Then, two weak initializing discharges are caused in all the discharge cells, wall charges necessary for the subsequent address operation are formed, and priming occurs in all the discharge cells.

  In the subsequent address period, scan electrodes SCN1 to SCNn are temporarily held at Vs (V). Next, a positive address pulse voltage Vw (V) is applied to the data electrode Dk of the discharge cell to be displayed in the first row among the data electrodes D1 to Dm, and the scan pulse voltage is applied to the scan electrode SCN1 in the first row. Vb (V) is applied. Then, address discharge occurs between scan electrode SCN1, data electrode Dk (k = 1 to m), and sustain electrode SUS1, and wall charges necessary for the sustain discharge following this discharge cell are accumulated. On the other hand, wall charges are not accumulated in the discharge cells to which the positive address pulse voltage Vw (V) is not applied. The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, first, sustain electrodes SUS1 to SUSn are returned to 0 (V), and positive sustain pulse voltage Vm (V) is applied to scan electrodes SCN1 to SCNn. At this time, in the discharge cell in which the address discharge has occurred, the voltage due to the wall charges is added to the sustain pulse voltage Vm (V), and the sustain discharge is generated exceeding the discharge start voltage. Then, the wall charges with the polarity reversed accumulate in the discharge cell. Subsequently, when the scan electrodes SUS1 to SUSn are returned to 0 (V) and a positive sustain pulse voltage Vm (V) is applied to the sustain electrodes SUS1 to SUSn, a sustain discharge occurs in the discharge cell, and the polarity of the wall charges is reversed. To do. Thereafter, similarly, by applying sustain pulses alternately to scan electrodes SCN1 to SCNn and sustain electrodes SUS1 to SUSn, the sustain discharge is continuously performed in the discharge cells in which the address discharge has occurred in the address period. It should be noted that a large amount of priming occurs in the discharge cell in which the sustain discharge has occurred along with the sustain discharge at this time.

  In the initialization period of the second SF, sustain electrodes SUS1 to SUSn are held at Vh (V), data electrodes D1 to Dm are held at 0 (V), and scan electrodes SCN1 to SCNn are supplied with voltage Va (V). Apply ramp-down voltage. Then, in a discharge cell that has undergone a sustain discharge in the sustain period of the previous subfield, a weak initializing discharge occurs, and wall charges necessary for the subsequent address operation are formed. On the other hand, the discharge cells in which the address discharge and the sustain discharge were not performed in the previous subfield are not discharged, and the wall charge state at the end of the initialization period of the previous subfield is maintained as it is. As described above, the initializing operation in the selective initializing subfield is a selective initializing operation in which initializing discharge is performed in the discharge cells that have undergone sustain discharge in the previous subfield.

  In the address period of the second SF, the address discharge is generated in the discharge cells to which the address pulse voltage Vw (V) is applied, as in the address period of the first SF. At this time, since sufficient priming associated with the sustain discharge remains in the discharge cell that has undergone the sustain discharge in the first SF, a stable address operation with a small discharge delay is performed. On the other hand, since the priming associated with the initialization of all the cells in the first SF remains in the discharge cells in which the sustain discharge has not been performed in the first SF, a stable address operation with a small discharge delay is performed.

  In the sustain period of the second SF, a sustain discharge is generated in the discharge cell that has caused the address discharge as in the sustain period of the first SF, and a large amount of priming occurs. Since the luminance weight of the second SF is larger than the luminance weight of the first SF, the amount of priming that occurs at this time is also larger than the amount of priming that occurs during the sustain period of the first SF.

  Since the operation of the initialization period of the third SF is the same as that of the second SF, description thereof is omitted. In the address period of the third SF, the address discharge is generated in the discharge cells to which the address pulse voltage Vw (V) is applied, as in the address period of the second SF. At this time, since sufficient priming associated with the sustain discharge remains in the discharge cell that has undergone the sustain discharge in the first SF or the second SF, a stable address operation with a small discharge delay is performed. On the other hand, since the priming associated with the initialization of all the cells in the first SF still remains in the discharge cells in which neither the first SF nor the second SF has been subjected to the sustain discharge, a stable address operation with a small discharge delay is performed. In the sustain period of the third SF, a sustain discharge occurs in the discharge cell that has caused the address discharge in the same manner as the sustain period of the second SF, and a large amount of priming occurs. Since the luminance weight of the third SF is larger than the luminance weight of the second SF, the amount of priming generated at this time is also larger than the amount of priming generated during the sustaining period of the second SF.

  In the address period of the fourth SF, as is apparent from FIG. 4, the discharge cells that should generate the address discharge are limited to discharge cells that have undergone the sustain discharge in at least the second SF or the third SF. Therefore, since sufficient priming associated with the sustain discharge up to the third SF remains in these discharge cells, a stable address operation with a small discharge delay is performed. In the sustain period of the fourth SF, a sustain discharge is generated in the discharge cell in which the address discharge has occurred, and a priming more than the priming amount generated in the sustain period of the third SF occurs.

  Also in the address period after the fifth SF, as is apparent from FIG. 4, the discharge cells that should generate the address discharge are limited to the discharge cells that have undergone the sustain discharge in the previous subfield or the previous subfield. . Therefore, since sufficient priming associated with the sustain discharge of the subfields so far remains in these discharge cells, a stable address operation with a small discharge delay is performed. In the subsequent sustain period, a sustain discharge occurs in the discharge cell in which the address discharge has occurred, and more priming occurs.

  As described above, in the subfields after the third SF, the luminance weight becomes larger as the subfield becomes later, and the priming amount generated so far also increases. Then, the discharge cells that should generate the address discharge do not have two or more intermediate non-light emitting subfields, except for the first SF. Accordingly, in the subfields after the third SF, the priming amount increases and the discharge delay also decreases as the subfield becomes later, so that the time for generating address discharge (hereinafter abbreviated as “address time”) is shortened. It becomes possible. In the first embodiment, the address time per cell from the first SF to the tenth SF is set to (2.4 μs, 2.4 μs, 2.1 μs, 2.1 μs, respectively, without impairing the stability of the address discharge. 2.1 μs, 1.8 μs, 1.8 μs, 1.8 μs, 1.7 μs, 1.7 μs). This means that when writing 240 vertical pixels in the sub-field writing period, the total writing period required per field is 4.78 ms, and the writing time per cell from the first SF to the 10th SF is uniformly 2 In the case of .4 μs, the writing period required per field is shortened by about 1 ms compared to the total of 5.76 ms.

  Here, the reason why the writing time can be set shorter in the rear subfield will be described again. The time required for addressing per discharge cell can be shortened as the discharge delay in address discharge is shorter. When the driving voltage is constant, the discharge delay generally becomes shorter as the amount of priming increases.

  In the subfield configuration in the first embodiment, the all-cell initializing operation is performed in the initializing period of the first SF, and priming is supplied to all the discharge cells. However, in addition to the weak initializing discharge, the amount of priming rapidly decreases with time. Therefore, when the priming relies only on the initializing discharge of the first SF, stable address discharge is performed. The effect can only be expected up to the first three subfields of one field. However, in the first embodiment of the present invention, as shown in FIG. 4, after the third SF, the gradation is selected so that the intermediate non-light emitting subfield does not continue, and the image display is performed. Therefore, in the discharge cells in which the subfields after the fourth SF emit light, light emission, that is, sustain discharge is always performed in at least one subfield of the previous subfield or the previous subfield. Since the sustain discharge is a very strong discharge and the amount of priming is very large, the discharge delay of the address discharge in the address period of the subsequent subfield is reduced, and the address time can be shortened. That is, the time for generating the address discharge in the subfield for performing the selective initialization operation can be set shorter than the time for generating the address discharge in the immediately preceding subfield.

  In addition, when the gradation for image display is limited in this way, gradation that cannot be displayed occurs. For these gradation that cannot be displayed, error diffusion or The image can be displayed in a pseudo manner using a known image display technique such as dither processing.

  In addition, since the writing period of the subfield having a small luminance weight, that is, a short sustaining period is long and the writing period of the subfield having a long sustaining period is short, the time difference between the subfields constituting one field is set small. be able to. Therefore, it is advantageous in improving the moving image pseudo contour using error diffusion, dither processing, or the like.

(Embodiment 2)
FIG. 7 is a configuration diagram of a plasma display device using the panel driving method according to Embodiment 2 of the present invention.

  As in the first embodiment, the plasma display device in the second embodiment includes the panel 1, the data electrode drive circuit 12, the scan electrode drive circuit 13, the sustain electrode drive circuit 14, the timing generation circuit 15, the AD converter 18, and the number of scans. A conversion unit 19 and a subfield conversion unit 20 are provided. A significant difference from the first embodiment is that an APL (Average Picture Level) detection unit 30 is provided.

  In FIG. 7, the image signal sig is input to the AD converter 18, and the APL detection unit 30 detects the average luminance level of the image data. Timing generating circuit 15 generates a timing signal based on horizontal synchronizing signal H and vertical synchronizing signal V, and supplies the timing signal to scan electrode driving circuit 13 and sustain electrode driving circuit 14, respectively. Scan electrode drive circuit 13 supplies a drive waveform to scan electrodes SCN1 to SCNn based on the timing signal, and sustain electrode drive circuit 14 supplies a drive waveform to sustain electrodes SUS1 to SUSn based on the timing signal. Here, the timing generation circuit 15 determines the initialization operation of each subfield constituting one field based on the APL output from the APL detection unit 30 as either all-cell initialization or selective initialization, The number of all-cell initialization operations in one field is controlled.

  Next, the subfield configuration of the driving method according to the second embodiment will be described. Also in the present embodiment, although one field is described as being composed of ten subfields, the number of subfields and the luminance weight of each subfield are not limited.

  FIG. 8 is a diagram showing a subfield configuration of the panel driving method according to the embodiment of the present invention, and the subfield configuration is switched based on the APL of the image signal to be displayed. FIG. 8A shows a configuration used when an APL is 0 to 1.5% for an image signal. The all-cell initialization operation is performed only during the initialization period of the first SF, and the initialization periods of the second SF to the tenth SF are This is a subfield configuration for performing a selective initialization operation. FIG. 8B shows a configuration used when an APL has an image signal of 1.5 to 5%. The initialization periods of the first SF and the fourth SF are the all-cell initialization period, the second SF, the third SF, and the fifth SF. The initialization period of the tenth SF has a subfield configuration that is a selective initialization period. FIG. 8C shows a configuration used for an image signal having an APL of 5 to 100%. The initialization periods of the first SF, the fourth SF, and the sixth SF are the all-cell initialization period, the second SF, the third SF, and the fifth SF. The initialization period of the seventh SF to the tenth SF has a subfield configuration that is a selective initialization period. Table 1 shows the relationship between the above-described subfield configuration and APL. The table also shows the write time per cell.

  As described above, in the second embodiment of the present invention, it is considered that there is no black display area or a small area when displaying an image with a high APL. Therefore, by increasing the number of all-cell initializations and increasing priming. The discharge is stabilized. Conversely, when an image with a low APL is displayed, the black image display area is considered to be wide, so the number of all-cell initializations is reduced and the black display quality is improved. Therefore, even if there is a region with high luminance, if the APL is low, it is possible to display an image with low luminance and high contrast in the black display region.

  When the all-cell initialization operation is performed only during the initialization period of the first SF, as in the first embodiment, the write time per cell from the first SF to the 10th SF is (2.4 μs, 2.. 4 μs, 2.1 μs, 2.1 μs, 2.1 μs, 1.8 μs, 1.8 μs, 1.8 μs, 1.7 μs, 1.7 μs). Also, when the all-cell initialization operation is performed in the initialization period of the first SF and the fourth SF, or when the all-cell initialization operation is performed in the initialization period of the first SF, the fourth SF, and the sixth SF, the first SF to the first SF The programming time per cell up to 10 SF (1.8 μs, 1.8 μs, 1.8 μs, 1.8 μs, 1.8 μs, 1.8 μs, 1.8 μs, 1.8 μs, 1.7 μs, 1. 7 μs).

  As described above, when the number of all-cell initialization operations is small and priming is insufficient, the writing time of the first SF is set relatively long, and the writing time of the subsequent subfield is set short. In addition, when there are two or more subfields for performing the all-cell initialization operation and priming is supplied to some extent, the write time of the first SF is set relatively short, and the write time of the subsequent subfield is set to be short. It is better to set it shorter.

  In the present embodiment, one field is configured with 10SF, the number of all-cell initializations is controlled within a range of 1 to 3, and the initialization of the subfield close to the top is prioritized. The present invention is not limited to this.

  Further, in the embodiment of the present invention, a gradation in which two or more intermediate non-light-emitting subfields are not used is used as a gradation for image display, but the gradation condition for image display is slightly relaxed, It is not impossible to use a gradation in which three or more intermediate non-light emitting subfields are not continuous.

  According to the panel driving method of the present invention, it is possible to suppress an increase in black luminance and shorten a writing period while guaranteeing a stable writing operation, which is useful as an image display device using the panel. is there.

The perspective view which shows the principal part of the panel used for Embodiment 1 of this invention. Electrode arrangement of the panel Configuration diagram of plasma display device using panel driving method according to Embodiment 1 of the present invention The figure which shows the combination of the display gradation and the subfield which emits light in order to express the gradation The figure which shows the combination of the display gradation and the subfield which emits light in order to express the gradation The figure which shows the combination of the display gradation and the subfield which emits light in order to express the gradation The figure which shows the combination of the display gradation and the subfield which emits light in order to express the gradation Drive waveform diagram applied to each electrode of panel in embodiment 1 of the present invention Configuration diagram of subfields constituting one field in Embodiment 1 of the present invention Configuration diagram of plasma display device using panel driving method in embodiment 2 of the present invention The figure which shows the subfield structure of the drive method of the panel in Embodiment 2 of this invention.

Explanation of symbols

1 Panel 2 Front substrate 3 Back substrate 4 Scan electrode 5 Sustain electrode 9 Data electrode

Claims (3)

A method for driving a plasma display panel in which discharge cells are formed at intersections of scan electrodes, sustain electrodes, and data electrodes,
One field period includes an initializing period for generating an initializing discharge in the discharge cell, an addressing period for generating an addressing discharge in the discharge cell, and a sustaining for generating a sustaining discharge for causing the discharge cell to emit light with a predetermined luminance weight. Consists of a plurality of subfields having a period,
The initializing period of each of the plurality of subfields includes an all-cell initializing operation for generating an initializing discharge for all discharge cells that perform image display, or a discharge cell that has generated a sustaining discharge in the immediately preceding subfield. In response to the selective initializing operation that selectively generates the initializing discharge,
Driving a plasma display panel, wherein a time for generating an address discharge in a subfield for performing the selective initialization operation is set to be shorter or equal to a time for generating an address discharge in the immediately preceding subfield Method. The multi-gradation display is performed by performing a control to emit or not emit light in each sustain period of the plurality of subfields,
2. The configuration according to claim 1, wherein two or more subfields that are selectively initialized and do not emit light immediately before the subfield that performs selective initialization and emit light have a gradation that is not continuous. Driving method of plasma display panel. The first subfield constituting one field is a subfield having the smallest luminance weight in the sustain period, and subsequent subfields are subfields in which the luminance weight in each sustain period is greater than or equal to the luminance weight of the immediately preceding subfield. 3. The method for driving a plasma display panel according to claim 1, wherein the driving method is a field.

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