JP2008047244A - Semiconductor memory device, semiconductor device, and method for writing data - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device, a semiconductor device and a method for writing data that improve a writing speed. <P>SOLUTION: The semiconductor memory device includes: a memory cell array 20; an output buffer 29 that outputs an enable signal/CE2 that enables an external memory device 3 to operate; an address buffer 33 that produces an address ADDint where data is stored in the external memory device 3; an input buffer 27 that receives the data to be stored at the address ADDint from the external memory device 3; and a write data buffer 25 that stores the data received at the input buffer 27 and writes the data in a plurality of memory cells collectively. The input buffer 27 receives the data of a size written in the memory cells MC's collectively from the external memory 3 every time the write data buffer 25 writes data. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, a semiconductor device, and a data writing method. For example, the present invention relates to a semiconductor memory including a MOS transistor having a floating gate and a control gate.

  Conventionally, an EEPROM (Electrically Erasable and Programmable ROM) is known as a nonvolatile semiconductor memory capable of electrically rewriting data. In an application system, the EEPROM may be used for the purpose of storing a program for operating the application. In this case, the program is written in the EEPROM at the time of system manufacture.

At this time, the amount of data to be written has a relatively large capacity such as 128 Mbits, but the amount of data that can be written with a single write command in the EEPROM is, for example, about 8 words (= 128 bits). Therefore, it is necessary to repeatedly input a write command to the EEPROM (see, for example, Patent Documents 1 and 2). Therefore, there is a problem that it takes a very long time to write data.
JP 2005-182983 A JP-A-5-81145

  The present invention provides a semiconductor memory device, a semiconductor device, and a data writing method capable of improving the writing speed.

  A semiconductor memory device according to an aspect of the present invention is a semiconductor memory device that can be connected to an external memory device, and includes a plurality of memory cells including a charge storage layer and a control gate formed on the charge storage layer Are arranged in a matrix, a word line that commonly connects the control gates of the memory cells in the same row in the memory cell array, and an enable signal that enables the external memory device to operate. An output buffer for outputting to the memory device; an address buffer for outputting an address of data to be read in the external memory device; and the address buffer from the external memory device operable by the enable signal. Input to receive the data held at the address output from A buffer and a write data buffer that holds the data received by the input buffer and writes the data to a plurality of the memory cells connected to the same word line in a batch. Each time the write data buffer writes data to the memory cell, it receives from the external memory the data of a size to be written to the memory cell at once.

  A semiconductor device according to one aspect of the present invention is a semiconductor device including first and second semiconductor chips in the same package, and is operable by a first enable signal and can hold data. A first semiconductor chip including a storage device, and a second semiconductor storage device including a memory cell that is operable by a second enable signal and includes a charge storage layer and a control gate formed on the charge storage layer. A second semiconductor chip, a data bus that connects the first and second semiconductor chips so that they can communicate with each other, and a first bus that is electrically connected to the data bus and that can receive the first enable signal from the outside. An external pin and a second external pin electrically connected to the data bus and capable of inputting the second enable signal from the outside, and electrically connected to the data bus And a third external pin commonly used for the first and second semiconductor chips and capable of inputting the data from outside, and a common external address signal for the first and second semiconductor chips. A fourth external pin that can be input, and when the data is written to the first semiconductor memory device, the first semiconductor chip receives the first enable signal input to the first external pin. The second semiconductor memory device is operable in response to the data input to the third external pin and the address signal input to the fourth external pin. The first semiconductor chip is operable by the generated first enable signal, and the address signal generated by the second semiconductor chip is applied to the first semiconductor chip. By being, writing the data held in the first semiconductor memory device to the memory cell.

  Furthermore, the data writing method according to one aspect of the present invention is a semiconductor memory device having a plurality of memory cells that can be connected to an external memory device and includes a charge storage layer and a control gate formed on the charge storage layer. A method of writing data, wherein a step of writing data of a first data size to the external memory device, and after the writing to the external memory device is completed, the semiconductor memory device is performing a write operation A step of generating a flag; a step of allowing the semiconductor memory device to operate the external memory device after generating the in-execution flag; and a voltage generating circuit included in the semiconductor memory device includes a first internal for writing Generating a voltage; and wherein the semiconductor memory device reduces the data from the external memory device to be smaller than the first data size. Reading in units of second data size, writing the data in the memory cells in units of the second data size using the first internal voltage, and the data to the memory cells for all of the data After the writing of data is completed, the voltage generation circuit generates a second internal voltage for verification, and the semiconductor memory device reads the data from the external memory device again in units of a second data size. Verifying the data written to the memory cell using the second internal voltage and the data read again from the external memory device; and after executing the verify for all the data, Stopping generation of the middle flag.

  According to the present invention, it is possible to provide a semiconductor memory device, a semiconductor device, and a data writing method capable of improving the writing speed.

  Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

[First Embodiment]
A semiconductor memory device, a semiconductor device, and a data writing method according to a first embodiment of the present invention will be described. FIG. 1 is a block diagram of a memory system according to this embodiment.

  As shown in the figure, the memory system 1 includes an EEPROM 2, a RAM 3, a CPU 4, a regulator circuit 5, a power supply circuit 6, an input device 7, an input interface (I / F) controller 8, a display device 9, a display device controller 10, a data bus 11, An address bus 12 is provided. In the figure, white arrows indicate the flow of address signals, black arrows indicate the flow of data, broken arrows indicate the flow of control signals, and solid arrows indicate the flow of power supply voltage.

The EEPROM 2 is, for example, a NOR flash memory, and holds programs and the like necessary for the system 1 to operate. The detailed configuration of the EEPROM will be described later.
The RAM 3 is, for example, SRAM or PSRAM (Pseudo SRAM). It may be a DRAM or the like.
The CPU 4 performs various arithmetic processes using a program held in the EEPROM 2 and using the RAM 3 as its work area. The CPU 4 selects the EEPROM 2 and RAM 3 and controls the operation of each block in the system 1.

The power supply circuit 6 is a battery or a battery, for example, and generates a predetermined voltage.
The regulator circuit 5 converts the voltage generated by the power supply circuit 6 into an optimum voltage for each block in the system 1 to operate.
The input device 7 is, for example, a keyboard and receives input from a user who uses the system 1.
The input I / F controller 8 controls the operation of the input device 7 according to the control of the CPU 4. Then, the data input from the input device 7 is transferred to the CPU 4.

The display device 9 is a liquid crystal panel or the like, for example, and displays a calculation result or the like in the CPU 2.
The display device controller 10 controls the operation of the display device 9 according to the control of the CPU 4. Then, the data to be displayed is output to the display device 9.

  The data bus 11 and the address bus 12 connect the EEPROM 2, the RAM 3, the CPU 4, and the display device controller 10 to each other. The data bus 11 and the address bus 12 transfer data and address signals between each other.

  In the above configuration, the CPU 4 functions as a host device for the EEPROM 2 and the RAM 3, and data is written to the EEPROM 2 and the RAM 3 and data is read from the EEPROM 2 and the RAM 3 in accordance with a request from the CPU 4. The EEPROM 2 and the RAM 3 are, for example, semiconductor devices packaged in different packages, and each have a connection pin with the outside. That is, each semiconductor device has a data pin connected to the data bus 11 and used for data input / output, an address pin connected to the address bus 12 and used for input / output of an address signal, a write enable signal, an output enable signal, etc. And a chip select pin to which a chip select signal for chip selection among the control signals is input. The EEPROM 2 can generate a chip enable signal for the RAM 3, and the chip enable signal can be input to the chip select pin of the RAM 3.

  Next, the configuration of the EEPROM 2 will be described with reference to FIG. FIG. 2 is a block diagram of the EEPROM 2. As shown, the EEPROM 2 includes a memory cell array 20, a row decoder 21, a column decoder 22, a column selector 23, a source line driver 24, a write data buffer 25, a sense amplifier 26, a data input / output buffer 27, a command register 28, and an output buffer 29. , An input / output buffer 30, an input buffer 31, an address register 32, an address input / output buffer 33, a voltage generation circuit 34, a verify circuit 35, and a control circuit 36.

  The memory cell array 20 includes a plurality of NOR flash memory cells arranged in a matrix. Each memory cell is connected to a bit line, a word line, and a source line. The row decoder 21 selects the row direction of the memory cell array 20. That is, the word line is selected. The column decoder 22 selects the column direction of the memory cell array 20. The column selector 23 selects a bit line based on the selection operation of the column decoder 22 and connects the bit line to the write data buffer 25 or the sense amplifier 26. The source line driver 24 applies a voltage to the source line. The sense amplifier 26 senses and amplifies data read from the memory cell selected by the row decoder 21 and the column decoder 22. The write data buffer 25 holds data to be written to the memory cells, and writes data to the memory cells in batches in a predetermined memory cell unit.

  The input buffer 31 receives the chip enable signal / CE1 input from the CPU 4 to the chip select pin. Then, the chip enable signal / CE1 is input to the command register 28. The chip enable signal / CE1 is a signal that enables the EEPROM 2 to operate.

  The input / output buffer 30 receives the write enable signal / WE and the output enable signal / OE input from the CPU 4 to the control pin and inputs them to the command register 28. The write enable signal / WE is a signal for permitting a write operation, and the output enable signal / OE is a signal for permitting the output of data. The input / output buffer 30 outputs a write enable signal / WE and an output enable signal / OE to the RAM 3.

  The output buffer 29 outputs a chip enable signal / CE2 to the RAM 3. The chip enable signal / CE2 is a signal that permits the operation of the RAM 3.

  The data input / output buffer 27 receives data input to the data pin from the RAM 3 or the like, and transfers it to the write data buffer. The data amplified by the sense amplifier 26 is output from the data pin to the outside.

  The command register 28 holds the chip enable signal / CE1 received by the input buffer 31, the write enable signal / WE received by the input / output buffer 30, and the output enable signal / OE. The output buffer 29 is instructed to output a chip enable signal / CE2, and the input / output buffer 30 is instructed to output a write enable signal / WE and an output enable signal / OE.

  The address register 32 outputs a column address CA to the column decoder 22 and outputs a row address RA to the row decoder 21. The column decoder 22 and the row decoder 21 perform a bit line and word line selection operation based on the column address CA and the row address RA, respectively. The address register 32 generates an address and outputs the generated address to the address input / output buffer 33. The address input / output buffer 33 outputs the address generated by the address register 32 to the RAM 3.

  The voltage generation circuit 34 generates a voltage. The verify circuit 35 performs a verify operation using the data in the write data buffer and the read data amplified by the sense amplifier. The control circuit 36 controls the operation of the circuit.

  Next, the configuration of the memory cell array 20 and the write data buffer 25 will be described with reference to FIG. FIG. 3 is a circuit diagram showing the configuration of the memory cell array and the write data buffer 25.

  First, the memory cell array 20 will be described. As shown in the figure, the memory cell array 20 includes ((m + 1) × (n + 1)) (m and n are natural numbers) memory cells MC. The memory cell MC is a MOS transistor having a stacked gate including a charge storage layer (for example, a floating gate) and a control gate. The control gates of the memory cells MC in the same row are commonly connected to any one of the same word lines WL0 to WLm. The drains of the memory cells MC in the same column are commonly connected to any one of the same bit lines BL0 to BLn. Further, the sources of the memory cells MC are commonly connected to the same source line SL. Hereinafter, for convenience of explanation, the word lines WL0 to WLm may be collectively referred to as the word line WL, and the bit lines BL0 to BLn may be collectively referred to as the bit line BL. A set of (n + 1) memory cells MC connected to the same word line is hereinafter referred to as “page”. Note that the “page” only needs to be a set of a plurality of memory cells connected to the same word line, but in this embodiment, a set of (n + 1) memory cells is used for simplicity of explanation. A description will be given using a case where “page” is used and the data size of one page is 128 bits.

  The write data buffer 25 holds data to be written to the memory cell for one page (128 bits) at maximum. Then, data is written to the plurality of memory cells MC at once. The unit of data to be collectively written is, for example, one word (for example, 16 bits). That is, data is simultaneously output to the bit line for one word selected by the column selector 23. Therefore, to write the data for one page, it is necessary to repeat the writing operation for one word eight times.

Next, a cross-sectional configuration of the memory cell MC will be described with reference to FIG. FIG. 4 is a cross-sectional view of a partial region of the memory cell array 20. As shown, an n-type well region 41 is formed in the surface region of the p-type semiconductor substrate 40, and a p-type well region 42 is formed in the surface region of the n-type well region 41. A gate insulating film 43 is formed on the p-type well region 42, and a gate electrode of the memory cell MC is formed on the gate insulating film 43. The gate electrode of the memory cell MC has a polycrystalline silicon layer 44 formed on the gate insulating film 43 and a polycrystalline silicon layer 46 formed on the polycrystalline silicon layer 44 with an inter-gate insulating film 45 interposed therebetween. ing. The inter-gate insulating film 43 is formed of, for example, a silicon oxide film, or an ON film, a NO film, or an ONO film that has a stacked structure of a silicon oxide film and a silicon nitride film. The polycrystalline silicon layer 44 functions as a floating gate (FG) and is separated for each memory cell MC. On the other hand, the polysilicon layers 46 adjacent to each other in the direction orthogonal to the bit lines are commonly connected and function as a control gate (word line WL). An n ⁺ -type impurity diffusion layer 47 is formed in the surface of the p-type well region 42 located between adjacent gate electrodes. The impurity diffusion layer 47 is shared by adjacent transistors and functions as a source region or a drain region. The source region of the memory cell MC is connected to the source line SL, and the drain is connected to the bit line BL. Further, a p ⁺ -type impurity diffusion layer 48 is formed in the surface region of the p-type well region 42, and an n ⁺ -type impurity diffusion layer 49 is formed in the surface region of the n-type well region 41. The same potential as the source line SL is applied to the p-type well region 42 through the impurity diffusion layer 48, and the well voltage VNW is applied to the n-type well region 41 through the impurity diffusion layer 49. .

  Next, a method of writing data to the EEPROM 2 in the memory system 1 having the above configuration will be described. In the memory system 1 according to the present embodiment, when data is written to the EEPROM 2, the RAM 3 is used as a data buffer. That is, first, data is temporarily written to the RAM 3, and then data is written from the RAM 3 to the EEPROM 2. As for the write operation, first, the operations among the EEPROM 2, RAM 3 and CPU 4 will be described with reference to FIG. 5, and the operation within the EEPROM 2 will be described with reference to FIG.

  FIG. 5 is a flowchart showing the flow of operations among the EEPROM 2, RAM 3, and CPU 4. As shown in the figure, first, writing of data to the RAM 3 is started (step S10). In writing data to the RAM 3, the CPU 4 outputs a chip enable signal / CE2 to the RAM 3, makes the RAM 3 operable, and initializes the RAM 3 (step S11). Next, the CPU 4 inputs a head address in the address space of the RAM 3 as a data write address to the RAM 3 (step S12). At this time, since the chip enable signal / CE 1 is negated (“H” level), the EEPROM 2 is in a non-operating state, and the address signal is input to the RAM 3 via the address bus 12. Then, the data is input to the RAM 3 via the data bus 11, and the data is written to the RAM 3 (step S13). Since writing to the RAM 3 normally ends in one write cycle per address, it is very fast. When the writing of all data to the RAM 3 is completed (step S14, YES), the writing operation to the RAM 3 is thereby completed (step S15).

  Next, a data write operation from the RAM 3 to the EEPROM 2 is started (step S16). First, a data write command is input to the EEPROM 2 (step S17). The write command is given from the RAM 3 or the CPU 4. Further, the chip enable signal / CE1 is asserted (“L” level), and the EEPROM 2 enters an operating state. Next, a write start address is set in the EEPROM 2 (step S18). Thereafter, external driving of the chip enable signal / CE2 and the address signal, write enable signal / WE, and output enable signal / OE in the EEPROM 2 is prohibited (step S19). That is, the EEPROM 2 does not accept these signals from the CPU 4 thereafter.

  Then, the data held in the RAM 3 is written into the EEPROM 2 (step S20). Whether or not writing has been completed for all the data can be determined by the executing flag output from the EEPROM 2. Therefore, the CPU 4 reads the in-execution flag of the EEPROM 2 (step S21), and if all the data has been written (step S22, YES), the writing operation to the EEPROM 2 is completed. When completed, driving from the outside of the chip enable signal / CE2 and the address signal, write enable signal / WE, and output enable signal / OE in the EEPROM 2 is permitted (step S23).

  Next, the operation in the EEPROM 2 will be described with reference to FIG. FIG. 6 is a flowchart showing the flow of processing inside the EEPROM 2, and corresponds to the processing in step S20 in FIG. The data writing operation in the EEPROM 2 roughly includes two steps. That is, a step of writing data to the memory cell MC and a step of verifying whether or not the writing to the memory cell MC has been normally performed. Hereinafter, the former is called a program operation, and the latter is called a verify operation.

  First, the EEPROM 2 outputs a running flag to the CPU 4 (step S30). The in-execution flag is a flag indicating that the writing operation to the EEPROM 2 is being performed as described above. Next, in response to receiving the write command, the control circuit 36 instructs the command register 28 to output the chip enable signal / CE2. Then, the command register 28 outputs the chip enable signal / CE2 from the output buffer 29 (step S31). As a result, the RAM 3 becomes operable. That is, at this time, both the EEPROM 2 and the RAM 3 included in the memory system 1 are operable.

  Then, the program operation is started (step S32). In starting the program operation, the control circuit 36 first sets the data write start address (step S33). This information is given from the control circuit 36 to the address register 32. The address register 32 generates a row address RA and a column address CA according to the set write head address. Next, the voltage generation circuit 34 generates an internal voltage for programming in accordance with a command from the control circuit 36 (step S34). This internal voltage is applied to the row decoder 21 and the write data buffer 25, for example.

  The EEPROM 2 reads data for one word from the RAM 3 (step S35). Then, the read data for one word is programmed into the memory cell MC (step S36). The state of steps S35 and S36 will be described in detail with reference to FIG. FIG. 7 is a block diagram of the EEPROM 2. As shown in the figure, the address register 32 generates an internal address ADDint in response to the address generation command of the control circuit 36 in step S35. The internal address ADDint is an address signal in the RAM 3 of data to be read from the RAM 3. Since data is read from the RAM 3 in units of one word, the address register 32 updates the internal address ADDint each time data for one word is read from the RAM 3. The internal address ADDint when reading data from the RAM 3 for the first time corresponds to the head address in the address space of the RAM 3. This information is given in advance from the CPU 4 to the EEPROM, for example, and the EEPROM 2 itself grasps this information. The address generated in the address register 32 is given from the address input / output buffer 33 to the RAM 3. Further, the input / output buffer 30 outputs an output enable signal / OE to the RAM 3 in accordance with an output enable signal output command from the control circuit 36 and the command register 28. This process may be performed in advance in step S31. Then, since the chip enable signal / CE2 and the output enable signal / OE are asserted and the address signal is input to the RAM 3, the data for one word held in the area corresponding to the address signal is stored in the EEPROM 2. Output.

  The EEPROM 2 receives the data for one word output from the RAM 3 by the data input / output buffer 27 and transfers it to the write data buffer 25. Then, the write data buffer 25 programs the transferred data to the memory cells for one word connected to the bit line selected by the column decoder 22 and the word line selected by the row decoder 21 ( Step S36).

  If the program has not been completed for all addresses (step S37, NO), the address register 32 advances the internal address ADDint by one word according to the instruction of the control circuit 36 (step S38). That is, the address register 32 generates an internal address ADDint corresponding to the data for one word next to the data for one word already written in the memory cell MC. That is, the internal address ADDint is updated so as to correspond to the next data. Then, steps S35 to S36 are repeated using the updated internal address ADDint.

  When the program is completed for all addresses (step S37, YES), the program operation is completed as described above (step S39). Next, a verify operation is started (step S40).

  At the start of the verify operation, the control circuit 36 first sets a verify address where data to be verified is held (step S41). The write start address is set as the verify address set first. This information is given from the control circuit 36 to the address register 32. The address register 32 generates a row address RA and a column address CA according to the set verify address. Next, the voltage generation circuit 34 generates an internal voltage for verification in accordance with a command from the control circuit 36 (step S42). This internal voltage is applied to the row decoder 21 and the write data buffer 25, for example.

  The EEPROM 2 reads verify data for one word from the RAM 3 (step S43). Then, using the read data for one word that has been read, the data for one word that has already been written is verified (step S44). Steps S43 and S44 will be described in detail. In step S43, the address register 32 generates the internal address ADDint in response to the address generation command of the control circuit 36. The internal address ADDint when reading data from the RAM 3 for the first time corresponds to the head address in the address space of the RAM 3. The address generated in the address register 32 is given from the address input / output buffer 33 to the RAM 3. As a result, the RAM 3 outputs the data for one word held in the area corresponding to the internal address ADDint to the EEPROM 2. This process is the same as step S35 at the time of programming.

  The EEPROM 2 receives the data for one word output from the RAM 3 by the data input / output buffer 27 and transfers it to the write data buffer 25. In addition, written data for one word is read from the memory cells for one word connected to the bit line selected by the column decoder 22 and the word line selected by the row decoder 21, and is sensed by a sense amplifier. Sense and amplified. The verify circuit 35 verifies the amplified read data using the data transferred to the write data buffer 25. That is, it is verified whether or not the data read from the memory cell MC matches the original correct data read from the RAM 3.

  If the data is not correctly written as a result of the verification (step S45, NO), the voltage generation circuit 34 generates an internal voltage for programming as in step S34 (step S46). Subsequently, as in step S35, data for one word corresponding to the address is read from the RAM 3 (step S47) and programmed (step S48). Since verify data has been read in step S43, this data may be written to the memory cell MC. In this case, step S47 can be omitted.

  If the data has been correctly written in step S45 (step S45, YES) and verification has not been completed for all addresses (step S49, NO), the address register 32 sets the internal address ADDint to 1 in accordance with the instruction of the control circuit 36. The word is advanced (step S50). That is, the address register 32 generates an internal address ADDint corresponding to the data for one word following the data for one word that has been verified. Then, steps S43 to S48 are repeated using the updated internal address ADDint.

When verify is completed for all addresses (step S49, YES), the verify operation is completed as described above (step S51). Then, the control circuit 36 initializes the internal power supply 34 to enter a stand-by state, and stops outputting the execution flag.
Thus, the writing operation in the EEPROM 2 is completed.

As described above, the memory system according to the present invention has the following effect (1).
(1) Data writing can be speeded up (part 1).
In the memory system according to the present embodiment, the RAM 3 is used as a buffer memory when writing data to the EEPROM 2. That is, write data is first temporarily written in the RAM 3. Thereafter, the EEPROM 2 reads the data in the RAM 3 and writes the data in the memory cell. Therefore, the speed of writing data to the EEPROM 2 can be improved without increasing the size of the write data buffer of the EEPROM 2.

  This effect will be described below in comparison with a case where the RAM 3 is not used as a buffer memory. FIG. 8 is a flowchart of the write operation to the EEPROM 2 when the RAM 3 is not used as a buffer memory.

  As shown in the drawing, first, when a write command is input to the EEPROM 2 (step S80), the voltage generation circuit generates an internal voltage for programming (step S81). Next, the write data in the write data buffer is updated (step S82). The write data buffer can hold, for example, one page of data, and can automatically write one page of data into the memory cell by one write command. In step S82, data for one word to be written is selected from the data for one page. Then, a program is performed for the data for one word selected in step S82 (step S83). Next, if the programming of the data for one page is not completed (step S84, NO), the address is updated to correspond to the data for the next one word in the write data buffer (step S85). The processes of S82 and S83 are performed.

  When the programming of the data for one page is completed (step S84, YES), the verify operation is performed next. That is, the voltage generation circuit generates an internal voltage for verification (step S86). Next, the verify data in the write data buffer is updated (step S87). That is, data for one word to be verified is selected from the data for one page. Then, one word of data is read from the memory cell MC, and the read data is verified (step S88). Next, if verification of data for one page is not completed (step S89, NO), the address is updated so as to correspond to data for the next one word in the write data buffer (step S90). The processes of S87 and S88 are performed.

  When the verification of the data for one page is completed (step S89, YES), flag determination is performed. If the program and verify have been completed for all pages (step S92, YES), the output of the execution flag is stopped and the write operation is completed. If not completed (step S92, NO), the process returns to step S80, and a series of processing is repeated.

  The above processing is shown as a timing chart in FIG. FIG. 9 is a timing chart showing chip enable signals / CE1, / CE2, write enable signal / WE, output enable signal / OE, and operation contents in the memory system in the write operation. An example in which one page size (the size of the write data buffer) is 128 bits, the size of data to be collectively written in the memory cells is one word (16 bits), and the total data size to be written is 128 Mbits will be described as an example. To do.

  As shown in the figure, the chip enable signal / CE2 is always negated ("H" level). When a write command is input at time t10, an internal voltage for programming is generated at the next time t11, and data update (step S82) and 1-word program (step S83) are performed at times t12 and t13, respectively. This data update and 1-word program are repeated (1 page size: 128 bits / 1 word size: 16 bits) = 8 times.

  When eight programs are completed, an internal voltage for verification is generated at time t14, and data update (step S87) and 1-word verification (step S88) are performed at times t15 and t16, respectively. This data update and 1-word verify are also repeated eight times.

When eight verifications are completed, flag determination is performed at time t17. The above processing from time t10 to t18 is repeated for all pages. That is, since the one-time command inputs (16 bits × 8 times) = 128-bit write is performed, all the data size when as the 128M bits, the above process is repeated 10 ⁶ times. Therefore, in order to write all data, it is necessary to perform write command input 10 ⁶ times, voltage generation 10 ⁶ times for each of program and verify, and flag determination 10 ⁶ times. In particular, the time required for voltage generation is relatively long as 3 to 4 μs, and the above method requires a long time for writing.

  This is because the data size writable by one command input is limited to the data size that can be held in the write data buffer 25. In other words, the larger the data size that can be held in the write data buffer 25, the more the write command input, voltage generation, and flag determination times can be reduced. However, when the data size that can be held in the write data buffer 25 is increased, the size of the write data buffer 25 is also increased, the ratio of the buffer 25 to the chip is increased, the chip size is increased, and the cost is increased. There's a problem.

  Compared to this, the method according to the present embodiment will be described. FIG. 10 is a flowchart of the write operation to the EEPROM 2 according to the present embodiment, and is a simplified illustration of FIG.

  As shown in the drawing, when a write command is first input to the EEPROM 2 (step S60), the voltage generation circuit 34 generates an internal voltage for programming (step S61). Next, write data for one word is read from the RAM 3 to the write data buffer 25 (step S62). Then, a program is performed for the data for one word read in step S62 (step S63). Next, if programming of all addresses, that is, all data is not completed (step S64, NO), the address is updated to correspond to the next one word data in the RAM 3 (step S65), and step S62. , S63 is performed.

  When the programming of all data is completed (step S64, YES), the verify operation is performed next. That is, the voltage generation circuit 34 generates an internal voltage for verification (step S66). Next, verify data for one word is read from the RAM 3 to the write data buffer (step S67). Then, one word of data is read from the memory cell MC, and the read data is verified (step S68). If verification of all the data has not been completed (step S69, NO), the address is updated so as to correspond to the next one word data in the RAM 3 (step S70), and the processes of steps S67 and S68 are performed. When the verification of all data is completed (step S69, YES), flag determination is performed and the write operation is completed.

  The above processing is shown as a timing chart in FIG. FIG. 11 is a timing chart showing chip enable signals / CE1, / CE2, write enable signal / WE, output enable signal / OE, and operation contents in the memory system 1 in the write operation according to the present embodiment. As in FIG. 9, an example will be described in which the size of one page is 128 bits, the size of data to be collectively written in memory cells is 1 word (16 bits), and the total data size to be written is 128 Mbits.

  The timing for enabling each control signal is, for example, as follows. Chip enable signals / CE1 and / CE2 are enabled ("L" level) at the time of each chip access. That is, the chip enable signal / CE1 is set to the “L” level at the time of command input and flag determination. The chip enable signal / CE2 is set to the “L” level when data is read from the RAM3. The output enable signal / OE is set to the “L” level when reading data or flags. The write enable signal WE is set to the “L” level only when a command is input.

As shown in the drawing, when a write command is input at time t0, chip enable signals / CE1 and / CE2 are asserted, and the EEPROM 2 and the RAM 3 are made operable. At the next time t1, a program internal voltage is generated. At times t2 and t3, data is read from the RAM 3 (step S62) and one word program (step S63) is performed. When reading data, the output enable signal / OE and the chip enable signal / CE2 are asserted. This data reading and 1-word program are repeated (total data size: 128M bits / 1 word size: 16 bits) = 8 × 10 ⁶ times.

When (8 × 10 ⁶ ) programs are completed, an internal voltage for verification is generated at time t4, and data reading from RAM 3 (step S67) and 1-word verification (step S68) are performed at times t5 and t6, respectively. Done. When reading data, the output enable signal / OE and the chip enable signal / CE2 are asserted. This data read update and 1 word verify are also repeated (8 × 10 ⁶ ) times.

When the (8 × 10 ⁶ ) verifications are completed, the chip enable signal / CE1 and the output enable signal / OE are asserted at time t7, flag determination is performed, and the write operation ends. In the method according to the present embodiment, programming and verification are performed for all data (128 Mbits) by a single command input. Therefore, in order to write all the data, it is only necessary to perform command input once, voltage generation once for each of program and verify, and flag determination once.

  As described above, the memory system according to the present embodiment can greatly reduce the number of write command inputs, voltage generation, and flag determination necessary for writing. Therefore, the writing speed can be improved. In this embodiment, the RAM 3 is used as the buffer memory of the EEPROM 2 in order to realize writing of all data by one write command input, voltage generation, and flag determination. As a result, all data can be written continuously, and the write command input count, voltage generation count, and flag determination count can be reduced to one. The EEPROM 2 generates a chip enable signal / CE2 and an output enable signal / OE. Thereby, the EEPROM 2 and the RAM 3 can be operated simultaneously, and the RAM 3 can be used as a buffer memory.

  Further, by using the RAM 3 as a buffer memory, it is not necessary to increase the data size that can be held in the write data buffer 25. That is, the above effect can be obtained without changing the size of the write data buffer 25.

  In the flowchart of FIG. 6, when it is determined as verify NG in step S45, the process of step S46 is performed. However, for example, the process may return to step S34. In this case, memory cells determined as verify OK may be stored in a register, and steps S36 and S44 for these cells may be omitted by putting the row decoder 21 in a non-operating state.

[Second Embodiment]
Next, a semiconductor memory device, a semiconductor device, and a data writing method according to a second embodiment of the present invention are described. In the present embodiment, a two-stage buffer is used as the write data buffer 25 of the first embodiment. Since the configuration of the memory system 1 is the same as the configuration of FIG. 1 described in the first embodiment, description thereof is omitted. FIG. 12 is a block diagram of the EEPROM 2 according to the present embodiment.

  As shown in the figure, the EEPROM 2 has a configuration in which the write data buffer 25 is replaced with a first write data buffer 37 and a second write data buffer 38 in the configuration described with reference to FIG. 2 in the first embodiment. ing. Other configurations are the same as those in FIG. The first write data buffer 37 receives data from the data input / output buffer 27 and holds it. The second write data buffer 38 receives data from the first write data buffer 37 and writes the received data to the memory cell array 20 in units of one word.

  Next, a method of writing data to the EEPROM 2 in the memory system 1 having the above configuration will be described. Since the operations among the EEPROM 2, RAM 3, and CPU 4 are the same as those in FIG. 5 described in the first embodiment, the operation in the EEPROM 2 will be described with reference to FIG. FIG. 13 is a flowchart showing the processing flow of the EEPROM 2.

  As shown in the drawing, the steps up to step S36 are the same as those in the first embodiment. However, the write data for one word read from the RAM 3 in step S35 is transferred to the first write data buffer 37 and then immediately transferred to the second write data buffer 38. Next, in step S36, programming of write data for one word is performed. At this time, the EEPROM 2 reads write data for the next one word from the RAM 3 simultaneously with the program (step S100). This is shown in FIG. FIG. 14 is a block diagram showing a partial configuration of the EEPROM 2. Note that data programmed in the memory cell MC in steps S36 and S37 is referred to as first data, and write data for the next one word read from the RAM 3 is referred to as second data.

  As shown, the first write data buffer 37 is empty while the data held in the second write data buffer 38 is being programmed into the memory cell MC. Therefore, the address input / output buffer 33 generates the internal address ADDint corresponding to the next one word and reads the second data to the first write data buffer 37 during the period of programming the first data. That is, the first data program and the reading of the second data from the RAM are performed in parallel.

  When the program is not completed for all addresses (step S37, NO), the write address is advanced by one word (step S38), and the process returns to step S36.

  The verify operation is the same. As shown in FIG. 13, the processes up to step S44 are the same as in the first embodiment. However, the verify data for one word read from the RAM 3 in step S43 is transferred to the first write data buffer 37 and then immediately transferred to the second write data buffer 38. In step S44, data for one word is verified. At this time, the EEPROM 2 reads verify data for the next one word from the RAM 3 simultaneously with the verify (step S101). That is, the verification using the first data (verification data) and the reading of the second data (verification data) from the RAM are performed in parallel. Then, the verify address is advanced by one word (step S50) while verify is not completed for all addresses (step S49, NO), and the process returns to step S44. Other operations are the same as those in the first embodiment.

As described above, in the memory system according to the present embodiment, the following effect (2) can be obtained in addition to the effect (1) described in the first embodiment.
(2) Data writing can be speeded up (part 2).
The EEPROM according to the present embodiment has two write data buffers 37 and 38 connected in series. Therefore, the time required for reading data during programming and verification can be greatly reduced, and the data writing speed can be dramatically improved. This effect will be described with reference to FIG. FIG. 15 is a timing chart showing chip enable signals / CE1, / CE2, write enable signal / WE, output enable signal / OE, and operation contents in the memory system 1 in the write operation according to the present embodiment. As in FIG. 11 described in the first embodiment, the size of one page is 128 bits, the size of data to be collectively written in memory cells is 1 word (16 bits), and the total data size to be written is 128 Mbits. A case will be described as an example.

As shown in the figure, until the time t3, the program operation is performed according to the same flow as in the first embodiment. At time t3, data for one word read from the RAM 3 at time t2 is programmed into the memory cell MC. At this time, data for the next one word is simultaneously read from the RAM 3 to the EEPROM 2. The time required for one word program is usually about 1 μs, but this period is long enough to read data for one word. Accordingly, since the next write data is already read at time t4 when the program started at time t3 ends, the write data read at time t3 to t4 is programmed at time t4. The above process is repeated for all data (8 × 10 ⁶ times / 128 Mbits).

The same applies to the verify operation. At time t7, verification is performed using the data for one word read from the RAM 3 at time t6. At this time, data for the next one word is simultaneously read from the RAM 3 to the EEPROM 2. The time required for one word verification is normally about 0.5 μs, but this period is also sufficiently long to read data for one word. Therefore, since the next verify data has already been read out at time t8 when the verification started at time t7 ends, verification is performed using the verify data read out at times t7 to t8. The above process is repeated for all data (8 × 10 ⁶ times / 128 Mbits).

As described above, of the data to be read from the RAM 3, data other than the first one word data to be written to the memory cell and the first one word data to be verified are read from the RAM 3 during the program or the verify. Read out. Therefore, the time required to read out these data is zero when viewed from the outside of the EEPROM 2. In other words, compared with the method described in the first embodiment, the time for reading data from the RAM 3 at the time of programming and the time for reading data from the RAM 3 at the time of verifying are each 1 / (8 × 10 ⁶ ). Can be made. Therefore, the data writing speed can be improved. Therefore, data can be written to the EEPROM 2 at the same speed as when the size of the write data buffer is the same as that of the RAM 3.

[Third Embodiment]
Next explained is a semiconductor memory device, semiconductor device and data writing method according to the third embodiment of the invention. The present embodiment relates to a multi-chip package in which the EEPROM 2 and the RAM 3 are combined into one package in the first and second embodiments. Since other configurations are the same as those of the first and second embodiments, description thereof will be omitted. FIG. 16 is a block diagram of the semiconductor device 50 included in the memory system 1 according to the present embodiment.

  As shown, the semiconductor device 50 includes a semiconductor chip 51 having an EEPROM, a semiconductor chip 52 having a RAM, a data bus 53, an address bus 54, a control bus 55, power supply pins 56 and 57, a chip select pin 58, 59, a control pin 60, an address pin 61, and a data pin 62. These are packaged in the same semiconductor package.

  The configurations of the semiconductor chip 51 and the semiconductor chip 52 are the same as those of the EEPROM 2 and the RAM 3 described in the first and second embodiments. The data bus 53, the address bus 54, and the control bus 55 connect the semiconductor chip 51 and the semiconductor chip 52 to each other. The data bus 53, the address bus 54, and the control bus 55 transfer data, address signals, and control signals to each other.

  The power supply pins 56 and 57 are respectively applied with a voltage from the outside, and apply the applied voltage to the semiconductor chips 51 and 52, respectively. The chip select pins 58 and 59 are respectively supplied with enable signals / CE1 and / CE2 from the outside, and supply them to the semiconductor chips 51 and 52, respectively. The control pins 60, address pins 61, and data pins 62 are used in common for the semiconductor chips 51 and 52. A control signal (/ WE, / OE, etc.) given from the outside to the control pin 60 is given to the semiconductor chip 51 or 52 via the control bus 55. An address signal applied to address pin 61 from the outside is applied to semiconductor chip 51 or 52 via an address bus. Data applied to the data pin 62 is applied to the semiconductor chip 51 or 52 via the data bus 53. Each signal applied to the control pin 60, the address pin 61, and the data pin 62 is applied to the semiconductor chip 51 or 52 enabled by the enable signals / CE1 and / CE2.

  As described in the first and second embodiments, the semiconductor chip 51 can output the enable signal / CE2 and the write enable signal / WE to the semiconductor chip 52.

  FIG. 17 is a cross-sectional view of the semiconductor device 50. As shown in the figure, the semiconductor device 50 is a BGA (Ball Grid Array) in which three semiconductor chips including the semiconductor chips 51 and 52 are three-dimensionally mounted. As illustrated, the semiconductor device 50 includes a mounting substrate 70, copper wiring 71, semiconductor chips 51, 52, 72, bonding wires 73, spacers 74, solder bumps 75, and a sealing resin 76.

  On the surface of the mounting substrate 70, the semiconductor chip 51 is bonded by a die attach material 77 with the bonding pad surface facing up. A spacer 74 is bonded onto the semiconductor chip 51 by a die attach material 78. The spacer 74 is smaller than the semiconductor chip 51, and the bonding pads of the semiconductor chip 51 are not covered with the spacer 74. On the spacer 74, the semiconductor chip 52 is bonded with a bonding pad surface up by a die attach material 79. Further, a semiconductor chip 72 is bonded onto the semiconductor chip 52 with a bonding pad surface facing upward by a die attach material 90. The semiconductor chip 72 is smaller than the semiconductor chip 52 so that the bonding pads of the semiconductor chip 52 are not covered with the semiconductor chip 72.

  A copper wiring 71 provided for each of the semiconductor chips 51, 52, 72 is provided on the surface of the mounting substrate 70, and the bonding pads of the semiconductor chips 51, 52, 72 and the copper wiring 71 are connected by the bonding wires 73. ing. A sealing resin 76 is provided on the surface of the mounting substrate 70 so as to cover the semiconductor chips 51, 52, 72, the copper wiring 71, and the bonding wires 73.

  A plurality of solder bumps 75 are provided on the back surface of the mounting substrate 70. The solder bump 75 functions as a connector with the outside. A multilayer metal wiring layer is provided inside the mounting substrate 70, and the solder bump 75 and the copper wiring 71 are connected via the wiring layer. One of the solder bumps 75 corresponds to each of the pins 56 to 62 described with reference to FIG.

  As described above, as long as the EEPROM can control the RAM, the EEPROM and the RAM may be provided in the same package.

  As described above, in the memory system according to the first to third embodiments of the present invention, the EEPROM 2 can output the enable signals / CE2 and / OE for setting the RAM 3 to the operation state, An address signal can be output. As a result, data is written to the EEPROM 2 using the RAM 3 provided outside the EEPROM 2 as a buffer memory. Accordingly, the writing speed to the EEPROM 2 can be improved without increasing the size of the write data buffer provided in the EEPROM 2.

  Note that the EEPROM 2 itself can determine in which area the EEPROM 2 writes the data read from the RAM 3. This is shown in FIG. FIG. 18 is a conceptual diagram showing the memory space of the EEPROM 2. For example, assume that EEPROM 2 is 128 Mbit and RAM is 32 Mbit. For example, if the memory space of the EEPROM 2 is divided into first to fourth areas each having 32 Mbits, the EEPROM 2 determines which of the first to fourth areas the 32 Mbit data held in the RAM 3 is to be written. I can do it. Of course, there may be a command from the CPU 4.

  In the above embodiment, the case where a NOR flash memory is used as the EEPROM 2 has been described as an example. However, a NAND flash memory may be used. FIG. 19 is a circuit diagram of a memory cell array provided in the NAND flash memory.

  As shown in the figure, the memory cell array has a plurality of NAND cells. Although FIG. 19 shows only one row of NAND cells, a plurality of NAND cells may be provided. Each of the NAND cells includes 32 memory cell transistors MT0 to MT31 and select transistors ST1 and ST2. Hereinafter, for simplification of description, the memory cell transistors MT0 to MT31 may be simply referred to as memory cell transistors MT. Memory cell transistor MT has a stacked gate structure having a floating gate formed on a semiconductor substrate with a gate insulating film interposed therebetween, and a control gate formed on the floating gate with an inter-gate insulating film interposed therebetween. Yes. The number of memory cell transistors MT is not limited to 32, but may be 8 or 16, and the number is not limited. Adjacent ones of the memory cell transistors MT share a source and a drain. And it arrange | positions so that the current path may be connected in series between selection transistor ST1, ST2. The drain region on one end side of the memory cell transistors MT connected in series is connected to the source region of the select transistor ST1, and the source region on the other end side is connected to the drain region of the select transistor ST2.

  The control gates of the memory cell transistors MT in the same row are commonly connected to any one of the word lines WL0 to WL31, and the gates of the selection transistors ST1 and ST2 of the memory cells in the same row are common to the select gate lines SGD and SGS, respectively. It is connected. Further, the drains of the select transistors ST1 in the same column in the memory cell array are commonly connected to any one of bit lines BL0 to BLn (n is a natural number). The sources of the selection transistors ST2 are commonly connected to the source line SL. Note that both the selection transistors ST1 and ST2 are not necessarily required, and only one of them may be provided as long as a NAND cell can be selected.

  The above embodiment can be applied to the NAND flash memory as described above. Further, the present invention is not limited to a flash memory, and can be applied to all semiconductor memories in which data is simultaneously written in a plurality of memory cells using a write data buffer. In addition, the data size written simultaneously is not limited to one word unit, and it is sufficient if there is a plurality of data.

  In addition, the above-described embodiment can achieve a remarkable effect when applied to a semiconductor memory used for the purpose of holding a program in an application system. In the application system, a program is written in the EEPROM using a ROM writer at the time of shipment of the product. In this case, a large amount of program data is written to the EEPROM in a lump. Therefore, in such a case, it is desirable to apply the methods of the first and second embodiments using a ROM writer as a host device.

  Further, in the above embodiment, the case where the size of the write data buffer is one page has been described. However, it is sufficient that the size of the write data buffer is equivalent to the data size (one word in the above embodiment) that can be simultaneously written in the memory cell. However, considering the case where the EEPROM 2 cannot be used together with the RAM 3 depending on how the semiconductor chip is used, it is desirable that the size of the write data buffer is larger than one word.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

1 is a block diagram of a memory system according to a first embodiment of the present invention. 1 is a block diagram of an EEPROM according to a first embodiment of the present invention. 1 is a circuit diagram of a memory cell array provided in an EEPROM according to a first embodiment of the invention. 1 is a cross-sectional view of a memory cell array provided in an EEPROM according to a first embodiment of the invention. 4 is a flowchart showing a method of writing data to the EEPROM in the memory system according to the first embodiment of the present invention. 3 is a flowchart showing a data writing method in the EEPROM according to the first embodiment of the present invention. 1 is a block diagram of an EEPROM according to a first embodiment of the present invention, showing a state when data is written. FIG. The flowchart which shows the data writing method to EEPROM. The timing chart which shows the operation | movement content in the writing method shown in FIG. 3 is a flowchart showing a data writing method in the EEPROM according to the first embodiment of the present invention. 11 is a timing chart showing operation contents in the writing method shown in FIG. The block diagram of EEPROM which concerns on 2nd Embodiment of this invention. 9 is a flowchart showing a data writing method in an EEPROM according to the second embodiment of the present invention. FIG. 5 is a block diagram of an EEPROM according to a second embodiment of the present invention, showing a state when data is written. 6 is a timing chart showing the operation contents when writing data in the EEPROM according to the second embodiment of the present invention; The block diagram of the multichip package which concerns on 3rd Embodiment of this invention. Sectional drawing of the multichip package which concerns on 3rd Embodiment of this invention. It is a conceptual diagram of the memory space of EEPROM which concerns on the 1st modification of the 1st thru | or 3rd embodiment of this invention, and shows a mode that data is written from RAM3 to EEPROM. FIG. 6 is a circuit diagram of a memory cell array provided in an EEPROM according to a second modification of the first to third embodiments of the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory system, 2 ... EEPROM, 3 ... RAM, 4 ... CPU, 5 ... Regulator circuit, 6 ... Power supply circuit, 7 ... Input device, 8 ... Input I / F controller, 9 ... Display device, 10 ... Display device controller 11, 53 ... Data bus, 12, 54 ... Address bus, 20 ... Memory cell array, 21 ... Row decoder, 22 ... Column decoder, 23 ... Column selector, 24 ... Source line driver, 25, 37, 38 ... Write data buffer , 26 ... sense amplifier, 27 ... data input / output buffer, 28 ... command register, 29 ... output buffer, 30 ... input / output buffer, 31 ... input buffer, 32 ... address register, 33 ... address input / output buffer, 34 ... voltage generation Circuit 35 ... Verify circuit 36 ... Control circuit 50 ... Multi-chip package 51 52 ... Semiconductor chip, 55 ... Control bus, 56, 57 ... Power supply pin, 58, 59 ... Chip select pin, 60 ... Control pin, 61 ... Address pin, 62 ... Data pin, 70 ... Mounting board, 71 ... Copper wiring 73 ... Bonding wire, 74 ... Spacer, 75 ... Solder bump, 76 ... Sealing resin, 77-80 ... Die attach material

Claims (5)

A semiconductor memory device connectable to an external memory device,
A memory cell array in which a plurality of memory cells each including a charge storage layer and a control gate formed on the charge storage layer are arranged in a matrix;
A word line commonly connecting the control gates of the memory cells in the same row in the memory cell array;
An output buffer that outputs to the external memory device an enable signal that enables the external memory device;
An address buffer for outputting an address of data to be read in the external memory device to the external memory device;
An input buffer for receiving the data held at the address output from the address buffer from the external memory device enabled by the enable signal;
A write data buffer that holds the data received by the input buffer and writes the data to a plurality of the memory cells connected to the same word line in a lump. Each time a write data buffer writes data to the memory cell, the semiconductor memory device receives the data of a size to be written to the memory cell at a time from the external memory. The write data buffer includes a first buffer circuit that temporarily holds the data received by the input buffer;
A second buffer circuit that receives the data held in the first buffer circuit and writes the data to the memory cell, and the data held in the second buffer circuit is written to the memory cell. The address buffer outputs an address at which the data to be written next to the memory cell in the external memory device is held to the external memory device, and the input buffer outputs the data to be written next. The semiconductor memory device according to claim 1, wherein the first buffer circuit holds the data. A semiconductor device comprising first and second semiconductor chips in the same package,
A first semiconductor chip comprising a first semiconductor memory device operable by a first enable signal and capable of holding data;
A second semiconductor chip comprising a second semiconductor memory device operable by a second enable signal and including a memory cell having a charge storage layer and a control gate formed on the charge storage layer;
A data bus for communicatively connecting the first and second semiconductor chips;
A first external pin electrically connected to the data bus and capable of receiving the first enable signal from outside;
A second external pin electrically connected to the data bus and capable of receiving the second enable signal from outside;
A third external pin electrically connected to the data bus and used in common for the first and second semiconductor chips and capable of inputting the data from the outside;
A fourth external pin commonly used for the first and second semiconductor chips and capable of inputting an address signal from the outside, and when the data is written to the first semiconductor memory device, One semiconductor chip is enabled by the first enable signal input to the first external pin, and receives the data input to the third external pin and the address signal input to the fourth external pin. Works according to
In the second semiconductor memory device, the first semiconductor chip is operable by the first enable signal generated by the second semiconductor chip, and the address signal generated by the second semiconductor chip is received by the first semiconductor chip. A semiconductor device, wherein the data held in the first semiconductor memory device is written to the memory cell by being applied to a chip. A method of writing data in a semiconductor memory device that can be connected to an external memory device and has a plurality of memory cells each having a charge storage layer and a control gate formed on the charge storage layer,
Writing data of a first data size in the external memory device;
Generating a running flag indicating that the semiconductor memory device is performing a write operation after the writing to the external memory device is completed;
Enabling the semiconductor memory device to operate the external memory device after generating the running flag;
A voltage generating circuit included in the semiconductor memory device generates a first internal voltage for writing;
The semiconductor memory device reading the data from the external memory device in a second data size unit smaller than the first data size;
Writing the data in the memory cell in the second data size unit using the first internal voltage;
After the writing of the data to the memory cell for all of the data is completed, the voltage generation circuit generates a second internal voltage for verification;
The semiconductor memory device reads the data from the external memory device again in a second data size unit;
Verifying the data written to the memory cell using the second internal voltage and the data read again from the external memory device;
And a step of stopping generation of the in-execution flag after the verification is completed for all of the data. The semiconductor memory device includes first and second buffer circuits capable of holding the data having a data size of at least the second data size,
The data held in the first buffer circuit is written into the memory cell;
While the data is being written to the memory cell, the data to be written next is read from the external memory device, stored in the second buffer circuit, and then transferred to the first buffer circuit. 5. The data writing method according to claim 4, wherein:

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