JPH0581145A - Data writing circuit to EEPROM - Google Patents

Abstract

PURPOSE:To record data changing in a cycle shorter than the time taken to write data for an EEPROM by writing the data stored by a RAM in the EEPROM without interposing a CPU. CONSTITUTION:When an abnormality occurs in a system, a CPU 1 writes a prescribed number of history data in a RAM 4 performing an increment for a writing address. When this writing is terminated, the CPU 1 determines addresses with a fixed interval before and after from the time when the abnormality occurs and designates these addresses to an address signal generation circuit 3. Then, the CPU 1 outputs a switch command making a state performing a data transfer from the RAM 4 to an EEPROM 5 to a control circuit 10. From the address signal generation circuit 3 and a write signal generation circuit 2, an address signal and a write signal are outputted. The data of the RAM 4 designated by the address signal is written in the same address of the EEPROM 5 by the write signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data writing circuit which is applied to a computer system using an EEPROM and writes data to the EEPROM.

[0002]

2. Description of the Related Art An EEPROM (electrical
A computer system using an electrically erasable programmable read only memory is known. Since this EEPROM is non-volatile, the recorded data is not erased even when the power supply to the EEPROM is turned off. However, on the other hand, RAM (rand
It takes more time to write data than volatile memory such as am access memory). Therefore, the EEPROM
Is often used to record data such as programs that do not need to be rewritten frequently once written.

In a computer system, when an operation abnormality occurs, it may be necessary to specify the cause of the abnormality later. When an abnormality occurs, C
The PU (Central Processing Unit) normally outputs data such as an error status indicating the state of the system at this time. Generally, a means for recording the data at this time (hereinafter, referred to as history data) in a memory to later identify the cause of the abnormality is often used.

FIG. 2 is a block diagram showing an example of this type of data write circuit. The memory 12 is the CPU 11
Directly connected to the address bus and data bus from. Therefore, the history data output from the CPU 11 is directly fetched from the CPU 11 into the memory 12.

[0005]

By the way, in the data write circuit shown in FIG.
When a PROM is used, the time required to write one piece of data becomes very long, so there is a problem that the cycle of writing data is inevitably long.

The present invention has been made under such a background, and provides a data writing circuit for an EEPROM capable of recording data that changes in a cycle shorter than the time required for writing data to the EEPROM. It is an object.

[0007]

In order to solve the above-mentioned problems, the present invention provides a computer system having an EEPROM as a storage means, wherein the E processor supplied from the central processing unit in the computer system.
R for temporarily storing data to be written in EPROM
It is characterized by comprising an AM and a writing means for writing the data stored in the RAM into the EEPROM without passing through the central processing unit.

[0008]

According to the above structure, the data to be written in the EEPROM is temporarily stored in the RAM, and later, this data is written in the EEPROM without passing through the CPU.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a data write circuit for an EEPROM according to an embodiment of the present invention. The part surrounded by the broken line is the range of the data write circuit according to the present embodiment. Reference numeral 10 denotes a control circuit, which controls each part of the data writing circuit according to the CPU 1. Reference numeral 5 is an EEPROM provided to write the history data output from the CPU 1. Reference numeral 4 denotes a RAM, which has the same capacity as the EEPROM 5. Both the RAM 4 and the EEPROM 5 are connected to the CPU 1 via the control circuit 10.

In the control circuit 10, 2 is a write signal generating circuit and 3 is an address signal generating circuit. When data is transferred from the RAM 4 to the EEPROM 5, the write signal generation circuit 2 outputs a write signal and the address signal generation circuit 3 outputs an address signal. Also,
The switch SW1 is for switching a plurality of address signals, the switch SW2 is for switching a plurality of data signals, the switch SW3 is for switching a write signal, and the switch SW4 is for switching a read signal. For switch SW
Reference numeral 5 is for switching the read signal of the EEPROM 5, and is composed of a gate circuit inside the integrated circuit. Switching control of these switches is performed by a command issued from the CPU 1.

A read signal terminal a1, a write signal terminal b1, an address signal terminal c1, and a data signal terminal d of the CPU 1
1 is connected to a read signal line a, a write signal line b, an address bus c, and a data bus d, respectively. The read signal line a is connected to A of the switch SW4 and A of the switch SW5. The switch SW4 C is connected to the read signal terminal a4 of the RAM 4, and the switch SW5 C is connected to the read signal terminal a5 of the EPROM 5. In addition, B of the switch SW4 is connected to a voltage level that allows data output, and B of the switch SW5 is
It is connected to a voltage level where data cannot be output. The write signal line b is a write signal terminal b of the RAM 4.
4 and A of the switch SW3. Then, C of the switch SW3 is a write signal terminal b of the EEPROM 5.
5 is connected. The switch SW3 B is connected to the write signal terminal b2 of the write signal generation circuit 2. The address bus c is connected to A of the switch SW1. The switch SW1 C is connected to the address signal terminal c4 of the RAM 4 and the address signal terminal c5 of the EEPROM 5. The switch SW1 B is connected to the address signal terminal c3 of the address signal generation circuit 3. The data bus d is connected to the data signal terminal d4 of the RAM 4 and the data signal terminal d5 of the EEPROM 5 via A and B of the switch SW2.

Next, the operation of the data write circuit will be described. While the system is operating normally, the control circuit 10 causes the switches SW1, SW3, SW4 and SW to operate.
5 is switched to the A side, and SW2 is turned on. In this state, the CPU 1 can write data in the RAM 4. During normal operation of the system,
The CPU 1 periodically writes the history data in the RAM 4 while cyclically incrementing the write address. Since writing to the RAM 4 is performed at high speed, the CPU 1 is not restricted by the writing process for a long time, unlike the case of writing to the EEPROM 5.

When an abnormality occurs in the system, C
The PU 1 writes a predetermined number of history data in the RAM 4 while incrementing the write address. When this writing is completed, R
A start address m before the write address of the AM4 by the predetermined number of addresses and an end address n after the predetermined number of addresses are obtained. And CP
U1 designates these addresses to the address signal generation circuit 3. After that, the CPU 1 uses the RAM 4 to E
A switching command to put the EPROM 5 in a state of transferring data is output to the control circuit 10.

When the switching command is input, the control circuit 10 switches SW1, SW3, SW4, SW.
5 is switched to the B side, and SW2 is turned off. Then, the address signal generating circuit 3 and the write signal generating circuit 2 respectively output the address signal and the write signal. FIG. 3 is a diagram showing these two signals. p1 is an address signal, which is sequentially output from the start address m to the end address n. P2 is a write signal,
It is output in synchronization with the address signal p1.

That is, the data of the RAM 4 designated by the address signal p1 is EE by the write signal p2.
It is written to the same address p1 of PROM5.

Generally, such data transfer is performed by DMA.
(Direct memory access), CPU1
During data transfer, RAM4 and EEPRO
It is electrically separated from M5. Therefore, EEPRO
Even if it takes time to write data to M5, C
The PU1 can execute other processing without waiting for this.

Then, the address signal p1 reaches the end address n, and the data transfer ends. In this way, history data at a constant interval before and after the occurrence of the abnormality is EEPRO
Recorded in M5. Then, the control circuit 10 automatically returns to the normal operating state of the system.

[0018]

As described above, according to the present invention, in a computer system having an EEPROM as a storage means, the data to be written in the EEPROM supplied from the central processing unit in the computer system is temporarily stored. RAM and the RAM
Since the writing means for writing the data stored in the EEPROM to the EEPROM without using the central processing unit is provided, it is possible to record the data that changes in a cycle shorter than the time required to write the data to the EEPROM. can get. Further, the central processing unit is a RAM
After writing data at high speed to RAM, EE from RAM
While the data is transferred to the PROM, another effect can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a data write circuit for an EEPROM according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventional history data write circuit.

3 is a diagram showing an address signal p1 output from an address signal generation circuit 3 and a write signal p2 output from a write signal generation circuit 2. FIG.

[Explanation of symbols]

 1, 11 CPU 2 write signal generation circuit 3 address signal generation circuit 4 RAM 5 EEPROM 10 control circuit 12 memory p1 address signal p2 write signal

Claims (1)

[Claims] 1. A computer system having an EEPROM as a storage means, a RAM for temporarily storing data to be written in the EEPROM, which is supplied from a central processing unit in the computer system, and data stored by the RAM, A writing means for writing to the EEPROM without using a central processing unit, and a data writing circuit to the EEPROM.