JP2007335463A - Electrostatic discharging protective element, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrostatic discharging protective element which can improve the performance of a semiconductor integrated circuit as an ESD protective element, and can make an ESD protective element formation area small. <P>SOLUTION: The electrostatic discharging protective element is provided with a gate insulation film 12 formed on a semiconductor substrate 1; a gate structure 11 comprised of a gate electrode 13 and a side wall film 14; a source area 15 and a drain area 16 which are formed on both side of the gate structure 11, respectively, and are comprised of a high-concentration impurity diffusion layer; an extension section 17 which is formed on the side of the gate structure 11 for the source area 15 and the drain area 16, and is comprised of a low-concentration impurity diffusion layer a source electrode; and a drain electrode. The element is multi-finger type which is comprised of a plurality of field effect transistors to which the gate electrode and the source electrode are grounded. In addition, the electrostatic discharging protective element is provided with a resistance area 18 comprised of a low-concentration impurity diffusion layer in the high-concentration impurity diffusion layers between the source electrode and the gate electrode 13, and between the drain electrode and the gate electrode 13. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an electrostatic discharge protection element and a semiconductor device for protecting an internal circuit from destruction due to electrostatic discharge in a semiconductor integrated circuit device.

  In general, in a semiconductor integrated circuit, an internal circuit is prevented from being destroyed by electrostatic discharge (ElectroStatic Discharge, hereinafter referred to as ESD) such as discharge of charge from the outside or discharge of charge charged in the semiconductor integrated circuit itself. An ESD protection element is provided. In particular, an ESD protection element in a conventional CMOS (Complementary Metal-Oxide Semiconductor) process is an n-channel field effect type having a gate width of several tens of μm, which can be produced by a normal CMOS technology and has a relatively high ESD resistance per area. A multi-finger type grounded-gate NMOS transistor (hereinafter referred to as ggNMOS transistor) having a comb-like structure in which a plurality of transistors (hereinafter referred to as NMOS transistors) are connected in parallel is mainly used (see, for example, Patent Document 1).

  FIG. 6A is a partial cross-sectional view schematically illustrating the structure of an ESD protection element using a conventional ggNMOS transistor, and FIG. 6B schematically illustrates the structure of an ESD protection element using a conventional ggNMOS transistor. FIG. As shown in the drawing, the ESD protection element is formed in a region (hereinafter referred to as an ESD protection element formation region) R for forming an ESD protection element on a semiconductor substrate 101 on which an internal circuit (not shown) is formed. In the example of this figure, an NMOS transistor having an LDD (Lightly Doped Drain) structure is formed in a region delimited by the element isolation insulating film 102 in the ESD protection element formation region R. Further, a P + diffusion layer 121 is formed outside the region separated by the element isolation insulating film 102 where the NMOS transistor is formed, and a back gate electrode is connected to the P + diffusion layer 121.

  The NMOS transistor includes a gate insulating film 112 and a gate electrode 113 formed at predetermined positions on the semiconductor substrate 101, and sidewalls 114 formed on both side surfaces of the gate insulating film 112 and the gate electrode 113 in the line width direction. A source region 115 and a drain region 116 constituted by a gate structure 111 having a channel structure underneath the gate structure 111 and a pair of N + diffusion layers sandwiching the channel region, and a gate structure 111 of the source region 115 and the drain region 116 And an extension portion 117 formed of an N-diffusion layer at the side end portion. Here, the N + diffusion layer has an N-type impurity concentration higher than that of the N− diffusion layer. Here, the source electrode connected to the gate electrode 113 and the source region 115 of each NMOS transistor is grounded, and the drain electrode connected to the drain region 116 is wired to be connected to the input / output terminal or the power supply terminal.

JP 2002-324842 A

  However, the structure of the conventional ggNMOS transistor constituting the ESD protection element has the same structure as that of the NMOS transistor constituting the internal circuit, and is formed by the same process. There is a problem that it is difficult to improve performance as an ESD protection element such as low impedance.

  In the case of a multi-finger type ggNMOS transistor, a method of intentionally adding a ballast resistor is generally employed in order to prevent current concentration and to ensure that all NMOS transistors operate. . In order to add this ballast resistance, the distance between the contact on the N + diffusion layer and the gate electrode is increased. However, since the sheet resistance value of the N + diffusion layer is usually not so high as several Ω / □ to several tens of Ω / □, the distance between the contact on the current N + diffusion layer and the gate is considerably large. As a result, the ESD protection element formation region becomes large.

  The present invention has been made in view of the above, and it is an object of the present invention to obtain an electrostatic discharge protection element and a semiconductor device capable of improving the performance as an ESD protection element of a semiconductor integrated circuit and reducing the ESD protection element formation region. Objective.

  In order to achieve the above object, an electrostatic discharge protection element according to the present invention includes a gate insulating film and a gate electrode that are sequentially stacked on a semiconductor substrate, and both sides of the stacked body of the gate insulating film and the gate electrode in the line width direction. A gate structure comprising the formed sidewall film, a source region and a drain region comprising a high concentration impurity diffusion layer formed on both sides of the gate structure on the sidewall film side, and the source region and the drain region. An extension portion formed of a low-concentration impurity diffusion layer formed on the gate structure side, a source electrode connected to the source region, and a drain electrode connected to the drain region, the gate electrode and the A plurality of field effect transistors with their source electrodes grounded are arranged so that their gate electrodes extend in parallel. In a multi-finger type electrostatic discharge protection element, a resistance region comprising a low concentration impurity diffusion layer in a high concentration impurity diffusion layer between the source electrode and the gate electrode and between the drain electrode and the gate electrode. It is characterized by providing.

  According to the present invention, since the N− diffusion layer has a sheet resistance value that is about two orders of magnitude higher than that of the N + diffusion layer, the N− diffusion layer is provided in the N + diffusion layer between the source electrode / drain electrode and the gate electrode. By providing, a ballast resistance can be added, and the distance between the gate electrode and the source electrode / drain electrode on the N + diffusion layer for securing a necessary ballast resistance value is shorter than in the conventional structure. can do. As a result, the ESD protection element formation region can be reduced as compared with the conventional one.

  Exemplary embodiments of an electrostatic discharge protection element and a semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments. Moreover, the cross-sectional views of the ESD protection element used in the following embodiments are schematic, and the relationship between the thickness and width of the layers, the ratio of the thicknesses of the layers, and the like are different from the actual ones.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing a schematic configuration of the first embodiment of the ESD protection element according to the present invention. As shown in the drawing, this ESD protection element is formed in an ESD protection element formation region R on a semiconductor substrate 1 on which an internal circuit (not shown) is formed. In the example of this figure, an N-channel field effect transistor (hereinafter referred to as an NMOS transistor) having an LDD structure in a region isolated by the element isolation insulating film 2 in the ESD protection element formation region R includes a gate electrode 13. A multi-finger type ESD protection element formed in a plurality of comb shapes so as to be parallel to each other is formed. In addition, the planar shape of this ESD protection element shall have a shape substantially the same as FIG. 6-2 demonstrated by background art.

  The NMOS transistor includes a gate insulating film 12 and a gate electrode 13 formed at predetermined positions on the semiconductor substrate 1, and sidewall films 14 formed on both side surfaces of the gate insulating film 12 and the gate electrode 13 in the line width direction. A source region 15 / drain region 16 composed of a pair of N + diffusion layers sandwiching a channel region below the gate structure 11, and a gate structure of the source region 15 / drain region 16 11, an extension portion 17 constituted by an N-diffusion layer, and a contact position of a source electrode (not shown) connected to the gate electrode 13 and the source region 15 and a contact of a drain electrode (not shown) connected to the drain region 16. And a resistance region 18 constituted by a low-concentration N-diffusion layer. Here, the N + diffusion layer has an N-type impurity concentration higher than that of the N− diffusion layer. In addition, the gate electrode 13 and the source electrode of each NMOS transistor are grounded, and the drain electrode is wired to be connected to the input / output terminal or the power supply terminal.

  The resistance region 18 formed in the source region 15 and the drain region 16 is constituted by an N− diffusion layer having an N-type impurity concentration lower than that of the N + diffusion layer in the N + diffusion layer constituting the source region 15 / drain region 16. Is done. Since the N− diffusion layer has a sheet resistance that is about two orders of magnitude higher than that of the N + diffusion layer, the N− diffusion layer serves as a ballast resistance in the source region 15 and the drain region 16.

  Next, a method for manufacturing the ESD protection element having such a configuration will be described. FIGS. 2-1 to 2-8 are cross-sectional views schematically showing an example of the manufacturing procedure of the ESD protection element according to the present invention. First, a P-type well (not shown) is formed in an ESD formation region of a semiconductor substrate 1 such as a P-type silicon substrate, and an element isolation insulating film 2 having a predetermined pattern is exposed so that a region for forming an NMOS transistor as an ESD protection element is exposed. (FIG. 2-1). The element isolation insulating film 2 is formed by, for example, a LOCOS (Local Oxidation of Silicon) method or an STI (Shallow Trench Isolation) method. Thereafter, an insulating film 12a serving as a base of the gate insulating film 12 is formed on the semiconductor substrate 1, and an electrode material layer 13a containing Si or Si is further deposited thereon with a predetermined thickness (FIG. 2-2). The insulating film 12a can be formed by a thermal oxidation method, a physical vapor deposition method (hereinafter referred to as PVD method), a chemical vapor deposition method (hereinafter referred to as CVD method), or the like. The electrode material layer 13a can be formed by a CVD method or the like.

  Next, a resist is applied to the entire surface of the electrode material layer 13a, and patterning is performed so as to leave the resist 30 in a region corresponding to the formation position of the gate electrode 13 in the ESD protection element formation region R (FIG. 2-3). Thereafter, the electrode material layer 13a and the insulating film 12a are etched using the resist pattern as a mask. At this time, etching is performed from the upper surface of the electrode material layer 13a to the interface between the insulating film 12a and the semiconductor substrate 1 (FIG. 2-4). Thereby, a stacked body of the gate insulating film 12 and the gate electrode 13 is formed.

  Next, a resist 31 is applied to the entire surface of the semiconductor substrate 1 and patterned so that regions other than the NMOS transistor formation region are masked, and the resist 31, the stacked body of the gate insulating film 12 and the gate electrode 13 are formed. Using the mask, a low concentration diffusion layer (N- diffusion layer) 22 in which impurities serving as donors are introduced at a low concentration is formed in the ESD protection element formation region R (FIG. 2-5). Thereafter, a sidewall insulating film serving as a base of the sidewall film is formed on the entire surface of the semiconductor substrate 1 on which the stacked body of the gate insulating film 12 and the gate electrode 13 is formed. Then, the upper surface of the gate electrode 13 on the ESD protection element forming region R and the sidewall insulating film formed on the semiconductor substrate 1 other than the gate electrode forming region R are removed, and the gate insulating film 12 and the gate electrode 13 are removed. Sidewall films 14 are formed on the side surfaces in the line width direction of the laminate (FIGS. 2-6). As a result, the gate structure 11 including the gate insulating film 12, the gate electrode 13, and the sidewall film 14 is formed on the ESD protection element forming region R of the semiconductor substrate 1.

  Next, a resist 32 is applied to the entire surface of the semiconductor substrate 1 on which the gate structure 11 is formed, and patterning is performed so that the resist 32 is left only at a predetermined position in the N− diffusion layer 22 in the NMOS transistor formation region. (Figure 2-7). Here, patterning is performed so that one mask is formed in each N- diffusion layer 22 on both sides in the line width direction with respect to one gate electrode 13.

  Next, in order to form the source region 15 / drain region 16 in the region on the semiconductor substrate 1 on both sides in the line width direction of the gate structure 11 using the gate structure 11 and the resist 32 formed on the N− diffusion layer 22 as a mask. N-type impurities are ion-implanted in At this time, N-type impurities are introduced at a concentration higher than the impurity concentration when the N- diffusion layer 22 is formed (FIGS. 2-8). Thereafter, the resist is removed, and the ion-implanted impurities are activated. As a result, source regions 15 a and 15 b and drain regions 16 a and 16 b made of N + diffusion layers are formed in the N− diffusion layer 22. Further, in the N− diffusion layer 22, the portion on the gate electrode 13 side of the source region 15 / drain region 16 becomes the extension portion 17, and the portion not masked when the N + diffusion layer is formed becomes the resistance region 18.

  Thereafter, an interlayer insulating film is formed on the semiconductor substrate 1 on which the gate structure 11 is formed, and a contact plug is formed at the position of the N + diffusion layer constituting the source region 15b / drain region 16b and the gate electrode 13, and this contact By forming a wiring pattern on the interlayer insulating film so as to be electrically connected to the plug, the ESD protection element shown in FIG. 1 is formed. The source electrode and the gate electrode 13 are wired so as to be grounded. In addition, three N + diffusion layers are formed between adjacent gate structures 11 in parallel with the gate structure, and a contact plug serving as a source electrode / drain electrode is formed in the middle N + diffusion layer of these N + diffusion layers. It is formed.

  According to the first embodiment, since the sheet resistance value of the N− diffusion layer 22 is about two orders of magnitude higher than that of the N + diffusion layer, the N− diffusion layer 22 is provided in the N + diffusion layer between the source / drain electrode and the gate electrode 13. By providing the N− diffusion layer 22, ballast resistance can be added, and the distance between the gate electrode 13 and the source electrode / drain electrode on the N + diffusion layer for securing a necessary ballast resistance value can be set. It can be shortened compared with the conventional structure. As a result, the ESD protection element formation region can be reduced as compared with the conventional one.

  Further, in the case of the first embodiment, in the photolithography process of the N + diffusion layer in the manufacturing method of the ESD protection element, in the conventional structure, the entire ESD protection element formation region is not covered with the resist. Only covers a part of the N-diffusion layer in the ESD protection element formation region with a resist. That is, the ESD protection element of the first embodiment can be formed only by changing the region covered with the resist of the ESD protection element from the conventional structure. Therefore, when manufacturing this ESD protection element, there is an effect that the manufacturing cost is not increased and the elements constituting other internal circuits are not affected. Therefore, it becomes easy to develop any CMOS process.

  When a ggPMOS transistor is used as the ESD protection element, a resistance region composed of a P− diffusion layer is provided in the P + diffusion layer between the gate electrode and the contact formed in the source region / drain region. Similar effects can be obtained.

Embodiment 2. FIG.
FIG. 3 is a plan view showing a schematic configuration of the second embodiment of the ESD protection element according to the present invention. This ESD protection element forms a lattice-like structure by crossing two-direction gate electrodes 13a and 13b at a predetermined angle (orthogonally) in an ESD protection element formation region adjacent to a formation region of an internal circuit of a semiconductor integrated circuit. It is characterized by being. A source electrode 15C or a drain electrode 16C is formed in the region surrounded by the gate electrodes 13a and 13b so as not to be the same type of electrode in the region surrounded by the adjacent gate electrodes 13a and 13b. In FIG. 3, the source electrode 15C and the drain electrode 16C indicate contacts electrically connected to the source region and the drain region on the semiconductor substrate, respectively. The gate electrodes 13a and 13b and the source electrode 15C are wired so as to be grounded.

  Here, the channel width Wa per unit area when the pitch of the gate electrodes 13a and 13b is a and the gate length is L is obtained by the following equation (1).

Wa = channel width / area = {4 (a−L)} / {(2a × 2a) / 2}
= 2 (a−L) / a ² (1)

  On the other hand, the channel width Wb per unit area in the conventional ESD protection element shown in FIG. 6-2 is obtained as in the following equation (2).

Wb = channel width / area = 2a / (2a × a)
= 1 / a (2)

Here, the condition (Wa> Wb) that the channel width Wa per unit area in the second embodiment is larger than the channel width Wb per unit area of the conventional ESD protection element is (1), ( 2) From the equation
2 (a−L) / a ² > 1 / a
From this, the condition of the following equation (3) is obtained.

  a> 2L (3)

  That is, when the pitch of the gate electrodes 13 is larger than twice the gate length L, the second embodiment can reduce the impedance of the electrostatic discharge path.

  Such a method of manufacturing an ESD protection element is based on the conventional gate electrode forming process of the conventional ggMOS type ESD protection element manufacturing method, and a plurality of gate electrodes parallel to each other as shown in FIG. What is formed by patterning in such a manner is merely formed by patterning so that gate electrodes 13a and 13b in two directions intersecting each other at a predetermined angle as shown in FIG. Since other processes are the same as those in the conventional method for manufacturing an ESD protection element, the description thereof is omitted.

  According to the second embodiment, since the lattice-like gate electrodes 13a and 13b are formed so that the pitch is larger than twice the gate length, the channel width per unit area is larger than that of the conventional ESD protection element. As a result, the impedance of the discharge path of the electrostatic discharge can be reduced. In addition, since the channel width per unit area can be increased, the ESD protection element formation region for obtaining the same channel width as the conventional one can be reduced.

Embodiment 3 FIG.
In a multi-finger type ggMOS transistor, in order to prevent ESD current concentration, it is important to align the turn-on voltage and impedance for each finger. Here, the turn-on voltage is a voltage on the drain end side of the gate electrode. Moreover, it is effective to reduce the impedance in order to increase the discharge capability of ESD. Therefore, in the third embodiment, an ESD protection element capable of matching the turn-on voltage and impedance for each finger in a multi-finger type ggMOS transistor will be described.

  FIG. 4 is a plan view showing a schematic configuration of the ESD protection element according to Embodiment 3 of the present invention. In the ESD protection element, in the multi-finger type ggMOS transistor, the distance between the gate electrode 13 and the drain electrode (drain contact) 16C is made larger than the distance between the gate electrode 13 and the source electrode (source contact) 15C. Characterized by being enlarged. That is, the gate electrode 13 is formed so that b> a, where a is the pitch of the gate electrode 13 sandwiching the source region and b is the pitch of the gate electrode 13 sandwiching the drain region. In this way, a sufficiently large diffusion resistance can be added by making the distance between the gate electrode 13 and the drain electrode 16C larger than the distance between the gate electrode 13 and the source electrode 15C.

  Conventionally, the resistance of the drain region is increased by the wiring resistance from the external pin to the drain electrode (drain contact) 16C. In the third embodiment, in addition to the wiring resistance described above, the drain electrode (drain) The distance between the contact 16C and the gate electrode 13 is made longer than the distance between the source electrode 15C and the gate electrode 13 to add diffusion resistance. As a result, the turn-on voltage and impedance for each finger can be made uniform.

  Further, regarding the distance between one gate electrode 13 and the source electrode (source contact) 15C / drain electrode (drain contact) 16C, the distance between the drain electrode 16C and the gate electrode 13 is set between the source electrode 15C and the gate electrode 13. If the distance is longer than the distance, the third embodiment has a higher tolerance for the same area.

  Note that this ESD protection element manufacturing method is the same as the conventional ESD protection element manufacturing method for a ggMOS transistor. When the gate electrode 13 is formed, the gate electrode 13 at the position sandwiching the source region and the gate electrode 13 at the position sandwiching the drain region are formed. Since the other steps are the same as those of the prior art only by changing the formation position of the conventional one, detailed description thereof will be omitted.

  In the above-described third embodiment, the ESD protection element formed in the ESD protection element formation region has been described. However, the same effect can be obtained even when applied to an output CMOS directly connected to an external pin. it can. FIG. 5 is a diagram showing test results when the third embodiment is applied to an output CMOS connected to an external pin of an internal circuit of a semiconductor integrated device. Here, as an ESD ability test, an MM (Machine Model) test and an HBM (Human Body Model) test were performed. In this test, as a back gate wiring process of the PMOS transistor, the contact electrode is increased to reduce the parasitic resistance component so as to improve the surge leakage. In addition, as the back gate wiring processing of the NMOS transistor, the back gate and the source are separated, and the back gate wiring is extended to add wiring resistance. As a result, the parasitic NPN transistor becomes easy to operate, and the surge through the parasitic NPN transistor is improved.

  First, as a conventional example, the ESD protection element has a structure in which both the distance between the gate electrode and the source electrode and the distance between the gate electrode and the drain electrode are the same length of 2.0 μm, As the output NMOS transistor, a semiconductor device having a structure in which both the distance between the gate electrode and the source electrode and the distance between the gate electrode and the drain electrode are the same length of 1.5 μm was used. This result is shown in “conventional example” in FIG. On the other hand, as an example, the ESD protection element has a structure in which both the distance between the gate electrode and the source electrode and the distance between the gate electrode and the drain electrode are as long as 2.0 μm, As the output NMOS transistor, a semiconductor device having a structure in which the distance between the gate electrode and the source electrode was 1.0 μm and the distance between the gate electrode and the drain electrode was 2.0 μm was used. The result is shown in “Example” of FIG. As shown in FIG. 5, when the third embodiment is applied to the output CMOS directly connected to the external pin, it can be seen that the ESD tolerance is remarkably increased.

  According to the third embodiment, in the multi-finger type ggMOS transistor, the distance between the drain electrode (drain contact) 16C and the gate electrode 13 is set to the distance between the source electrode (source contact) 15C and the gate electrode 13. Therefore, the turn-on voltage and impedance of each finger can be made uniform. In addition, compared with the conventional ESD protection element, the ESD protection element according to the third embodiment has an effect that the same tolerance as that of the conventional ESD protection element can be obtained with a smaller area.

  As described above, the ESD protection element according to the present invention is useful for all semiconductor devices using the CMOS process. Particularly, the semiconductor device having a small chip size and the number of pins in which the ratio of the ESD protection element region is large. Suitable for many semiconductor devices.

It is sectional drawing which shows the typical structure of Embodiment 1 of the ESD protection element by this invention. It is sectional drawing which shows typically an example of the manufacturing procedure of the ESD protection element by this invention (the 1). It is sectional drawing which shows typically an example of the manufacturing procedure of the ESD protection element by this invention (the 2). It is sectional drawing which shows typically an example of the manufacturing procedure of the ESD protection element by this invention (the 3). It is sectional drawing which shows typically an example of the manufacturing procedure of the ESD protection element by this invention (the 4). It is sectional drawing which shows typically an example of the manufacturing procedure of the ESD protection element by this invention (the 5). It is sectional drawing which shows typically an example of the manufacturing procedure of the ESD protection element by this invention (the 6). It is sectional drawing which shows typically an example of the manufacturing procedure of the ESD protection element by this invention (the 7). It is sectional drawing which shows typically an example of the manufacturing procedure of the ESD protection element by this invention (the 8). It is a top view which shows the typical structure of Embodiment 2 of the ESD protection element by this invention. It is a top view which shows the typical structure of Embodiment 3 of the ESD protection element by this invention. It is a figure which shows the test result at the time of applying this Embodiment 3 to output CMOS connected to the external pin of the internal circuit of a semiconductor integrated device. It is a partial cross section figure which shows typically the structure of the ESD protection element using the conventional ggNMOS transistor. It is a partial top view which shows typically the structure of the ESD protection element using the conventional ggNMOS transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation insulating film 11 Gate structure 12 Gate insulating film 13 Gate electrode 14 Side wall 15 Source region 16 Drain region 17 Extension part 18 Resistance region

Claims (4)

A gate structure comprising a gate insulating film and a gate electrode, which are sequentially stacked on a semiconductor substrate; and a sidewall film formed on both sides of the stacked body of the gate insulating film and the gate electrode in a line width direction; and the gate structure A source region and a drain region composed of high-concentration impurity diffusion layers formed on both sides of the sidewall film side, and an extension composed of a low-concentration impurity diffusion layer formed on the gate structure side of the source region and the drain region A field effect transistor having a gate electrode and a source electrode grounded, wherein the gate electrode and the source electrode are grounded. In the multi-finger type electrostatic discharge protection element that is arranged so that the directions are parallel,
Electrostatic discharge protection comprising a resistance region comprising a low concentration impurity diffusion layer in the high concentration impurity diffusion layer between the source electrode and the gate electrode and between the drain electrode and the gate electrode. element. A gate structure including a gate insulating film and a gate electrode, which are sequentially stacked on a semiconductor substrate; and a sidewall film formed on both sides of the stacked body of the gate insulating film and the gate electrode in a line width direction; and the gate structure A source region and a drain region composed of high-concentration impurity diffusion layers formed on both sides of the sidewall film side, and an extension composed of a low-concentration impurity diffusion layer formed on the gate structure side of the source region and the drain region An electrostatic discharge protection element comprising a field effect transistor comprising: a gate electrode; a source electrode connected to the source region; and a drain electrode connected to the drain region, wherein the gate electrode and the source electrode are grounded. ,
The gate electrode of the field effect transistor has a lattice shape extending across two directions, and the source region and the drain region are adjacent to the region surrounded by the gate electrode, The electrostatic discharge protection element is characterized in that the pitch of the grid-like gate electrodes is longer than twice the gate length of the field-effect transistor. A gate structure including a gate insulating film and a gate electrode, which are sequentially stacked on a semiconductor substrate; and a sidewall film formed on both sides of the stacked body of the gate insulating film and the gate electrode in a line width direction; and the gate structure A source region and a drain region composed of high-concentration impurity diffusion layers formed on both sides of the sidewall film side, and an extension composed of a low-concentration impurity diffusion layer formed on the gate structure side of the source region and the drain region An electrostatic discharge protection element comprising a field effect transistor comprising: a gate electrode; a source electrode connected to the source region; and a drain electrode connected to the drain region, wherein the gate electrode and the source electrode are grounded. ,
The electrostatic discharge protection element, wherein a distance between the drain electrode and the gate electrode is longer than a distance between the source electrode and the gate electrode. A gate structure including a gate insulating film and a gate electrode, which are sequentially stacked on a semiconductor substrate; and a sidewall film formed on both sides of the stacked body of the gate insulating film and the gate electrode in a line width direction; and the gate structure A source region and a drain region composed of high-concentration impurity diffusion layers formed on both sides of the sidewall film side, and an extension composed of a low-concentration impurity diffusion layer formed on the gate structure side of the source region and the drain region A semiconductor device comprising a field effect transistor, comprising: a portion; a source electrode connected to the source region; and a drain electrode connected to the drain region, wherein the drain electrode is directly connected to an external pin.
A semiconductor device, wherein a distance between the drain electrode and the gate electrode is longer than a distance between the source electrode and the gate electrode.

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