JP2007317771A - Semiconductor light emitting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor light emitting device which reduces clogging and jamming of the dicing blade or lifting of an insulating layer or a metal layer from a semiconductor comprising a light emitting layer, when performing dicing separation for every chip by simple composition. <P>SOLUTION: The semiconductor light emitting device 10 having a junction down structure comprises: a semiconductor substrate 11 provided with a light emitting layer 12 at the mounting surface side, an insulating film 13 formed in the surface of this light emitting layer where patterning is carried out, a first electrode layer 14 coming into ohmic contact partially with the above emitting layer in a region without having an insulating film which is formed on this insulating film, a joining layer 17 formed via a barrier metal layer 15 on this first electrode layer, and a second electrode layer 16 formed in the surface opposite to the emitting layer of the above semiconductor substrate. The semiconductor light emitting device 10 is constituted so that the insulating film or the metal layer, the barrier metal layer and the joining layer may be formed smaller than the semiconductor substrate and the emitting layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor light emitting device having a so-called junction down structure.

Conventionally, a so-called junction down structure semiconductor light emitting device is configured as shown in FIG. 3, for example.
In FIG. 3, the semiconductor light emitting device 1 has a light emitting layer 3 formed on the surface (lower surface) of a semiconductor substrate 2, and further, an insulating film 4 sequentially patterned below the light emitting layer 3, A p-type electrode 5 and a barrier metal layer 6 are formed, and an n-type electrode 7 is formed on the upper surface of the semiconductor substrate 2 to form a chip.

  Further, when the semiconductor light emitting device 1 is mounted, the bonding layer 8 is formed on the lower surface so that the lower surface can be bonded to a connection land formed on a mounting substrate such as a package or a submount. Is formed.

The semiconductor substrate 2 is made of a semiconductor having translucency with respect to the emission wavelength so that light generated in the light emitting layer 3 is transmitted upward.
The light-emitting layer 3 is a light-emitting layer having a known configuration, and is actually configured by laminating a plurality of semiconductor layers.

The insulating film 4 is made of SiO ₂ or the like, and an alloy layer as a light absorber generated by alloying in the ohmic contact between the light emitting layer 3 and the p-type electrode 5 is formed on the entire lower surface of the light emitting layer 3. It is formed by patterning so that it can be partially avoided. As a result, light traveling downward from the light emitting layer 3 is reflected by the insulating film 4 and can be effectively extracted upward.

  The p-type electrode 5 is electrically connected by being in ohmic contact with the lower surface of the light emitting layer 3 in the region where the insulating film 4 is not formed.

  The barrier metal layer 6 prevents the bonding layer 8 from seeping out to the light emitting layer 3 side when the semiconductor light emitting device 1 is mounted on a package, a submount, or the like.

In the bonding layer 8, since the light emitting layer 3 is close to the mounting surface (the lower surface of the semiconductor light emitting device 1), when a bonding agent such as silver paste is used, the molten bonding agent crawls up the chip side surface and leaks. In order to avoid this, a eutectic material such as AuSn is used.
Thereby, the semiconductor light emitting device 1 is eutectic bonded to the mounting substrate.
Note that the eutectic material such as AuSn needs to have a certain thickness in consideration of the uneven shape of the surface of the mounting substrate such as a package.

By the way, in the semiconductor light emitting device 1 having such a configuration, as shown in FIG. 3, after a plurality of chips are integrally formed, the chips 1a are separated by dicing or braking. It has become so.
However, at the time of separation for each chip 1a, the insulating film 4 is cracked and peeled off, or a relatively soft and thick metal film such as AuSn constituting the bonding layer 8 clogs the dicing blade. As a result, there is a problem that chipping occurs.
In particular, in the case of the junction down structure described above, there is a problem that the active layer of the light emitting layer 3 is easily damaged, the characteristics of the semiconductor light emitting device 1 are deteriorated, and the yield is lowered.

  Such a problem is that a patterned metal layer is formed on the lower surface of the light emitting layer instead of the patterned insulating film 4, and the electrode layer formed in the region without the metal layer is in ohmic contact with the light emitting layer. At the same time, the same occurs in the semiconductor light emitting device that acts as a reflecting surface for the light from the light emitting layer.

  In view of the above, the present invention has a simple structure, and when the semiconductor chip constituting the light emitting layer is separated from each other by dicing, the insulating film, the electrode layer, and the metal layer are peeled off, or the dicing blade has an eye. An object of the present invention is to provide a semiconductor light-emitting device that reduces clogging.

  According to the present invention, the object is to provide a semiconductor substrate having a light emitting layer on the mounting surface side, a patterned insulating film or metal layer formed on the surface of the light emitting layer, and the insulating film or metal layer. A first electrode layer formed on the first electrode layer that is partially in ohmic contact with the light emitting layer in a region without an insulating film or metal layer, and formed on the first electrode layer via a barrier metal layer A junction down structure semiconductor light emitting device comprising: a bonding layer formed on the surface of the semiconductor substrate opposite to the light emitting layer; and the insulating film or the metal layer. The semiconductor light emitting device is characterized in that the electrode layer, the barrier metal layer, and the bonding layer are smaller than the semiconductor substrate and the light emitting layer.

  In the semiconductor light emitting device according to the present invention, preferably, the insulating film or the metal layer, the electrode layer, the barrier metal layer, and the bonding layer are more than half the thickness of a dicing blade used for dicing when separating each chip, It is smaller than the semiconductor substrate and the light emitting layer.

  In the semiconductor light emitting device according to the present invention, preferably, a patterned insulating film is provided between the light emitting layer and the first electrode layer, and the first electrode layer is formed in a region without the insulating film. While being in ohmic contact with the light emitting layer, the insulating film reflects light from the light emitting layer.

  In the semiconductor light emitting device according to the present invention, preferably, a patterned metal layer is provided between the light emitting layer and the first electrode layer, and the first electrode layer is located in a region without the metal layer. While being in ohmic contact with the light emitting layer, the metal layer reflects light from the light emitting layer.

  In the semiconductor light emitting device according to the present invention, preferably, the bonding layer is made of a eutectic material such as AuSn.

  According to the above configuration, when a driving voltage is applied to the first and second electrode layers, the driving voltage is applied to the light emitting layer by ohmic contact, and light is emitted from the light emitting layer.

  In this case, the insulating film or the metal layer, the electrode layer, the barrier metal layer, and the bonding layer are particularly preferably half or more of the thickness of the dicing blade used for dicing when separating each chip, the semiconductor substrate, and the light emission It is formed smaller than the layer. As a result, this dimensional difference acts as a dicing street when separating each chip.

  Accordingly, the insulating film or metal layer, electrode layer, barrier metal layer, and bonding layer are not cut during chip separation. As a result, the insulating film and the metal layer are not broken or separated from the semiconductor layer constituting the light emitting layer by the chip separation process, and the active layer of the light emitting layer is not damaged and is stable. A semiconductor light emitting device can be fabricated.

  Further, when dicing, the dancing blade is not clogged by a soft metal such as AuSn constituting the bonding layer, and chipping does not occur.

  A patterned insulating film is provided between the light emitting layer and the first electrode layer, and the first electrode layer is in ohmic contact with the light emitting layer in a region without the insulating film, and the insulating When the film reflects light from the light emitting layer, the insulating film acts as a reflecting surface, so that light emitted from the light emitting layer to the mounting surface is reflected by the insulating film. Thereby, the light extraction efficiency is improved.

  A patterned metal layer is provided between the light emitting layer and the first electrode layer. The electrode layer formed in the region without the metal layer is in ohmic contact with the light emitting layer, and the metal layer is In the case of reflecting light from the light emitting layer, the metal layer similarly acts as a reflecting surface, so that light emitted from the light emitting layer to the mounting surface is reflected by the metal layer. Thereby, the light extraction efficiency is improved.

  When the bonding layer is made of a eutectic material such as AuSn, the bonding layer is not diced during dicing. For this reason, clogging of the dicing blade by AuSn can be avoided.

Thus, according to the present invention, dicing streets are defined on the outer periphery of each chip when a plurality of chips are manufactured integrally. Thus, the insulating film or metal layer, electrode layer, barrier metal layer, and bonding layer are not cut during dicing.
Therefore, the dicing does not break the insulating film or the metal layer or peel off from the semiconductor layer constituting the light emitting layer, and further, the active layer of the light emitting layer is not damaged and forms the bonding layer. The dancing blade is not clogged by a soft metal such as AuSn, and chipping does not occur.
As a result, a semiconductor light emitting device having stable characteristics can be manufactured with high yield.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS.
The embodiments described below are preferable specific examples of the present invention, and thus various technically preferable limitations are given. However, the scope of the present invention particularly limits the present invention in the following description. As long as there is no description of the effect, it is not restricted to these aspects.

FIG. 1 shows a configuration of an embodiment of a semiconductor light emitting device according to the present invention.
In FIG. 1, a semiconductor light emitting device 10 is a so-called junction down structure semiconductor light emitting device, in which a light emitting layer 12 is formed on the surface (lower surface) of a semiconductor substrate 11, and further below the light emitting layer 12, A p-type electrode 14 and a barrier metal layer 15 are formed through the sequentially patterned insulating film 13. Further, an n-type electrode 16 is formed on the upper surface of the semiconductor substrate 11 to form a chip.

  Further, when the semiconductor light emitting device 10 is mounted, the bonding layer 17 is formed on the lower surface so that the lower surface can be bonded to a connection land formed on a mounting substrate such as a package or a submount. Is formed.

The semiconductor substrate 11 is made of a semiconductor having translucency with respect to the emission wavelength so that light generated in the light emitting layer 12 is transmitted upward.
The light emitting layer 12 is a light emitting layer having a known configuration, and is actually formed by laminating a plurality of semiconductor layers.

The insulating film 13 is composed of SiO ₂ , Si ₃ N ₄ or the like, and is formed by vapor deposition to a thickness that maximizes the reflectance (in the case of SiO ₂ , for example, about 100 nm).
The insulating film 13 is partially removed by patterning so as to enable ohmic contact between the light emitting layer 12 and the p-type electrode 14.
Thereby, an alloy layer as a light absorber is not partially formed by alloying in the ohmic contact between the light emitting layer 3 and the p-type electrode 5. Therefore, in the region where the insulating film 13 exists, light traveling downward from the light emitting layer 12 is reflected by the insulating film 13 and can be effectively extracted upward.

The p-type electrode 14 is formed as an AuZn p-type electrode having a thickness of, for example, 100 to 400 nm, and is brought into ohmic contact with the lower surface of the light emitting layer 12 in a region where the above-described insulating film 13 is not formed. Connected. Here, for each chip, the p-type electrode 14 is formed in a region on the inner side by a size larger than 0 and smaller by 30 μm from the boundary line to be the outer periphery of the chip after chip separation.
Preferably, the film is formed 10 μm or more smaller than the boundary line to be the outer periphery of the chip in consideration of misalignment during element separation, light extraction efficiency due to the size of the p-type electrode, and increase in Vf.

The barrier metal layer 15 is formed by, for example, EB, sputtering, or vapor deposition as a composite barrier metal layer having a TaN / Ta periodic structure, and when the semiconductor light emitting device 10 is mounted on a package, a submount, or the like. In addition, the bonding layer 17 is prevented from exuding to the light emitting layer 12 side.
Here, the size of the barrier metal layer 15 is selected to be slightly smaller than that of the p-type electrode 14.

Further, the barrier metal layer 15 includes an adhesion layer 15 a on the lower surface thereof in order to improve the adhesion of the bonding layer 17.
The adhesion layer 15a is formed by EB, sputtering or vapor deposition similarly to the barrier metal layer 15, and the size thereof is selected to be approximately the same as that of the barrier metal layer 15.

  The n-type electrode 16 is formed as an Au-Ge-Ni n-type electrode on the upper surface of the semiconductor substrate 11 by, for example, vacuum deposition and alloyed.

Since the light emitting layer 12 is close to the mounting surface (the lower surface of the semiconductor light emitting device 10), the bonding layer 17, when a bonding agent such as silver paste is used, causes the molten bonding agent to crawl up the chip side surface and cause leakage. In order to avoid this, a eutectic material such as AuSn is used.
This eutectic material has a thickness sufficient to level the unevenness of the surface of the mounting surface, for example, a thickness of about 1 to 3 μm.
As a result, the semiconductor light emitting device 10 is eutectic bonded to a mounting substrate such as a stem or a package or a submount.

  As described above, the semiconductor device 10 according to the embodiment of the present invention has substantially the same configuration as that of the conventional semiconductor light emitting layer 10. However, in the semiconductor light emitting device 10 according to the embodiment of the present invention, the outer periphery of the chip is provided for each chip. The p-type electrode 14, the barrier metal layer 15, the adhesion layer 15a, and the bonding layer 17 are formed small by 30 to 50 μm along the boundary line to be a part. Thereby, it has a different configuration in that a gap acting as a dicing street is defined between adjacent chip outer peripheral portions.

The semiconductor light emitting device 10 according to the embodiment of the present invention is configured as described above, and is manufactured as follows in the manufacturing process.
That is, first, the light emitting layer 12 is formed on the entire surface of the wafer-like semiconductor substrate 11. Next, the insulating film 13 is formed on the entire surface on the light emitting layer 12 side of the semiconductor substrate 11 having the wafer-like light emitting layer 12.

Subsequently, for patterning the insulating film 13, a resist pattern is formed, and the insulating film 13 is partially removed.
Thus, in the region where the insulating film 13 remains, the formation of the alloy layer is prevented when the p-type electrode 14 is formed.

Thereafter, a resist pattern is formed on the patterned insulating film 13, and a p-type electrode 14 is formed in a region excluding dicing street for each chip. Then, using the p-type electrode 14 as a mask, the insulating film 13 exposed at the periphery is removed to etch the dicing street.
Next, the n-type electrode 16 is formed on the opposite surface of the semiconductor substrate 11.

Further, a resist pattern is formed on the p-type electrode 14 on the light-emitting layer 12 side of the semiconductor substrate 11 and is slightly smaller than the p-type electrode 14 in a region excluding dicing streets. The adhesion layer 15a is formed.
Then, a bonding layer 17 made of a eutectic material is formed which is slightly smaller than the barrier metal layer 15 and the adhesion layer 15a.

Thereafter, dicing is performed for each chip 18 at a pitch of 400 μm, for example. At that time, by using a dicing blade having a kerf width of 20 μm, the finished chip size of each chip 18 after dicing becomes 380 μm.
As the chip separation method, braking may be used.

Here, since the insulating film 13, the barrier metal layer 15, the adhesion layer 15a, and the bonding layer 17 have a dicing street wider than the dicing blade along the boundary line for each chip, In addition, the dicing blade does not hit these insulating film 13, barrier metal layer 15, adhesion layer 15 a, and bonding layer 17.
In this way, the chip 18 of the semiconductor light emitting device 10 shown in FIG. 2 is completed.

According to the semiconductor light emitting device 10 having such a configuration, when mounting on a mounting substrate such as a package or a submount on the stem, the semiconductor light emitting device 10 uses the light emitting layer 12 side as a mounting surface to mount the mounting substrate. Then, the bonding layer 17 is eutectic bonded to the chip mounting portion on the mounting substrate by die bonding. Further, the n-type electrode 16 on the upper surface is wire-bonded to the connection land on the mounting substrate with a gold wire or the like.
Thereby, the mounting of the chip 18 of the semiconductor light emitting device 10 is completed.

In this case, the dicing blade does not hit the insulating film 13 or the metal layer, the electrode layer, or the barrier metal layer when dicing or braking is performed by the dicing blade in order to divide each chip 18. The same applies when braking is used. For this reason, the insulating film 13, the metal layer, the electrode layer, and the barrier metal layer are not cracked or peeled off during chip separation.
Therefore, the yield is improved and the productivity is increased without cracking or peeling of the insulating film 13 or deterioration of the characteristics of the semiconductor light emitting device of the light emitting layer 12.

  Furthermore, the dicing blade does not clog and generate chipping particularly when it hits a soft metal such as AuSn. In this way, it is effective to provide the above-described dicing street when the soft metal has a thickness of 1 μm or more.

  In the above-described embodiment, the semiconductor light emitting device 10 is separated for each chip by dicing after the bonding layer 17 is formed. However, the present invention is not limited to this, and when the barrier metal layer 15 is formed. Alternatively, after being separated for each chip by dicing, die bonding may be performed to the mounting substrate or the like by paste.

In the above-described embodiment, the patterned insulating film 13 is disposed between the p-type electrode 14 and the light emitting layer 12. However, the present invention is not limited to this, and a patterned metal film such as AuZn is formed. Subsequently, an Au—Ge—Ni n-type electrode 16 is formed on the opposite surface of the semiconductor substrate 11 and alloyed, and then the AuZn p-type electrode 14 is removed except for a region to be a dicing street. May be formed.
In this case, the alloying process is not performed after the formation of the p-type electrode 14. For this reason, ohmic contact is formed in the alloyed part, and the other part becomes a mirror, and sufficient light extraction efficiency can be ensured.
In the embodiment, an insulating film, a barrier metal, or the like is formed on the p side of the semiconductor and the p side is the junction surface. However, the same effect can be obtained when the n side opposite to pn is the junction surface. It is done.

  In this way, according to the present invention, when the chips are separated by dicing with a simple configuration, the semiconductor constituting the light emitting layer is separated from the insulating film or the metal layer, or the dicing blade is clogged. Thus, a semiconductor light emitting device can be provided.

It is a schematic sectional drawing which shows the structure of one Embodiment of the semiconductor light-emitting device by this invention. It is a schematic sectional drawing which shows the state isolate | separated for every chip | tip of the semiconductor light-emitting device of FIG. It is a schematic sectional drawing which shows the structure of an example of the conventional semiconductor light-emitting device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor light-emitting device 11 Semiconductor substrate 12 Light emitting layer 13 Patterned insulating film 14 P-type electrode 15 Barrier metal layer 15a Adhesion layer 16 N-type electrode 17 Bonding layer 18 Chip

Claims (5)

A semiconductor substrate having a light emitting layer on the mounting surface side, a patterned insulating film or metal layer formed on the surface of the light emitting layer, and an insulating film or metal layer formed on the insulating film or metal layer A first electrode layer that is partially in ohmic contact with the light-emitting layer in a region having no contact, a bonding layer formed on the first electrode layer via a barrier metal layer, and the semiconductor substrate A semiconductor light emitting device having a junction down structure including a second electrode layer formed on a surface opposite to the light emitting layer,
A semiconductor light emitting device characterized in that the insulating film or metal layer, electrode layer, barrier metal layer and bonding layer are smaller than the semiconductor substrate and the light emitting layer.   2. The semiconductor light emitting device according to claim 1, wherein the insulating film or metal layer, electrode layer, barrier metal layer, and bonding layer are 10 [mu] m or more smaller than an end face of the semiconductor substrate from which elements are separated.   A patterned insulating film is provided between the light emitting layer and the first electrode layer, and the first electrode layer is in ohmic contact with the light emitting layer in a region without the insulating film, and the insulating The semiconductor light emitting device according to claim 1, wherein the film reflects light from the light emitting layer.   A patterned metal layer is provided between the light emitting layer and the first electrode layer, and the first electrode layer is in ohmic contact with the light emitting layer in a region without the metal layer, and the metal The semiconductor light-emitting device according to claim 1, wherein the layer reflects light from the light-emitting layer.   5. The semiconductor light emitting device according to claim 1, wherein the bonding layer is made of a eutectic material such as AuSn.

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