WO2015141166A1

WO2015141166A1 - Semiconductor light-emitting device and method for manufacturing same

Info

Publication number: WO2015141166A1
Application number: PCT/JP2015/001188
Authority: WO
Inventors: 竜馬斎藤; 優志竹原
Original assignee: スタンレー電気株式会社
Priority date: 2014-03-17
Filing date: 2015-03-05
Publication date: 2015-09-24
Also published as: JP2015177087A

Abstract

A semiconductor light-emitting device has: a semiconductor stacked layer including stacked layers of a first semiconductor layer having a first conductivity type, an active layer, and a second semiconductor layer having a second conductivity type; a second electrode formed on the second semiconductor layer and having a high reflectivity; a recess extending from the surface of the second semiconductor layer into the first semiconductor layer through the second semiconductor layer and the active layer, exposing the semiconductor stacked layers to the side surface, and exposing the first semiconductor layer to the bottom surface; an insulating film having an opening at the bottom surface of the recess and covering the side surface of the recess; a contact region formed by digging down the first semiconductor layer exposed to the opening; a first semiconductor layer side contact electrode forming an electrical contact with the surface of the contact region, creeping up to the upper surface of the insulating film in the vicinity of the opening, and having a smoothly continuous hook portion; and a first semiconductor layer side high-reflectivity electrode having a high reflectivity to the light emitted from the semiconductor stacked layer and extending from above the first semiconductor layer side contact electrode onto the insulating film.

Description

Semiconductor light emitting device and manufacturing method thereof

The present invention relates to a semiconductor light emitting device and a method for manufacturing the same.

Al _1-xy Ga _x In _y N (0 ≦ x, y ≦ 1, 0 ≦ (x + y) ≦ 1, hereinafter referred to as GaN-based GaN series) light emitting diodes capable of generating white light and the like have been developed. For example, an n-type GaN-based layer, a multiple quantum well GaN-based active layer, and a p-type GaN-based layer are grown on a sapphire substrate by metal organic chemical vapor deposition (MOCVD) to form a GaN-based semiconductor epitaxial stack. In order to function as a light emitting diode (LED), it is necessary to connect an electrode capable of supplying charge carriers to the p-type GaN-based layer and the n-type GaN-based layer. For example, a p-side electrode layer is formed on the exposed p-type GaN-based layer, etched into a predetermined shape to form a p-side electrode, and then the p-type GaN-based layer and the GaN-based active layer are etched to form n A via hole exposing the type GaN layer is formed, a necessary insulating structure is formed, and an n-side electrode connected to the bottom surface of the via hole is formed (for example, JP-T-2010-525585). A support substrate provided with a connection wiring layer connected to the p-side electrode and the n-side electrode can be bonded above the p-type layer.

The sapphire substrate cannot be said to have excellent heat dissipation characteristics. A configuration is known in which an n-type GaN-based layer is exposed by removing a sapphire substrate that functions as a growth substrate. When a p-side electrode and an n-side electrode are formed on the p-type GaN-based layer side, the entire surface of the n-type GaN-based layer exposed by removing the growth substrate can be used as a light emitting surface. When the exposed n-type layer surface is roughened (fine processing such as micro cones), the light extraction efficiency can be improved.

The p-side electrode is formed by widely reflecting a reflective electrode mainly composed of Ag on the surface of the p-type layer, and can reflect the light directed toward the back side in the p-type layer to the surface (n-type layer) side. . By increasing the reflectance, the light extraction efficiency can be improved (for example, JP 2010-123717 A).

When the n-side electrode is arranged in the via hole and the wiring is routed to the p-type layer surface side, the light emitting function is lost because the active layer in the via hole is removed. However, the n-type GaN-based layer exists on the n-side electrode (on the light emission surface side) and can propagate light from the surrounding region. It can be considered that the n-side electrode is used as a reflective electrode to reflect as much propagating light as possible on the surface side of the n-type layer to alleviate luminance unevenness.

The contact electrode that ensures contact with the n-type layer generally has a low reflectance. In order to increase the reflectivity, it is conceivable to form the n-side electrode with a contact electrode and a reflective metal layer that covers the contact electrode and has a high reflectivity and is mainly composed of Ag or the like.

DISCLOSURE OF THE INVENTION A first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer are laminated, a second conductivity type side high reflectance electrode having an opening is formed on the second conductivity type semiconductor layer, Etching the second conductive type semiconductor layer and the active layer to expose the first conductive type semiconductor layer, forming a contact electrode on the first conductive type semiconductor layer to ensure contact, and providing a high reflectivity above the contact electrode The structure which forms the 1st conductivity type side high reflectance electrode to ensure, and radiate | emits light from the 1st conductivity type semiconductor layer side was examined. Note that the high reflectance indicates an average reflectance of 80% or more in the wavelength range of 350 nm to 850 nm including the visible light region (380 nm to 760 nm).

Since the reflectivity of the contact electrode is low, the area of the contact electrode extending outside the contact surface is limited as narrow as possible, and the first conductivity type side high reflectivity electrode is distributed around the first conductivity type layer. An attempt was made to reflect the propagating light at the high reflectivity electrode. However, a phenomenon occurs in which the electrical continuity between the contact electrode and the connection wiring, and thus the light emission phenomenon itself, is impaired. It has been difficult to realize a highly reliable first-conductivity-type side electrode with high reflectivity.

According to the example,
A semiconductor stack including a stack of a first semiconductor layer having a first conductivity type, an active layer, and a second semiconductor layer having a second conductivity type;
A second electrode having a high reflectance formed on the second semiconductor layer;
A recess that penetrates the second semiconductor layer and the active layer from the surface of the second semiconductor layer, enters the first semiconductor layer, exposes the semiconductor stack on a side surface, and exposes the first semiconductor layer on a bottom surface; ,
An insulating film having an opening on a bottom surface of the recess and covering the side surface of the recess;
A contact region formed by digging down the first semiconductor layer exposed in the opening;
A first semiconductor layer-side contact electrode that forms an electrical contact with the surface of the contact region, has a hook portion that smoothly wraps around the upper surface of the insulating film adjacent to the opening and is continuous;
A first semiconductor layer-side high reflectivity electrode having a high reflectivity with respect to light emitted from the semiconductor stack, and extending from the first semiconductor layer-side contact electrode to the insulating film;
A semiconductor light emitting device is provided.

According to the example,
Epitaxially growing a semiconductor stack including a stack of a first semiconductor layer having a first conductivity type, an active layer, and a second semiconductor layer having a second conductivity type on a growth substrate;
Etching from the surface of the second semiconductor layer through the second semiconductor layer and the active layer and entering the first semiconductor layer, exposing the semiconductor stack on the side, and exposing the first semiconductor layer on the bottom Forming a recess to be
Covering the recess inner surface and forming an insulating film;
Forming a laminated resist layer of a sacrificial resist lower layer and a photoresist upper layer on the insulating film;
Exposing the photoresist upper layer with a pattern having an opening in the recess bottom;
Developing the laminated resist layer, lowering the sacrificial resist lower layer end from the photoresist upper layer end to form a drawing space above the insulating film;
Etching the insulating film using the laminated resist layer as an etching mask, digging down the first semiconductor layer below to form a contact region of the first semiconductor layer;
A contact metal layer is deposited on the first semiconductor layer in the contact region, the insulating film thereon, and the laminated resist layer to form a contact electrode having a hook portion disposed on the bottom shoulder of the lead-in space. And a process of
Removing the laminated resist layer and lifting off the contact metal deposited thereon;
Forming a high reflectivity electrode covering the contact electrode and extending over the surrounding insulating film;
A method of manufacturing a semiconductor light-emitting device having the above is provided.

1A to 1H are cross-sectional views showing main processes of a method for manufacturing a semiconductor light emitting device according to an embodiment.

2A to 2F are cross-sectional views showing main processes of a method for manufacturing a semiconductor light-emitting device based on a preliminary experiment.

3A and 3B are cross-sectional views showing the main points of a method for manufacturing a semiconductor light emitting device according to an embodiment.

4A is a plan view showing an arrangement example of the p-side electrode and the n-side electrode, FIG. 4B is a cross-sectional view showing an example of the configuration of the p-side electrode, and FIGS. 4C-4E are plan views showing other arrangement examples of the recesses.

FIG. 5 is a cross-sectional view showing a configuration example of the semiconductor light emitting device in a completed state.

First, a preliminary experiment will be described.

As shown in FIG. 2A, an n-type GaN layer 2, an active layer 3, and a p-type GaN layer 4 are grown on a sapphire growth substrate 1 by metal organic chemical vapor deposition (MOCVD). On the p-type GaN layer 4, a p-side electrode 5 such as Ag having a high reflectance is formed. A cap insulating layer 10 such as silicon oxide is deposited so as to cover the p-side electrode 5. A photoresist pattern is formed on the insulating layer 10 to serve as a mask when etching the recesses in the semiconductor layer. Etching the entire thickness of the insulating layer 10, the p-type layer 4 and the active layer 3 in the opening of the mask, and further etching a part of the thickness of the n-type layer 2 to form a recess 15 exposing the n-type layer 2. To do. Thereafter, the photoresist pattern is removed. A float insulating film 12 such as silicon oxide covering the inner surface of the recess 15 is deposited. On the insulating film 12, a new photoresist pattern PR1 having an opening on the bottom surface (central portion) of the recess 15 is formed.

2B, using the photoresist pattern PR1 as an etching mask, the insulating film 12 and the n-type layer 2 are partially etched to form a contact region 16 on the bottom surface of the recess 15. Contact region 16 includes a region from which insulating layer 12 has been removed and a region from which n-type layer 2 has been removed. The insulating layer 12 has a bottom surface portion having a surface parallel to the bottom surface of the recess 15 around the contact region 16.

2C, a contact metal layer CM such as Ti is deposited on the surface of the contact region 16 and the surface of the resist pattern PR1. The photoresist pattern PR1 used as an etching mask is also used as a lift-off resist pattern for shaping the contact metal layer.

2D, the photoresist pattern PR1 is removed and the contact metal on the photoresist pattern PR1 is removed by lift-off. The photoresist pattern PR1 is a resist pattern that can withstand the dry etching process shown in FIG. 2B, and is a forward tapered resist pattern in which the opening width becomes narrower from the top to the bottom.

In order to perform the lift-off, it is preferable to use a positive resist pattern having a reverse taper shape in which the opening width becomes narrower from the bottom to the top, in other words, the upper part of the resist pattern protrudes from the lower part. However, if the photoresist pattern is once removed and re-formed at this stage, the displacement will almost certainly occur. Therefore, the same photoresist pattern must be used as an etching mask and a lift-off mask.

In the step shown in FIG. 2D, after the contact metal layer CM is patterned by lift-off, a high reflectivity electrode RM is formed, covers the contact metal layer CM, and further extends on the insulating layer 12 to end the p-side electrode 5 Patterning is performed so as to cover a region almost reaching the part.

As shown in FIG. 2E, a lift-off resist pattern PR2 for patterning the high reflectance electrode RM is formed on the insulating film 12. A high reflectivity electrode RM such as Ag is formed on the contact metal layer CM and the insulating film 12 by electron beam evaporation, sputtering, or the like.

As shown in FIG. 2F, the high reflectivity electrode RM deposited on the photoresist pattern PR2 is lifted off together with the photoresist pattern PR2 to be removed. The patterned high reflectivity electrode RM covers the contact metal layer CM and the region above between the contact metal layer CM and the p-side electrode 5.

The n-side electrode formed by laminating the contact metal layer CM and the high reflectivity electrode RM thus formed does not exhibit stable characteristics and often breaks when a large current is passed. When the cause is investigated, irregularities such as irregularities are formed at the end of the contact metal layer CM after lift-off shown in FIG. 2D, and the high reflectance electrode RM is formed as shown in FIG. 2E. However, there is a high possibility that the high reflectance electrode RM on the contact metal layer CM and the high reflectance electrode RM on the insulating film 12 are not electrically continuous.

If the resist pattern for lift-off is created separately from the resist pattern for the etching mask, the end shape of the contact metal layer after the lift-off will be able to be suitably created, but if the mask is re-created, positional deviation will occur. It is not preferable. Therefore, the contact metal layer is deposited on the n-type layer and the resist pattern while leaving the resist pattern used for the recess etching, and the contact metal on the resist pattern is completely separated from the contact metal layer on the n-type layer. I examined that.

Consider an example in which a sacrificial layer made of a material that can be wet etched with a resist developer is formed under the resist layer. An example of the material for the sacrificial layer is the LOR series available from Nippon Kayaku Co., Ltd. The sacrificial layer is gradually dissolved only by being immersed in a developer such as TMAH (tetramethylammonium hydroxide).

A photoresist layer is formed with a laminated structure of a lower sacrificial layer and an upper photoresist layer. When the upper photoresist layer is exposed and developed, the upper photoresist layer becomes the desired pattern. In the development process of the upper photoresist layer, the lower sacrificial layer exposed by removing the upper photoresist layer is etched into the developer. The end of the lower sacrificial layer is drawn from the end of the upper photoresist layer.

As shown in FIG. 3A, the photoresist layer PR1 in the step shown in FIG. 2A is replaced with a two-stage resist DLR of a lower sacrificial layer SR and an upper photoresist layer PR. The lower sacrificial layer SR is formed by, for example, LOR available from Nippon Kayaku Co., Ltd., and the upper photoresist layer PR that can withstand dry etching is formed by, for example, AZ6130 manufactured by AZ.

Following the etching of the recess 15 and the formation of the float insulating film 12, the lower sacrificial layer SR is spin-coated, for example, with a thickness of about 300 nm to 500 nm, and the upper photoresist layer PR is, for example, several μm thick, to form a two-stage resist DLR. . For example, exposure is performed at 400 mJ and development is performed for 50 seconds.

The upper photoresist layer PR of the opening set on the bottom of the recess is patterned as usual. The lower sacrificial layer SR exposed by the removal of the upper photoresist layer PR is also etched by the developer, and opens in a wider range than the resist pattern. A pull-in region 17 in which the lower sacrificial layer SR is side-etched (under-etched) is formed with a width of about 2.5 μm, for example.

Using this two-stage resist, the contact region 16 is formed by etching to form a recess in the insulating film 12 and the n-type layer 2 as in the step shown in FIG. 2B. The upper photoresist layer PR functions as an etching mask. A lead-in region 17 is disposed on the shoulder 14 of the patterned insulating film 12.

As shown in FIG. 3B, a contact metal layer CM is deposited by sputtering. Here, between the photoresist layer PR and the insulating film 12, there is a lead-in region 17 generated by side etching of the sacrificial layer SR. The sputtered high-energy metal raw material also enters the pull-in region 17 and continues to the tip of the main part of the contact metal layer formed on the side wall of the recess, and is smoothly bent into a hook shape (enters the pull-in region 17). A film 18 having a smooth surface is formed. The metal film CM1 having a hook-shaped tip formed so as to surround the shoulder of the insulating film 12 is completely separated from the metal film CM2 deposited on the photoresist pattern PR, and deformation caused by stress is suppressed.

Thereafter, the sacrificial layer SR and the photoresist pattern PR are removed, and the metal thereon is lifted off. Since the metal layer CM2 deposited on the photoresist pattern PR is completely separated from the metal layer CM1 deposited on the n-type layer 2 and the insulating layer 12, the end of the metal layer CM1 is deformed by lift-off. There is nothing to do. An end portion of the hook-shaped metal layer CM1 having a smoothly continuous surface from the surface of the insulating film 12 is obtained. When the reflective metal layer is deposited, a continuous reflective metal layer is obtained from the contact layer CM1 to the insulating film 12. Although only the main points have been described, the main steps of the method for manufacturing a semiconductor light emitting device according to the embodiment will be described below.

Refer to FIG. 1A. For example, a sapphire substrate is prepared as the growth substrate 1. The growth substrate 1 is put into an MOCVD apparatus and thermal cleaning is performed. After growing the GaN buffer layer and the undoped GaN layer, an n-type GaN layer 2 having a thickness of about 5 μm doped with Si or the like is grown. In FIG. 1A and the like, the GaN buffer layer and the undoped GaN layer are collectively shown as the n-type GaN layer 2.

A light emitting layer (active layer) 3 is grown on the n-type GaN layer 2. As the light emitting layer 3, for example, a multiple quantum well structure in which an InGaN layer is a well layer and a GaN layer is a barrier layer can be formed. A p-type GaN layer 4 having a thickness of about 0.5 μm doped with Mg or the like is grown on the light emitting layer 3.

The growth substrate 1 is a single crystal substrate having a lattice constant capable of epitaxial growth of GaN, and is transparent to light having a wavelength of 362 nm which is an absorption edge wavelength of GaN so that the substrate can be peeled off by laser lift-off in a later process. Selected from ones. In addition to sapphire, spinel, SiC, ZnO, or the like may be used.

On the p-type GaN layer 4, for example, a layer having a thickness of 200 nm is deposited by electron beam evaporation and Ag is added with an additive such as Al, Pt, Rh, or an alloy thereof, and patterning is performed by lift-off. Then, the high reflectance p-side electrode 5 having a predetermined shape is formed. The p-side electrode 5 preferably contains Ag, Al, Pt, Rh, or an alloy thereof in order to function as a reflective electrode.

The p-side electrode 5 has a plurality of openings and is covered with a cap insulating layer 10 such as silicon oxide. A recess 15 is formed by etching the cap insulating layer and the semiconductor layer in the opening, and the contact region is further etched in the recess to form a contact metal layer in the contact region. A high reflectivity electrode is formed above the contact metal layer to form an n-side electrode including the contact metal layer and the high reflectivity electrode.

FIG. 4A shows an example of a schematic planar structure of the contact portion between the p-side electrode 5 and the n-side contact electrode CM in the semiconductor light emitting element with the semiconductor layer. A p-side electrode 5 is formed extending over the upper surface of the p-type semiconductor layer. Openings are formed discretely in a matrix, for example, in the p-side electrode 5, and the recesses RC are disposed in the openings. An n-side contact electrode CM is formed inside each recess RC. One element has, for example, a rectangular shape with a size of about 600 μm × 1300 μm, and the number of contact electrodes CM arranged in one element is several tens to several hundreds, for example, about 40. FIGS. 1A to 1H typically show one n-side contact electrode CM and one opening HL formed in the p-side electrode 5.

Returning to FIG. 1A, covering the p-side electrode 5, for example, a SiO ₂ film having a thickness of 300 nm is deposited by sputtering, and patterned by lift-off to form a cap insulating layer 10. As a patterning method, in addition to lift-off, for example, dry etching using a CF ₄ gas may be used after depositing SiO ₂ on the entire surface. The cap insulating layer 10 has a function of preventing leakage and diffusion of the material used for the p-side electrode 5, particularly Ag. In order to prevent leakage and diffusion of Ag, a metal material such as TiW can be used in addition to an insulating material such as SiO ₂ and SiN.

The insulating layer 10 is also formed in the vicinity of the edge of the opening HL of the p-side electrode, and is formed so as to extend also on the side surface of the p-side electrode 5 that defines the opening HL. A photoresist pattern having an opening in the opening HL of the p-side electrode 5 is formed on the insulating layer 10, the insulating layer 10, the p-type layer 4, and the active layer 3 are etched, and further, a partial thickness of the n-type layer 2 The recess 15 is formed by etching.

A float insulating layer 12 made of silicon oxide or the like is formed so as to cover the inner surface of the recess 15, and a two-step resist DLR is applied on the insulating layer 12. The two-step resist is exposed and developed to form an opening above the bottom surface of the recess 15. It is the process demonstrated with reference to FIG. 3A. When the two-stage resist DLR is exposed and developed, the sacrificial layer SR forms an opening in a wider range than the photoresist layer PR. For example, an undercut region having a width of about 2.5 μm can be formed by developing for 50 seconds.

As shown in FIG. 1B, openings are formed in the photoresist layer PR and the sacrificial layer SR of the two-stage resist DLR above the bottom surface of the recess 15, and the openings of the sacrificial layer SR are further widened. A lead-in region 17 is formed between the photoresist layer PR and the insulating layer 12. This is the configuration described with reference to FIGS. 3A and 3B.

As shown in FIG. 1C, using the two-stage resist DLR as an etching mask, the insulating layer 12 and the n-type layer 2 are partially etched with a chlorine-based gas to form a contact region 16 in the n-type layer 2. . It is a process corresponding to FIG. 2B. The inner side surface of the insulating layer 12 and the inner side surface of the photoresist PR are separated by a drawing region 17.

As shown in FIG. 1D, a contact metal layer CM is deposited by sputtering a contact metal, for example, Ti. The contact metal deposited on the n-type layer 2 and the insulating layer 12 forms the contact metal layer CM, and the migrated contact metal extends on the bottom surface of the lead-in region 17. The contact metal layer CM extending from the side surface to the bottom surface of the recess has a hook portion whose tip is bent into a hook shape, and improves the adhesion. The contact metal deposited on the photoresist PR is separated from the contact metal layer CM on the bottom surface and the lower side surface of the recess in the drawing region 17. Since both contact metal layers are separated, no stress is exerted.

As shown in FIG. 1E, the two-stage resist is removed and the contact metal on the photoresist layer PR is lifted off. The contact metal layer CM formed on the bottom and side surfaces of the contact region 16 further extends on the upper surface of the opening peripheral edge of the insulating film 12.

As shown in FIG. 1F, a photoresist pattern PR2 for patterning the high reflectivity electrode by lift-off is formed. The photoresist pattern PR2 has a reverse tapered cross-sectional shape. It is a process corresponding to FIG. 2E.

As shown in FIG. 1G, an Ag / Ti / Pt / Au layer is deposited on the n-side contact metal electrode CM and the insulating film 12 by, for example, electron beam evaporation or sputtering, with a film thickness of 200 nm / 100 nm / 200 nm / 200 nm, respectively. The n-side high reflectivity electrode RM is formed by patterning by lift-off. The n-side high reflectivity electrode RM is formed so that the edge thereof overlaps with the edge of the p-side electrode 5 in plan view. Note that a Ti layer may be formed as a base for the Ag layer in order to improve adhesion.

However, since the reflectance decreases, the thickness of this Ti layer is 5 nm or less, for example, 1 nm. The contact metal layer CM preferably contains any one of Ti, Ni, and Cr, and the high reflectivity electrode preferably contains Ag, Al, Pt, Rh, or any of these alloys.

As shown in FIG. 1H, a photoresist pattern for lift-off is formed, and a Ti / Pt / Au layer is deposited to a thickness of 50 nm / 100 nm / 400 nm by electron beam evaporation or sputtering, respectively, and patterned by lift-off to provide cap conductivity. Layer NC is formed. Note that the cap conductive layer is not an essential component.

In this way, an n-side electrode including contact metal electrodes and high reflectivity electrodes having different shapes can be formed. The area of the contact metal electrode is limited, and the high reflectance electrode is widely disposed around the contact metal electrode, so that the reflectance as a whole is improved.

In order to improve the adhesion of the high reflectivity electrode RM to the insulating film 12, the surface of the insulating film 12 may be roughened by performing reverse sputtering of Ar gas, for example, in the state of FIG. 1E.

The case where the single-layer p-side electrode 5 is formed as the p-side electrode has been described. Other various configurations of the p-side electrode can also be used. FIG. 4B shows one example. In FIG. 4B, the state of the electrode end portion on the surface of the p-type layer 4 is also shown together with the configuration in the recess RC. An Ag alloy layer 6 and an insulating fringe layer 13 containing an additive for improving contact properties are formed on the p-type layer 4, and no additive is contained in a region including the upper surface of the Ag alloy layer 6 and extending to the upper surface of the insulating fringe layer 13. A pure silver layer 7 and a cap metal layer 8 such as TiW having an Ag diffusion preventing function are laminated to form a p-side electrode 5, and a cap insulating layer 10 and a float insulating film 12 are formed to cover the insulating fringe layer 13. In this case, the cap insulating layer is preferably formed of a light-transmitting insulating material such as SiO ₂ or SiN.

The configuration in which the p-side electrode and the n-side electrode are formed above the AlGaInN epitaxial layer has been described. Subsequently, after the supporting substrate having the connection wiring is bonded, the epitaxial layer and the supporting substrate are cut, the growth substrate is peeled off, and the light emitting devices can be divided.

FIG. 5 is a cross-sectional view showing one configuration example of such a semiconductor light emitting device. A wiring layer 23 including an n-side connection wiring layer and a p-side connection wiring layer is formed on the support substrate 21 via an insulating layer 22 and is coupled to the n-side electrode and the p-side electrode of the light emitting diode. The growth substrate is removed by laser lift-off or the like. Microcones are formed on the exposed n-type layer surface by alkali treatment or the like. Street separation, scribing, and the like are performed to constitute a unit having a desired number of

light emitting elements

31A and 31B. The support substrate 21 of the unit is mounted on the mounting

substrates

41 and 42 via the adhesive layer 26, and the pads 44 and the wire bonding 43 are performed. The light emitting diode structure is sealed with a sealing resin 45 containing a phosphor.

The case where a plurality of n-side contact electrodes are formed in a distributed manner has been described with reference to FIG. 4A. In FIG. 4A, the recesses RC are arranged as via electrode formation regions that are dispersed in the plane. The cross section of each recess RC is configured as shown in FIG. 1H. The shape of the n-side contact electrode and the recess RC that accommodates it is not limited thereto. As shown in FIG. 4C, the n-side electrode may be formed with the chip periphery as a recess RC. As shown in FIG. 4D, the recess RC may be a continuous groove. In FIG. 4D, a cross section perpendicular to the direction in which the groove extends is as shown in FIG. 1H. In FIG. 4C, the cross section perpendicular to the direction in which the side of the peripheral portion of the chip extends is such that the contact metal layer CM in FIG. 1H is cut from the center. As shown in FIG. 4E, the recess RC may be a combination of a hole area and a groove area.

As mentioned above, although it demonstrated along the Example, these do not have a restrictive meaning. The semiconductor exemplified by GaN may be other AlGaInN such as InGaN. Various materials can be used as the n-type impurity and the p-type impurity. As the active layer, a homo to hetero single layer active layer may be used instead of the multilayer quantum well structure. The exemplified materials and numerical values do not have a restrictive meaning unless otherwise specified. Various additions, changes, improvements, combinations, and the like are possible.

Claims

A semiconductor stack including a stack of a first semiconductor layer having a first conductivity type, an active layer, and a second semiconductor layer having a second conductivity type;
A second electrode having a high reflectance formed on the second semiconductor layer;
A recess that penetrates the second semiconductor layer and the active layer from the surface of the second semiconductor layer, enters the first semiconductor layer, exposes the semiconductor stack on a side surface, and exposes the first semiconductor layer on a bottom surface; ,
An insulating film having an opening on a bottom surface of the recess and covering the side surface of the recess;
A contact region formed by digging down the first semiconductor layer exposed in the opening;
A first semiconductor layer-side contact electrode that forms an electrical contact with the surface of the contact region, has a hook portion that smoothly wraps around the upper surface of the insulating film adjacent to the opening and is continuous;
A semiconductor light emitting device having a high reflectivity with respect to light emitted from the semiconductor stack and having a first semiconductor layer side high reflectivity electrode extending from the first semiconductor layer side contact electrode to the insulating film .
The semiconductor light emitting device according to claim 1, wherein the first semiconductor layer, the active layer, and the second semiconductor layer are formed of an AlGaInN epitaxial layer.
The semiconductor light emitting device according to claim 1, wherein the first semiconductor layer side contact electrode includes any one of Ti, Ni, and Cr.
2. The semiconductor light emitting device according to claim 1, wherein the first semiconductor layer side high reflectivity electrode includes Ag, Al, Pt, Rh, or an alloy thereof.
The semiconductor light emitting device according to claim 1, wherein the recess is distributed in a plurality of regions.
The semiconductor light emitting device according to claim 1, wherein the recess includes a combination of a hole-shaped region and a groove-shaped region.
The semiconductor light emitting device according to claim 1, further comprising a concavo-convex structure formed on the surface of the first semiconductor layer.
The semiconductor light emitting device according to claim 1, further comprising a phosphor layer covering the surface of the first semiconductor layer.
Epitaxially growing a semiconductor stack including a stack of a first semiconductor layer having a first conductivity type, an active layer, and a second semiconductor layer having a second conductivity type on a growth substrate;
Etching from the surface of the second semiconductor layer through the second semiconductor layer and the active layer and entering the first semiconductor layer, exposing the semiconductor stack on the side, and exposing the first semiconductor layer on the bottom Forming a recess to be
Covering the recess inner surface and forming an insulating film;
Forming a laminated resist layer of a sacrificial resist lower layer and a photoresist upper layer on the insulating film;
Exposing the photoresist upper layer with a pattern having an opening in the recess bottom;
Developing the laminated resist layer, lowering the sacrificial resist lower layer end from the photoresist upper layer end to form a drawing space above the insulating film;
Etching the insulating film using the laminated resist layer as an etching mask, digging down the first semiconductor layer below to form a contact region of the first semiconductor layer;
Wherein the first semiconductor layer of said contact region, said insulating layer thereon, said depositing a contact metal layer on the laminated resist layer, a contact electrode having a hook component which is arranged on the bottom shoulder of the pull-space Forming, and
Removing the laminated resist layer and lifting off the contact metal deposited thereon;
Forming a high reflectivity electrode covering the contact electrode and extending over the surrounding insulating film;
A method of manufacturing a semiconductor light emitting device having
The method for manufacturing a semiconductor light emitting device according to claim 9, further comprising a step of forming a second conductive layer side electrode having high reflectivity on the second semiconductor layer after the step of epitaxially growing the semiconductor stack.
The method of manufacturing a semiconductor light emitting device according to claim 10, wherein the second conductive layer side electrode includes Ag, Al, Pt, Rh, or an alloy thereof.
The method of manufacturing a semiconductor light emitting device according to claim 10, further comprising a step of forming a diffusion prevention film that covers the second conductive layer side electrode.
After the step of forming the second conductive layer side electrode, further comprising the step of forming a cap insulating film covering the second conductive layer side electrode;
11. The method of manufacturing a semiconductor light emitting layer device according to claim 10, wherein the step of forming a recess exposing the first semiconductor layer is performed by forming a resist mask on the cap insulating film.
The method for manufacturing a semiconductor light emitting device according to claim 9, wherein the developing process of the laminated resist layer uses a developer containing TMAH.
The method for manufacturing a semiconductor light emitting device according to claim 9, wherein in the step of forming the contact electrode, a raw material containing any one of Ti, Ni, and Cr is sputtered.
10. The method of manufacturing a semiconductor light emitting device according to claim 9, wherein the step of forming the high reflectivity electrode includes electron beam evaporation or sputtering of a raw material containing any of Ag, Al, Pt, Rh, and alloys thereof.
The method of manufacturing a semiconductor light emitting device according to claim 9, further comprising a step of roughing the surface of the second insulating film by reverse sputtering with Ar gas before the step of forming the high reflectivity electrode.
After the high reflectivity electrode formation step, a step of bonding a support substrate to the second semiconductor layer side surface;
Removing the growth substrate;
Applying a phosphor layer over the first semiconductor layer side surface;
The method for manufacturing a semiconductor light emitting device according to claim 9, further comprising:
The method of manufacturing a semiconductor light emitting device according to claim 18, wherein the step of removing the growth substrate includes laser lift-off, and the growth substrate is formed of sapphire, spinel, SiC, or ZnO.
The method of manufacturing a semiconductor light emitting device according to claim 18, further comprising a step of forming a concavo-convex structure on the surface of the first semiconductor layer after the step of removing the growth substrate.