JP2007223093A - Optical head and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make an optical head compact by arranging each light emitting element and a selecting circuit so as to overlap each other. <P>SOLUTION: A first substrate 10 and a second substrate 20 are opposed to each other in the optical head. Both a plurality of the light emitting elements E and a plurality of unit circuits U corresponding respectively to the light emitting elements E are arranged on a surface of the second substrate 20. Both a data signal line LD where a data signal D designating a tone of each light emitting element E is supplied, and a shift register 43 sequentially selecting each unit circuit U are arranged on a surface of the first substrate 10. Each unit circuit U controls light emission of the light emitting element E corresponding to the unit circuit U on the basis of the data signal D acquired from the data signal line LD in accordance with the selection by the shift register 43. Both a transistor Q constituting the shift register 43 and each light emitting element E overlap each other when seen from a direction perpendicular to the first substrate 10 and the second substrate 20. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for controlling a light emitting element such as an organic light emitting diode element.

2. Description of the Related Art Conventionally, an image forming apparatus using an optical head (line head) in which a large number of light emitting elements are arranged on a substrate for exposure of an image carrier such as a photosensitive drum has been proposed. For example, Patent Document 1 discloses an optical head in which various elements related to driving of each light emitting element are arranged on the surface of one substrate together with many light emitting elements. On the surface of the substrate, for example, a plurality of signal lines to which a data signal designating the gradation of each light emitting element is supplied, or a plurality of data signals acquired (sampled) from the signal line for driving each light emitting element. Switching elements, a shift register for sequentially switching each switching element to an ON state, and the like are arranged.
Japanese Patent Laying-Open No. 2005-231171 (FIG. 7)

However, in the configuration of Patent Document 1, a large substrate is required for the arrangement of the various elements as described above, and thus there is a problem that miniaturization of the optical head and the image forming apparatus using the same is restricted. was there. Against this background, the present invention aims to solve the problem of downsizing the optical head.

In order to solve the above problems, an optical head according to the present invention is supplied with a plurality of light emitting elements, a plurality of unit circuits corresponding to each light emitting element, and a data signal designating the gradation of each light emitting element. 2 includes a signal line (for example, the data signal line LD in FIG. 2) and a selection circuit (for example, the shift register 43 in FIG. 2 and the sampling circuit 45 in FIG. 10) for sequentially selecting each unit circuit. Based on the data signal acquired from the signal line according to the selection by the selection circuit, the light emission of the light emitting element corresponding to the unit circuit is controlled. Each light emitting element and the selection circuit are, for example, a substrate on which each light emitting element is arranged. Overlapping when viewed from the direction perpendicular to More specifically, in an optical head in which the selection circuit includes a transistor (for example, the transistor Q in FIG. 6 or the transistor SW in FIG. 10), each light-emitting element is, for example, a semiconductor layer (for example, FIG. 6
Of the semiconductor layer 11).

According to the above configuration, since each light emitting element and the selection circuit are arranged so as to overlap each other, the optical head can be downsized as compared with the configuration arranged so that each light emitting element and the selection circuit do not overlap each other. It is possible. For example, if each light emitting element and the selection circuit overlap each other when viewed from the direction perpendicular to the substrate on which each light emitting element is arranged, the light emitting element and the selection circuit are arranged in separate areas of the substrate. Thus, the substrate can be reduced in size.

The light-emitting element of the present invention is an element that emits light by application of electric energy (for example, supply of electric current or application of an electric field), for example, an organic light-emitting diode element that emits light by supplying electric current. The “plurality of light emitting elements” in the present invention may be all light emitting elements included in the optical head or a part of the light emitting elements. Therefore, it is not necessary that all the light emitting elements of the optical head overlap the selection circuit.

In a preferred aspect of the present invention, each light emitting element includes a first electrode and a second electrode facing each other, and a light emitting layer interposed between the two electrodes, and the second electrode of each light emitting element includes a plurality of light emitting elements. And are interposed between the light emitting layer of each light emitting element and the selection circuit. According to this aspect, since the second electrode is interposed between the light emitting layer and the selection circuit, an electrical influence (for example, noise) from one of the selection circuit and the light emitting layer to the other can be shielded by the second electrode. Is possible. Further, according to the configuration in which the second electrode is formed of a light-shielding (light-absorbing or light-reflecting) conductive material, the light emitted from the light-emitting layer is shielded by the second electrode and does not reach the selection circuit. There is an advantage that a malfunction of the selection circuit due to irradiation is prevented.

A configuration in which each unit circuit and the signal line overlap is also preferable. According to this configuration, it is possible to reduce the size of the optical head as compared with a configuration in which each unit circuit and the signal line are arranged so as not to overlap each other. In addition, if the second electrode is interposed between each unit circuit and the signal line, the electrical influence on one of the unit circuit and the signal line from the other can be shielded by the second electrode.
Note that the second electrode does not have to be interposed between the entire area where the unit circuit and the signal line overlap. However, in a configuration in which each unit circuit includes a holding circuit that holds a data signal acquired from the signal line, a configuration in which the second electrode is interposed between the holding circuit of each unit circuit and the signal line is preferable. . According to this configuration, the influence of the fluctuation of the voltage of the signal line on the data signal held by the holding circuit is suppressed by the second electrode. Therefore, the light emission of each light emitting element can be reliably controlled according to the data signal.

In a preferred aspect of the present invention, an auxiliary wiring formed of a material having a lower resistivity than the second electrode and conducting to the second electrode is further disposed, and each unit circuit is formed of a semiconductor layer (for example, the semiconductor layer of FIG. 7). 21) (for example, the transistor R in FIG. 7), and the auxiliary wiring overlaps with the semiconductor layer of the transistor of the unit circuit. According to this configuration, since the voltage drop in the second electrode is suppressed by the auxiliary wiring, each light emitting element can be controlled to the desired luminance with high accuracy. In addition, since the auxiliary wiring is formed so as to overlap with the semiconductor layer of the transistor of the unit circuit, an electrical influence on the semiconductor layer can be suppressed by the auxiliary wiring. In addition, according to the configuration in which the auxiliary wiring is formed of a light-shielding material, light traveling toward the semiconductor layer is shielded by the auxiliary wiring, so that the transistor malfunctions due to light irradiation (
Current leakage) can be prevented.

An optical head according to a preferred aspect of the present invention includes a first substrate and a second substrate facing each other. The selection circuit is disposed on a surface of the first substrate facing the second substrate, and the plurality of light emitting elements are disposed on a surface of the second substrate facing the first substrate. According to the above configuration, a configuration in which the selection circuit and each light emitting element overlap can be easily realized by joining the first substrate and the second substrate.

The position where each unit circuit is arranged is arbitrary. For example, a configuration in which all the unit circuits are arranged on the surface of the first substrate facing the second substrate and the surface of the second substrate facing the first substrate is employed. However, in a configuration in which all elements of each unit circuit are arranged on only one substrate, the circuit scale on that substrate is excessive compared to the other substrate, and miniaturization of the optical head is restricted. There is also. Therefore, in a preferred aspect of the present invention, each element constituting one unit circuit is distributed and arranged on the first substrate and the second substrate. For example, in a configuration in which each unit circuit includes a holding circuit that holds a data signal acquired from a signal line, and a light emission control circuit that controls light emission of the light emitting element according to the data signal held by the holding circuit, each unit circuit The circuit holding circuit is disposed on the surface of the first substrate facing the second substrate, and the light emission control circuit of each unit circuit is disposed on the surface of the second substrate facing the first substrate. According to this aspect, the first
An imbalance between the scale of the circuit on the substrate and the scale of the circuit on the second substrate can be suppressed. Further, since the holding circuit is arranged on the first substrate together with the selection circuit, there is an advantage that it is not necessary for the selection circuit to transmit a signal for selecting each unit circuit from the first substrate to the second substrate. In addition, the specific example of this aspect is later mentioned as 2nd Embodiment and 3rd Embodiment.

In a specific embodiment of the present invention, an element formed on the first substrate and an element formed on the second substrate are conductors arranged in the gap between the first substrate and the second substrate (for example, in FIG. 4). Conductive particles 31)
The connection terminals for electrically connecting the optical head and the outside are formed only on the surface of the first substrate. According to this aspect, since the connection terminal is formed only on the surface of the first substrate, there is an advantage that the configuration for connecting the optical head and the outside is simplified.

The optical head according to the present invention is used in various electronic devices. A typical example of the electronic apparatus according to the present invention is an image forming apparatus using the optical head according to each of the above aspects for exposure of an image carrier such as a photosensitive drum. This image forming apparatus includes an image carrier (for example, the photosensitive drum 70 in FIG. 11) on which a latent image is formed by exposure, the optical head of the present invention that exposes the image carrier, and development of the latent image on the image carrier. And a developing unit that forms a visible image by adhesion of an agent (for example, toner). However, the use of the optical head according to the present invention is not limited to the exposure of the image carrier. For example, in an image reading apparatus such as a scanner, the optical head according to the present invention can be used for illuminating a document. The image reading apparatus includes an optical head according to the present invention and a light receiving device (for example, a CCD (Charge Coupled D) that converts light emitted from the optical head and reflected by a reading target (original) into an electrical signal.
evice).

<A: First Embodiment>
FIG. 1 is a perspective view showing a partial configuration of an image forming apparatus using an optical head (exposure head) according to a first embodiment of the present invention for exposure of a photosensitive drum. As shown in the figure, the image forming apparatus includes an optical head H, a condensing lens array 60, and a photosensitive drum 70. The optical head H includes a large number of light emitting elements (not shown in FIG. 1) arranged in the X direction (main scanning direction). The photosensitive drum 70 is supported by a rotation shaft extending in the X direction, and rotates with the outer peripheral surface facing the optical head H.

The condensing lens array 60 is disposed in the gap between the optical head H and the photosensitive drum 70. The condensing lens array 60 includes a large number of gradient index lenses arranged in an array with each optical axis directed to the optical head H (Z direction). As the condensing lens array 60, for example, there is SLA (selfoc lens array) available from Nippon Sheet Glass Co., Ltd. (
SELFOC is a registered trademark of Nippon Sheet Glass Co., Ltd. Light emitted from each light emitting element in the optical head H passes through each refractive index distribution type lens of the condensing lens array 60 and then reaches the surface of the photosensitive drum 70. By this exposure, a latent image (electrostatic latent image) corresponding to a desired image is formed on the surface of the photosensitive drum 70.

FIG. 2 is a block diagram showing an electrical configuration of the optical head H. As shown in FIG. As shown in FIG. 2, the optical head H includes an element array portion A in which a plurality of light emitting elements E are arranged in the X direction, a power line 41 and a ground line 42, and a plurality of light emitting elements E (light emitting elements). E) (number of unit circuits U). Each light emitting element E is an organic light emitting diode (OLED) in which a light emitting layer made of an organic EL (ElectroLuminescence) material is interposed between an anode and a cathode.
It is an element and emits light with luminance (luminous intensity) corresponding to the current supplied to the light emitting layer.

A power supply potential VDD is supplied to the power supply line 41 from an external power supply circuit 46 through an external connection terminal Tp1. A ground potential VSS is supplied to the ground line 42 from the power supply circuit 46 via the external connection terminal Tp2. The cathode of each light emitting element E is connected to the ground line 42. The plurality of unit circuits U include m blocks B (B1, B2,..., N units (U1, U2,..., Un) adjacent to each other in the X direction.
.., Bm) (each of m and n is an integer of 2 or more). In the present embodiment, for convenience of explanation, a configuration in which the same number of unit circuits U are included in each block B is illustrated, but a configuration in which the number of unit circuits U is different for each block B may be employed.

Further, the optical head H includes an m-bit shift register 43 corresponding to the total number of blocks B and n data signal lines LD (LD1 to LDn) corresponding to the number of unit circuits U of each block B.
And a signal line group L including The shift register 43 is supplied with a start pulse SP and a clock signal CLK from an external control circuit 47 via an external connection terminal Ts. The shift register 43 is a means for selecting each unit circuit U for each block B, and generates m selection signals S1 to Sm by shifting the start pulse SP in synchronization with the clock signal CLK. Each of the selection signals S1 to Sm sequentially becomes an active level every one cycle of the clock signal CLK. The selection signal Si (i is an integer satisfying 1 ≦ i ≦ m) is commonly supplied to the n unit circuits U belonging to the block Bi. The transition of the selection signal Si to the active level means selection of each unit circuit U belonging to the block Bi.

The image processing circuit 48 of FIG. 2 generates n data signals D1 to Dn corresponding to the total number of unit circuits U belonging to one block B. The data signal Dj (j is an integer satisfying 1 ≦ j ≦ n) is supplied to the data signal line LDj via each external connection terminal Td. The jth stage unit circuits Uj (m in total) belonging to each of the blocks B1 to Bm are commonly connected to the data signal line LDj. The data signal Dj is a voltage signal that specifies the luminance of the light emitting element E corresponding to the j-th unit circuit Uj of each of the blocks B1 to Bm in time division in the order of the arrangement of the blocks B1 to Bm. More specifically, the data signal Dj has a high level and a low level according to the luminance (gradation) designated for the light emitting element E corresponding to the unit circuit Uj of the block Bi during the period in which the selection signal Si is at the active level. It becomes either.

Next, a specific configuration of one unit circuit U will be described with reference to FIG. In the figure, only one unit circuit Uj belonging to the block Bi is shown, but all the unit circuits U (U1 to Un) have the same configuration. As shown in FIG. 3, one unit circuit Uj
A holding circuit 441 and a light emission control circuit 442 are included.

The holding circuit 441 receives the data signal line LDj according to the selection of the block Bi by the selection signal Si.
Means for acquiring and holding the data signal Dj from (eg, a latch circuit). More specifically, the holding circuit 441 acquires (samples) the data signal Dj from the data signal line LDj at the timing when the selection signal Si changes to the active level, and the data until the selection signal Si changes to the active level next time. The output of the signal Dj is maintained.

The light emission control circuit 442 generates the light emitting element E according to the data signal Dj held by the holding circuit 441.
A p-channel transistor (hereinafter referred to as “driving transistor”).
Rdr) and an n-channel transistor R0. The drive transistor Rdr is a means for controlling the current supplied to the light emitting element E, and is interposed between the power supply line 41 and the anode of the light emitting element E. The transistor R0 is the drain of the driving transistor Rdr (the anode of the light emitting element E).
And the ground wire 42. The data signal Dj output from the holding circuit 441 is supplied to the gates of the drive transistor Rdr and the transistor R0. Holding circuit 441
Holds the low level data signal Dj, the drive transistor Rdr is turned on and the transistor R0 is turned off. Therefore, the light emitting element E emits light by supplying current from the power supply line 41 via the driving transistor Rdr. In contrast, the data signal D
When j is at a high level, the drive transistor Rdr is turned off and the light emitting element E is turned off. Since the leakage current when the driving transistor Rdr is in the OFF state flows into the ground line 42 via the transistor R0 in the ON state, the light emitting element E is surely turned off when the data signal Dj is at the high level. Can do.

Next, the mechanical structure of the optical head H will be described. 4 is a cross-sectional view taken along line IV-IV in FIG. As shown in FIGS. 1 and 4, the optical head H includes a first substrate 10 and a second substrate 20 that are bonded to each other. The second substrate 20 is the first substrate 1
It is located on the photosensitive drum 70 (condensing lens array 60) side when viewed from zero. The 1st board | substrate 10 and the 2nd board | substrate 20 are elongate board materials fixed to the attitude | position which makes X direction a longitudinal direction.

Part (a) of FIG. 5 is a surface of the first substrate 10 that faces the second substrate 20 (hereinafter referred to as “opposing surface”).
10B is a plan view showing the structure of the elements arranged on 10s, and part (b) of the figure is a surface (hereinafter referred to as "opposing surface") 20s of the second substrate 20 facing the first substrate 10. It is a top view which shows the structure of the element arrange | positioned on the top. The first substrate 10 and the second substrate 20 are bonded so that the front side of the paper surface in each of the part (a) and the part (b) in FIG. 5 faces each other.

As shown in part (a) of FIGS. 4 and 5, the shift register 43 and the signal line group L are disposed on the facing surface 10 s of the first substrate 10. As shown in part (a) of FIG. 5, the shift register 43 is a long circuit disposed along the positive side periphery in the Y direction with the X direction as the longitudinal direction.
The first substrate 10 is connected to an external connection terminal Ts formed on the peripheral edge on the negative side in the X direction. A plurality of connection terminals Ca (Ca1 and Ca2) arranged in the X direction are formed in a region along the negative edge of the opposing surface 10s in the Y direction. N data signal lines L constituting the signal line group L
D1 to LDn extend in the X direction in the gap between the shift register 43 and the arrangement of the connection terminals Ca on the facing surface 10s. Each data signal line LD is connected to an external connection terminal Td formed on the periphery of the first substrate 10 on the negative side in the X direction.

As shown in FIG. 4 and FIG. 5B, the plurality of light emitting elements E and the plurality of unit circuits U are second
It is disposed on the facing surface 20 s of the substrate 20. The plurality of light emitting elements E are arranged in the X direction so as to follow the positive edge of the second substrate 20 in the Y direction. Further, a plurality of connection terminals Cb (Cb1 and Cb2) arranged in the X direction are formed in a region along the peripheral edge on the negative side in the Y direction in the facing surface 20s. The plurality of unit circuits U are arranged in the X direction at a gap (a central region in the width direction of the second substrate 20) between the arrangement of the light emitting elements E and the arrangement of the connection terminals Cb.

As shown in FIG. 4, each connection terminal Ca of the first substrate 10 and each connection terminal Cb of the second substrate 20 face each other in a state where the first substrate 10 and the second substrate 20 are joined. First substrate 10 and second
An anisotropic conductor 30 is used for bonding to the substrate 20. The anisotropic conductor 30 is a film body in which a large number of conductive particles (hereinafter referred to as “conductive particles”) 31 are dispersed in an adhesive 32. When the anisotropic conductor 30 is inserted into the gap between the first substrate 10 and the second substrate 20 and the two substrates are thermocompression bonded, the first substrate 10 and the second substrate 20 are fixed to each other by the adhesive 32. In addition, the connection terminal Ca and the connection terminal Cb opposite to the connection terminal Ca are in contact with the conductive particles 31. In this way, the portion where the connection terminal Ca and the connection terminal Cb are electrically connected via the conductive particles 31 is the inter-substrate conductive portion C of FIG. The conductive particles 31 also function as a spacer that maintains a predetermined distance between the first substrate 10 and the second substrate 20.

As shown in FIG. 4, the shift register 43 of the first substrate 10 (more specifically, the transistor Q constituting the shift register 43) and the light emitting elements E of the second substrate 20 are the first substrate 10 and the second substrate. They overlap each other when viewed from the Z direction perpendicular to the surface of 20. According to this configuration, the substrate (the first substrate 10 and the second substrate 20) is smaller than the configuration in which the shift register 43 and the light emitting element E are arranged in separate regions partitioned on the surface of one substrate. It becomes. Furthermore, in the present embodiment, the signal line group L of the first substrate 10 and the unit circuits U of the second substrate 20 overlap each other when viewed from the Z direction. According to this configuration, the substrate is reduced in size as compared with the configuration in which the unit circuit U and the signal line group L are arranged in separate regions of one substrate. As described above, according to the present embodiment, the area required for the first substrate 10 and the second substrate 20 is reduced by the overlap between the elements on the first substrate 10 and the elements on the second substrate 20. . Therefore, there is an advantage that the optical head H and the image forming apparatus incorporating the same are reduced in size.

Next, FIG. 6 is a cross-sectional view (a cross-sectional view taken along line VI-VI in part (a) of FIG. 5) showing a configuration of elements formed on the first substrate 10. 6 and 4 are upside down (Z direction). As shown in FIG. 6, a large number of transistors Q (only one is shown in FIG. 6) forming the shift register 43 are formed on the surface of the first substrate 10.

The transistor Q includes a semiconductor layer 11 formed of a semiconductor material on the surface of the first substrate 10.
And a gate electrode 12 facing the semiconductor layer 11 (channel region) with a gate insulating layer Fa0 covering the semiconductor layer 11 interposed therebetween. The semiconductor layer 11 is a polysilicon film formed by laser annealing on amorphous silicon, for example. The gate electrode 12 is covered with the first insulating layer Fa1. The source electrode 131 and the drain electrode 132 of the transistor Q are formed on the surface of the first insulating layer Fa1 with a low resistance metal such as aluminum and are electrically connected to the semiconductor layer 11 (source region and drain region) through the contact hole. . The surface of the first substrate 10 on which the transistor Q is formed is covered with the second insulating layer Fa2. The first insulating layer Fa1 and the second insulating layer Fa2 are film bodies formed of an insulating material such as SiO ₂ or SiN.

As shown in FIG. 6, the data signal lines LD (LD1 to LDn) constituting the signal line group L are formed on the surface of the gate insulating layer Fa0. The gate electrode 12 of the transistor Q and the data signal line LD
Are collectively formed in the same process by patterning a conductive film (for example, an aluminum thin film) formed continuously over the entire area of the gate insulating layer Fa0. Gate electrode 1
2 and the data signal line LD, a plurality of elements are formed in the same process by selective removal of a common film body (whether it is a single layer or a plurality of layers). Hereinafter, this is simply expressed as “formed from the same layer”. Naturally, the material of each element formed from the same layer is the same, and the film thicknesses thereof are substantially the same. According to the configuration in which a plurality of elements are formed from the same layer, there is an advantage that the manufacturing process can be simplified and the manufacturing cost can be reduced as compared with the configuration in which each element is formed from a separate film body.

As shown in FIG. 6, each connection terminal Ca has a structure in which a first layer 133 and a second layer 14 are laminated in this order from the first substrate 10 side. The first layer 133 is on the surface of the first insulating layer Fa1,
It is formed from the same layer as the source electrode 131 and the drain electrode 132 of the transistor Q. An opening Oa1 is formed in a portion of the second insulating layer Fa2 that overlaps the first layer 133. Second layer 14
Is formed so as to enter the inside of the opening Oa1 and is electrically connected to the first layer 133.
The second layer 14 is formed of a conductive oxide (light-transmissive conductive material) such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). By covering the first layer 133 made of a material having low corrosion resistance such as aluminum with the second layer 14 having high corrosion resistance in this way, corrosion of the first layer 133 is effectively prevented.

The plurality of connection terminals Ca formed on the first substrate 10 include a connection terminal Ca1 used for transmission of data signals D1 to Dn and a connection terminal Ca2 used for transmission of selection signals S1 to Sm. FIG.
As shown in FIG. 6A and FIG. 6, the wiring Ld1 is continuous with the first layer 133 of the connection terminal Ca1.
The wiring Ld1 extends from the first layer 133 in the Y direction and electrically connects the data signal line LD and the connection terminal Ca1, and the source electrode 131 and the drain electrode 132 of the first layer 133 and the transistor Q. And the same layer. The end of the wiring Ld1 opposite to the connection terminal Ca1 is electrically connected to the lower data signal line LD through a contact hole h1 that penetrates the first insulating layer Fa1. Further, the wiring Ls1 shown in part (a) of FIG. 5 is the first layer 1 of the connection terminal Ca2.
33 is a wiring continuous to 33, extends in the Y direction, and is electrically connected to the shift register 43 (eg, transistor Q).

Next, FIG. 7 is a cross-sectional view (a cross-sectional view taken along the line VII-VII in the part (b) of FIG. 5) showing the configuration of elements formed on the second substrate 20. As shown in FIG. 7, the opposing surface 2 of the second substrate 20.
A large number of transistors R constituting the unit circuit U are formed on 0s. In FIG. 7, the driving transistor Rdr of the light emission control circuit 442 and the transistor R constituting the holding circuit 441 are illustrated. If it is not necessary to distinguish each of the transistors formed on the second substrate 20 (that is, the transistors constituting the driving transistor Rdr and the transistor R0 and the holding circuit 441 in FIG. 2), they are simply expressed as “transistor R”. To do.

The transistor R is a thin film transistor having the same material and structure as the transistor Q of the first substrate 10, and includes a semiconductor layer 21 formed on the facing surface 20s and a gate electrode 22 facing the semiconductor layer 21 with the gate insulating layer Fb0 interposed therebetween. Including. The source electrode 231 and the drain electrode 232 of the transistor R are formed on the surface of the first insulating layer Fb1 covering the gate electrode 22 and are electrically connected to the semiconductor layer 21 (source region and drain region) through the contact hole. As shown in part (b) of FIG. 5 and FIG. 7, a power supply line 41 extending in the X direction is formed in the gap between the arrangement of the unit circuits U and the arrangement of the light emitting elements E in the facing surface 20 s. The power supply line 41 and the gate electrode 22 of each transistor R are formed from the same layer. 1st board | substrate 1 among the power wires 41
An end portion that reaches the peripheral edge on the positive side in the X direction at 0 functions as the external connection terminal Tp1 in FIG.

As shown in FIG. 7, the surface of the first insulating layer Fb1 is covered with the second insulating layer Fb2. Second insulating layer F
The first electrodes 241 are formed on the surface of b2 so as to be separated from each other for each light emitting element E. 1st electrode 2
Reference numeral 41 denotes a substantially circular electrode that functions as an anode of the light-emitting element E, and is formed of a light-transmitting conductive material such as ITO or IZO. As shown in FIG. 7, the first electrode 241 is electrically connected to the drain electrode 232 of the driving transistor Rdr through a contact hole CH that penetrates the second insulating layer Fb2.

Similar to the connection terminals Ca of the first substrate 10, each connection terminal Cb has a structure in which a first layer 233 and a second layer 242 are laminated. The first layer 233 is formed from the same layer as the source electrode 231 and the drain electrode 232 of the transistor R, and the second layer 242 is formed from the same layer as the first electrode 241. The second layer 242 is connected to the first layer 233 through the opening Ob1 formed in the second insulating layer Fb2.
Is electrically connected.

As shown in part (b) of FIG. 5, the plurality of connection terminals Cb arranged on the second substrate 20 include a connection terminal Cb1 facing the connection terminal Ca1 of the first substrate 10 and a connection terminal of the first substrate 10. A distinction is made between connection terminals Cb2 facing Ca2. Each connection terminal Cb1 is electrically connected to the unit circuit U through the wiring Ld2 continuous from the first layer 233 in the Y direction. Accordingly, the unit circuits Uj belonging to each of the blocks B1 to Bm are electrically connected to the data signal line LDj through the wiring Ld2, the connection terminal Cb1, the conductive particle 31, the connection terminal Ca1, and the wiring Ld1.

Each connection terminal Cb2 is connected to n unit circuits U1 to Un of one block B via m wirings LsA and one wiring LsB. Each wiring LsA is connected to the source electrode 231 of the transistor R.
The wiring LsB is formed from the same layer as the drain electrode 232 and the wiring LsB is the gate electrode 22 of the transistor R.
And the same layer. The wiring LsA reaching the unit circuit Un is continuous with the first layer 233 of the connection terminal Cb2. Accordingly, the unit circuit Un is electrically connected to the connection terminal Cb2 via the wiring LsA. Each wiring LsA is electrically connected to the lower wiring LsB through the contact hole h2 of the first insulating layer Fb1. Accordingly, the unit circuits U1 to Un-1 of the block Bi are connected to the connection terminal Cb2 via the wiring LsA, the wiring LsB, and the nth wiring LsA. And connection terminal C
b2 is electrically connected to the shift register 43 through the conductive particles 31, the connection terminal Ca2, and the wiring Ls1.

The surface of the second insulating layer Fb2 on which the first electrode 241 and the second layer 242 are formed is covered with the third insulating layer Fb3. An opening portion Ob2 is formed in a portion of the third insulating layer Fb3 that overlaps the second layer 242 of the connection terminal Cb. Furthermore, a substantially circular opening Ob3 is formed in a portion of the third insulating layer Fb3 that overlaps the first electrode 241. The light emitting layer 25 of the light emitting element E is formed in a space inside the opening Ob3 and having the first electrode 241 as a bottom surface. That is, the third insulating layer Fb3 plays a role of defining the planar shape of the light emitting layer 25. As shown in FIG. 4, the light emitting layer 25 overlaps the semiconductor layer 11 of the transistor Q on the first substrate 10 when viewed from the Z direction. For the formation of the light emitting layer 25, for example, an ink jet method (droplet discharge method) in which droplets of a light emitting material are discharged from a nozzle and adhered to the surface of the first electrode 241 is suitably employed. Various functional layers (a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, a hole block layer, and an electron block layer) for promoting or improving light emission by the light emitting layer 25 are used as the light emitting layer. 25 may be laminated.

On the surface of the third insulating layer Fb3, a partition wall Fb4 is formed of various insulating materials such as an organic material such as acrylic and an inorganic material such as SiO ₂ and SiN. The partition wall Fb4 is the light emitting layer 25.
And functions as an element for partitioning the region where the droplets of the light emitting material reach when the light emitting layer 25 is formed by the ink jet method, for each light emitting element E. As shown in FIG. 7, an opening Ob5 is formed in a region of the partition wall Fb4 that overlaps with the connection terminal Cb. Of the second layer 242 of the connection terminal Cb, a portion exposed from the third insulating layer Fb3 and the partition wall Fb4 is in contact with the conductive particles 31 of the anisotropic conductor 30.

The second electrode 27 in FIG. 7 is an electrode (corresponding to the ground line 42 in FIG. 2) facing the first electrode 241 with the light emitting layer 25 interposed therebetween, and as shown in a part (b) of FIG. The light emitting elements E are continuously formed and electrically connected to the external connection terminal Tp2 on the periphery of the second substrate 20. In the state where the first substrate 10 and the second substrate 20 are joined, the external connection terminals Tp1 and Tp2 on the second substrate 20 do not actually overlap the first substrate 10. That is, the external connection terminals Tp1 and Tp2 are formed in a region of the second substrate 20 that protrudes from the periphery of the first substrate 10. Similarly, the external connection terminals Ts and Td on the first substrate 10 do not overlap with the second substrate 20.

As the material of the second electrode 27, various light-reflective conductive materials such as metals such as aluminum and silver and alloys containing these metals as main components are employed. From the light emitting layer 25 to the first electrode 241
The light radiated to the side and the light emitting layer 25 radiated to the opposite side of the first electrode 241 and the second electrode 27.
The light reflected by the surface of the light passes through the first electrode 241 and the second substrate 20 and is emitted to the photosensitive drum 70 side, as shown by white arrows in FIG. Therefore, the second substrate 20 is required to have light transmittance, but the first substrate 10 does not need light transmittance.

As shown in FIG. 4, since the light emitting element E and the shift register 43 overlap each other when viewed from the Z direction, the second electrode 27 is interposed between the transistor Q of the shift register 43 and the light emitting layer 25 of the light emitting element E. . Accordingly, for example, noise generated when the transistor Q is switched on and off is shielded by the second electrode 27 and does not affect the light emitting layer 25 and the first electrode 241. As described above, according to the present embodiment, the shift register 43 is reduced in order to reduce the size of the optical head H.
However, there is an advantage that the electrical influence between the shift register 43 and the light emitting element E can be reduced.

Further, if the emitted light from the light emitting layer 25 directly reaches the transistor Q of the shift register 43, a malfunction (for example, current leakage) may occur in the transistor Q due to photoexcitation of the semiconductor layer 11. is there. On the other hand, according to the present embodiment, since the second electrode 27 having light shielding properties (light reflectivity) is interposed between the light emitting layer 25 and the shift register 43, the light emitting layer 25 is directed to the first substrate 10 side. Is shielded by the second electrode 27 and the transistor Q
Will not reach. Therefore, it is possible to prevent malfunction of the transistor Q due to light irradiation.

As shown in part (b) of FIG. 5 and FIG. 7, the second electrode 27 is formed on the surface of the partition wall Fb4 in addition to the light emitting layer 25. As shown in FIG. 7, since the partition wall Fb4 is formed so as to cover each unit circuit U, the second electrode 27 is formed so that each transistor R or the holding circuit 4 of the unit circuit U is viewed from the Z direction.
41 and overlap. Further, as shown in FIG. 4, the unit circuit U and the signal line group L overlap each other when viewed from the Z direction. Therefore, each transistor R of the unit circuit U and each data signal line LD1-L
A second electrode 27 is interposed between Dn. According to this configuration, noise caused by fluctuations in the voltage of each data signal line LD is shielded by the second electrode 27 and does not reach the unit circuit U.
Similarly, noise associated with the on / off switching of the transistor R is shielded by the second electrode 27 and does not affect the data signal line LD. As described above, according to the present embodiment, there is an advantage that the electrical influence between the signal line group L and each unit circuit U can be reduced. Particularly in the present embodiment, since the second electrode 27 is interposed between the signal line group L and the holding circuit 441,
The possibility that the data signal Dj held in the holding circuit 441 varies according to the voltage (data signal) of the data signal line LD is reduced. Therefore, each light emitting element E can be reliably controlled according to the data signal Dj.

By the way, in the inter-substrate conducting part C in which the elements of the first substrate 10 and the elements of the second substrate 20 are electrically connected via the conducting particles 31, the state of the distribution of the conducting particles 31 and the conducting particles 31 and the substrate. Due to various factors such as the state of contact with the upper element, variations in resistance value are likely to occur at each electrical connection position. Therefore, a configuration in which the inter-substrate conductive portion C is interposed on the path from the power supply line 41 to the ground line 42 (for example, a configuration in which the drive transistor Rdr is disposed on the first substrate 10).
In, the current value of the current supplied to each light emitting element E may be different due to the variation in the resistance value in the inter-substrate conducting portion C. On the other hand, in the present embodiment, all elements on the path from the power supply line 41 to the ground line 42 via the drive transistor Rdr and the light emitting element E are formed on the second substrate 20. That is, the inter-substrate conducting portion C is not interposed on the path from the power supply line 41 to the ground line 42. According to this configuration, since the influence of the variation in the resistance value in the inter-substrate conducting portion C on the current of each light emitting element E is eliminated, the luminance of the light emitting element E can be controlled with high accuracy according to the data signal. There is.

The auxiliary wiring 28 illustrated in FIG. 7 is a wiring that is formed of a conductive material having a lower resistivity than the second electrode 27 and is electrically connected to the second electrode 27. According to this configuration, since the voltage drop at the second electrode 27 is suppressed, the ground potential VSS supplied to each light emitting element E is made uniform.
Therefore, unevenness in luminance of each light emitting element E due to the voltage drop in the second electrode 27 can be suppressed. In the state where the first substrate 10 and the second substrate 20 are bonded, the auxiliary wiring 28 is the first wiring.
The surface of the second insulating layer Fa2 on the substrate 10 is contacted. In the present embodiment, the configuration in which the auxiliary wiring 28 is formed on the surface of the second electrode 27 is illustrated, but the position where the auxiliary wiring 28 is formed is appropriately changed. For example, the auxiliary wiring 28 may be interposed between the second electrode 27 and the partition wall Fb4.

The auxiliary wiring 28 is formed of a light shielding (for example, light reflective) conductive material on the surface of the portion of the second electrode 27 located on the surface of the partition wall Fb4. Therefore, the auxiliary wiring 28 overlaps with each transistor R of the unit circuit U when viewed from the Z direction, and is interposed between the unit circuit U and the signal line group L like the second electrode 27. According to this configuration, the above-described effect that the mutual influence between the signal line group L and each unit circuit U can be reduced is further enhanced as compared with the configuration in which the auxiliary wiring 28 is not formed. Further, since the auxiliary wiring 28 has a light shielding property, there is an advantage that light emitted from the light emitting element E can be shielded by the auxiliary wiring 28.

<B: Second Embodiment>
Next, a second embodiment of the present invention will be described. In the present embodiment, elements having the same functions and functions as those of the first embodiment are denoted by the same reference numerals as those described above, and detailed description thereof is omitted as appropriate.

Part (a) of FIG. 8 is a plan view showing elements on the facing surface 10 s of the first substrate 10, and part (b) of FIG. 8 is a plan view showing elements on the facing surface 20 s of the second substrate 20. It is. As shown in part (a) of the figure, the holding circuit 441 of each unit circuit U is disposed on the facing surface 10s. The part of the figure (
As shown in b), the light emission control circuit 442 of each unit circuit U is disposed on the facing surface 20s. The configuration in which each light emitting element E and the shift register 43 overlap and the configuration in which the signal line group L and each unit circuit U overlap are the same as those in the first embodiment. Therefore, the first embodiment is also the first.
The same effect as the embodiment is achieved.

The holding circuit 441 of the unit circuit Uj in each of the blocks B1 to Bm is connected to the data signal line LDj via the wiring Ld1 formed from the same layer as the source electrode 131 and the drain electrode 132 of the transistor Q. Further, the holding circuits 441 of the unit circuits U1 to Un belonging to the block Bi.
Are connected to the shift register 43 by wiring in the same manner as in the first embodiment (wiring LsA formed from the same layer as the source electrode 131 and wiring LsB formed from the same layer as the gate electrode 12). As described above, since the holding circuit 441 that acquires and holds the data signal Dj according to the selection signal Si is arranged on the first substrate 10, the connection terminal Ca2 for transmitting the selection signal Si to the second substrate 20 and The connection terminal Cb2 is not necessary in this embodiment. That is, according to this embodiment, since the number of connection terminals Ca and connection terminals Cb is reduced, the possibility of occurrence of defects in the connection between the elements on the first substrate 10 and the elements on the second substrate 20 is reduced. There is an advantage that you can.

<C: Third Embodiment>
Next, a third embodiment of the present invention will be described. In the present embodiment, elements having the same functions and functions as those in the first embodiment and the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

Part (a) of FIG. 9 is a plan view showing elements on the facing surface 10 s of the first substrate 10, and part (b) of FIG. 9 is a plan view showing elements on the facing surface 20 s of the second substrate 20. It is. In the present embodiment, as in the second embodiment, among the unit circuits U, the holding circuit 441 is disposed on the facing surface 10s, and the light emission control circuit 442 is disposed on the facing surface 20s. The configuration in which each light emitting element E and the shift register 43 overlap or the configuration in which the signal line group L and each unit circuit U overlap are the first.
This is the same as the embodiment.

The power supply line 41 to which the source electrode 231 of each driving transistor Rdr is connected is formed from the same layer as the gate electrode 22 of the transistor R, and as shown in part (b) of FIG. 9, the arrangement of the connection terminals Cb1 and light emission control. It extends in the X direction with a gap from the arrangement of the circuits 442. Second of power line 41
The end of the substrate 20 that reaches the peripheral edge on the negative side in the Y direction becomes the connection terminal Cb3. A connection terminal Cb4 electrically connected to the second electrode 27 is formed on the facing surface 20s from the same layer as the power line 41.

As shown in part (a) of FIG. 9, the outer peripheral surface facing the connection terminal Cb4 and the external connection terminal Tp1 facing the connection terminal Cb3 are disposed on the peripheral edge on the negative side in the X direction of the facing surface 10s of the first substrate 10. Connection terminal T
p2 is formed. The connection terminal Cb3 and the external connection terminal Tp1 are electrically connected to each other via the conductive particles 31. Similarly, the connection terminal Cb4 and the external connection terminal Tp2 are electrically connected by the conductive particles 31. As described above, in this embodiment, all external connection terminals (Ts, Td, Tp1, T
Since p2) is formed on the first substrate 10, there is an advantage that the configuration for connecting the optical head H and the outside is simplified. For example, in the first embodiment, a wiring board (typically a flexible wiring board) that is electrically connected to the external connection terminal Ts and the external connection terminal Td is used as the first board 10.
It is necessary to mount on the second substrate 20 a wiring board that is mounted on the external connection terminals Tp1 and Tp2. On the other hand, in the present embodiment, it is sufficient to mount the wiring board only on the first substrate 10, so that the number of components of the optical head H is reduced and the manufacturing cost is thereby reduced.

<D: Modification>
Various modifications can be made to each of the above embodiments. An example of a specific modification is as follows. In addition, you may combine each following aspect suitably.

(1) Modification 1
In each of the above embodiments, the first substrate 10 on which the shift register 43 and the signal line group L are arranged.
A configuration in which the second substrate 20 on which the light emitting element E and the unit circuit U (the light emission control circuit 442 in the second embodiment) are disposed is bonded to each other is illustrated. Is not necessarily required. For example, the second substrate 20 in which each element is arranged as shown in FIG. 7 is covered with an insulating layer, and each element shown in FIG. 6 such as the shift register 43 and the signal line group L is formed on the surface of this insulating layer. Good. The method for forming each element in FIG. 6 on the surface of the insulating layer is the same as the method for forming each element on the surface of the first substrate 10 in the first embodiment. In the above configuration, the connection terminal Ca, the connection terminal Cb, and the anisotropic conductor 30 are unnecessary.

(2) Modification 2
In the first embodiment, a configuration in which all of the unit circuits U are arranged on the second substrate 20 is illustrated,
In the second embodiment and the third embodiment, the configuration in which the holding circuit 441 and the light emission control circuit 442 are dispersedly arranged on the first substrate 10 and the second substrate 20 is illustrated, but the entire unit circuit U ( A configuration in which both the holding circuit 441 and the light emission control circuit 442) are disposed on the first substrate 10 is also employed. In this configuration, the semiconductor layer 11 of the transistor Q and the semiconductor layer 21 of the transistor R can be formed from the same layer on the surface of the first substrate 10, and the semiconductor layer 21 needs to be formed on the second substrate 20. Therefore, there is an advantage that the manufacturing process of the optical head H is simplified as compared with the first to third embodiments.

(3) Modification 3
In each of the above embodiments, the configuration (bottom emission structure) in which the radiated light from each light emitting element E is transmitted through the second substrate 20 on which the light emitting element E is disposed is exemplified. The present invention is also applied to a top emission structure that emits light to the opposite side of the two substrates 20. In the optical head H having the top emission structure, the second electrode 27 is formed of a light transmissive conductive material. However, in order to emit a sufficient amount of emitted light to the photosensitive drum 70 in this configuration, it is desirable that the elements (for example, the transistor Q) constituting the shift register 43 are sufficiently smaller than the light emitting layer 25. .

(4) Modification 4
The configuration of the unit circuit U is changed as appropriate. For example, in each of the above embodiments, the configuration in which the latch circuit is used as the holding circuit 441 is illustrated, but a configuration in which the capacitor connected to the gate of the driving transistor Rdr is the holding circuit 441 is also employed. In this configuration, a switching element for controlling the electrical connection (conduction / non-conduction) between the gate of the drive transistor Rdr and the data signal line LD according to the selection signal Si is arranged. Even after the data signal Dj is supplied from the data signal line LD to the gate electrode 22 of the drive transistor Rdr via the switching element that is turned on, and the switching element is turned off, the voltage of the gate electrode 22 remains the capacitive element ( The holding circuit 441) maintains the voltage according to the data signal Dj.

(5) Modification 5
In each of the above embodiments, the configuration in which the shift register 43 sequentially selects each unit circuit U is exemplified, but the configuration of the circuit for selecting the unit circuit U (selection circuit in the present invention) is arbitrary.
For example, a configuration in which the sampling circuit (demultiplexer) 45 of FIG. 10 is arranged on the first substrate 10 instead of the shift register 43 of FIG. The sampling circuit 45 includes a plurality (“m × n”) of transistors SW each corresponding to a separate unit circuit U.

As shown in FIG. 10, m data signal lines LD (L
A signal line group L including D1 to LDm) and a signal line group La including n selection signal lines LS (LS1 to LSn) are formed. The n unit circuits U1 to Un belonging to the block Bi are commonly connected to the data signal line LDi via the corresponding transistors SW. Also, block B1 ~
The gates of the transistors SW (a total of m) corresponding to the unit circuits Uj in each of Bm are commonly connected to the selection signal line LSj.

A selection signal SELj is supplied from the control circuit 47 to the selection signal line LSj. Selection signal SEL1 to SEL
n is a signal that sequentially becomes an active level in a predetermined cycle. A data signal Di is supplied from the image processing circuit 48 to the data signal line LDi. When the selection signal SELj transitions to the active level, a total of m transistors SW corresponding to the unit circuits Uj are turned on at the same time. At this time, the data signals D1 to Dm supplied to the data signal lines LD1 to LDm are changed. Dm is input in parallel to the unit circuit Uj of each block B. That is, the sampling circuit 45
It functions as means for selecting a unit circuit Uj to be taken in from the data signal D among n unit circuits U1 to Un belonging to each block B. When n selections by the selection signals SEL1 to SELn are completed, the holding circuits 441 of all the unit circuits U are in the same manner as the above embodiments.
A data signal Dj corresponding to the unit circuit U is held.

Each transistor SW (more specifically, a semiconductor layer) in the configuration of FIG.
And overlaps with the light emitting element E when viewed from the direction perpendicular to the second substrate 20. Each data signal line L
D and each selection signal line LS overlap each transistor R constituting the unit circuit U on the second substrate 20. Therefore, the same operation and effect as in the first embodiment can be achieved by this modification. The configuration in which each unit circuit U is selected by the sampling circuit 45, the signal line group L, and the signal line group La in FIG. 10 is similarly adopted in the second embodiment and the third embodiment.

(6) Modification 6
In each of the above embodiments, the configuration in which the power supply line 41 is formed so as not to overlap with each unit circuit U is illustrated. However, the power supply so as to overlap with the transistor R (more specifically, the semiconductor layer 21) of each unit circuit U. A configuration in which the line 41 is formed is also adopted. The power supply line 41 in this configuration is formed from the same layer as the source electrode 231 (drain electrode 232) and the first electrode 241 of the transistor R, for example. According to this configuration, there is an advantage that malfunction of the transistor R due to an electrical influence (for example, voltage fluctuation in the element on the first substrate 10) due to the element on the first substrate 10 is suppressed.

(7) Modification 7
In each of the above embodiments, the configuration in which the OLED element is employed as the light emitting element E is illustrated, but the present invention is also applied to various optical heads using other light emitting elements. For example, a light emitting element or a light emitting diode element including a light emitting layer made of an inorganic EL material, field emission (FE: Field)
Emission device, surface-conduction electron emission (SE)
) Devices, ballistic electron surface emitting (BS) devices, and other various light emitting devices can be applied to the present invention.

<E: Application example>
Next, an image forming apparatus is illustrated as one form of equipment using the optical head according to the present invention.
FIG. 11 is a cross-sectional view showing a configuration of an image forming apparatus employing the optical head H according to each of the above embodiments. The image forming apparatus is a tandem type full-color image forming apparatus, and includes four optical heads H (HK, HC, HM, and HY) according to the above-described form and four photosensitive drums corresponding to each optical head H. 70 (70K, 70C, 70M, 70Y). One optical head H is disposed so as to face the image forming surface (outer peripheral surface) of the corresponding photosensitive drum 70. Note that the subscripts “K”, “C”, “M”, and “Y” of each symbol are used for forming each visible image of black (K), cyan (C), magenta (M), and yellow (Y). Means.

As shown in FIG. 11, an endless intermediate transfer belt 72 is wound around a driving roller 711 and a driven roller 712. The four photosensitive drums 70 are arranged around the intermediate transfer belt 72 at a predetermined interval from each other. Each photosensitive drum 70 rotates in synchronization with driving of the intermediate transfer belt 72.

In addition to the optical head H, a corona charger 731 (731K,
731C, 731M, 731Y) and developing unit 732 (732K, 732C, 732M, 732Y)
And are arranged. The corona charger 731 uniformly charges the image forming surface of the photosensitive drum 70 corresponding thereto. Each of the optical heads H exposes this charged image forming surface to form an electrostatic latent image. Each developing device 732 forms a visible image (visible image) on the photosensitive drum 70 by attaching a developer (toner) to the electrostatic latent image.

Each color (black, cyan, magenta, yellow) formed on the photosensitive drum 70 as described above.
Are sequentially transferred (primary transfer) to the surface of the intermediate transfer belt 72 to form a full-color visible image. Inside the intermediate transfer belt 72 are four primary transfer corotrons (transfer devices).
74 (74K, 74C, 74M, 74Y) are arranged. Each primary transfer corotron 74 electrostatically attracts a visible image from the corresponding photosensitive drum 70, thereby the photosensitive drum 7.
The visible image is transferred to the intermediate transfer belt 72 that passes through the gap between 0 and the primary transfer corotron 74.

The sheets (recording material) 75 are fed one by one from the paper feed cassette 762 by the pickup roller 761 and conveyed to the nip between the intermediate transfer belt 72 and the secondary transfer roller 77. The full-color visible image formed on the surface of the intermediate transfer belt 72 is transferred (secondary transfer) to one side of the sheet 75 by the secondary transfer roller 77 and is fixed to the sheet 75 by passing through the fixing roller pair 78. . The paper discharge roller pair 79 discharges the sheet 75 on which the visible image is fixed through the above steps.

Since the image forming apparatus exemplified above uses an OLED element as a light source (exposure means), the apparatus is made smaller than a configuration using a laser scanning optical system. Note that the present invention can also be applied to image forming apparatuses having configurations other than those exemplified above. For example, a rotary development type image forming apparatus, an image forming apparatus that directly transfers a visible image from a photosensitive drum to a sheet without using an intermediate transfer belt, or an image forming that forms a monochrome image The optical head according to the present invention can also be used in the apparatus.

The use of the optical head according to the present invention is not limited to the exposure of the image carrier. For example, the optical head of the present invention is employed in an image reading apparatus as a line-type optical head (illumination device) that irradiates a reading target such as a document with light. As this type of image reading apparatus, there is a scanner, a copying machine or a reading part of a facsimile, a barcode reader, or a two-dimensional image code reader for reading a two-dimensional image code such as a QR code (registered trademark).

1 is a perspective view showing a partial configuration of an image forming apparatus according to a first embodiment. It is a block diagram which shows the electrical structure of an optical head. It is a block diagram which shows the structure of a unit circuit. It is sectional drawing which shows the structure of an optical head. It is a top view which shows the structure of the element arrange | positioned at a 1st board | substrate and a 2nd board | substrate. It is sectional drawing which shows the structure of a 1st board | substrate and the element on the surface. It is sectional drawing which shows the structure of a 2nd board | substrate and the element on the surface. It is a top view which shows the structure of the element arrange | positioned in 1st board | substrate and 2nd board | substrate in 2nd Embodiment. It is a top view which shows the structure of the element arrange | positioned in 1st board | substrate and 2nd board | substrate in 3rd Embodiment. It is a block diagram which shows the electrical structure of the optical head which concerns on a modification. 1 is a conceptual diagram illustrating a specific form of an image forming apparatus according to the present invention.

Explanation of symbols

H: Optical head, 10: First substrate, 20: Second substrate, 10s, 20s: Opposing surface, 30
…… Anisotropic conductor, 31 …… Conductive particles, 32 …… Adhesive, 41 …… Power line, 42 …… Ground line, 43 …… Shift register, 441 …… Holding circuit, 442 …… Light emission control circuit , 45 ……
Sampling circuit 46... Power supply circuit 47... Control circuit 48.
... Element array part, E ... Light emitting element, L ... Signal line group, LD (LD1 to LDn) ... Data signal line, U (U1 to Un) ... Unit circuit, B (B1 to Bm) ... Block , Ts, Td, Tp1, T
p2: External connection terminal, Q, R: Transistor, Ca (Ca1, Ca2), Cb (Cb1, Cb2)
... Connection terminals, 60 ... Condensing lens array, 70 ... Photosensitive drum.

Claims (12)

A plurality of light emitting elements;
A plurality of unit circuits corresponding to each of the light emitting elements;
A signal line to which a data signal specifying the gradation of each light emitting element is supplied;
A selection circuit for sequentially selecting the unit circuits,
Each unit circuit controls light emission of the light emitting element corresponding to the unit circuit based on a data signal acquired from the signal line according to the selection by the selection circuit,
Each of the light emitting elements and the selection circuit overlap each other. The selection circuit includes a transistor having a semiconductor layer,
The optical head according to claim 1, wherein each of the light emitting elements overlaps a semiconductor layer of a transistor of the selection circuit. Each of the light emitting elements includes a first electrode and a second electrode facing each other, and a light emitting layer interposed between both electrodes, and the second electrode of each of the light emitting elements is formed continuously over the plurality of light emitting elements. The optical head according to claim 1, wherein the optical head is interposed between a light emitting layer of each of the light emitting elements and the selection circuit. The optical head according to claim 3, wherein the second electrode has a light shielding property. Each unit circuit and the signal line overlap,
The optical head according to claim 3, wherein the second electrode is interposed between the unit circuits and the signal line. Each unit circuit includes a holding circuit that holds a data signal acquired from the signal line,
The optical head according to claim 5, wherein the second electrode is interposed between a holding circuit of each unit circuit and the signal line. An auxiliary wiring formed of a material having a lower resistivity than the second electrode and conducting to the second electrode;
Each unit circuit includes a transistor having a semiconductor layer,
The optical head according to claim 3, wherein the auxiliary wiring overlaps a semiconductor layer of a transistor of the unit circuit. A first substrate and a second substrate facing each other;
The selection circuit is disposed on a surface of the first substrate facing the second substrate,
The optical head according to claim 1, wherein the plurality of light emitting elements are disposed on a surface of the second substrate that faces the first substrate. The optical head according to claim 8, wherein the plurality of unit circuits are arranged on a surface of the second substrate that faces the first substrate. Each unit circuit includes a holding circuit that holds a data signal acquired from the signal line, and a light emission control circuit that controls light emission of the light emitting element according to the data signal held by the holding circuit,
The holding circuit of each unit circuit is disposed on a surface of the first substrate that faces the second substrate, and the light emission control circuit of each unit circuit faces the first substrate of the second substrate. The optical head according to claim 8, wherein the optical head is disposed on a surface to be operated. The element formed on the first substrate and the element formed on the second substrate are electrically connected via a conductor disposed in a gap between the first substrate and the second substrate,
11. The optical head according to claim 8, wherein a connection terminal for electrically connecting the optical head and the outside is formed only on the surface of the first substrate. An image carrier on which a latent image is formed by exposure; and
The optical head according to any one of claims 1 to 11, which exposes the image carrier;
An image forming apparatus comprising: a developing unit that forms a visible image by attaching a developer to the latent image of the image carrier.

Images