JP2007202317A - Charge pump circuit and electrical equipment with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a charge pump circuit, which can reduce the rush current generated at power ON while suppressing the deterioration of efficiency, and electrical equipment with the same. <P>SOLUTION: The charge pump circuit has current mirror circuits Q5 and Q1 which mirror and output constant currents and a controller CNT which controls the propriety of drive of the current mirror circuits, according to Vo. The current circuit uses a transistor Q1, which is connected between one end of a capacitor C1 and an input voltage applying terminal and is switched on when charging the capacitor C1, as a transistor for mirror output. The controller CNT permits the drive of the current mirror circuit until Vo reaches Vth1, and switches on/off it periodically, according to CLK. On the other hand, after Vo reaches Vth1, it inhibits the drive of the current mirror circuit, and directly switches on/off the transistor Q1, according to CLK. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a charge pump circuit that generates a desired output voltage from an input voltage by periodically turning on / off a plurality of charge transfer transistors according to a clock signal and charging and discharging a charge storage capacitor, And it is related with an electric equipment provided with this.

  FIG. 5 is a circuit diagram showing a conventional example of a charge pump circuit. Note that the charge pump circuit of this figure periodically turns on / off the plurality of charge transfer transistors Q1 to Q4 according to the clock signal CLK (and the inverted clock signal CLKB) to charge / discharge the charge storage capacitor C1. By doing so, a desired output voltage Vo (≧ −Vi) is generated from the input voltage Vi. The output voltage Vo can be arbitrarily set within a range of −Vi ≦ Vo ≦ 0 by a feedback circuit (not shown).

  The negative voltage output operation will be specifically described. In generating the output voltage Vo, first, the transistors Q1 and Q3 are turned on, and the transistors Q2 and Q4 are turned off. By such switching control, the input voltage Vi is applied to one end (point A) of the capacitor C1 via the transistor Q1, and the other end (point B) is grounded via the transistor Q3. Therefore, the capacitor C1 is charged until the potential difference between both ends becomes the input voltage Vi.

  After the charging of the capacitor C1, the transistors Q1 and Q3 are turned off and the transistors Q2 and Q4 are turned on. By such switching control, the point A is grounded via the transistor Q2, and therefore the potential at the point A is lowered from the input voltage Vi to the ground voltage GND. Here, since a potential difference substantially equal to the input voltage Vi is given between the both ends of the capacitor C1 by the previous charging, when the above-described fluctuation occurs in the A point potential, the B point potential is changed from the ground voltage GND to the negative voltage. Pulled down to -Vi. At this time, since the point B is in conduction with the output voltage extraction terminal via the transistor Q4, the charge of the capacitor C1 moves to the output capacitor Co, and the potential of the output voltage extraction terminal is lowered to the negative voltage −Vi. It is done.

  In the above-described conventional charge pump circuit, generation of an inrush current that flows into the capacitor C1 when the power is turned on has been a problem (see FIG. 6). That is, in the conventional charge pump circuit, transistors Q1 to Q4 having a large current capacity must be used so that element destruction and abnormal heat generation due to inrush current do not occur, which is one factor hindering chip area reduction. It was. In addition, as the manufacturing process of the charge pump circuit, only those whose latch-up characteristics due to a large current have been verified can be used, resulting in the result that the manufacturing process options are unnecessarily limited. Furthermore, in a system having a high impedance in the power supply system, such as a negative power supply device of a hard disk drive device, the supply voltage to the device becomes insufficient when the above inrush current occurs, so that the operation becomes unstable. It was.

  Conventionally, as means for solving the above-described problem, a charge pump circuit that limits a rush current to a capacitor using a constant current circuit has been disclosed and proposed (see Patent Document 1).

JP 2005-57969 A

  Certainly, with the prior art of Patent Document 1, it is possible to reduce the inrush current that occurs when the power is turned on.

  However, in the prior art of Patent Document 1, since a separate constant current circuit is interposed in addition to the charge transfer transistors Q1 to Q4 on the current path of the charge pump circuit, the on-resistance of the entire system is increased. The deterioration of efficiency was invited.

  In view of the above problems, an object of the present invention is to provide a charge pump circuit capable of reducing inrush current generated at the time of power-on while suppressing deterioration of efficiency, and an electric device including the same. To do.

  In order to achieve the above object, a charge pump circuit according to the present invention periodically turns on / off a plurality of charge transfer transistors in accordance with a clock signal, and charges and discharges a charge storage capacitor. A charge pump circuit that generates a desired output voltage from a voltage, a current mirror circuit that mirrors a constant current flowing through one of a pair of transistors and outputs the current from the other, and the current according to a voltage value of the output voltage A control unit that controls whether or not the mirror circuit can be driven, and the current mirror circuit includes, among the plurality of charge transfer transistors, an end of the charge storage capacitor and an input voltage application end. The first transistor that is connected to the charge storage capacitor and is turned on when the charge storage capacitor is charged is connected to the transistor on the mirror current output side. The control unit permits driving of the current mirror circuit until the output voltage reaches a predetermined threshold voltage, and periodically turns it on / off according to the clock signal. After the output voltage reaches a predetermined threshold voltage, the driving of the current mirror circuit is prohibited and the first transistor is directly turned on / off according to the clock signal (first Composition).

  In the charge pump circuit having the first configuration, the first transistor is subdivided into a plurality of transistors connected in parallel to each other, and the control unit controls whether the current mirror circuit is driven, After the output voltage reaches a predetermined threshold voltage, the drive enable / disable control is performed so that the number of subdivided transistors increases as the output voltage approaches its target voltage value. (Second configuration) is preferable.

  Moreover, the electric device according to the present invention has a configuration (third configuration) including the charge pump circuit having the first or second configuration.

  With the charge pump circuit according to the present invention, it is possible to reduce the inrush current generated when the power is turned on while suppressing the deterioration of the efficiency, so that it is not necessary to increase the current capacity of the charge transfer transistor unnecessarily. The chip area can be reduced. In addition, the charge pump circuit according to the present invention can provide a margin for the latch-up characteristics caused by a large current, and therefore, a wide range of manufacturing processes can be selected. In addition, if the charge pump circuit according to the present invention is mounted on an electric device, it is possible to improve the operational stability when the power is turned on.

  FIG. 1 is a circuit diagram (partly including a block diagram) showing a first embodiment of a charge pump circuit according to the present invention.

  As shown in the figure, the charge pump circuit of this embodiment includes P-channel field effect transistors Q1a to Q1c and N-channel field effect transistors Q2 to Q4 as charge transfer transistors. These charge transfer transistors Q1a to Q1c and Q2 to Q4 are periodically turned on / off according to the clock signal CLK (and the inverted clock signal CLKB) to charge / discharge the charge storage capacitor C1, thereby providing an input voltage. This is a negative voltage output charge pump circuit that generates a desired output voltage Vo (≧ −Vi) from Vi. The output voltage Vo can be arbitrarily set within a range of −Vi ≦ Vo ≦ 0 by a feedback circuit (not shown).

  Further, the clock signal CLK and the inverted clock signal CLKB are not completely inverted in each other's logic, and are generally short-circuited at the input voltage application terminal or the output voltage extraction terminal (that is, the transistors Q1a to Q1c and the transistor Q2). Are not coincident with each other in order to prevent simultaneous turn-on of transistors Q3 and Q4).

  The sources of the transistors Q1a to Q1c are all connected to the application terminal for the input voltage Vi. The drains of the transistors Q1a to Q1c are all connected to one end (point A) of the capacitor C1. The gates of the transistors Q1a to Q1c are all connected to the application terminal of the clock signal CLK via the driver DRV1. That is, all of the transistors Q1a to Q1c correspond to switch means for turning on / off the connection line between the application end of the input voltage Vi and one end (point A) of the capacitor C1 according to the clock signal CLK. From another viewpoint, the switch means that is turned on when charging the capacitor C1 is subdivided into transistors Q1a to Q1c connected in parallel to each other, or transistors Q1a to Q1c connected in parallel to each other. Thus, it can be considered that one gate division transistor is formed. Hereinafter, these transistors Q1a to Q1c will be collectively referred to as transistor Q1 as appropriate.

  As described above, the charge pump circuit according to this embodiment is configured to be subdivided into transistors Q1a to Q1c in which the transistor Q1 is connected in parallel to each other. With such a configuration, it is possible to appropriately switch and control the on-resistance of the transistor Q1 when charging the capacitor C1, depending on which of the transistors Q1a to Q1c is driven when charging the capacitor C1. Become. The on-resistance switching control of the transistor Q1 will be described in detail later.

  The source of the transistor Q2 is connected to one end (point A) of the capacitor C1. The drain of the transistor Q2 is connected to the ground terminal. The gate of the transistor Q2 is connected to the application terminal of the clock signal CLK through the driver DRV2. That is, the transistor Q2 corresponds to switch means for turning on / off the connection line between the ground terminal and one end (point A) of the capacitor C1 in accordance with the clock signal CLK.

  The source of the transistor Q3 is connected to the ground terminal. The drain of the transistor Q3 is connected to the other end (point B) of the capacitor C1. The gate of the transistor Q3 is connected to the application terminal of the inverted clock signal CLKB through the driver DRV3. That is, the transistor Q3 corresponds to switch means for turning on / off the connection line between the ground terminal and the other end (point B) of the capacitor C1 according to the inverted clock signal CLKB.

  The drain of the transistor Q4 is connected to the other end (point B) of the capacitor C1. The source of the transistor Q4 is connected to the ground terminal via the output capacitor Co, and is also connected to the output voltage extraction terminal. The gate of the transistor Q4 is connected to the application terminal of the clock signal CLK through the driver DRV4. That is, the transistor Q4 corresponds to switch means for turning on / off the connection line between the output voltage extraction terminal and the other end (point B) of the capacitor C1.

  The negative voltage output operation of the charge pump circuit configured as described above will be specifically described. In generating the output voltage Vo, first, the transistors Q1 and Q3 are turned on, and the transistors Q2 and Q4 are turned off. By such switching control, the input voltage Vi is applied to one end (point A) of the capacitor C1 via the transistor Q1, and the other end (point B) is grounded via the transistor Q3. Therefore, the capacitor C1 is charged until the potential difference between both ends becomes the input voltage Vi.

  After the charging of the capacitor C1, the transistors Q1 and Q3 are turned off and the transistors Q2 and Q4 are turned on. By such switching control, the point A is grounded via the transistor Q2, and therefore the potential at the point A is lowered from the input voltage Vi to the ground voltage GND. Here, since a potential difference substantially equal to the input voltage Vi is given between the both ends of the capacitor C1 by the previous charging, when the above-described fluctuation occurs in the A point potential, the B point potential is changed from the ground voltage GND to the negative voltage. Pulled down to -Vi. At this time, since the point B is in conduction with the output voltage extraction terminal via the transistor Q4, the charge of the capacitor C1 moves to the output capacitor Co, and the potential of the output voltage extraction terminal is lowered to the negative voltage −Vi. It is done.

  Thus, in the charge pump circuit of the present embodiment, the desired output voltage Vo (≧ −Vi) is generated from the input voltage Vi by repeatedly charging and discharging the capacitor C1.

  In the charge pump circuit of this embodiment, the driver DRV1 that transmits the clock signal CLK to the transistor Q1 includes a P-channel field effect transistor Q5, a constant current source I1, a control unit CNT, as shown in FIG. The switches SW1 to SW5 are included.

  The source of the transistor Q5 is connected to the input voltage application terminal. The drain of the transistor Q5 is connected to the ground terminal via the constant current source I1. The gate of the transistor Q5 is connected to the gate of the transistor Q1a.

  One end of the switch SW1 is connected to the gates of the transistors Q1a and Q5. The other end of the switch SW1 is connected to the drain of the transistor Q5. One end of the switch SW2 is connected to the input voltage application terminal. The other end of the switch SW2 is connected to the gates of the transistors Q1a and Q5. One end of the switch SW3 is connected to the gates of the transistors Q1a and Q5. The other end of the switch SW3 is connected to the ground terminal. One end of the switch SW4 is connected to the gates of the transistors Q1a and Q5. The other end of the switch SW4 is connected to the gate of the transistor Q1b. One end of the switch SW5 is connected to the gates of the transistor Q1a and the transistor Q5. The other end of the switch SW5 is connected to the gate of the transistor Q1c.

  As described above, the driver DRV1 of this embodiment includes a current mirror circuit that mirrors a constant current flowing through the transistor Q5 and outputs it from the transistor Q1 among the pair of transistors Q5 and Q1. That is, the current mirror circuit is turned on when the charge storage capacitor C1 is charged by being connected between one end of the charge storage capacitor C1 and the input voltage application terminal among the charge transfer transistors Q1 to Q4. The transistor Q1 is used as a transistor on the mirror current output side.

  With such a configuration, when performing constant current control at the time of power-on described later, there is no separate constant current circuit in addition to the charge transfer transistors Q1 to Q4 on the current path of the charge pump circuit. It is possible to avoid deterioration of efficiency without causing an unnecessary increase in the on-resistance of the entire system.

  On the other hand, the control unit CNT is means for performing the above-described current mirror circuit drivability control (constant current switching control) and the on-resistance switching control of the transistor Q1 in accordance with the voltage value of the output voltage Vo.

  The constant current switching control and on-resistance switching control of the charge pump circuit configured as described above will be described in detail with reference to FIG. 2 together with FIG.

  FIG. 2 is a diagram illustrating an example of constant current switching control and on-resistance switching control. In addition, the symbol CLK, the symbol Vo, and the symbol i in the figure indicate the behavior of the clock signal CLK, the output voltage Vo, and the current i that flows into the capacitor C1, respectively. In addition to the above behavior, the figure also shows the on / off state of the switches SW1 to SW5, the presence or absence of constant current control, and the on-resistance state of the transistor Q1.

  As shown in FIG. 2, until the output voltage Vo reaches a predetermined first threshold voltage Vth1 from when the power is turned on, the control unit CNT permits the driving of the current mirror circuit described above according to the clock signal CLK. To turn it on and off periodically. At this time, the control unit CNT permits the driving of only the transistor Q1a and prohibits the driving of the other transistors Q1b and Q1c in order to maximize the on-resistance value of the transistor Q1.

  More specifically, during the period, the control unit CNT turns off the switches SW3 to SW5 in the switch group constituting the driver DRV1, and switches SW1 and SW2 according to the clock signal CLK. Complementary on / off drive.

  As a result, the current i flowing from the input voltage application terminal when the capacitor C1 is charged is limited to a predetermined upper limit value (mirror current of the current mirror circuit) by the constant current control of the current mirror circuit. Current is effectively suppressed.

  Therefore, with the charge pump circuit of this embodiment, there is no need to unnecessarily increase the current capacities of the charge transfer transistors Q1 to Q4, and the chip area can be reduced. In addition, since the charge pump circuit according to the present embodiment can earn a margin with respect to latch-up characteristics due to a large current, the manufacturing process can be widely selected. Further, if the charge pump circuit of the present embodiment is mounted as a negative power supply device of an electric device (for example, a hard disk drive device), it is possible to improve the operational stability when the power is turned on.

  Note that inrush current can be suppressed at power-on only by controlling the on-resistance of the transistor Q1 described below, but the on-resistances of the transistors Q1a to Q1c include variations due to the manufacturing process. In particular, it is desirable to perform the above-described constant current control without relying only on the on-resistance control of the transistor Q1 immediately after turning on the power, which is judged to have a high risk of inrush current.

  On the other hand, in order to utilize the current capability of the transistor Q1, it is better not to perform the constant current control. Therefore, if it can be determined that the risk of inrush current has been reduced to some extent, the constant current control is stopped. Therefore, it should be shifted only to the on-resistance control of the transistor Q1.

  Therefore, in the charge pump circuit of this embodiment, after the output voltage Vo reaches the first threshold voltage Vth1, the control unit CNT prohibits the driving of the current mirror circuit described above, and causes the transistor Q1 to respond to the clock signal CLK. It is configured to be directly turned on / off. At this time, the controller CNT maximizes the on-resistance value of the transistor Q1 until the output voltage Vo reaches the second threshold voltage Vth2 that is lower than the first threshold voltage Vth1. Therefore, only the transistor Q1a is allowed to be driven, and the other transistors Q1b and Q1c are prohibited from being driven.

  More specifically, during the period, the control unit CNT turns off the switches SW1, SW4, and SW5 of the switch group constituting the driver DRV1, and switches the switches SW2 and SW3 to the clock signal CLK. Accordingly, on / off driving is complementarily performed.

  As a result, after the risk of the inrush current has been reduced to a certain extent, it becomes possible to remove the restriction due to the constant current control and utilize the current capability of the transistor Q1.

  In view of the characteristics of the charge pump circuit, the on-resistance of the transistor Q1 should be as small as possible. Therefore, the on-resistance value of the transistor Q1 should be lowered during normal operation. However, if the on-resistance value of the transistor Q1 is sharply reduced, the current i to the capacitor C1 rises rapidly, and the meaning of suppressing the inrush current is halved.

  Therefore, in the charge pump circuit of this embodiment, the control unit 2 decreases the on-resistance value of the transistor Q1 as the output voltage Vo approaches its target voltage value, that is, the number of driving transistors Q1a to Q1c. These drive enable / disable control is performed so as to increase.

  More specifically, the control unit 2 turns on the switch SW4 when the output voltage Vo decreases to the second threshold voltage Vth1 described above, and the output voltage Vo is lower than the second threshold voltage Vth2. The switch SW5 is turned on when the voltage drops to three threshold voltages Vth3.

  In this way, while monitoring the voltage value of the output voltage Vo, the configuration in which the number of transistors Q1a to Q1c is increased stepwise, that is, the on-resistance value of the transistor Q1 is decreased stepwise. For example, the maximum current value can be suppressed without changing the characteristics of the charge pump circuit during normal operation.

  The configuration of the present invention can be variously modified within the scope of the present invention in addition to the above embodiment.

  For example, as shown in FIG. 3, a configuration using diodes D1 to D2 instead of the transistors Q3 to Q4 may be used.

  In the above embodiment, the case where the present invention is applied to a negative voltage output charge pump circuit has been described as an example. However, the application target of the present invention is not limited to this, and is shown in FIG. Thus, the present invention can also be applied to a positive boost charge pump circuit.

  The present invention is a technique useful for preventing an inrush current of a charge pump circuit.

These are the circuit diagrams which show 1st Embodiment of the charge pump circuit based on this invention. These are figures which show an example of constant current switching control and on-resistance switching control. These are the circuit diagrams which show 2nd Embodiment of the charge pump circuit based on this invention. These are the circuit diagrams which show 3rd Embodiment of the charge pump circuit based on this invention. These are circuit diagrams showing a conventional example of a charge pump circuit. These are figures which show the mode of inrush current generation | occurrence | production.

Explanation of symbols

Q1a to Q1c Charge transfer transistor (also a current mirror transistor)
Q2, Q3, Q4 Charge transfer transistor C1 Charge storage capacitor Co Output capacitor DRV1 to DRV4 driver Q5 Current mirror transistor I1 Constant current source CNT control unit SW1 to SW5 Switch D1 to D2 Diode

Claims (3)

A charge pump circuit that generates a desired output voltage from an input voltage by periodically turning on / off a plurality of charge transfer transistors according to a clock signal and charging and discharging a charge storage capacitor,
A current mirror circuit that mirrors a constant current flowing through one of the pair of transistors and outputs the current from the other; and a control unit that controls whether the current mirror circuit is driven according to the voltage value of the output voltage. Consisting of
The current mirror circuit is connected between one end of the charge storage capacitor and the input voltage application end among the plurality of charge transfer transistors, and is turned on when charging the charge storage capacitor. The first transistor is used as a mirror current output transistor,
The control unit permits driving of the current mirror circuit until the output voltage reaches a predetermined threshold voltage, and periodically turns it on / off according to the clock signal, while the output voltage is predetermined. After the threshold voltage is reached, the drive of the current mirror circuit is prohibited, and the first transistor is directly turned on / off according to the clock signal.   The first transistor is subdivided into a plurality of transistors connected in parallel to each other, and the control unit controls whether the current mirror circuit is driven or not, and after the output voltage reaches a predetermined threshold voltage, 2. The charge according to claim 1, wherein the drive enable / disable control is performed so that the number of drive of the subdivided transistors is increased as the output voltage approaches the target voltage value. Pump circuit.   An electric apparatus comprising the charge pump circuit according to claim 1.

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