JP2014089560A - Semiconductor device - Google Patents

Abstract

A conventional semiconductor device has a problem that the charge of a capacitor accumulated during operation cannot be reliably reduced when the operation is stopped.
According to one embodiment, a semiconductor device has a switch circuit including a transistor MN4 that discharges the charge of a capacitor provided outside, and the switch circuit according to the stop of operation of the regulator circuit. The transistor MN4 is kept on for at least the period until the power supply of 15 is cut off and the charge of the capacitor is stabilized.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device, for example, a semiconductor device including a switch circuit that discharges an externally connected capacitor when operation is stopped.

  In a DC voltage conversion circuit such as a switching regulator circuit, a smoothing capacitor having a large capacity is provided outside, and an output voltage having a preset voltage value is generated by controlling the amount of charge accumulated in the smoothing capacitor. In such a DC voltage conversion circuit, after the operation is stopped, the charge accumulated in the smoothing capacitor is not sufficiently discharged, and the output voltage does not decrease even after the operation is stopped. Therefore, Patent Documents 1 to 3 disclose a technique for discharging charges from a smoothing capacitor when operation is stopped.

  Patent Document 1 discloses a system having a power supply circuit that drives a load circuit, a discharge circuit that discharges a charge of a capacitive component of the load circuit to reduce the voltage of the load circuit, and a sequence control circuit. . In this system, the sequence control circuit controls the output voltage by forcibly discharging the capacitance component of the load in the discharge circuit when stopped.

  Patent Document 2 has a latch circuit connected in parallel with a capacitor, and by turning on the switch of the latch circuit, a resistor connected in series with the latch circuit until the potential between the terminals of the capacitor becomes a predetermined value or less. Maintain discharge.

  Patent Document 3 is an electric circuit that has a power-off mode and an on-mode, and is always supplied with power, but substantially performs a predetermined function only in the power-on mode. This electric circuit includes a capacitor that may be charged or discharged by a leakage current in the power-off mode, and forms a loop that discharges the accumulated charge of the capacitor through a diode in the power-off mode. A capacitor control circuit for closing the discharge loop by putting the diode in a reverse bias state in the mode is included. Thereby, the electric circuit of patent document 3 implement | achieves the capacitor voltage control function in the time of standby.

JP 2010-226863 A Japanese Patent Laid-Open No. 06-113490 Japanese Unexamined Patent Publication No. 07-046056

  However, in the prior art described in Patent Documents 1-3, there is a problem that the residual charge of the capacitor cannot be sufficiently extracted when the power supply of the entire circuit is cut off. In other words, the conventional technique has a problem that the residual charge of the capacitor cannot be reduced reliably.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a semiconductor device has a switch circuit including a transistor that discharges the charge of a capacitor provided outside, and shuts off the power supply of the switch circuit in response to the operation stop of the regulator circuit. The transistor is kept on for at least a period until the charge of the capacitor is stabilized.

  In addition, what replaced the apparatus of the said embodiment with the method and the system, etc. are effective as an aspect of this invention.

  According to the embodiment, the residual charge of the capacitor can be reliably reduced.

1 is a block diagram of a power supply circuit according to a first exemplary embodiment; 1 is a circuit diagram of a switch circuit according to a first exemplary embodiment; 3 is a timing chart showing the operation of the power supply circuit according to the first exemplary embodiment; 3 is a timing chart showing the operation of the power supply according to the first exemplary embodiment. FIG. 3 is a circuit diagram of a circuit as a comparative example of the switch circuit according to the first exemplary embodiment; 6 is a timing chart illustrating an operation of a power supply circuit including the circuit illustrated in FIG. 5. FIG. 3 is a block diagram of a power supply circuit according to a second exemplary embodiment. FIG. 6 is a block diagram of a switch circuit according to a third exemplary embodiment. FIG. 6 is a block diagram of a power supply system including a power supply circuit according to a fourth embodiment.

  For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. Note that, in each drawing, the same element is denoted by the same reference numeral, and redundant description is omitted as necessary.

  Hereinafter, embodiments will be described with reference to the drawings. First, FIG. 1 shows a block diagram of a power supply circuit 1 according to the first embodiment. As illustrated in FIG. 1, the power supply circuit 1 according to the first embodiment includes a semiconductor device 10, an inductor L, and a capacitor C. The semiconductor device 10 includes a regulator circuit. The inductor L and the capacitor C are provided as external components for the regulator circuit. One end of the inductor L is connected to the external terminal Tout serving as the output terminal of the regulator circuit. The capacitor C has one end connected to the ground wiring and the other end connected to the other end of the inductor L. Then, the output voltage VOUT is generated on the wiring connecting the inductor L and the capacitor C. The output voltage VOUT is supplied to a power supply target circuit (for example, a load circuit) and is also supplied to an external terminal Tfb that functions as a feedback terminal in the semiconductor device 10.

  The semiconductor device 10 has an external terminal Tin to which the input voltage VIN is applied and an external terminal Tsin to which the standby control signal Sin is applied. The semiconductor device 10 generates an output voltage VOUT based on the input voltage VIN. Further, the semiconductor device 10 switches between an operating state and a non-operating state based on the standby control signal. When the semiconductor device 10 enters a non-operating state, the power supply to the internal circuit elements is suppressed as much as possible in order to reduce power consumption. The semiconductor device 10 includes a control unit 11, an internal power generation circuit 12, a regulator circuit 13, and a switch circuit 15.

  The control unit 11 is a standby control circuit. The control unit 11 stops the generation of the second voltage V2 by the internal power generation circuit 12 and the operation of the regulator circuit 13 according to a standby control signal input from the outside. The control unit 11 outputs a standby shift instruction signal Scnt that is enabled when the standby control signal Sin is enabled (for example, at a low level). It is assumed that the control unit 11 operates based on the input voltage VIN.

  The internal power supply generation circuit 12 generates the second voltage V2 based on the input voltage VIN input from the outside. The second voltage V2 is, for example, the internal power supply voltage VDD obtained by stepping down the input voltage VIN. The regulator circuit 13 and the switch circuit 15 operate based on the internal power supply voltage VDD. The internal power generation circuit 12 stops generating the second voltage V2 in response to the standby transition instruction signal output from the control unit 11 being enabled. In the first embodiment, the internal power supply generation circuit 12 supplies the internal power supply voltage VDD having the same voltage value to the regulator circuit 13 and the switch circuit 15, but the regulator circuit 13 and the switch circuit 15 can also be operated at different voltages.

  The regulator circuit 13 generates an output voltage VOUT having a preset voltage value by charging a smoothing capacitor (for example, a capacitor C) connected to the external terminal Tout based on the input voltage VIN. More specifically, in the semiconductor device 10 according to the first embodiment, a switching regulator circuit is used as the regulator circuit 13. The regulator circuit 13 includes a regulator control circuit 14, a power PMOS transistor PMP, and a power NMOS transistor PMN.

  The regulator control circuit 14 has a reference voltage that is a target value of the voltage value of the output voltage VOUT. The regulator control circuit 14 generates a PWM (Pulse Width Modulation) signal whose duty ratio changes according to the voltage difference between the reference voltage and the output voltage VOUT. In the first embodiment, the regulator control circuit 14 enables the discharge enable signal EN in response to the standby transition instruction signal Scnt output from the control unit 11 being enabled.

  In the power PMOS transistor PMP, the input voltage VIN is applied to the source, and one of the PWM signals output from the regulator control circuit 14 is applied to the gate. In the power NMOS transistor PMN, the ground voltage is supplied to the source, and the other of the PWM signals output from the regulator control circuit 14 is supplied to the gate. The drain of the power PMOS transistor PMP and the drain of the power NMOS transistor PMN are connected to the external terminal Tout.

  The switch circuit 15 discharges the electric charge of the smoothing capacitor (for example, the capacitor C) in response to the operation of the regulator circuit 14 being stopped. More specifically, the switch circuit 15 includes a discharge control circuit 16 and a first MOS transistor (for example, a transistor MN4).

  The discharge control circuit 16 turns on the transistor MN4 in response to the enable signal EN being enabled. In addition, the discharge control circuit 16 maintains the on state even when the second voltage V2 (for example, the internal power supply voltage VDD) is cut off after the transistor MN4 is turned on. The transistor MN4 extracts electric charge from the capacitor C provided outside under the control of the discharge control circuit 16. The transistor MN4 functions as a switch transistor.

  From the above description, the semiconductor device 10 operates the regulator circuit 13 and the switch circuit 15 based on the internal power supply voltage VDD obtained by stepping down the input voltage VIN, and stops the operation of the regulator circuit 13 along with the transition to the standby state. The generation of the power supply voltage VDD is stopped. Further, even after the generation of the internal power supply voltage VDD is stopped, the semiconductor device 10 keeps the transistor MN4 of the switch circuit 15 in the on state and extracts the charge of the capacitor provided outside. Therefore, a more detailed configuration of the switch circuit 15 will be described. FIG. 2 shows a circuit diagram of the switch circuit 15.

  As shown in FIG. 2, the switch circuit 15 includes the discharge control circuit 16 and the transistor MN4. However, in the following description, the switch circuit 15 is treated as an integrated circuit including the discharge control circuit 16 and the transistor MN4.

  As shown in FIG. 2, the switch circuit 15 includes inverters INV1 and INV2 and transistors MN1 to MN4. The inverters INV1 and INV2 are logic circuits that generate the first control signal NL and the second control signal NH based on the enable signal EN. This logic circuit operates based on the second voltage V2 and the first voltage V1. In the first embodiment, the second voltage V2 is the internal power supply voltage VDD supplied to the second power supply wiring. The first voltage V1 is a ground voltage VSS supplied to the first power supply wiring, and is an operation reference voltage supplied to the switch circuit 15 even when the supply of the internal power supply voltage VDD is stopped. At this time, the second voltage V2 (internal power supply voltage VDD) whose supply is stopped approaches the voltage value of the first voltage V1 (ground voltage VSS) by the circuit of the semiconductor device 10 and the parasitic circuit.

  The inverter INV1 includes transistors MN5 and MP1. The transistor MN5 is a first conductivity type (N-type in this embodiment) NMOS transistor. The transistor MP1 is a PMOS transistor of the second conductivity type (P type in this embodiment). The transistor MN5 has a source connected to the first power supply line to which the first voltage V1 is supplied, a drain connected to the drain of the transistor MP1, and a gate to which the enable signal EN is input. The transistor MP1 has a source connected to the second power supply line to which the second voltage V2 is supplied, a drain connected to the drain of the transistor MN5, and an enable signal EN input to the gate. The inverter INV1 outputs a second control signal having a logic level obtained by inverting the enable signal EN from a node connecting the drain of the transistor MN5 and the drain of the transistor MP1. In FIG. 2, NH is used as the reference sign of the second control wiring to which the second control signal is transmitted. However, in the following description, the second control signal may be indicated with NH sign.

  The inverter INV2 includes transistors MN6 and MP2. The transistor MN6 is a first conductivity type (N-type in this embodiment) NMOS transistor. The transistor MP2 is a PMOS transistor of the second conductivity type (P type in this embodiment). The transistor MN6 has a source connected to the first power supply line to which the first voltage V1 is supplied, a drain connected to the drain of the transistor MP2, and a gate to which a second control signal is input. The transistor MP2 has a source connected to the second power supply line to which the second voltage V2 is supplied, a drain connected to the drain of the transistor MN6, and a second control signal input to the gate. The inverter INV2 outputs a first control signal having a logic level obtained by inverting the second control signal from a node connecting the drain of the transistor MN5 and the drain of the transistor MP2. In FIG. 2, NL is used as the reference sign of the first control wiring to which the first control signal is transmitted. However, in the following description, the NL reference sign may be attached to the first control signal.

  The transistor MN4 functions as a first MOS transistor. The transistor MN4 is a first conductivity type (N-type in this embodiment) NMOS transistor. The transistor MN4 has a source connected to the first power supply line to which the first voltage V1 is supplied, a gate connected to the switch control line Ngate, and a drain connected to the external terminal Tout.

  The transistor MN2 functions as a second MOS transistor. The transistor MN2 is a first conductivity type (N-type in this embodiment) NMOS transistor. The transistor MN2 has a source and a back gate connected to a first power supply line to which the first voltage V1 is supplied, a drain connected to the switch control line Ngate, and a gate to which a first control signal is input. That is, the first control wiring NL is connected to the gate of the transistor MN2.

  The transistor MN1 functions as a third MOS transistor. The transistor MN1 is a first conductivity type (N-type in this embodiment) NMOS transistor. The transistor MN1 has a source connected to the switch control line Ngate, a drain connected to a second power supply line to which the second voltage V2 is supplied, and a gate having a logic level that is inverted from the first control signal. A control signal is input. That is, the second control wiring NH is connected to the gate of the transistor MN1.

  The transistor MN3 functions as a fourth MOS transistor. The transistor MN3 is a first conductivity type (N-type in this embodiment) NMOS transistor. The transistor MN3 has a source connected to the switch control line Ngate, a drain and a back gate connected to the back gate of the third MOS transistor (for example, the transistor MN1), and a gate connected to the second power supply line to which the second voltage V2 is supplied. Connected.

  Next, the operation of the power supply circuit 1 according to the first embodiment will be described. Since the power supply circuit 1 according to the first embodiment is particularly characterized in the operation when the operation of the regulator circuit 13 is stopped, the operation when the operation of the regulator circuit 13 is stopped will be described in detail below. First, FIG. 3 shows a timing chart showing the operation of the power supply circuit 1 according to the first embodiment when the operation of the regulator circuit 13 is stopped while the internal power supply generation circuit 12 is operated.

  As shown in FIG. 3, when the operation of the regulator circuit 13 is stopped while the internal power supply generation circuit 12 is generating the internal power supply voltage VDD, the regulator circuit 13 shifts to the operation stop state at timing t1. The enable signal EN is enabled (for example, low level). Then, in response to the enable signal EN being enabled, the first control signal NL is changed from a high level to a low level, whereby the transistor MN2 is switched from on to off. Further, when the second control signal NH changes from the low level to the high level, the transistor MN1 is switched from off to on.

  As described above, when the transistor MN2 is turned off and the transistor MN1 is turned on, the switch control wiring Ngate is switched from the low level to the high level, and the transistor MN4 is switched from the off state to the on state. Thereby, the discharge of the capacitor C is started from the timing t1, and the output voltage VOUT is lowered to the first voltage V1 (for example, the ground voltage). In addition, since the internal power supply voltage VDD is applied to the gate of the transistor MN3, the transistor MN3 is maintained in an ON state, and a voltage substantially equal to the voltage level generated in the switch control wiring Ngate is applied to the back gate of the transistor MN1.

  As described above, in the power supply circuit 1, the enable signal EN is enabled to turn on the transistor MN4, and the capacitor C is extracted. In the power supply circuit 1, the transistor MN4 can be kept on even after the generation of the internal power supply voltage VDD is stopped. FIG. 4 is a timing chart showing the operation of the power supply circuit 1 according to the first embodiment when the operation of the regulator circuit 13 is stopped and the generation of the internal power supply voltage VDD is stopped.

  As shown in FIG. 4, the internal power generation circuit 12 stops the generation of the internal power supply voltage VDD by switching the standby control signal from the high level to the low level (disenabled state to enabled state) at timing t2. As a result, the internal power supply voltage VDD decreases to the first voltage V1. Further, as shown in FIG. 4, the regulator circuit 13 sets the enable signal EN to an enable state (for example, low level) in response to the standby control signal becoming low level. Then, in response to the enable signal EN being enabled, the first control signal HL changes from the high level to the low level, whereby the transistor MN2 is switched from on to off. Further, when the second control signal NH changes from the low level to the high level, the transistor MN1 is switched from off to on. However, in the example shown in FIG. 4, since the decrease of the internal power supply voltage VDD starts at the timing t2, the second control signal NH decreases once according to the decrease of the internal power supply voltage VDD after the voltage once increases. .

  In the example shown in FIG. 4, once the transistor MN2 is turned off and the transistor MN1 is turned on, the switch control wiring Ngate is switched from the low level to the high level, and the transistor MN4 is turned on from the off state. Switch to Thereby, the discharge of the capacitor C is started from the timing t2, and the voltage drop of the output voltage VOUT is started. At this time, the switch control wiring Ngate is charged to a voltage value lower than the second power supply V2 by the threshold value (Vt) of the NMOS transistor MN1, and the voltage value is mainly held by the gate capacitance of the NMOS transistor MN4. . The discharge path of charge on the circuit of the switch control wiring Ngate is divided into three main paths by the drain current of the NMOS transistor MN2, the source / drain current of the MNOS transistor MN1, and the body diode of the NMOS transistor MN1 through the NMOS transistor MN3. Become. In addition to this, there is discharge due to a parasitic leak path, but this value can be ignored when the effect of this embodiment is examined.

  In the example shown in FIG. 4, the internal power supply voltage VDD starts to decrease from timing t2. Of these three paths, the NMOS transistor MN2 remains off regardless of the voltage value of the internal power supply voltage VDD, and may be excluded from the examination. In this embodiment, it will be described below that the remaining two discharge paths are cut off as the VDD voltage decreases. First, since the gate voltage of the NMOS transistor MN1 is substantially the same voltage as the internal power supply voltage VDD, the drain and gate of the NMOS transistor MN1 are lowered with substantially the same voltage. At this time, the internal power supply voltage VDD decreases first, and the voltage of the switch control wiring Ngate decreases through the NMOS transistor MN1 that is turned on. That is, the voltage of the internal power supply voltage VDD decreases before the voltage of the switch control wiring Ngate. The NMOS transistor MN1 is turned off when the internal power supply voltage VDD is lower than the voltage of the switch control wiring Ngate, and the drain and source are switched. In other words, the voltage of the drain and gate is the internal power supply voltage VDD, which has been turned on because it is higher than the voltage of the source switch control wiring Ngate. Since the drain and source of the NMOS transistor MN1 are switched by being lower than the voltage of the switch control wiring Ngate, the gate voltage is also changed from the previous drain voltage to a new source voltage. Therefore, since the gate voltage of the NMOS transistor MN1 becomes the same as the source voltage, the NMOS transistor MN1 is turned off. As a result, the charge discharge path of the switch control wiring Ngate through the NMOS transistor MN1 is blocked.

  Further, since the internal power supply voltage VDD is applied to the gate of the transistor MN3, the transistor MN3 remains in the on state from before the timing t2, but the internal power supply voltage VDD is decreased to be lower than the voltage of the switch control wiring Ngate. It turns off at that point. Details of this operation will be described after the description of FIGS. As a result, the two main discharge paths of the charges on the switch control wiring Ngate are cut off, so that the voltage of the switch control wiring Ngate is maintained at a constant voltage after being slightly lowered. Therefore, in the example shown in FIG. 4, even after the generation of the internal power supply voltage VDD is stopped, the capacitor C is discharged by the transistor MN4, and the voltage of the output voltage VOUT is lowered. Note that the voltage of the back gate NBG of the transistor MN1 is discharged by the parasitic diode formed between the back gate and the drain of the transistor MN1, and thus decreases as the internal power supply voltage VDD decreases.

  Here, in order to further describe the operation of the power supply circuit 1 according to the first embodiment, a power supply circuit including the switch circuit 100 obtained by removing the transistor MN3 from the switch circuit 15 will be described. First, FIG. 5 shows a circuit diagram of a switch circuit 100 as a comparative example of the switch circuit 15 according to the first embodiment. As shown in FIG. 5, the switch circuit 100 is obtained by removing the transistor MN3 from the switch circuit 15 and connecting the back gate of the transistor MN1 to the switch control wiring Ngate.

  Next, a timing chart showing the operation of the power supply circuit including the switch circuit 100 is shown in FIG. The timing chart shown in FIG. 6 is obtained by performing the operation of the power supply circuit 1 shown in FIG. 4 on a power supply circuit including the switch circuit 100 (hereinafter referred to as a comparative power supply circuit). Therefore, in the description related to FIG. 6, only an operation different from the operation described in FIG. 4 will be described.

  As shown in FIG. 6, in the comparative power supply circuit, since the back gate of the transistor MN1 is connected to the switch control wiring Ngate, there is no timing chart regarding the back gate of the transistor MN1. In the example illustrated in FIG. 6, the voltage of the switch control wiring Ngate increases in response to the switching of the logic levels of the first control signal HL and the second control signal NH at the timing t2. However, in the comparative power supply circuit, since the switch control wiring Ngate is connected to the back gate of the transistor MN1, the voltage of the switch control wiring Ngate decreases according to the decrease of the internal power supply voltage VDD. This is because the back gate NBG of the transistor MN1 is a P-type semiconductor and the drain of the transistor MN1 connected to the internal power supply voltage VDD is an N-type semiconductor, so that a diode (body diode) is formed at the contact point between the back gate NBG and the drain. It is because it has been.

  That is, when the VDD connected to the drain (cathode) becomes a voltage lower than the voltage of the switch control wiring Ngate connected to the back gate NBG (anode) by a certain value (for example, the forward voltage VF of the diode), the body diode moves forward. This is because it turns on with bias. Here, the forward voltage VF of the diode is a value of the forward voltage drop of the body diode, and is about 0.7 V in a silicon semiconductor, for example. At this time, the voltage of the switch control wiring Ngate has a value of VDD + VF. For this reason, when the internal power supply voltage VDD becomes approximately 0 V (VSS voltage), the voltage of the switch control wiring Ngate becomes approximately 0.7 V. This voltage value is lower than the threshold value of the NMOS transistor MN4. Therefore, in the comparison power supply circuit, the charge of the capacitor C cannot be sufficiently extracted after the internal power supply voltage VDD is cut off, and the output voltage VOUT is maintained at a high voltage.

  In contrast, in the discharge control circuit 16 according to the first embodiment, the NMOS transistor MN3 is connected between the back gate NBG of the NMOS transistor MN1 and the switch control wiring Ngate, so that the switch control wiring via the body diode is connected. Ngate charge discharge can be prevented. This will be described in detail below. Before the timing t2 in FIG. 4, the gate of the NMOS transistor MN3 is connected to the internal power supply voltage VDD which is the highest potential in the switch circuit 15, so that the NMOS transistor MN3 is on. As a result, the voltage of the switch control wiring Ngate is supplied to the back gate NBG of the NMOS transistor MN1 through the NMOS transistor MN3 that is turned on. Here, after the timing t2 of FIG. 4, the voltage of the internal power supply voltage VDD decreases. The voltage of the back gate NBG decreases with the decrease of VDD on the same principle as in FIG. During this time, the voltage of the switch control line Ngate also decreases through the NMOS transistor MN3 that is turned on. However, at this time, the voltage drop of the internal power supply voltage VDD is the fastest, and the voltage of the back gate NBG of the NMOS transistor MN1 becomes the value of VDD + VF, so that the internal voltage is higher than the source voltage of the NMOS transistor MN3 connected to the back gate NBG. The gate voltage of the NMOS transistor MN3 connected to the power supply voltage VDD becomes lower, and the NMOS transistor MN3 is turned off. For this reason, the discharge of charges through the body diode of the NMOS transistor MN1 of the switch control wiring Ngate, which did not stop in the comparison power supply circuit, is blocked. As a result, it is possible to suppress a decrease in the voltage of the switch control wiring Ngate that provides the gate voltage of the NMOS transistor MN4.

  From the above description, the power supply circuit 1 according to the first embodiment has the transistor MN3 that applies the back gate voltage to the back gate NBG of the transistor MN1, and the transistor MN3 is switched according to the interruption of the internal power supply voltage VDD supplied to the switch circuit. By setting the OFF state, the flow path of charges from the switch control wiring Ngate is blocked. Thus, in the power supply circuit 1, even when the operation of the regulator circuit 13 is stopped and the generation of the internal power supply voltage VDD is stopped, the transistor MN4 is kept on even after the generation of the internal power supply voltage VDD is stopped. The electric charge of the capacitor C can be reduced.

  Further, in Patent Document 1, since it is necessary to maintain the sequence control circuit in an operating state in order to discharge the electric charge accumulated in the capacitor, power consumption of the sequence control circuit is required. However, in the semiconductor device 10 according to the first embodiment, since the charge extraction by the switch circuit 15 can be continued even after the internal power supply voltage VDD is shut off, the waste of power consumption for maintaining the discharge operation as in Patent Document 1 is eliminated. be able to.

  Further, in Patent Document 3, in order to deactivate a diode that performs charge extraction after power is shut off when power is supplied, current is supplied to a resistor that applies a reverse bias to the diode during normal operation before power is shut off. I must continue. Therefore, the technique described in Patent Document 3 has a problem that the power consumption during normal operation increases. However, in the semiconductor device 10 according to the first embodiment, it is not necessary to flow a static current through the resistor. In particular, when the switch circuit 15 is entirely formed of a low power consumption CMOS transistor structure as in the first embodiment, one of the purposes of the semiconductor device 10 according to the first embodiment is to reduce the power consumption. Considering this, a circuit that allows a static current to flow through the resistor cannot be used. As described above, in the semiconductor device 10 according to the first embodiment, the power consumption during the normal operation can be reduced as compared with the technique described in Patent Document 3.

  Further, in Patent Document 3, since the diode is used for extracting the charge, there is a problem that a residual charge of at least a forward bias voltage drop of the diode remains in the capacitor from which the charge is extracted. In Patent Document 2, a resistor connected in parallel to a capacitor from which charges are extracted and a latch circuit connected in series to the resistor are used. Further, in Patent Document 2, this latch circuit is constituted by a circuit having a thyristor structure. For this reason, the latch circuit does not operate when the residual charge of the capacitor decreases and the voltage drops, and there is a problem that the residual charge of the capacitor cannot be sufficiently reduced. However, in the semiconductor device 10 according to the first embodiment, an NMOS transistor (for example, the transistor MN4) is used for extracting charges. Therefore, in the semiconductor device 10, the charge of the capacitor C can be extracted until the drain voltage of the transistor MN4 becomes the source voltage (for example, the ground voltage), and the residual charge can be reduced as compared with other techniques.

  In the semiconductor device 10 according to the first embodiment, the internal power supply generation circuit 12 generates the internal power supply voltage VDD obtained by stepping down the input voltage VIN, and the regulator circuit 13 and the switch circuit 15 operate based on the internal power supply voltage VDD. Let Thereby, in the semiconductor device 10, it is possible to reduce the withstand voltage required for the transistors constituting the regulator circuit 13 (in particular, the regulator control circuit 14) and the switch circuit 15. In general, a transistor with a small withstand voltage has a smaller element size than a transistor with a large withstand voltage. Therefore, the semiconductor device 10 according to the first embodiment can reduce the chip size compared to the case where the internal power generation circuit 12 is not provided.

  Further, in the semiconductor device 10 according to the first embodiment, the internal circuit is operated with the internal power supply voltage VDD having a voltage value lower than the input voltage VIN, so that power consumption can be reduced. Furthermore, in the semiconductor device 10 according to the first embodiment, in the standby state, the generation of the internal power supply voltage VDD is stopped, so that the leakage current can be reduced as compared with the case where the circuit operation is simply stopped. Therefore, the semiconductor device 10 can reduce power consumption during standby as compared with the case where the internal power generation circuit 12 is not provided.

Embodiment 2
In the second embodiment, another form of connection destination of the transistor MN4 will be described. FIG. 7 shows a block diagram of the power supply circuit 2 including the semiconductor device 20 according to the second embodiment. As shown in FIG. 7, in the semiconductor device 20, the drain of the transistor MN4 is connected to an external terminal Tfb serving as an input terminal for inputting a feedback signal (for example, the output voltage VOUT).

  Thus, by connecting the drain of the transistor MN4 to the external terminal Tfb, the charge of the capacitor C is extracted by the transistor MN4 without passing through the inductor L. Therefore, the semiconductor device 20 according to the second embodiment can complete the discharge operation earlier than the semiconductor device 10 according to the first embodiment.

Embodiment 3
In the third embodiment, a switch circuit 15a which is another form of the switch circuit 15 will be described. For example, when the output voltage VOUT is a negative voltage, the switch circuit 15a can reduce the residual charge of the capacitor C (negative residual charge in which the charge amount is negative in the third embodiment). The semiconductor device including the switch circuit 15a generates a negative voltage as the second voltage V2 in the internal power generation circuit 12 of the semiconductor device shown in FIG. 1 or FIG. Is replaced with a circuit that generates The switch circuit 15a is supplied with an enable signal EN having the first voltage V1 as an upper limit voltage and the second voltage V2 as a lower limit voltage.

  FIG. 8 is a circuit diagram of the switch circuit 15a according to the third embodiment. As shown in FIG. 8, the switch circuit 15a includes inverters INV3 and INV4 and transistors MP11 to MP14. The inverters INV3 and INV4 are logic circuits that generate the first control signal NL and the second control signal NH based on the enable signal EN. This logic circuit operates based on the second voltage V2 and the first voltage V1. In the third embodiment, the second voltage V2 is a negative voltage lower than the ground voltage and is an internal power supply voltage supplied to the second power supply wiring. The first voltage V1 is a ground voltage VSS supplied to the first power supply wiring, and is an operation reference voltage supplied to the switch circuit 15a even when the internal power supply voltage supply is stopped.

  The inverter INV3 includes transistors MN11 and MP15. The transistor MN11 is a second conductivity type (N-type in this embodiment) NMOS transistor. The transistor MP15 is a PMOS transistor of the first conductivity type (P type in this embodiment). The transistor MN11 has a source connected to the second power supply line to which the second voltage V2 is supplied, a drain connected to the drain of the transistor MP15, and an enable signal EN input to the gate. The transistor MP15 has a source connected to the first power supply line to which the first voltage V1 is supplied, a drain connected to the drain of the transistor MN11, and an enable signal EN input to the gate. The inverter INV3 outputs a second control signal having a logic level obtained by inverting the enable signal EN from a node connecting the drain of the transistor MN11 and the drain of the transistor MP15. In FIG. 8, NH is used as the reference sign of the second control wiring to which the second control signal is transmitted. However, in the following description, the second control signal may be indicated with NH sign.

  The inverter INV4 includes transistors MN12 and MP16. The transistor MN12 is a second conductivity type (N-type in this embodiment) NMOS transistor. The transistor MP16 is a PMOS transistor of the first conductivity type (P type in this embodiment). The transistor MN12 has a source connected to a second power supply line to which the second voltage V2 is supplied, a drain connected to the drain of the transistor MP16, and a gate to which a second control signal is input. The transistor MP16 has a source connected to the first power supply line to which the first voltage V1 is supplied, a drain connected to the drain of the transistor MN12, and a gate to which a second control signal is input. The inverter INV4 outputs a first control signal having a logic level obtained by inverting the second control signal from a node connecting the drain of the transistor MN12 and the drain of the transistor MP16. In FIG. 8, NL is used as the reference sign of the first control wiring to which the first control signal is transmitted. However, in the following description, the NL reference sign may be attached to the first control signal.

  The transistor MP14 functions as a first MOS transistor. The transistor MP14 is a first conductivity type (P-type in the present embodiment) PMOS transistor. The transistor MP14 has a source connected to the first power supply line to which the first voltage V1 is supplied, a gate connected to the switch control line Ngate, and a drain connected to the external terminal Tout.

  The transistor MP12 functions as a second MOS transistor. The transistor MP12 is a first conductivity type (P-type in this embodiment) PMOS transistor. The transistor MP12 has a source and a back gate connected to the first power supply line to which the first voltage V1 is supplied, a drain connected to the switch control line Ngate, and a gate to which a first control signal is input. That is, the first control wiring NL is connected to the gate of the transistor MP12.

  The transistor MP11 functions as a third MOS transistor. The transistor MP11 is a first conductivity type (P-type in this embodiment) PMOS transistor. The transistor MP11 has a source connected to the switch control line Ngate, a drain connected to the second power supply line to which the second voltage V2 is supplied, and a gate having a logic level that is inverted from the first control signal. A control signal is input. That is, the second control wiring NH is connected to the gate of the transistor MP11.

  The transistor MP13 functions as a fourth MOS transistor. The transistor MP13 is a PMOS transistor of the first conductivity type (P type in this embodiment). The transistor MP13 has a source connected to the switch control line Ngate, a drain and a back gate connected to the back gate of a third MOS transistor (for example, the transistor MP11), and a gate connected to a second power supply line to which the second voltage V2 is supplied. Connected.

  That is, the switch circuit 15a is obtained by replacing the NMOS transistor of the switch circuit 15 with a PMOS transistor. The switch circuit 15a turns off the transistor MP12 and turns on the transistor MP11 in response to the enable signal EN being enabled (for example, high level), thereby turning on the transistor MP14. Discharge (decrease negative residual charge).

  In addition, when the enable signal EN is enabled and the supply of the internal power supply voltage is stopped, the switch circuit 15a sets the transistor MP13 to the shut-off state on the basis of the same principle as the switch circuit 15 and charges the switch control wiring Ngate. Is prevented from flowing out to the second power supply wiring through the parasitic diode of the transistor MP11, and the transistor MP14 is maintained in the ON state.

  In other words, the switch circuit 15a according to the third embodiment corresponds to the case where the output voltage VOUT is a negative voltage, and as with the switch circuit 15 according to the first embodiment, the residual charge of the capacitor C is reliably ensured. And power consumption can be suppressed.

Embodiment 4
In the fourth embodiment, a power supply system 3 using a plurality of power supply circuits will be described. FIG. 9 shows a block diagram of the power supply system according to the fourth embodiment. As illustrated in FIG. 9, the power supply system 3 according to the fourth embodiment includes semiconductor devices 300 and 301 and power supply target circuits 40 and 41 in addition to the semiconductor device 10 according to the first embodiment. In FIG. 9, the illustration of the inductor L and the capacitor C connected to the output terminal VOUT0 of the semiconductor devices 10, 300, and 301 is omitted.

  In the fourth embodiment, the input voltage VIN of the semiconductor device 10 has a voltage value of about 5V to 12V, and the output voltage VOUT0 is set to about 5V. In the fourth embodiment, the components described in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and the description thereof is omitted.

  The main power supply circuit 10 is basically the same circuit as the semiconductor device 10 according to the first embodiment. The difference is that the regulator circuit 13 outputs a standby transition instruction signal Scnt1 whose high level is the same as the output voltage VOUT0 and whose low level is the same as the operation reference voltage V1. The semiconductor device 300 includes a regulator circuit 330 and a switch circuit 350. The regulator circuit 330 generates the output voltage VOUT1 using the output voltage VOUT0 output from the semiconductor device 10 as an input voltage. This output voltage VOUT1 is set to about 1V. The regulator circuit 330 includes an input voltage detection circuit (not shown) that detects that the input voltage has fallen below a preset operable voltage and enables the enable signal EN. The regulator circuit 330 uses the input voltage as the operating power supply voltage. That is, the regulator circuit 330 is obtained by adding an input voltage detection circuit to the regulator circuit 13 according to the first embodiment and operating based on the input voltage. Further, the regulator circuit 330 receives the standby shift instruction signal Scnt1 from the main power supply circuit 10 and outputs the discharge enable signal EN to the switch circuit 350. The switch circuit 350 is the same circuit as the switch circuit 15 according to the first embodiment, but uses an input voltage as an operation power supply voltage. That is, the switch circuit 350 is supplied with the input voltage input from the outside as the second voltage V2 to the second power supply wiring.

  The semiconductor device 301 includes a regulator circuit 331 and a switch circuit 351. The regulator circuit 331 generates the output voltage VOUT2 using the output voltage VOUT0 output from the semiconductor device 10 as an input voltage. This output voltage VOUT2 is set to about 3V. The regulator circuit 331 includes an input voltage detection circuit (not shown) that detects that the input voltage has fallen below a preset operable voltage and enables the enable signal EN. The regulator circuit 331 uses the input voltage as the operating power supply voltage. That is, the regulator circuit 331 is obtained by adding an input voltage detection circuit to the regulator circuit 13 according to the first embodiment and operating based on the input voltage. Further, the regulator circuit 331 receives the standby shift instruction signal Scnt1 from the main power supply circuit 10 and outputs the discharge enable signal EN to the switch circuit 351. The switch circuit 351 is the same circuit as the switch circuit 15 according to the first embodiment, but uses an input voltage as an operation power supply voltage. That is, the switch circuit 351 is supplied with the input voltage input from the outside as the second voltage V2 to the second power supply wiring.

  The power supply target circuit 40 is a circuit that operates using the output voltage VOUT1 as an operating voltage, and is a functional circuit such as a microcomputer, for example. The power supply target circuit 41 is a circuit that operates using the output voltage VOUT2 as an operating voltage, and is a functional circuit such as a microcomputer, for example.

  Next, the operation of the power supply system 3 according to the fourth embodiment will be described. In the power supply system 3 according to the fourth embodiment, the semiconductor device 10 reduces the input voltage VIN to generate the output voltage VOUT0. Then, the power supply system 3 generates the output voltages VOUT1 and VOUT2 by the semiconductor devices 300 and 301 using the output voltage VOUT0 as an input voltage, and operates the power supply target circuits 40 and 41 by the output voltages VOUT1 and VOUT2.

  At this time, in the power supply system 3, since the semiconductor devices 10, 300, and 301 each have a switch circuit having the same configuration as that of the switch circuit 15 according to the first embodiment, the standby control signal Sin instructs the transition to the standby state. In this case, the output voltages VOUT0 to VOUT2 are reliably lowered. Further, in the power supply system 3, since it is not necessary to consume power for the discharge operation from the capacitor C by the switch circuit, the power consumption of the semiconductor device can be reduced.

  From the above description, in the power supply system 3, the semiconductor devices 300 and 301 that operate based on the output voltage VOUT generated by the semiconductor device 10 have a low withstand voltage without using an internal power supply generation circuit because the voltage value of the input voltage is low. A circuit can be configured with small transistors. That is, the semiconductor device 10 serves as a control unit and an internal power generation circuit common to the semiconductor devices 300 and 301. Therefore, in the power supply system 3, since it is not necessary to provide the internal power supply control generation circuit and the control circuit for the semiconductor devices 300 and 301, the number of circuit elements can be reduced. That is, in the power supply system 3, the chip size of the semiconductor devices 300 and 301 controlled by the semiconductor device 10 can be reduced. In the semiconductor devices 300 and 301 of the fourth embodiment, the connection destination of the drain of the transistor MN4 can be the external terminal Tfb as in the second embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

DESCRIPTION OF SYMBOLS 1 Power supply circuit 10, 20, 300, 301 Semiconductor device 20 Semiconductor device 11 Control part 12 Internal power generation circuit 13, 330, 301 Regulator circuit 14 Regulator control circuit 15, 350, 351 Switch circuit 16 Discharge control circuit 40, 41 Power supply Target circuit C Capacitor L Inductor Tin External terminal Tout External terminal Tfb External terminal Tsin External terminal VIN Input voltage VOUT Output voltage INV1 Inverter INV2 Inverter NL First control wiring NH Second control wiring NBG Back gate control wiring Ngate Switch control wiring

Claims (20)

A first conductivity type first MOS transistor having a source connected to a first power supply line, a gate connected to a switch control line, and a drain connected to an external terminal;
A second MOS transistor of the first conductivity type in which a source and a back gate are connected to the first power supply wiring, a drain is connected to the switch control wiring, and a first control signal is input to the gate;
The first conductivity type in which a source is connected to the switch control wiring, a drain is connected to a second power supply wiring, and a second control signal having a logic level inverted from the first control signal is input to a gate A third MOS transistor of
A fourth MOS transistor of the first conductivity type having a source connected to the switch control wiring, a drain and a back gate connected to a back gate of the third MOS transistor, and a gate connected to the second power supply wiring;
A semiconductor device.   A logic circuit that outputs the first control signal and the second control signal and operates based on a first voltage supplied to the first power supply wiring and a second voltage supplied to the second power supply wiring; The semiconductor device according to claim 1.   The semiconductor device according to claim 2, further comprising an internal power supply generation circuit that generates the second voltage based on an input voltage input from outside.   The semiconductor device according to claim 3, further comprising a regulator circuit that generates an output voltage having a preset voltage value by charging a capacitor connected to the external terminal based on the input voltage.   5. The semiconductor device according to claim 4, further comprising a standby control circuit that stops the generation of the second voltage by the internal power supply generation circuit and the operation of the regulator circuit in accordance with a standby control signal input from the outside. The external terminal is an output terminal of the regulator circuit,
The semiconductor device according to claim 4, wherein the output voltage is generated at a node connecting the inductor connected between the capacitor and the external terminal and the capacitor. The external terminal is an input terminal that feeds back the output voltage to the regulator circuit,
The semiconductor device according to claim 4, wherein the output voltage is generated at a node connecting the inductor connected between the capacitor and the external terminal and the capacitor.   The semiconductor device according to claim 2, wherein an input voltage input from the outside is supplied as the second voltage to the second power supply wiring.   9. The semiconductor device according to claim 8, further comprising a regulator circuit that generates an output voltage having a preset voltage value by charging a capacitor connected to the external terminal based on the input voltage. The external terminal is an output terminal of the regulator circuit,
The semiconductor device according to claim 9, wherein the output voltage is generated at a node connecting the inductor connected between the capacitor and the external terminal and the capacitor. The external terminal is an input terminal that feeds back the output voltage to the regulator circuit,
The semiconductor device according to claim 9, wherein the output voltage is generated at a node connecting the inductor connected between the capacitor and the external terminal and the capacitor.   The semiconductor device according to claim 1, wherein the first conductivity type is an N type.   The semiconductor device according to claim 1, wherein the first conductivity type is a P type. A regulator circuit that generates an output voltage having a preset voltage value by charging a capacitor connected to an external terminal based on an input voltage;
A switch circuit that discharges the charge of the capacitor in response to the regulator circuit stopping operation,
The switch circuit is
A first conductivity type first MOS transistor having a source connected to a first power supply line, a gate connected to a switch control line, and a drain connected to an external terminal;
A source and a back gate are connected to the first power supply wiring, a drain is connected to the switch control wiring, and a first control signal having a first logic level in response to the operation of the regulator circuit being stopped at the gate Is input to the first conductivity type second MOS transistor,
The first conductivity type in which a source is connected to the switch control wiring, a drain is connected to a second power supply wiring, and a second control signal having a logic level inverted from the first control signal is input to a gate A third MOS transistor of
A fourth MOS transistor of the first conductivity type having a source connected to the switch control wiring, a drain and a back gate connected to a back gate of the third MOS transistor, and a gate connected to the second power supply wiring;
A semiconductor device.   The switch circuit outputs the first control signal and the second control signal, and is based on a first voltage supplied to the first power supply wiring and a second voltage supplied to the second power supply wiring. The semiconductor device according to claim 14, further comprising a logic circuit that operates.   The semiconductor device according to claim 15, further comprising an internal power generation circuit that generates the second voltage based on the input voltage and supplies the second voltage to the regulator circuit and the logic circuit.   17. The semiconductor device according to claim 16, further comprising a standby control circuit that stops generation of the second voltage by the internal power supply generation circuit and operation of the regulator circuit in accordance with a standby control signal input from the outside.   The semiconductor device according to claim 15, wherein an input voltage input from the outside is supplied to the second power supply wiring as the second voltage, and the regulator circuit and the logic circuit operate based on the input voltage. The external terminal is an output terminal of the regulator circuit,
The semiconductor device according to claim 14, wherein the output voltage is generated at a node connecting the inductor connected between the capacitor and the external terminal and the capacitor. The external terminal is an input terminal that feeds back the output voltage to the regulator circuit,
The semiconductor device according to claim 14, wherein the output voltage is generated at a node connecting the inductor connected between the capacitor and the external terminal and the capacitor.

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