JP2007251194A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce short-channel effect and leakage current that accompany the miniaturization of a transistor. <P>SOLUTION: A semiconductor has transistor structures, which comprise an epitaxial Si layer formed on the main surface of a p-type silicon substrate 101, a channel region formed at least in the epitaxial layer, and a gate electrode 107 formed on the channel region via a gate insulating film 106. This transistor structures are formed across an element isolation insulating film 105, respectively, and a punch-through stopper layer 102 under the channel region contains impurity concentration higher than that of the channel region, and a source-drain diffusion 108 does not extend on the element isolation insulating film 105. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a transistor structure for forming a punch-through stopper layer mainly in a semiconductor substrate and reducing the impurity concentration of a channel region, and a manufacturing method thereof.

  In a semiconductor device having a MOS structure, high performance of a MOS transistor is a big problem. The enhancement of the performance of MOS transistors mainly indicates (1) increase in drive current, (2) reduction in threshold variation, and (3) reduction in parasitic resistance / parasitic capacitance. In order to increase the driving capability, the gate size (also referred to as channel size or gate length) has been shortened. However, there is a problem that the short channel effect increases as the channel becomes shorter.

Therefore, in order to suppress the short channel effect, efforts have been made to reduce the thickness of the gate oxide film as much as possible or to increase the impurity concentration of the channel region to about 10 ⁸ cm ⁻³ . However, because of the limitation by the maximum allowable electric field (E _max ) that can guarantee reliability, the thickness of the gate oxide film cannot be made much thinner than the maximum electric field. Further, excessively high channel impurity concentration causes saturation of drain current due to scattering of high concentration impurities in the channel region, and the problem that drain current does not increase even when the channel is shortened has become obvious. Further, with the miniaturization, high resistance of the gate electrode and parasitic resistance of the source / drain are becoming problems. Further, with the miniaturization, high resistance of the gate electrode and parasitic resistance of the source / drain are becoming problems.

  In order to solve such problems, low concentration of the channel region formed on the high concentration channel stopper layer, salicide of the source / drain, and metalization of the gate electrode have been proposed and put into practical use individually. Has been.

  For example, IEDM Technical Digest pp. 433-436 (1993) (T-Ohguro et al.) And IEEE Transactions on E1ectron Devices, Vo1.45, No.3 (March 1998), pp. 710-716 (T. Ohguro et al.) As disclosed, after element isolation such as LOCOS is performed, a high-concentration ion implantation layer is formed as a punch-through stopper in the channel region, and an epitaxial Si layer not doped with impurities is thinly formed (10 mm). There is an example in which a MOS transistor is formed as a channel region having a low impurity concentration.

  18A to 18C are a top view, a cross-sectional view in the channel length direction, and a cross-sectional view in the channel width direction of this conventional semiconductor device, respectively. As shown in FIG. 18B, an element isolation insulating film 201 is formed on a silicon substrate 101, and a punch-through stopper layer 102 into which high-concentration impurities are implanted is formed in the silicon substrate 101. An epitaxial Si layer 103 is formed on the surface of the silicon substrate 101, and a gate electrode 107 is formed on the epitaxial Si layer 103 via a gate insulating film 106. In regions other than the lower portion of the gate electrode 107, source / drain diffusion layers 108 are formed in the epitaxial Si layer 103 and the silicon substrate 101 so as to be separated from each other.

  As a method of manufacturing a semiconductor device having this transistor structure, first, an element isolation insulating film 201 is formed as an element isolation on a silicon substrate 101, and then an epitaxial Si layer 103 is formed on the silicon substrate 101 at about 600 ° C. . Thus, since the epitaxial Si layer 103 is grown after the element isolation insulating film 201 is formed, the epitaxial Si layer 103 with poor crystallinity may be formed at the end of the element isolation region. The Si layer 103 is formed in the region shown in FIG. 18A along the channel width direction, and there is a problem that leakage current occurs in the region shown in A.

  In order to avoid the occurrence of this leakage current, first, a punch-through stopper layer 102 made of high-concentration impurities is formed on the silicon substrate 101, then an epitaxial Si layer 103 is formed, and then an element isolation insulating film 201 is formed. There is a way to do it. However, since a high-temperature process is used in the element isolation process, impurities are re-diffused from the punch-through stopper layer 102, which is a high-concentration impurity layer of the silicon substrate 101, and the concentration of the low-concentration impurity layer is increased. Was causing the problem.

That is, high-temperature processes such as interfacial oxide film formation and buried oxide film densification processes during element isolation, high-temperature processes for gate oxide film formation and post-oxidation, high-temperature processes for source / drain activation, source / drain silicidation The high temperature process at the time became an obstacle, and it was difficult to form a low concentration impurity layer in the channel surface region.
IEDM Technical Digest pp. 433-436 (1993) (T-Ohguro et al.) IEEE Transactions on E1ectron Devices, Vo1.45, No.3 (March 1998), pp. 710-716 (T. Ohguro et al.) JP-A-8-213478 JP-A-7-263673

  As described above, in the conventional semiconductor device, since the epitaxial Si layer that functions as the channel layer is formed after element isolation, the Si layer having poor crystallinity extends to the element isolation end portion, and leakage current is generated. There is a problem. In order to solve this problem, a method of forming an epitaxial Si layer first and then performing element isolation is also conceivable. However, interfacial oxide film formation at the time of element isolation performed after epitaxial Si layer formation, element isolation insulating film High-temperature processes such as a densification process, a gate oxide film formation process, and a source / drain activation process become obstacles, and it is difficult to form a low concentration impurity layer in the channel surface region.

  SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device having a transistor structure capable of reducing a short channel effect and a leakage current accompanying miniaturization of the transistor, and a method for manufacturing the same. Is to provide.

  A semiconductor device according to the present invention includes a first conductivity type single crystal semiconductor layer formed on a main plane of a first conductivity type semiconductor substrate, and a second conductivity type formed at least apart from the single crystal semiconductor layer. A conductive type source region and drain region, a first conductive type channel region formed between the source region and the drain region, and a gate electrode formed on the channel region via a gate insulating film. A transistor structure including a plurality of transistor structures, wherein the transistor structures are formed with an element isolation region sandwiched between each other, wherein the first conductivity type punch-through stopper layer is provided below the source region and the drain region. The channel region in the vicinity of the interface with the gate insulating film has a lower impurity concentration than the punch-through stopper layer, and the source region and the drain region. The punch-through stopper layer is composed of a first high-concentration impurity layer and a second high-concentration impurity layer, and the first high-concentration impurity layer is a source region. The second high-concentration impurity layer partially overlaps the source region and the drain region and is selectively formed at least below the channel region, and the first high-concentration impurity layer and the second high-concentration impurity layer are formed separately from the drain region and the drain region. It is characterized in that it is in contact with the high concentration impurity layer.

  Further, another semiconductor device according to the present invention is formed on the first conductive type epitaxial semiconductor layer formed on the main plane of the first conductive type semiconductor substrate and at least spaced from the epitaxial semiconductor layer. A source region and a drain region of the second conductivity type, a channel region of the first conductivity type formed between the source region and the drain region, and a gate electrode formed on the channel region via a gate insulating film The transistor structure is formed by sandwiching an element isolation region between each other, and the first conductivity type punch-through layer is formed under the source region and the drain region. Forming a stopper layer, wherein the channel region at the interface with the gate insulating film has a lower impurity concentration than the punch-through stopper layer; and The source region and the drain region do not extend on the element isolation region, and the punch-through stopper layer includes a first high-concentration impurity layer and a second high-concentration impurity layer, and the first high-concentration impurity layer The layer is formed separately from the source region and the drain region, and the second high-concentration impurity layer partially overlaps with the source region and the drain region and is selectively formed at least under the channel region. The layer and the second high concentration impurity layer are in contact with each other.

  Desirable embodiments of the present invention are shown below.

(1) A silicide film is formed on the source region and the drain region.

(2) The gate electrode has a laminated structure of a polycrystalline Si film doped with impurities and a metal film or a silicide film formed on the polycrystalline Si film.

(3) In (2), a silicide film is formed on the source region and the drain region.

(4) The high-concentration impurity layer includes a first high-concentration impurity layer and a second high-concentration impurity layer, and the first high-concentration impurity layer is formed separately from the source region and the drain region. The high concentration impurity layer 2 partially overlaps with the source region and the drain region, and is selectively formed at least under the channel region.

(5) The high concentration impurity layer is formed separately from the source region and the drain region.

(6) The source region and the drain region are a first portion formed in the epitaxial semiconductor layer and a second portion further selectively formed on the source region and the drain region of the first portion on the epitaxial semiconductor layer. It consists of parts.

(7) The high concentration impurity layer exists in at least a part of the channel, and a well layer having the same conductivity type as the high concentration impurity layer is formed under the high concentration impurity layer so as to be in contact with the high concentration impurity layer. The

(8) The silicide film is cobalt silicide, titanium silicide, palladium silicide (PdSi ₂ ), platinum silicide (PtSi), iridium silicide (IrSi ₃ ), or the like.

  Further, another method of manufacturing a semiconductor device according to the present invention includes a step of forming a first conductivity type high concentration impurity layer on at least a part of a first conductivity type semiconductor substrate, and a main plane of the semiconductor substrate. Forming a first conductive type semiconductor layer by epitaxial growth, forming a groove by selectively removing the semiconductor layer and the semiconductor substrate, and embedding an element isolation insulating film in the groove; Forming a gate insulating film and a gate electrode selectively on the semiconductor layer; and forming a source region and a drain region of the second conductivity type using the gate electrode as a mask, and forming the high-concentration impurity layer The subsequent process is performed under conditions of 700 ° C. or less, the high-concentration impurity layer is formed under the source region and the drain region, and the channel region in the vicinity of the interface with the gate insulating film. The impurity concentration is lower than that of the high-concentration impurity layer, and the high-concentration impurity layer includes a first high-concentration impurity layer and a second high-concentration impurity layer, and the first high-concentration impurity layer includes a source region and a drain region. The second high-concentration impurity layer partially overlaps with the source region and the drain region and is selectively formed at least under the channel region, and the first high-concentration impurity layer and the second high-concentration layer are formed. It is characterized by being in contact with the impurity layer.

  Desirable embodiments of the present invention are shown below.

(1) After forming the trench and before embedding the element isolation insulating film, an oxide film using radical oxidation is formed so as to cover the trench surface.

(2) After forming the semiconductor substrate and before forming the semiconductor layer, the natural oxide film formed on the surface of the semiconductor substrate is removed using hydrogen radicals under conditions of 700 ° C. or lower.

(3) The source region and the drain region are formed by cooling the semiconductor substrate to a low temperature below room temperature and performing ion implantation.

(4) For activation of the source region and the drain region, a short-time rapid heat treatment step of milliseconds or less at a temperature of 700 ° C. or higher is used.

(5) A step of performing heat treatment using an excimer laser is used to activate the source / drain impurity layer.

(6) A step of forming an oxide film on the surface of the semiconductor layer using a radical oxidation method is used for forming the gate insulating film.

(7) After forming the groove and before embedding the element isolation insulating film, an oxide film is formed using radical oxidation under conditions of 700 ° C. or less so as to cover the surface of the groove.

(8) A silicide film is formed in a self-aligned manner in the source region and the drain region formed in the semiconductor substrate.

(9) The silicide film is cobalt silicide, titanium silicide, palladium silicide (PdSi ₂ ), platinum silicide (PtSi), iridium silicide (IrSi ₃ ), or the like.

(10) A silicide film is formed on the surface of the gate electrode, and a silicide film is also formed on the source region and the drain region.

(Function)
In the present invention, due to the structure of the MOS transistor in which the epitaxial semiconductor layer does not extend over the element isolation region, there is no semiconductor layer with poor crystallinity at the element isolation end portion, so that the generation of leakage current can be reduced. Further, the resistance value of the gate electrode can be reduced by adopting a stacked structure in which a silicide film or a metal film is formed on a polycrystalline Si film doped with impurities. In addition, since the channel region in the vicinity of the interface with the gate insulating film is formed with a lower impurity concentration than the semiconductor substrate, it is possible to prevent the drain current from decreasing while suppressing the short channel effect.

  In addition, by realizing the low temperature (<700 ° C.) of the steps after the formation of the high concentration impurity layer in the total process of the MOS transistor formation step, it is possible to form a channel lower region composed of the high concentration impurity layer. . That is, by reducing impurity diffusion from the high-concentration impurity layer to the channel region when forming the channel region, the channel region in the vicinity of the interface with the gate insulating film can be kept at a lower impurity concentration than the semiconductor substrate. The channel effect can be suppressed. By manufacturing a semiconductor device by a low-temperature process of 700 ° C. or lower, it is possible to suppress diffusion of impurities from the high-concentration impurity layer to the channel region, according to IEDM Technical Digestpp. 433-436 (1993) (T-Ohguro et al) It is clear as disclosed in Transactions on E1ectron Devices, Vo1.45, No.3 (March 1998), pp. 710-716 (T. Ohguro et al.).

  Furthermore, a semiconductor layer having poor crystallinity extending on the element isolation insulating film formed by forming the element isolation insulating film first by performing a process of forming the element isolation insulating film after the formation of the channel region by epitaxial growth. Can be prevented.

  Further, by using the low temperature process in this manner, extension of the diffusion layer depth of the source region and the drain region can be prevented, so that a transistor structure in which the short channel effect is suppressed can be realized.

  According to the semiconductor device of the present invention, since the channel region in the vicinity of the interface with the gate insulating film has an impurity concentration lower than that of the semiconductor substrate, it is possible to prevent the drain current from decreasing while suppressing the short channel effect. Further, since the source / drain region does not extend over the element isolation region, there is no semiconductor layer with poor crystallinity in the element isolation portion, and the leakage current can be reduced.

  Further, according to the method for manufacturing a semiconductor device according to the present invention, by using a low temperature process of 700 ° C. or lower, the channel region is kept at a low impurity concentration while the source region and the drain region are formed with a shallow depth. Diffusion of impurities from the high concentration impurity region formed in the lower portion of the region can be suppressed. In addition, since the element isolation insulating film is formed after the high concentration impurity layer is formed, a semiconductor device in which the source region and the drain region do not extend over the element isolation region can be manufactured.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
1A and 1B are diagrams showing an overall configuration of a semiconductor device (single transistor) according to a first embodiment of the present invention, where FIG. 1A is a top view and FIG. 1B is a cross-sectional view taken along line AA ′ in the channel length direction. (C) is a BB 'cross-sectional view cut in the channel width direction. Hereinafter, the case of an n-channel transistor will be described.

A p-well (not shown) is formed in the transistor region of the p-type silicon substrate 101 having an impurity concentration of about 5 × 10 ¹⁵ cm ^−3, and 2 × 10 ¹⁸ cm ⁻³ in the transistor channel formation region in the p-well. A punch-through stopper layer 102 into which a high-concentration impurity having a moderate concentration is introduced is formed. On the punch-through stopper layer 102, an epitaxial Si layer 103 not doped with impurities is formed with a film thickness of, for example, about 20 nm. A region where the silicon substrate 101 and the epitaxial Si layer 103 are dug and a transistor is not formed is an STI (Shallow Trench Isolation) element isolation region, and the element isolation region is interposed via an oxide film 104. Thus, an insulating film 105 is embedded and formed.

A part of the epitaxial Si layer 103 operates as a channel region. In order to control the threshold voltage (V _th ) of the transistor, a p-type channel impurity layer (not shown) having an impurity concentration of about 5 × 10 ¹⁶ cm ⁻³ is mainly formed in the channel region of the epitaxial Si layer 103 as necessary. Only selected formed. Note that when the impurity concentration is increased, a decrease in channel current due to impurity scattering becomes a problem. Therefore, the impurity concentration in the channel region does not exceed about 1 × 10 ¹⁷ cm ⁻³ . The impurity concentration of the entire channel region is higher than that of the silicon substrate 101, but the impurity concentration in the vicinity of the interface with the gate insulating film 106 is lower than that of the silicon substrate 101.

In addition, a gate electrode 107 made of metal (for example, a TiN film, a Ru film, a W film, or a laminated film thereof) is formed through the gate insulating film 106, and as an impurity diffusion layer formed using the gate electrode 107 as a mask, An n-type diffusion layer 108a having an impurity concentration of about 5 × 10 ¹⁹ cm ⁻³ and a diffusion layer depth of about 0.04 μm, and an n ⁺ type diffusion having an impurity concentration of about 5 × 10 ²⁰ cm ⁻³ and a diffusion layer depth of about 0.08 μm. A layer 108b is formed on each side of the gate electrode 107 (hereinafter, the diffusion layers 108a and 108b are collectively referred to as a source / drain diffusion layer 108). Further, a silicide film 110 (for example, TiSi ₂ , CoSi ₂ , PtSi, Pd ₂ Si, IrSi ₃ , RhSi, etc.) is formed on the surface of the source / drain diffusion layer 108 using a sidewall film 109 formed on the sidewall of the gate electrode 107. Are formed in a self-aligning manner.

  Further, an interlayer insulating film 111 is formed so as to cover the gate electrode 107, the silicide film 110, and the like. The contact plug 112 connected to the silicide film 110 through the interlayer insulating film 111, and the contact plug 112 are connected. A wiring 113 is formed, and a transistor structure is realized.

  A manufacturing process of the transistor having the above-described structure will be described with reference to process cross-sectional views in FIGS. 2A to 8A are plan views of FIG. 1A, and FIG. 8B is a manufacturing process diagram corresponding to the A-A ′ sectional view of FIG.

First, as shown in FIG. 2, in the transistor channel region of the (100) p-type silicon substrate 101 having an impurity concentration of about 5 × 10 ⁻⁵ cm ⁻³ , for example, ap having a peak impurity concentration of about 4 × 10 ¹⁷ cm ^−3. A well (not shown) is formed, for example, by implanting boron at about 260 KeV and 2 × 10 ¹³ cm ⁻² .

Next, the punch-through stopper layer 102 in which high-concentration impurities are introduced into the transistor / channel formation region in the p-well is used as a mask with a resist film (not shown) as a mask, for example, using boron or the like at a peak concentration by ion implantation. It is formed so as to have an impurity distribution of about 2 × 10 ¹⁸ cm ⁻³ . At this time, an oxide film 121 such as SiO _{2 having a} thickness of about 8 mm is formed on the surface of the Si substrate 101 to prevent contamination of the Si substrate 101 from the resist. For activation of the ion implantation layer at this time, a p-type impurity layer having a steep profile is formed by using RTA (Rapid Thermal Anneal) in N ₂ at 900 ° C. for 5 minutes, for example.

Next, as shown in FIG. 3, first, the oxide film 121 is removed, the natural oxide film is further removed, the surface of the Si substrate 101 is exposed, and then an epitaxial Si layer 103 is grown on the entire surface. The film forming temperature is, for example, about 700 ° C., and the film thickness of the epitaxial Si layer 103 is, for example, about 20 nm. For removal of the natural oxide film, a method of treating at about 700 ° C. using hydrogen radical (H ^* ) or the like in a furnace of an epitaxial film growth apparatus may be used.

  By this epitaxial Si growth process and subsequent thermal process, re-diffusion of impurities from the punch-through stopper layer 102 previously formed on the surface of the Si substrate 101 to the epitaxial Si layer 103 occurs. For this reason, in order to form a low impurity channel region, the formation of the epitaxial Si layer 103 and the subsequent thermal process are made as low as possible.

Next, a trench 124 of about 0.2 μm, for example, is formed in the epitaxial Si layer 103 and the Si substrate 101 using, for example, reactive ion etching (RIE method). At this time, a buffer oxide film 122 (for example, a film thickness of 8 nm) and a silicon nitride film (Si ₃ N ₄ ) 123 (for example, a film thickness of 100 mm) are stacked and formed as an etching mask material, and a resist (not shown) is used as a mask. The nitride film 123, the buffer oxide film 122, the epitaxial Si layer 103, and the Si substrate 101 are processed.

  Next, etching / damage or the like of the inner wall of the groove 124 is cleaned and removed by using ashing and wet processing to expose the surface of the Si substrate 101 in the groove 124. Further, the formation of the buffer oxide film 122 at this time uses an oxygen radical oxidation method capable of forming a high-quality oxide film at a low temperature of about 700 ° C., for example. Radical oxidation is a method of forming a high-performance silicon oxide film at a low temperature (about 700 ° C.) by supplying an oxidation source gas whose main component is an oxygen atom radical to the silicon substrate 1 and oxidizing the Si surface. It is. Next, an oxide film 104 having a thickness of about 7 nm is formed using a radical oxidation method capable of forming a good quality oxide film at a low temperature on the side and bottom surfaces of the trench 124.

  Next, as shown in FIG. 4, an insulating film 105 such as a TEOS oxide film is buried in the trench 124 through the oxide film 104 to form a so-called trench type element isolation layer (STI: Shal1ow Trench Iso1ation). Specifically, after depositing a TEOS oxide film of about 300 nm on the entire surface by a CVD method using a film formation temperature of 650 ° C., the CVD oxide film is densified in a radical oxidation atmosphere of about 700 ° C., for example. Is flattened by a CMP (Chemical Mechanical Po1ishing) method. At this time, the insulating film 105 is flatly embedded in the groove 124 using a difference in CMP rate from the silicon nitride film 123. Further, the silicon nitride film 123 is wet removed with, for example, hot phosphoric acid, and then the buffer oxide film 122 is peeled off with a hydrofluoric acid solution to expose the surface of the epitaxial Si layer 103.

  Next, as shown in FIG. 5, a gate insulating film 106 (oxide film) having a thickness of, for example, about 5 mm is formed on the exposed surface of the epitaxial Si layer 103 by using, for example, a radical oxidation method of about 700 ° C. By forming the gate insulating film 106 by radical oxidation, an oxide film with less unevenness on the Si surface can be realized. Therefore, in combination with channel impurity concentration reduction (i-layer channelization) described later, channel interface scattering and impurity scattering It is possible to realize a MOS transistor channel in which channel mobility is hardly reduced by the above. In addition, in radical oxidation, only a certain film thickness is formed at a certain temperature, and therefore, there is a feature that variation in the film thickness of the oxide film within the wafer surface and between chips can be reduced.

A Ta ₂ O ₅ (tantalum oxide) film may be used instead of the gate insulating film 106 made of SiO ₂ . The Ta ₂ O ₅ film has a relative dielectric constant (ε _r ) larger than that of SiO ₂ (ε _r = 3.9), which is about 20 to 27. For this reason, the oxide film equivalent film thickness when the film thickness is converted into an oxide film may be 2 mm or less. Specifically, in order to reduce the interface state density with the interface of the epitaxial Si layer 103, for example, a SiO ₂ film system film of about 1 nm is formed at the interface of the epitaxial Si layer 103, and then a Ta ₂ O ₅ film is formed thereon. A laminated gate insulating film structure can be used.

If necessary, channel ion implantation is performed only in a channel region including a desired epitaxial Si layer 103 using a resist film (not shown) as a mask. In the case of an n-channel transistor, in order to set a threshold value (V _th ) of about 0.7 V, for example, boron (B ⁺ ) is ion-implanted at about 10 KeV, 5 × 10 ¹² cm ⁻² and only in the channel region. A p-type channel impurity layer (not shown) is selectively formed. This process, through the buffer oxide film such as SiO ₂ film (not shown) so performing ion implantation, after stripping the buffer oxide film, SiO ₂ film (not shown) is formed as a sacrificial oxide film Further, ion implantation may be performed through this SiO ₂ film.

  The channel impurity layer may be activated by this additional ion implantation after the channel ion implantation, for example, by heat treatment at 750 ° C. for about 10 seconds using, for example, RTA. Since the thermal process after the formation of the additional channel impurity layer requires a low temperature (desirably 700 ° C. or less), the temperature of the semiconductor device during the ion implantation is lowered for ion implantation of the channel layer, that is, the epitaxial Si layer 103. The crystal damage at the time of ion implantation is reduced by using a so-called “cryo ion implantation method” which is performed under control so that activation can be performed at a low temperature. The channel impurity layer may be activated by activation at a low temperature of about 700 ° C. with an excimer laser.

  Next, for example, a polycrystalline Si film doped with an n-type impurity (film thickness of about 200 mm) is deposited on the entire surface, and patterning is performed using a resist film (not shown) as a mask to form the gate electrode 107.

Next, as shown in FIG. 6, using the gate electrode 107 as masks n ^- hardly enters the ion implantation damage to the type of the source-drain diffusion layer 108a for example an epitaxial Si layer 103 "low-temperature ion implantation (cryo ion implantation Method) ”. At this time, in order to alleviate the electric field concentration on the side wall and bottom corner of the gate electrode 107, the gate electrode 107 is oxidized to a thickness of about 5 nm by using, for example, radical oxidation or low temperature RTO (Rapid Thermal Oxidation). A film (not shown) may be formed on the sidewall or bottom corner of the gate electrode 107.

The shallow source / drain diffusion layer 108a may be formed by solid phase diffusion instead of ion implantation. As the ion implantation conditions, for example, phosphorus (P ⁺ ) ions are implanted at about 40 KeV and 4 × 10 ¹³ cm ⁻² to form the source / drain diffusion layer 108a. Of course, ion implantation of arsenic (As) or the like may be performed.

Next, as shown in FIG. 7, after depositing by CVD a SiO ₂ film on the entire surface, subjected to the entire surface of the RIE, leaving the SiO ₂ film on the side wall of the gate electrode 107 pattern, leaving the side wall of the so-called "SiO ₂ ”To form a sidewall film 109 film having a thickness of about 20 nm on the sidewall of the gate electrode 107. Thereafter, for example, arsenic (As ⁺ ) ions are implanted at about ¹⁵ KeV and 5 × 10 ¹⁵ cm ⁻² to form an n ⁺ -type source / drain diffusion layer 108b, and a so-called gate extension structure is formed together with the diffusion layer 108a. A held source / drain diffusion layer 108 is formed.

Here, a gate extension structure is used, but a so-called single source / drain system having only an n ⁻ type diffusion layer or only an n ⁺ type diffusion layer may be used. The depth of each diffusion layer is determined by the thermal activation of the final ion implantation layer at a temperature of 700 ° C. or lower, so that the n ⁻ -type diffusion layer 108a has a junction depth X _{j of} about 0.05 μm, n ⁺ The ion implantation conditions and the activation conditions are controlled so that X _j of the type diffusion layer 108b is about 0.06 μm. For this low-temperature activation, it is desirable to perform heat treatment using an excimer laser, but it is also possible to perform high-speed heat treatment for a short time at about 850 ° C. for milliseconds. Further, heat treatment using an excimer laser and rapid heat treatment can be used in combination. Thus, by performing low-temperature ion implantation and activation, the source / drain diffusion layer 108 can be highly concentrated and shallow.

Next, a silicide film 110 such as TiSi ₂ , CoSi ₂ , PtSi, Pd ₂ Si, IrSi ₃ , and RhSi is formed at a low temperature (<700 ° C.) on the exposed surface of the source / drain diffusion layer 108. The silicide film 110 is formed on the source / drain diffusion layer 108 in a self-aligning manner. Thereby, the specific resistance of the source / drain diffusion layer 108 can be reduced to, for example, about <50 μΩcm. In particular, Pd ₂ Si is effective for reducing the contact resistance with the p ⁺ -type diffusion layer. Thus, by introducing a new silicide material that can form silicide at a low temperature, such as Pd ₂ Si, the contact resistance of the p ⁺ -type diffusion layer can be lowered, so that the parasitic resistance of the source / drain diffusion layer 108 is small. A MOS transistor can be realized.

Next, as shown in FIG. 8, the entire surface by CVD and interlayer insulating film 111, for example, 300nm approximately deposit consisting of SiO _2, for example, performing a radical oxidation atmosphere at about 700 ° C. For example about 3 minutes densified. This thermal process may also be performed to activate the ion implantation layer of the source / drain diffusion layer 108. When the depth (X _j ) of the source / drain diffusion layer 108 is desired to be suppressed, the densification temperature is lowered to about 700 ° C., or short-time annealing is performed at about 850 ° C. for about ms (milliseconds) using the RTA method. The ion implantation layer may be activated by using them together. Thereafter, the entire surface of the interlayer insulating film 111 is planarized by CMP, and the surface of the interlayer insulating film 111 is planarized.

  Next, a contact hole 125 is formed using a resist film (not shown) and the RIE method so that the silicide film 110 is exposed. Thereafter, as shown in FIGS. 1A and 1B, a contact plug 112 is formed in the contact hole 125, and a wiring 113 made of Al is further formed. Then, a passivation film (not shown) is deposited on the entire surface, and the basic structure of the transistor is completed. At this time, the contact plug 112 may be a W (tungsten) film, an Al (aluminum) film, a TiN (titanium nitride) film / Ti (titanium) film, or a laminated film thereof.

The reason for manufacturing a semiconductor device by a low-temperature process at 700 ° C. or lower will be described with reference to FIG. FIG. 9 is a graph showing the dependence of the source / drain diffusion layer depth on the RTA temperature after formation of the diffusion layer. The horizontal axis represents the heating temperature, and the vertical axis represents the diffusion layer depth. The case where boron (B ⁺ ) ions are performed at about 1 keV and about 3.0 × 10 ¹⁴ cm ⁻² is shown. As shown in FIG. 9, at a temperature of 700 ° C. or lower, the source / drain diffusion layer depth can be as shallow as 0.05 μm regardless of whether the annealing time is 1 minute or 10 minutes. When heated at a temperature, expansion of the source / drain diffusion layer in the heating process increases the depth of the diffusion layer, and the short channel effect cannot be suppressed. On the other hand, when the low temperature process of 700 ° C. or lower is used, the diffusion layer can be expanded shallowly and the short channel effect can be suppressed.

  In addition, it is possible to suppress the diffusion of impurities from the punch-through stopper layer 102 to the channel region by manufacturing a semiconductor device by a low-temperature process of 700 ° C. or lower, as described in IEDM Technical Digest pp. 433-436 (1993) (T- Ohguro et al.) And IEEE Transactions on E1ectron Devices, Vo1.45, No. 3 (March 1998), pp. 710-716 (T. Ohguro et al.).

  As shown in the above steps, in the step after the formation of the punch-through stopper layer 102, the oxidation of the STI Si sidewall, the densification of the CVD oxide film 104, or the like is performed by using radical oxidation, or the sacrificial oxidation. A transistor structure realized in a completely low temperature process realized by introducing a low temperature oxide film forming method such as gate oxidation, and the like, and an epitaxial Si layer 103 from a punch-through stopper layer 102 of a high concentration impurity formed in the silicon substrate 101 Impurity diffusion into the channel region can be suppressed, and a low impurity concentration in the channel region in the vicinity of the interface with the gate insulating film can be realized. Thereby, it is possible to prevent the drain current from decreasing while suppressing the short channel effect. This is largely due to the fact that the formation of a high-quality oxide film can be performed at a low temperature using the radical oxidation method and the low-temperature activation can be achieved using the cryo-ion implantation method for the ion implantation method. In addition, since the temperature of the transistor formation process can be reduced, for example, a high dielectric film can be easily applied to the gate insulating film 106. Thereby, the gate insulating film 106 can be further thinned.

  Further, by using such a low temperature process, the extension of the depth of the source / drain diffusion layer 108 can be prevented, so that a transistor structure in which the short channel effect is suppressed can be realized.

  Further, by forming the silicide film 110 that can be formed by the low temperature process on the source / drain diffusion layer 108, the contact resistance can be reduced, and a MOS transistor having a low parasitic resistance of the source / drain diffusion layer 108 can be realized.

In addition, since the radical oxidation method is used to form the gate insulating film 106, the maximum electric field (E _max ) that can guarantee the 10-year reliability of the gate insulating film 106 becomes larger than that of a normal thermal oxide film, so The thickness of the film 106 can be further reduced as compared with a normal thermal oxide film. In addition, since an oxide film with less surface irregularities can be realized, a MOS transistor channel with less deterioration of channel mobility due to channel interface scattering and impurity scattering can be realized in combination with channel impurity concentration reduction. In addition, since radical oxidation forms only a certain thickness at a certain temperature, the oxide film thickness variation within the wafer surface of the oxide film and between chips can be reduced.

  In addition, since the STI is performed after the epitaxial Si layer 103 is formed, the epitaxial Si layer 103 is not formed so as to protrude on the element isolation (STI), and thus an increase in leakage current in the channel width direction can be suppressed. Further, since the above-described process can follow the conventional planar transistor manufacturing process, the transistor performance can be improved without complicating the process / structure.

(Second Embodiment)
FIG. 10 is a cross-sectional view showing the overall configuration during the manufacturing process of the semiconductor device according to the second embodiment of the present invention. The manufacturing process of the semiconductor device of the present embodiment is almost the same as that in FIGS. 2 to 8, and detailed description thereof is omitted. FIG. 10 shows only a diagram corresponding to the AA ′ sectional view of FIG.

  In the first embodiment, an example in which a polycrystalline Si film doped with n-type or p-type impurities as the gate electrode is used for the gate electrode 107 has been described. However, in this embodiment, the gate electrode 107 has a gate electrode structure. The present invention relates to a structure in which a silicide film 131 is selectively formed on the surface of a gate electrode 107 in order to reduce wiring resistance. Since other configurations are the same as those in the first embodiment, the same reference numerals are given and detailed descriptions thereof are omitted.

The silicide film 131 can be formed simultaneously with the silicide film 110 formed on the source / drain diffusion layer 108. That is, when the surface of the source / drain diffusion layer 108 is exposed, the surface of the polycrystalline Si layer of the gate electrode 107 may be exposed at the same time. As the material of the silicide film 131, as described in the first embodiment, a film made of TiSi ₂ , CoSi ₂ , PtSi, Pd ₂ Si, IrSi ₃ , RhSi or the like is used. The silicide film 131 is formed by a low temperature process (<700 ° C.). Other processes are the same as those in the first embodiment.

  Thus, by selectively forming the silicide film 131 on the surface of the gate electrode 107 as the gate electrode structure, the wiring resistance of the gate electrode structure can be reduced.

(Third embodiment)
FIG. 11 is a diagram showing an overall configuration in the course of the manufacturing process of the semiconductor device according to the third embodiment of the present invention. The manufacturing process of the semiconductor device of this embodiment is almost the same as that in FIGS. 2 to 8, and detailed description thereof is omitted. FIG. 7A corresponding to the AA ′ cross-sectional view of FIG. (B) is a cross-sectional view taken along the line (corresponding to the BB ′ cross-sectional view in FIG. 1).

The present embodiment relates to a structure in which a distance d is provided between most of the bottom of the source / drain diffusion layer 108 and the punch-through stopper layer 102. For example, the distance d is about 0.01 μm. In order to realize this structure, for example, the peak impurity concentration position (R _p ) of the first punch-through stopper layer 141 (corresponding to the punch-through stopper layer 102 of the first embodiment) is set on the silicon substrate 101 in the first embodiment. This can be achieved by forming the film about 0.01 μm lower than the above case.

Further, the peak impurity concentration position (R _p ) of the first punch-through stopper layer 141 is formed below the punch-through stopper layer 102 of the first embodiment, thereby reducing the ability to suppress the short channel effect. In such a case, the second punch-through stopper layer 142 may be selectively formed in the channel region immediately below the gate electrode 107 as shown in FIG.

  The manufacturing process of the semiconductor device according to this embodiment is the same as that of the first embodiment. In this embodiment, the second punch-through stopper layer is formed immediately before or after the formation of the first punch-through stopper layer 141. The difference is that 142 is formed. The second punch-through stopper layer 142 is formed by selectively implanting ions into a desired region on the surface of the silicon substrate 101 using a resist film (not shown) as a mask. Alternatively, after the epitaxial Si layer is formed, the resist film mask may be formed by ion implantation.

In any case, the surface of the epitaxial Si layer 103 in the channel region becomes a low concentration region of about 5 × 10 ¹⁶ cm ⁻³ or less, and a high concentration punch-through stopper layer is provided immediately below the channel region so that the short channel effect can be reduced. What is necessary is just to become the structure in which 142 is formed.

  The reason why the distance d is provided between most of the bottom of the source / drain diffusion layer 108 and the punch-through stopper layer 141 will be described below.

  In the first embodiment, the channel region of the transistor is formed by the epitaxial Si layer 103, and the high-concentration impurities are slightly re-diffused from the punch-through stopper layer 102 formed on the silicon substrate 101 to the epitaxial Si layer 103 by a subsequent thermal process. Designed to be.

  However, the high concentration punch-through stopper layer 102 and the high concentration source / drain diffusion layer 108 in the silicon substrate 101 are in contact with each other at the bottom of the source / drain diffusion layer 108. In such a structure, a high-concentration pn junction is formed, and the junction leakage current is considered to increase from each concentration relationship, and it is expected that it cannot be used depending on the device.

  Thus, by adopting a structure in which the distance d is provided between the source / drain diffusion layer 108 and the first punch-through stopper layer 141 as in the present embodiment, re-diffusion of high-concentration impurities hardly occurs and the pn junction is not formed. Formation can be prevented and junction leakage current can be reduced. Further, since the second punch-through stopper layer 142 is formed below the low concentration channel region below the gate electrode 107, the short channel effect can be suppressed.

In addition, if the short channel effect can be suppressed without providing the second punch-through stopper layer 142, the second punch-through stopper layer 142 can be omitted. A cross-sectional view along the line AA ′ in this case is as shown in FIG. The distance d ₂ between the source / drain diffusion layer 108 and the first punch-through stopper layer 141 can be set to about 0.01 μm to 0.005 μm.

  Even with such a structure, the source / drain junction leakage current can be reduced because the high-concentration pn junction area of the source / drain diffusion layer 108 and the first punch-through stopper layer 141 can be reduced.

(Fourth embodiment)
FIG. 13 is a diagram showing an overall configuration in the course of the manufacturing process of the semiconductor device according to the fourth embodiment of the present invention. The manufacturing process of the semiconductor device of the present embodiment is almost the same as that in FIGS. 2 to 8, and detailed description thereof is omitted. FIG. 13 shows a diagram corresponding to the AA ′ cross-sectional view of FIG.

  In the first embodiment, an example in which normal polycrystalline Si is used for the gate electrode 107 will be described. In the second embodiment, a silicide film 131 is formed on the polycrystalline Si gate electrode 107 in order to reduce the wiring resistance of the gate electrode 107. An example was explained. The present embodiment relates to a structure in which the gate electrode structure is changed in order to reduce the wiring resistance of the gate electrode 107.

  As shown in FIG. 13, a silicide film 152 is formed to a thickness of, for example, 75 nm on a polycrystalline Si layer (for example, the film thickness is about 75 nm) 151 doped with an n-type or p-type impurity, and further, for example, The SiN film 153 is formed to 20 nm, for example.

  Next, the SiN film 153 is patterned using a resist film (not shown) and the RIE method, and then the underlying silicide film 152 and the polycrystalline Si film 151 are patterned using the SiN film 153 to form a stacked gate electrode structure. To realize.

The type of the silicide film 152 may be the same as or different from that of the silicide film 110 on the source / drain diffusion layer 108. As the silicide, for example, TiSi ₂ , WSi ₂ or the like is desirable. Further, a metal film can be used instead of the silicide film 152. In this case, 152 may be, for example, a W / WN laminated film in which a W (tungsten) film or a WN (tungsten nitride) film is thinly formed (about 3 nm) at the interface with the polycrystalline Si layer 151.

  Further, the polycrystalline Si layer 151 at the interface of the gate insulating film 106 is omitted, and a metal film such as an Al film / TiN film, W film / TiN film, Ru film / TiN film is formed directly on the gate insulating film 106. May be. Since the oxide film formed by radical oxidation is a dense and high-quality film, even if the metal film is formed in direct contact with the gate insulating film 106, diffusion of the metal material into the gate insulating film 106 can be reduced. it can. With such a structure, the wiring resistance of the gate electrode can be reduced.

(Fifth embodiment)
14 and 15 are diagrams showing an overall configuration in the course of the manufacturing process of the semiconductor device according to the fifth embodiment of the present invention. The manufacturing process of the semiconductor device of this embodiment is almost the same as that in FIGS. 2 to 8, and detailed description thereof is omitted. FIGS. 14 and 15 are diagrams corresponding to the AA ′ cross-sectional view of FIG.

  As shown in FIG. 14, in this embodiment, a thin epitaxial Si layer 161 having a thickness of, for example, about 20 nm is formed on the source / drain diffusion layer 108 by selective epitaxial Si growth. The source / drain diffusion layer 108 includes only the diffusion layer 108a in the first embodiment, and the diffusion layer 108b is not formed.

  A method for manufacturing the semiconductor device according to the embodiment will be described below.

First, as in FIGS. 2 to 6 of the first embodiment, the source / drain diffusion layer 108a is formed in the epitaxial Si layer 103 using the gate electrode 107 as a mask. Next, as shown in FIG. 14, after forming the n ⁻ -type source / drain diffusion layer 108, the epitaxial Si layer 161 is formed on the source / drain diffusion layer 108, and the n ⁺ -type source / drain diffusion layer 108 is formed on the epitaxial Si layer 161. Perform impurity doping of the mold.

  The epitaxial Si layer 161 may be formed on the source / drain diffusion layer 108, and then the source / drain diffusion layer 108 may be ion-implanted, or the epitaxial Si layer 161 may be doped with high-concentration impurities. The source / drain diffusion layer 108 may be formed from the layer 161 by a re-diffusion method. In the case of the present embodiment, the source / drain diffusion layer 108 and the punch-through stopper layer 102 may overlap as in the first embodiment, or may be separated as shown in FIG. Further, a double punch-through stopper structure using the second punch-through stopper layer 142 as shown in FIG. 15 may be used.

  In the structure of the present embodiment, when the selective epitaxial Si layer 161 is formed, a thermal process such as pretreatment for removing a natural oxide film on the surface of the epitaxial Si layer 161 is performed at a temperature as low as about 700 ° C. by using a hydrogen radical atmosphere. In addition, since the Si epitaxial growth itself can be lowered to about 700 ° C., the thermal influence on the re-diffusion of impurities in the punch-through stopper layer 102 and the source / drain diffusion layer 108 can be suppressed. Further, when a high dielectric film is used for the gate insulating film 106 and a metal is used for the gate electrode 107, the thermal influence can be suppressed.

  The reason why the epitaxial Si layer 161 is formed as in this embodiment will be described below.

Although it is effective to suppress the short channel effect of the transistor to make the depth of the source / drain diffusion layer 108 as shallow as possible, the source / drain diffusion layer 108 is extremely shallow, for example, at a junction depth of about X _j = 0.001 μm. There is a problem that the diffusion resistance of the drain becomes large. In addition, in the extremely shallow source / drain diffusion layer 108, it may be difficult to form the silicide film 110 formed on the source / drain diffusion layer 108 in a self-aligned manner.

  Therefore, the parasitic resistance of the source / drain diffusion layer 108 can be reduced by forming the selective epitaxial Si layer 161 in the source / drain diffusion layer 108 at a low temperature in a self-aligned manner as in this embodiment.

As in the first to fourth embodiments, an n ⁺ -type source / drain layer 108b may be formed in addition to the source / drain diffusion layer 108a.

(Sixth embodiment)
FIG. 16 is a diagram showing an overall configuration in the course of the manufacturing process of the semiconductor device according to the sixth embodiment of the present invention. The manufacturing process of the semiconductor device of the present embodiment is almost the same as that in FIGS. 2 to 8, and detailed description thereof is omitted. FIG. 16 shows a diagram corresponding to the AA ′ sectional view of FIG.

  In the third embodiment, as an example in which the source / drain diffusion layer 108 and the punch-through stopper layer are separated from each other, the first and second punch-through stopper layers 141 and 142 are used. The present invention relates to a method for preventing the second punch-through stopper layer 142 from contacting the source / drain diffusion layer in a large area by suppressing the short channel effect using the layer 142.

In this embodiment, the first punch-through stopper layer 141 used in the third embodiment is omitted, and only the second punch-through stopper layer 142 constitutes a punch-through stopper layer. Further, a p-well layer 171 is formed at a distance d ₃ from the source / drain diffusion layer 108 instead of the first punch-through stopper layer.

  With such a structure, the leakage current between the source / drain diffusion layer 108 and the silicon substrate 101 can be reduced, and the area of the second punch-through stopper layer 142 formed before the formation of the epitaxial Si layer 103 can be reduced. Therefore, the undoped epitaxial Si layer 103 can be formed stably.

(Seventh embodiment)
FIG. 17 is a diagram showing an overall configuration in the course of the manufacturing process of the semiconductor device according to the seventh embodiment of the present invention. The manufacturing process of the semiconductor device of the present embodiment is almost the same as that in FIGS. 2 to 8, and detailed description thereof is omitted. FIG. 17 shows a diagram corresponding to the AA ′ sectional view of FIG.

The semiconductor device according to the present embodiment is the same as the third embodiment in that punch-through is suppressed by the first and second punch-through stopper layers 141 and 142, but both stopper layers 141 and 142 are provided. Both are different in that they are selectively formed in an arbitrary shape in the transistor formation region. That is, the first and second punch-through stopper layers 141 and 142 are formed near and on the surface of the silicon substrate 101. Specifically, the first punch-through stopper layer 141 has a slightly larger area in a region deeper than the second punch-through stopper layer 142 and is formed with a distance d _{4 from} the source / drain diffusion layer 108.

  As described above, the punch-through stopper is composed of the two punch-through stopper layers 141 and 142, so that the distance between the source / drain diffusion layer 108 and the high-concentration impurity layer of the silicon substrate 101 can be arbitrarily set while suppressing punch-through. Since the leakage current can be reduced and the area of the high concentration impurity layer formed in the silicon substrate 101 before the formation of the epitaxial Si layer 103 can be reduced, the undoped epitaxial Si layer 103 can be stably formed. .

  The present invention is not limited to the above embodiment. In the present embodiment, the case of all n-channel transistors has been described. However, it is obvious that the present invention can be similarly applied to a p-channel transistor by switching n-type and p-type conductivity types. It is also possible to configure as a so-called CMOS in which the n channel and the p channel are formed in the same chip and operate as an element having the same features.

1A and 1B are a plan view and a cross-sectional view showing the overall configuration of a semiconductor device according to a first embodiment of the invention. A top view and a sectional view showing a manufacturing process of a semiconductor device concerning the embodiment. A top view and a sectional view showing a manufacturing process of a semiconductor device concerning the embodiment. A top view and a sectional view showing a manufacturing process of a semiconductor device concerning the embodiment. A top view and a sectional view showing a manufacturing process of a semiconductor device concerning the embodiment. A top view and a sectional view showing a manufacturing process of a semiconductor device concerning the embodiment. A top view and a sectional view showing a manufacturing process of a semiconductor device concerning the embodiment. A top view and a sectional view showing a manufacturing process of a semiconductor device concerning the embodiment. The figure which shows the RTA temperature dependence of the source / drain diffused layer depth concerning the embodiment. Sectional drawing which shows the whole structure of the semiconductor device which concerns on 2nd Embodiment of this invention. Sectional drawing which shows the whole structure of the semiconductor device which concerns on 3rd Embodiment of this invention. Sectional drawing which shows the whole structure of the semiconductor device which concerns on the modification of the embodiment. Sectional drawing which shows the whole structure of the semiconductor device which concerns on 4th Embodiment of this invention. Sectional drawing which shows the whole structure of the semiconductor device which concerns on 5th Embodiment of this invention. Sectional drawing which shows the whole structure of the semiconductor device which concerns on the modification of the embodiment. Sectional drawing which shows the whole structure of the semiconductor device which concerns on 6th Embodiment of this invention. Sectional drawing which shows the whole structure of the semiconductor device which concerns on 7th Embodiment of this invention. The figure for demonstrating the problem of the conventional semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 ... P-type silicon substrate, 102 ... Punch through stopper layer, 103, 161 ... Epitaxial Si layer, 104, 121 ... Oxide film, 105 ... Insulating film, 106 ... Gate insulating film, 107 ... Gate electrode, 108 ... Source Drain diffusion layer, 109 ... sidewall film, 110, 131 ... silicide film, 111 ... interlayer insulating film, 112 ... contact plug, 113 ... wiring, 122 ... buffer oxide film, 123 ... silicon nitride film, 124 ... groove, 125 ... contact Hole 141 first punch-through stopper layer 142 second punch-through stopper layer

Claims (26)

A first conductivity type single crystal semiconductor layer formed on a main plane of a first conductivity type semiconductor substrate, and a second conductivity type source region and drain region formed at least apart from each other in the single crystal semiconductor layer A first conductivity type channel region formed between the source region and the drain region, and a gate electrode formed on the channel region via a gate insulating film, The transistor structures are semiconductor devices formed with an element isolation region interposed therebetween,
A first conductivity type punch-through stopper layer is formed under the source region and the drain region, and the channel region in the vicinity of the interface with the gate insulating film has a lower impurity concentration than the punch-through stopper layer. And the source region and the drain region do not extend over the element isolation region,
The punch-through stopper layer includes a first high-concentration impurity layer and a second high-concentration impurity layer, and the first high-concentration impurity layer is formed separately from the source region and the drain region, The second high concentration impurity layer partially overlaps with the source region and the drain region and is selectively formed at least under the channel region, and the first high concentration impurity layer and the second high concentration impurity layer are formed. A semiconductor device which is in contact with a layer. A first conductivity type epitaxial semiconductor layer formed on a main plane of a first conductivity type semiconductor substrate; a second conductivity type source region and a drain region formed at least apart from each other in the epitaxial semiconductor layer; A transistor structure including a channel region of a first conductivity type formed between the source region and the drain region, and a gate electrode formed on the channel region via a gate insulating film; The semiconductor devices are formed with an element isolation region between each other,
A first conductivity type punch-through stopper layer is formed under the source region and the drain region, and the channel region at the interface with the gate insulating film has a lower impurity concentration than the punch-through stopper layer, The source region and the drain region do not extend on the element isolation region,
The punch-through stopper layer includes a first high-concentration impurity layer and a second high-concentration impurity layer, and the first high-concentration impurity layer is formed separately from the source region and the drain region, The second high concentration impurity layer partially overlaps with the source region and the drain region and is selectively formed at least under the channel region, and the first high concentration impurity layer and the second high concentration impurity layer are formed. A semiconductor device which is in contact with a layer.   The semiconductor device according to claim 1, wherein a silicide film is formed on the source region and the drain region.   3. The semiconductor according to claim 1, wherein the gate electrode has a stacked structure of a polycrystalline Si film doped with impurities and a metal film or a silicide film formed on the polycrystalline Si film. apparatus. Forming a first conductivity type high concentration impurity layer on at least a part of the first conductivity type semiconductor substrate; forming a first conductivity type semiconductor layer by epitaxial growth on a main plane of the semiconductor substrate; Forming a groove by selectively removing the semiconductor layer and the semiconductor substrate and embedding an element isolation insulating film in the groove; and forming a gate insulating film and a gate electrode selectively on the semiconductor layer. And a step of forming a source region and a drain region of the second conductivity type using the gate electrode as a mask, and the step after the formation of the high concentration impurity layer is performed under a condition of 700 ° C. or lower,
The high-concentration impurity layer is formed under the source region and the drain region, and the channel region in the vicinity of the interface with the gate insulating film has a lower impurity concentration than the high-concentration impurity layer, and the high-concentration impurity layer Is composed of a first high-concentration impurity layer and a second high-concentration impurity layer, and the first high-concentration impurity layer is formed separately from the source region and the drain region, and the second high-concentration impurity layer is formed. The impurity layer partially overlaps the source region and the drain region and is selectively formed at least under the channel region, and the first high concentration impurity layer and the second high concentration impurity layer are in contact with each other. A method for manufacturing a semiconductor device.   6. The oxide film is formed by radical oxidation under conditions of 700 ° C. or lower so as to cover the groove plane after forming the groove and before embedding the element isolation insulating film. The manufacturing method of the semiconductor device of description. Forming a first conductivity type high concentration impurity layer on at least a part of the first conductivity type semiconductor substrate;
Forming a first conductivity type epitaxial Si layer in contact with the high-concentration impurity layer by epitaxial growth on a main plane of the semiconductor substrate;
Forming a trench by selectively removing the epitaxial Si layer and the semiconductor substrate, and embedding an element isolation insulating film in the trench;
Forming a second conductivity type source region in a region where the element isolation insulating film is not formed and a second conductivity type drain region in a region sandwiching the source region and the epitaxial Si layer;
The height of at least a part of the lower surface of the source region and the drain region with respect to the main surface of the semiconductor substrate is a boundary surface between the lower surface of the epitaxial Si layer and the upper surface of the high-concentration impurity layer with respect to the main surface of the semiconductor substrate. It is formed deeper than the height of
Forming the high-concentration impurity layer under the source region and the drain region, the channel region in the vicinity of the interface with the gate insulating film on the channel region has a lower impurity concentration than the high-concentration impurity layer, The high concentration impurity layer includes a first high concentration impurity layer and a second high concentration impurity layer. The first high concentration impurity layer is formed separately from the source region and the drain region, and The second high concentration impurity layer partially overlaps with the source region and the drain region and is selectively formed at least under the channel region, and the first high concentration impurity layer, the second high concentration impurity layer, Is in contact with the semiconductor device. Forming a first conductivity type high concentration impurity layer on at least a part of the first conductivity type semiconductor substrate;
Forming a first conductivity type epitaxial layer Si layer in contact with the high-concentration impurity layer by epitaxial growth on a main plane of the semiconductor substrate;
Forming a trench by selectively removing the epitaxial Si layer and the semiconductor substrate, and embedding an element isolation insulating film in the trench;
Forming a second conductivity type source region in a region where the element isolation insulating film is not formed and a second conductivity type drain region in a region sandwiching the source region and the epitaxial Si layer;
The source region has a first source region and a second source region whose lower surface is shallower than the height of the lower surface of the first drain region with respect to the main surface of the semiconductor substrate;
The drain region has a first drain region and a second drain region whose bottom surface is shallower than the height of the bottom surface of the first drain region with respect to the main surface of the semiconductor substrate;
The height of the lower surface of the first source region and the first drain region with respect to the main plane of the semiconductor substrate is the boundary surface between the lower surface of the epitaxial Si layer and the upper surface of the high-concentration impurity layer with respect to the main surface of the semiconductor substrate. Deeper than the height,
Forming the high-concentration impurity layer under the source region and the drain region, the channel region in the vicinity of the interface with the gate insulating film on the channel region has a lower impurity concentration than the high-concentration impurity layer, The high concentration impurity layer includes a first high concentration impurity layer and a second high concentration impurity layer. The first high concentration impurity layer is formed separately from the source region and the drain region, and The second high concentration impurity layer partially overlaps with the source region and the drain region and is selectively formed at least under the channel region, and the first high concentration impurity layer, the second high concentration impurity layer, Is in contact with the semiconductor device.   9. The method of manufacturing a semiconductor device according to claim 7, wherein the high concentration impurity layer is formed under conditions of 700 [deg.] C. or less after the high concentration impurity layer is formed. After forming the source and drain regions, forming contacts penetrating the source and drain regions,
The method for manufacturing a semiconductor device according to claim 7, wherein the steps after forming the high-concentration impurity layer and before forming the contact are performed under conditions of 700 ° C. or less.   The step after forming the high-concentration impurity layer is performed under conditions of 700 ° C. or lower, and the step performed under the conditions of 700 ° C. or lower includes a step of forming an oxide film, and at least one of the steps of forming this oxide film. The method of manufacturing a semiconductor device according to claim 7, wherein radical oxidation is used for the part.   The step after forming the high-concentration impurity layer is performed under conditions of 700 ° C. or lower, and the step performed under the conditions of 700 ° C. or lower includes an ion implantation step for implanting impurities, and at least part of the ion implantation step. 9. The method of manufacturing a semiconductor device according to claim 7, wherein a cryo ion implantation method is used.   The step after forming the high-concentration impurity layer is performed under conditions of 700 ° C. or less, and the step of performing conditions under 700 ° C. or less includes an ion implantation step of implanting impurities into the channel region. 9. The method for manufacturing a semiconductor device according to claim 7, wherein a cryo ion implantation method is used.   9. The method of manufacturing a semiconductor device according to claim 7, further comprising forming a silicide film in the source region and the drain region. The method of manufacturing a semiconductor device according to claim 7, further comprising: forming a silicide film on surfaces of the source region and the drain region, and the silicide film is Pd ₂ Si. further,
Forming a gate electrode,
9. The method of manufacturing a semiconductor device according to claim 7, wherein a silicide film is formed on the surface of the gate electrode. further,
Forming a gate electrode, a silicide film is formed on the gate electrode surface, the silicide film, a method of manufacturing a semiconductor device according to claim 7 or 8, characterized in that a Pd ₂ Si.   9. The method of manufacturing a semiconductor device according to claim 7, wherein the high concentration impurity layer is formed by ion implantation.   The method for manufacturing a semiconductor device according to claim 7, wherein a heat treatment is performed at a temperature of 700 ° C. or higher after the ion implantation. A first conductivity type semiconductor substrate;
A high-concentration impurity layer of a first conductivity type formed on at least a part of the semiconductor substrate;
An epitaxial Si layer of a first conductivity type formed on the main plane of the semiconductor substrate in contact with the high-concentration impurity layer;
A groove portion selectively formed from the epitaxial Si layer to a predetermined height of the semiconductor substrate;
An element isolation insulating film formed in the groove;
A source region of a second conductivity type formed in a region where the element isolation insulating film is not formed;
A drain region of a second conductivity type formed in a region where the element isolation insulating film is not formed, and formed in a region sandwiching the epitaxial Si layer;
At least part of the height of the lower surface of the source region and the drain region with respect to the main surface of the semiconductor substrate is a boundary surface between the lower surface of the epitaxial Si layer and the upper surface of the high-concentration impurity layer with respect to the main surface of the semiconductor substrate. Deeper than the height of
Forming the high-concentration impurity layer under the source region and the drain region, the channel region in the vicinity of the interface with the gate insulating film on the channel region has a lower impurity concentration than the high-concentration impurity layer, The high concentration impurity layer includes a first high concentration impurity layer and a second high concentration impurity layer. The first high concentration impurity layer is formed separately from the source region and the drain region, and The second high concentration impurity layer partially overlaps with the source region and the drain region and is selectively formed at least under the channel region, and the first high concentration impurity layer, the second high concentration impurity layer, Is in contact with a semiconductor device. A first conductivity type semiconductor substrate;
A high-concentration impurity layer of a first conductivity type formed in at least a part of the semiconductor;
An epitaxial Si layer of a first conductivity type formed on the main plane of the semiconductor substrate in contact with the high-concentration impurity layer;
A groove portion selectively formed from the epitaxial Si layer to a predetermined height of the semiconductor substrate;
An element isolation insulating film formed in the groove;
A source region of a second conductivity type formed in a region where the element isolation insulating film is not formed and having a first and a second source region;
A second conductivity type drain region formed in a region where the element isolation insulating film is not formed, formed in a region sandwiching the source region and the epitaxial Si layer, and having a first and a second drain region; Equipped,
The height of the lower surface of the first source region relative to the main surface of the semiconductor substrate is deeper than the height of the lower surface of the second source region relative to the main surface of the semiconductor substrate,
The height of the lower surface of the first drain region relative to the main surface of the semiconductor substrate is deeper than the height of the lower surface of the second drain region relative to the main surface of the semiconductor substrate,
The height of the lower surface of the first source region and the first drain region with respect to the main surface of the semiconductor substrate is a boundary surface between the lower surface of the epitaxial Si layer and the upper surface of the high-concentration impurity layer with respect to the main surface of the semiconductor substrate. Deeper than the height,
Forming the high-concentration impurity layer under the source region and the drain region, the channel region in the vicinity of the interface with the gate insulating film on the channel region has a lower impurity concentration than the high-concentration impurity layer, The high concentration impurity layer includes a first high concentration impurity layer and a second high concentration impurity layer. The first high concentration impurity layer is formed separately from the source region and the drain region, and The second high concentration impurity layer partially overlaps with the source region and the drain region and is selectively formed at least under the channel region, and the first high concentration impurity layer, the second high concentration impurity layer, Is in contact with a semiconductor device. An interlayer insulating film formed on the epitaxial Si layer, source and drain regions;
The semiconductor device according to claim 20, further comprising a contact formed in the interlayer insulating film and penetrating through the source and drain regions.   The semiconductor device according to claim 20, further comprising a silicide film formed on surfaces of the source region and the drain region. The semiconductor device according to claim 20 or 21, further comprising a silicide film formed on the surface of the source region and the drain region and made of Pd ₂ Si. A gate insulating film selectively formed on the epitaxial Si layer;
A gate electrode formed on the gate insulating film;
The semiconductor device according to claim 20, further comprising a silicide film formed on the surface of the gate electrode. A gate insulating film selectively formed on the epitaxial Si layer;
A gate electrode formed on the gate insulating film;
The semiconductor device according to claim 20 or 21, further comprising a silicide film formed on the surface of the gate electrode and made of Pd ₂ Si.

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