JP2007019708A - Image processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing apparatus in which a video signal utilizing sharp image quality suitably through IP conversion can be obtained by considering the scale factor of resize processing after IP conversion for such parameters as movement detection or slanting detection which are utilized in processing of IP conversion thereby reducing impact of incorrect decision on the final image. <P>SOLUTION: For the movement evaluation circuit and the slanting evaluation circuit of an IP conversion circuit, a scale factor for scaling is input and scaling is performed after controlling IP conversion operation or decision parameters of IP conversion depending on the scale factor. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus that involves video enlargement / reduction processing in so-called IP conversion processing for converting an interlaced video signal into a non-interlaced signal.

  There is a so-called IP conversion process in which an interlaced video signal is converted into a non-interlaced video signal in order to process an interlaced video signal captured, recorded, and transmitted by a TV system such as NTSC as a sharper video signal.

  The IP conversion is usually composed of a motion adaptation or oblique adaptation algorithm that analyzes image difference information between fields and a two-dimensional high-frequency component in the field.

  Also, there is a digital signal processing called so-called electronic zoom in which a video signal is cut out and enlarged at a free size and position, or a video signal having a large number of pixels is reduced to a predetermined number of pixels. .

  A sharp image that maintains vertical resolution to some extent even when the magnification is greatly enlarged by electronic zoom processing by converting the interlaced video signal into a non-interlaced signal by IP conversion. A signal can be obtained.

  However, the IP conversion may cause a misjudgment of motion judgment or oblique judgment. In particular, when the non-interlaced video signal subjected to the interpolation process including the misjudgment is enlarged, the image quality of the misjudged pixel is reduced. Deterioration is conspicuous.

  In addition, when the zoom process is performed, dot misalignment may occur due to random repetition of the above-mentioned misjudgment or non-occurrence due to fluctuations in the angle of view caused by noise or panning superimposed on the image. This is also noticeable.

As a conventional method for solving such a problem, for example, an imaging apparatus disclosed in Patent Document 1 can be cited.
JP 2004-153668 A

  In the above-described conventional method, whether to use IP-converted non-interlaced frame video or interlaced field video is controlled for each field period according to the result of the motion detection means.

  However, in such a control, although the scanning line interpolation process such as motion detection is performed in units of pixels, the interpolation result selection is performed only in units of fields, and motion detection of the entire field is performed. Depending on the state, the still image area whose sharpness has been improved by the IP conversion cannot be effectively used.

  The present invention has been made paying attention to the above points, and it is possible to reduce the influence of erroneous determination on the final image and to obtain a video signal that preferably uses sharp image quality in IP conversion. An object is to provide an image processing apparatus.

In order to solve the above-described problem, the first image processing apparatus of the present invention receives an interlaced video signal that is interlaced and scanned in units of fields, and has a capacity of at least one field that sequentially delays the interlaced video signals in units of fields. Memory,
A motion determination circuit that performs motion determination of a video in a field in units of pixels from an input interlace signal and a video signal delayed by the memory, and outputs a motion determination coefficient;
A diagonal determination circuit that performs a pixel-by-pixel determination of a diagonal component of a video in a field from an input interlace signal and a video signal delayed by the memory, and outputs a diagonal determination coefficient;
A line interpolation circuit that performs an interpolating operation on a scanning line located between the scanning lines of the field in units of pixels from the motion determination coefficient and the oblique determination coefficient, and converts and outputs an interlaced video signal to a non-interlaced video signal;
An enlargement / reduction circuit that outputs the non-interlaced video signal output from the line interpolation circuit after being expanded or reduced in the horizontal and vertical directions;
In an image processing apparatus provided with a magnification coefficient generation circuit that generates horizontal and vertical magnification coefficients for interpolation calculation according to a magnification instructed from outside,
The enlargement / reduction circuit executes an enlargement / reduction process based on the horizontal and vertical magnification coefficients that are output from the magnification coefficient generation circuit, and the motion determination circuit and the oblique determination circuit correspond to the magnification coefficient. It is characterized in that a motion determination coefficient and a diagonal determination coefficient with weighted determination results are output.

In order to solve the above-described problem, the second image processing apparatus of the present invention has a capacity of at least one field that receives an interlaced video signal that is interlaced and operated in units of fields and sequentially delays the interlaced video signals in units of fields. A first memory;
A motion determination circuit that performs motion determination of a video in a field in units of pixels from the input interlace signal and the video signal delayed in the first memory, and outputs a motion determination coefficient;
An oblique determination circuit for performing an oblique component determination of an image in a field from an input interlace signal and an image signal delayed in the first memory in units of pixels, and outputting an oblique determination coefficient;
A line interpolation circuit that performs an interpolating operation on a scanning line located between the scanning lines of the field in units of pixels from the motion determination coefficient and the oblique determination coefficient, and converts and outputs an interlaced video signal to a non-interlaced video signal;
A second memory having a capacity of at least one frame for holding a non-interlaced video signal output from the line interpolation circuit;
A memory control circuit for controlling writing and reading of the second memory;
An enlarging / reducing circuit for enlarging or reducing the non-interlaced video signal output from the second memory in the horizontal and vertical directions;
In an image processing apparatus provided with a magnification coefficient generation circuit that generates horizontal and vertical magnification coefficients for interpolation calculation according to a magnification instructed from outside,
The enlargement / reduction circuit executes an enlargement / reduction process based on the horizontal and vertical magnification coefficients that are output from the magnification coefficient generation circuit, and the motion determination circuit and the oblique determination circuit correspond to the magnification coefficient. The motion determination coefficient and the diagonal determination coefficient weighted to the determination result are output, and the memory control circuit writes or reads the second memory that holds the non-interlaced video signal that is line-interpolated according to the magnification coefficient. Control is performed.

  According to the present invention, the influence of misjudgment on the final image can be reduced by adding the magnification of resizing processing after IP conversion to parameters such as motion detection and oblique detection used for IP conversion processing. Thus, it is possible to obtain a video signal that preferably uses sharp image quality in IP conversion.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

  The first embodiment of the present invention will be described. FIG. 1 is an example of a video signal processing block diagram suitable for the present invention.

  The interlaced video signal Si input from the input terminal 1 is input to the memory 2, delayed by one field period, and output from the memory 2 as a field delay signal Sm.

  The motion determination circuit 3 receives the interlaced video signal Si and the field delay signal Sm, receives the vertical magnification coefficient Czv, performs the motion determination process, and then outputs the motion determination signal Dm.

  The oblique determination circuit 4 receives the interlaced video signal Si and the field delay signal Sm, receives the vertical magnification coefficient Czv, and performs the oblique determination process, and then outputs the oblique determination signal Dd.

  The line interpolation circuit 5 receives the interlaced video signal Si and the field delay signal Sm, and also receives the motion determination signal Dm and the diagonal determination signal Dd. Interpolation is performed for each interpolated pixel position in accordance with Dm and the diagonal determination signal Dd, and sequentially output as a non-interlace video signal Sp while performing timing control with the horizontal synchronization signal HDi of the interlace signal and the horizontal synchronization signal HDp of the non-interlace signal.

  The enlargement / reduction circuit 6 performs an enlargement / reduction operation in the horizontal direction and the vertical direction based on the horizontal magnification coefficient Czh and the vertical magnification coefficient Czv with respect to the non-interlaced video signal Sp, and the horizontal synchronization signal HDi of the interlace signal and the non-interlace signal While performing timing control with the horizontal synchronizing signal HDp of the signal, an interlaced video signal Sr having a predetermined image size is output.

  At this time, the magnification coefficient generation circuit 8 that has received an enlargement / reduction instruction from the microcomputer 7 generates a horizontal magnification coefficient Czh and a vertical magnification coefficient Czv in pixel units in accordance with the designated enlargement / reduction ratio, and a motion determination circuit. 3 and the oblique determination circuit 4 are inputted with a vertical magnification coefficient Czv, and the enlargement / reduction circuit 6 is inputted with a horizontal magnification coefficient Czh and a vertical magnification coefficient Czv.

  The horizontal magnification coefficient Czh and the vertical magnification coefficient Czv include information necessary for the interpolation calculation, such as the center of gravity of the interpolation position in each interpolation direction and the movement amount of the original sample to be referenced.

  Next, each circuit configuration and control based on the horizontal magnification coefficient Czh and the vertical magnification coefficient Czv which are outputs of the magnification generation circuit 8 will be described in detail.

  The motion determination circuit 3 has a configuration as shown in FIG. 2, for example. Also, the physical positional relationship of each signal is shown in FIG.

  The input interlaced video signal Si is made into SiA delayed by one line by the line delay element 301 and the current line signal SiC.

  The subtractor 302 calculates a difference between SiA and SiC, and calculates an inter-line difference value Egv in the Si field for each pixel as an absolute value by the absolute value circuit 303.

  The adder 304 calculates the average value of SiA and SiC, the subtractor 305 calculates the difference from the line signal SmB in the Sm field, and the absolute value circuit 306 calculates the absolute value as the Sm field and Si at the interpolation line position. The inter-field difference value Fdd with the field is calculated in units of pixels.

  The vertical magnification coefficient Czv is input to the offset circuit 307. The offset circuit 307 is a function circuit having input / output characteristics as shown in FIG. 4, for example. When the vertical magnification coefficient Czv is in the reduced region, the offset value Dof is zero, but gradually enters the enlarged region. When the value increases and reaches a certain enlargement magnification, the offset value is controlled to the maximum value.

  The inter-field difference value Fdd is added to the offset value Dof by the adder 308 to become Fdd ', and is input to the comparison circuit 309 together with the inter-line difference value Egv.

In the comparison circuit 309, the motion determination signal Dm is set to Dm = Fdd ′ / Edv (where Dm ≦ 1)
And output as a multi-valued coefficient.

  The motion determination signal Dm output by such calculation indicates that the larger the value is, the lower the correlation between the fields is, and it is determined that the motion portion. Conversely, the smaller the value is, the higher the correlation between the fields is, and it is determined that it is a stationary part.

  The offset value Dof may be given so that the motion determination value finally becomes a determination result based on motion. For example, the offset value Dof may be given so as to be subtracted from the inter-line difference value Egv, or may be added to the motion determination signal Dm. You may give so that it may add.

  The configuration of the motion determination circuit is a very simple example and shows that the motion determination signal Dm is calculated from the inter-line difference value Egv and the inter-field difference value Fdd.

  Therefore, the calculation method of the inter-line difference value Egv and the inter-field difference value Fdd, and the calculation method of the motion determination signal Dm using them are not limited.

  The oblique determination circuit 3 has a configuration as shown in FIG. 5, for example. Also, the physical positional relationship of each signal is shown in FIG.

  The input interlaced video signal Si is made into SiA delayed by one line by the line delay element 401 and the current line signal SiC.

  The one-line delay signal SiA is sequentially delayed by one pixel unit by the delay elements 402 and 403, and outputs SiA2 and SiA1, respectively. The current pixel signal is SiA3.

  The current line signal SiC is sequentially delayed by one pixel unit by the delay elements 404 and 405, and outputs SiC2 and SiC1, respectively. The current pixel signal is SiC3.

  The subtractor 406 calculates a difference between SiA1 and SiC3, and calculates an oblique direction difference value D1 with respect to the interpolation pixel position in the Si field as an absolute value in the absolute value circuit 407 for each pixel.

  The subtractor 408 calculates the difference between SiA2 and SiC2, and calculates the vertical direction difference value D2 with respect to the interpolation pixel position in the Si field as an absolute value in the absolute value circuit 409 for each pixel.

  The subtractor 410 calculates the difference between SiA3 and SiC1, and calculates the diagonal direction difference value D3 with respect to the interpolation pixel position in the Si field as an absolute value in the absolute value circuit 411 in units of pixels.

  The vertical magnification coefficient Czv is input to the offset circuit 412. The offset circuit 412 is a function circuit having input / output characteristics as shown in FIG. 7, for example. When the vertical magnification coefficient Czv is in the reduced region, the offset value Dof is zero, but gradually enters the enlarged region. When the value increases and reaches a certain enlargement magnification, the offset value is controlled to the maximum value.

  The oblique direction difference value D1 and the oblique direction difference value D3 are added to the offset value Dof by the adders 413 and 414 to become D1 'and D3', respectively, and are input to the comparison circuit 415 together with the vertical direction difference value D2.

The comparison circuit 415 obtains the diagonal determination signal Dd with the smallest one of Dd = D1 ′, D2, and D3 ′, and outputs it as a multivalued coefficient indicating the direction. This is merely an example of a method for calculating Dd. For example, a multi-value expression such as outputting each difference value as it is can be considered.

  The oblique determination signal Dd output by such calculation indicates the direction with the highest correlation among the pixel directions of the upper and lower lines centering on the interpolation pixel.

  The offset value Dof may be given so that the oblique judgment value finally becomes a judgment result that tends to be in the vertical direction. For example, the offset value Dof may be given to be subtracted from the vertical direction difference value D2.

  Further, the configuration of the oblique determination circuit is a very simple example, and shows that the oblique determination signal Dd is calculated from the pixel directions of the upper and lower lines with the interpolation pixel as the center.

Therefore, the calculation method of each diagonal direction difference value line difference value Dx (x is an arbitrary number) and the diagonal determination signal Dd using them is not limited.
The line interpolation circuit 5 is configured as shown in FIG. 8, for example. The physical positional relationship of each signal is shown in FIG. 3 for explaining the motion judging circuit and FIG. 6 for explaining the oblique judging circuit.

  The input interlaced video signal Si is made into SiA delayed by one line by the line delay element 401 and the current line signal SiC.

  The one-line delay signal SiA is sequentially delayed by one pixel unit by the delay elements 502 and 503, and outputs SiA2 and SiA1, respectively. The current pixel signal is SiA3.

  The current line signal SiC is sequentially delayed by one pixel unit by the delay elements 504 and 505, and outputs SiC2 and SiC1, respectively. The current pixel signal is SiC3.

  The adder 506 calculates an average value of SiA1 and SiC3, and calculates an oblique direction interpolation value P1 with respect to the interpolation pixel position in the Si field in units of pixels.

  The subtractor 507 calculates an average value of SiA2 and SiC2, and calculates a vertical direction interpolation value P2 for the interpolation pixel position in the Si field in units of pixels.

  The subtractor 508 calculates an average value of SiA3 and SiC1, and calculates an oblique direction interpolation value P3 with respect to the interpolation pixel position in the Si field in units of pixels.

  The synthesis circuit 509 selects one of the interpolation values P1, P2, and P3 according to the oblique determination signal Dd, and outputs the intra-Si field interpolation signal SiB.

Note that this combining circuit is not necessarily a selector, and if the oblique determination signal is output so as to indicate the weight of each interpolation pixel, each interpolation value P1, P2, P3 is weighted and SiB = D1 · P1 + D2 · P2 + D3 · P3
It is also possible to synthesize.

The interpolation circuit 510 weights the interpolation signal SiB in the Si field and the line signal SmB in the Sm field according to the motion determination signal Dm, and determines the interpolation line signal SB as SB = Dm · SiB + (1−Dm) · SmB (where Dm ≦ 1)
As shown in FIG.

  If Dm is zero, the motion determination is completely stationary, and the interpolation line signal SB is performed with the Sm field value itself.

  The line sequential circuit 511 has a configuration as shown in FIG. 9, for example. The signal timing is shown in FIG. The alphabets in parentheses in the sentence are the same as those in FIG.

  The line memories 5111 and 5112 are dual port line memories (denoted as LM1 and LM2 in FIG. 10) having a capacity capable of holding at least one line of data, capable of independently controlling clocks and read / write addresses. is there.

  The horizontal synchronization signal HDi (A) of the interlace signal is input to the write control circuit 5113, and the write control circuit 5113 generates an address Aw so that one line of data is sequentially written in one interlace line period, and the line memory 5111, 5112 holds the line signal SiC (B) of the Si field and the interpolation signal SB (C) of the Sm field, respectively (D) and (E).

  At this time, since the write control circuit 5113 operates in the dot clock cycle of the interlace signal, the line signals 5111 and 5112 are respectively supplied to the line signals 5111 and 5112 in the interlace line line. All the data for one line of the signal SB (C) can be written.

  The horizontal synchronization signal HDp (F) of the non-interlace signal is input to the read control circuit 5114, and the read control circuit 5114 reads the data of one line alternately in the line memories 5111 and 5112 in the non-interlace one-line period. Address Ar is generated, and the line signal SiC (G) in the Si field and the interpolation signal SB (H) in the Sm field are intermittently read from the line memories 5111 and 5112, respectively.

  At this time, since the read control circuit 5114 operates in the dot clock cycle of the non-interlace signal, which is twice the frequency of the interlace signal, the line signal SiC (B (SiB) of the Si field of the line memory 5111 in one non-interlace line period. ) Or the interpolated line signal SB (C) in the Sm field of the line memory 5112 can be all read out.

  The selector 5115 switches the line signal SiC (G) in the Si field and the interpolation signal SB (H) in the Sm field from the line memories 5111 and 5112 so that the order is non-interlaced and outputs the non-interlace signal Sp. .

  The enlargement / reduction circuit 6 has a configuration as shown in FIG. 11, for example. Signal timing is shown in FIGS. The alphabets in parentheses in the sentence are the same as those in FIG.

  The non-interlace signal Sp is input to the dual port line memory 601 having a capacity capable of holding at least one line of data, which can control the clock and the read / write address independently.

  The horizontal synchronization signal HDp of the non-interlace signal is input to the write control circuit 602. The write control circuit 602 generates an address Awh1 so that one line of data is sequentially written in one line period of non-interlace, and the non-interlace signal HDp is stored in the line memory 601. The interlace signal Sp is held.

  The non-interlaced signal horizontal synchronization signal HDp and the horizontal magnification factor Czh are input to the read control circuit 603. The read control circuit 603 cuts an arbitrary part of the line in the horizontal direction by setting the initial value of the address Arh1. The address Arh1 is held in a pixel unit in a predetermined pattern determined by the horizontal magnification coefficient Czh, and the address Arh1 is generated so that data of one line width is read in one non-interlaced line period, and the non-interlaced signal is generated from the line memory 601. Read SpB.

  The horizontal magnification coefficient Czh is input to the hold control circuit 605, and a hold control signal Chh is generated in a predetermined pattern determined by the horizontal magnification coefficient Czh. This pattern is the same as the pattern generated internally by the read control circuit 603.

  The non-interlace signal SpB is input to a delay element 604 capable of hold control, and the delay element 604 sequentially outputs a delay signal SpA in units of pixels while holding the non-interlace signal SpB according to the hold control signal Chh.

  Note that the read control circuit 603 and the hold circuit 605 activate the pixel-by-pixel hold function only when the enlargement process is performed in the horizontal direction.

The non-interlace signal SpB, the delay signal SpA and the horizontal magnification factor Czh are
Sph = (SpA−SpB) · k + SpB (k is the center of gravity value in Czh)
Is calculated by a subtractor 606, a multiplier 607, and an adder 608 so that an interpolated pixel signal Sph is output.

  The interpolated pixel signal Sph is input to a dual port line memory 609 having a capacity capable of holding at least one line of data and capable of independently controlling a clock and a read / write address.

  The horizontal synchronization signal HDp of the non-interlace signal and the horizontal magnification factor Czh are input to the write control circuit 610, and the write control circuit 610 holds the address Awh2 in a predetermined pattern determined by the horizontal magnification factor Czh, and the non-interlace 1 An address Awh2 is generated so that data of one line width is written in the line period, and the interpolation pixel signal Sph is held in the line memory 609.

  The horizontal synchronization signal HDp of the non-interlace signal is input to the read control circuit 611. The read control circuit 611 sequentially generates the address Arh2 so as to read the data of one line width in one non-interlace one line period, and from the line memory 609 The non-interlace signal Sph ′ is read out.

  Note that the write control circuit 610 activates the address hold function for each pixel only when the reduction process is performed in the horizontal direction.

  The non-interlace signal Sph 'is input to a memory 612 having a capacity capable of holding data for at least one field.

  The horizontal synchronization signal HDp of the non-interlace signal is input to the write control circuit 613, and the write control circuit 613 generates an address Awv1 so that one line of data is sequentially written in one non-interlace line period, and the memory 612 is non-interlaced. The signal Sph ′ is held.

  The non-interlaced signal horizontal synchronization signal HDp and the vertical magnification factor Czv are input to the read control circuit 614. The read control circuit 614 cuts out any part of the field in the vertical direction by setting the initial value of the address Arv1. The address Arv1 is held line by line in a predetermined pattern determined by the vertical scaling factor Czv, and the address Arv1 is generated so as to read out data of one field line in one field period of non-interlace. The non-interlace signal Sp2 is generated from the memory 612. Is read.

  The vertical magnification coefficient Czv is input to the hold control circuit 616, and a hold control signal Chv is generated in a predetermined pattern determined by the vertical magnification coefficient Czv. This pattern is the same as the pattern generated internally by the read control circuit 614.

  The non-interlace signal Sp2 is input to the line memory 615, and the line memory 615 sequentially outputs the delay signal Sp2 in units of pixels while holding the non-interlace signal Sp2 in units of lines according to the hold control signal Chv.

  Note that the read control circuit 614 and the hold circuit 616 activate the hold function in units of lines only when the enlargement process is performed in the vertical direction.

The non-interlace signal Sp2, the delay signal Sp1, and the horizontal magnification factor Czv are:
Spv = (Sp1-Sp2) · k + Sp2 (k is the center of gravity value in Czv)
Is calculated by a subtractor 617, a multiplier 618, and an adder 619 so that the interpolation pixel signal Spv is output.

  The interpolated pixel signal Spv is input to a memory 620 having a capacity capable of holding at least one field of data.

  The horizontal synchronization signal HDp of the non-interlace signal and the horizontal magnification coefficient Czv are input to the write control circuit 621, and the write control circuit 621 holds the address Awv2 in a predetermined pattern determined by the horizontal magnification coefficient Czv, and the non-interlace 1 An address Awv2 is generated so that data of one field line is written in the field period, and the interpolation pixel signal Spv is held in the memory 620.

  The non-interlace signal horizontal synchronization signal HDp and the interlace signal horizontal synchronization signal HDi are input to the read control circuit 622.

  When the output is non-interlaced, the read control circuit 622 sequentially generates an address Arv2 so as to read out data of one frame line in one frame period of non-interlace based on the horizontal synchronization signal HDp of the non-interlace signal, and the memory 620 Reads the non-interlace signal Sr.

  When the output is interlaced, the read control circuit 622 sequentially generates an address Arv2 so as to read data of one field line in one field period of the interlace based on the horizontal synchronization signal HDi of the interlace signal, and the interlace signal is read from the memory 620. Read Sr.

  Note that the write control circuit 621 activates the address hold function in units of lines only when the reduction process is performed in the vertical direction.

  In the case of a non-interlace signal, the video signal Sr obtained in this way is a non-interlace signal that has been subjected to high-definition IP conversion by motion adaptation and oblique adaptation processing, and at the same time has an enlargement / reduction ratio by electronic zoom. Accordingly, image quality deterioration due to IP conversion misjudgment that becomes conspicuous accordingly can be suitably suppressed, and as a result, a high-quality non-interlace signal can always be obtained.

  When the video signal Sr is an interlaced signal, high-definition IP conversion can be performed by shifting the vertical phase of the interpolated field image so that the non-interlaced signal is converted to an interlaced signal again by the enlargement / reduction circuit 6. The field image can be interpolated from the frame image while suitably suppressing deterioration in image quality due to IP conversion misjudgment, which becomes more conspicuous according to the enlargement / reduction ratio by electronic zoom, from the non-interlaced signal that has been performed. As a result, a high-quality interlace signal can always be obtained.

  The second embodiment of the present invention will be described. FIG. 12 is an example of a video signal processing block diagram suitable for the present invention. The same numbers are assigned to those common to the first embodiment of the present invention.

  The interlaced video signal Si input from the input terminal 1 is input to the memory 2, delayed by one field period, and output from the memory 2 as a field delay signal Sm.

  The motion determination circuit 3 receives the interlaced video signal Si and the field delay signal Sm, receives the vertical magnification coefficient Czv, performs the motion determination process, and then outputs the motion determination signal Dm.

  The oblique determination circuit 4 receives the interlaced video signal Si and the field delay signal Sm, receives the vertical magnification coefficient Czv, and performs the oblique determination process, and then outputs the oblique determination signal Dd.

  The line interpolation circuit 5 receives the interlaced video signal Si and the field delay signal Sm, and also receives the motion determination signal Dm and the diagonal determination signal Dd, and the interpolation scanning line (Si for the current scanning line (current field)) ( The interpolated field) is interpolated for each interpolated pixel position in accordance with the motion determination signal Dm and the diagonal determination signal Dd, and the timing control is performed with the horizontal synchronization signal HDi of the interlace signal and the horizontal synchronization signal HDp of the non-interlace signal. The signals are sequentially output as current field signal SiC and interpolated field signal SB.

  In the memory 9, the memory control circuit 10 controls the write address Aw and the read address Ar based on the horizontal synchronization signal HDi of the interlace signal and the horizontal synchronization signal HDp of the non-interlace signal, and the current field signal SiC and the interpolation field signal SB are It holds as an interlace frame and outputs a non-interlace signal Sp.

  The enlargement / reduction circuit 6 performs an enlargement / reduction operation in the horizontal direction and the vertical direction based on the horizontal magnification coefficient Czh and the vertical magnification coefficient Czv with respect to the non-interlaced video signal Sp, and performs the horizontal synchronization signal HDi of the interlace signal and the non-interlace signal. A video signal Sr having a predetermined image size and scanning method is output while performing timing control with the horizontal synchronizing signal HDp.

  At this time, the magnification coefficient generation circuit 8 that has received an enlargement / reduction instruction from the microcomputer 7 generates a horizontal magnification coefficient Czh and a vertical magnification coefficient Czv in pixel units in accordance with the designated enlargement / reduction ratio, and a motion determination circuit. 3. The vertical magnification coefficient Czv is input to the oblique determination circuit 4 and the memory control circuit 10, and the horizontal magnification coefficient Czh and the vertical magnification coefficient Czv are input to the enlargement / reduction circuit 6.

  The horizontal magnification coefficient Czh and the vertical magnification coefficient Czv include information necessary for the interpolation calculation, such as the center of gravity of the interpolation position in each interpolation direction and the movement amount of the original sample to be referenced.

  Next, each circuit configuration and control based on the horizontal magnification coefficient Czh and the vertical magnification coefficient Czv which are outputs of the magnification generation circuit 8 will be described in detail.

  The motion determination circuit 3 has a configuration as shown in FIG. 2, for example. Also, the physical positional relationship of each signal is shown in FIG.

  The input interlaced video signal Si is made into SiA delayed by one line by the line delay element 301 and the current line signal SiC.

  The subtractor 302 calculates a difference between SiA and SiC, and calculates an inter-line difference value Egv in the Si field for each pixel as an absolute value by the absolute value circuit 303.

  The adder 304 calculates the average value of SiA and SiC, the subtractor 305 calculates the difference from the line signal SmB in the Sm field, and the absolute value circuit 306 calculates the absolute value as the Sm field and Si at the interpolation line position. The inter-field difference value Fdd with the field is calculated in units of pixels.

  The vertical magnification coefficient Czv is input to the offset circuit 307. The offset circuit 307 is a function circuit having input / output characteristics as shown in FIG. 4, for example. When the vertical magnification coefficient Czv is in the reduced region, the offset value Dof is zero, but gradually enters the enlarged region. When the value increases and reaches a certain enlargement magnification, the offset value is controlled to the maximum value.

The inter-field difference value Fdd is added to the offset value Dof by the adder 308 to become Fdd ′, and is input to the comparison circuit 309 together with the inter-line difference value Egv.
In the comparison circuit 309, the motion determination signal Dm is set to Dm = Fdd ′ / Edv (where Dm ≦ 1)
And output as a multi-valued coefficient.

  The motion determination signal Dm output by such calculation indicates that the larger the value is, the lower the correlation between the fields is, and it is determined that the motion portion. Conversely, the smaller the value is, the higher the correlation between the fields is, and it is determined that it is a stationary part.

  The offset value Dof may be given so that the motion determination value finally becomes a determination result based on motion. For example, the offset value Dof may be given so as to be subtracted from the inter-line difference value Egv. You may give so that it may add.

  The configuration of the motion determination circuit is a very simple example and shows that the motion determination signal Dm is calculated from the inter-line difference value Egv and the inter-field difference value Fdd.

  Therefore, the calculation method of the inter-line difference value Egv and the inter-field difference value Fdd, and the calculation method of the motion determination signal Dm using them are not limited.

  The oblique determination circuit 3 has a configuration as shown in FIG. 5, for example. Also, the physical positional relationship of each signal is shown in FIG.

  The input interlaced video signal Si is made into SiA delayed by one line by the line delay element 401 and the current line signal SiC.

  The one-line delay signal SiA is sequentially delayed by one pixel unit by the delay elements 402 and 403, and outputs SiA2 and SiA1, respectively. The current pixel signal is SiA3.

  The current line signal SiC is sequentially delayed by one pixel unit by the delay elements 404 and 405, and outputs SiC2 and SiC1, respectively. The current pixel signal is SiC3.

  The subtractor 406 calculates a difference between SiA1 and SiC3, and calculates an oblique direction difference value D1 with respect to the interpolation pixel position in the Si field as an absolute value in the absolute value circuit 407 for each pixel.

  The subtractor 408 calculates the difference between SiA2 and SiC2, and calculates the vertical direction difference value D2 with respect to the interpolation pixel position in the Si field as an absolute value in the absolute value circuit 409 for each pixel.

  The subtractor 410 calculates the difference between SiA3 and SiC1, and calculates the diagonal direction difference value D3 with respect to the interpolation pixel position in the Si field as an absolute value in the absolute value circuit 411 in units of pixels.

  The vertical magnification coefficient Czv is input to the offset circuit 412. The offset circuit 412 is a function circuit having input / output characteristics as shown in FIG. 7, for example. When the vertical magnification coefficient Czv is in the reduced region, the offset value Dof is zero, but gradually enters the enlarged region. When the value increases and reaches a certain enlargement magnification, the offset value is controlled to the maximum value.

  The oblique direction difference value D1 and the oblique direction difference value D3 are added to the offset value Dof by the adders 413 and 414 to become D1 'and D3', respectively, and are input to the comparison circuit 415 together with the vertical direction difference value D2.

The comparison circuit 415 obtains the diagonal determination signal Dd with the smallest one of Dd = D1 ′, D2, and D3 ′, and outputs it as a multivalued coefficient indicating the direction. This is merely an example of a method for calculating Dd. For example, a multi-value expression such as outputting each difference value as it is can be considered.

  The oblique determination signal Dd output by such calculation indicates the direction with the highest correlation among the pixel directions of the upper and lower lines centering on the interpolation pixel.

  The offset value Dof may be given so that the oblique judgment value finally becomes a judgment result that tends to be in the vertical direction. For example, the offset value Dof may be given so as to be subtracted from the vertical direction difference value D2.

  Further, the configuration of the oblique determination circuit is a very simple example, and shows that the oblique determination signal Dd is calculated from the pixel directions of the upper and lower lines with the interpolation pixel as the center.

Therefore, the calculation method of each diagonal direction difference value line difference value Dx (x is an arbitrary number) and the diagonal determination signal Dd using them is not limited.
The line interpolation circuit 5 is configured as shown in FIG. 8, for example. The physical positional relationship of each signal is shown in FIG. 3 for explaining the motion judging circuit and FIG. 6 for explaining the oblique judging circuit.

  The input interlaced video signal Si is made into SiA delayed by one line by the line delay element 401 and the current line signal SiC.

  The one-line delay signal SiA is sequentially delayed by one pixel unit by the delay elements 502 and 503, and outputs SiA2 and SiA1, respectively. The current pixel signal is SiA3.

  The current line signal SiC is sequentially delayed by one pixel unit by the delay elements 504 and 505, and outputs SiC2 and SiC1, respectively. The current pixel signal is SiC3.

  The adder 506 calculates an average value of SiA1 and SiC3, and calculates an oblique direction interpolation value P1 with respect to the interpolation pixel position in the Si field in units of pixels.

  The subtractor 507 calculates an average value of SiA2 and SiC2, and calculates a vertical direction interpolation value P2 for the interpolation pixel position in the Si field in units of pixels.

  The subtractor 508 calculates an average value of SiA3 and SiC1, and calculates an oblique direction interpolation value P3 with respect to the interpolation pixel position in the Si field in units of pixels.

  The synthesis circuit 509 selects one of the interpolation values P1, P2, and P3 according to the oblique determination signal Dd, and outputs the intra-Si field interpolation signal SiB.

Note that this combining circuit is not necessarily a selector, and if the oblique determination signal is output so as to indicate the weight of each interpolation pixel, each interpolation value P1, P2, P3 is weighted and SiB = D1 · P1 + D2 · P2 + D3 · P3
It is also possible to synthesize.

The interpolation circuit 510 weights the interpolation signal SiB in the Si field and the line signal SmB in the Sm field according to the motion determination signal Dm, and determines the interpolation line signal SB as SB = Dm · SiB + (1−Dm) · SmB (where Dm ≦ 1)
As shown in FIG.

  If Dm is zero, the motion determination is completely stationary, and the interpolation line signal SB is performed with the Sm field value itself.

  Finally, the line interpolation circuit 5 outputs the interpolation line signal SB and the current line signal SiC simultaneously.

  The line interpolation circuit 5 can have the same configuration as that of the first embodiment of the present invention, but in this embodiment, the memory control circuit 9 described later can perform an operation equivalent to a line sequential circuit, Since the result line sequential circuit can be omitted, it is advantageous in reducing the hardware scale.

  The memory 9 and the memory control circuit 10 are configured as shown in FIG. 16, for example. The signal timing is shown in FIG. The alphabets in parentheses in the sentence are the same as those in FIG.

  The memory 9 has a capacity capable of holding data for at least one frame.

  The horizontal synchronization signal HDi (A) of the interlace signal is input to the write control circuit 1001, and the write control circuit 1001 converts the data for two lines of the interpolated line signal SB and the current line signal SiC in the upper and lower pairs in one interlace line period. The addresses Aw are generated so as to be sequentially written, and SiC (B) and SB (C) are respectively stored in the memory 9 as frame images (D) and (E).

  At this time, the write control circuit 1001 operates in the dot clock cycle of the non-interlace signal that is twice the frequency of the interlace signal, and the addresses corresponding to the upper and lower sides of the scanning line are switched to time division in the clock cycle. In the line period, all the data for two lines of the Si field line signal SiC (B) and the Sm field interpolation line signal SB (C) can be written in the memory 9.

  The horizontal synchronization signal HDp (F) of the non-interlace signal is input to the read control circuit 5114, and the read control circuit 1002 generates the address Ar so that one line of data is sequentially read in one non-interlace one line period, and the memory 9 The non-interlace signal Sp is read out from (J).

  At this time, since the read control circuit 1002 operates in the dot clock cycle of the non-interlace signal that is twice the frequency of the interlace signal, all the data for one line in the memory 9 is read in one non-interlace line period. Can do.

  The enlargement / reduction circuit 6 has a configuration as shown in FIG. 11, for example. Signal timing is shown in FIGS. The alphabets in parentheses in the sentence are the same as those in FIG.

  The non-interlace signal Sp is input to the dual port line memory 601 having a capacity capable of holding at least one line of data, which can control the clock and the read / write address independently.

  The horizontal synchronization signal HDp of the non-interlace signal is input to the write control circuit 602. The write control circuit 602 generates an address Awh1 so that one line of data is sequentially written in one line period of non-interlace, and the non-interlace signal HDp is stored in the line memory 601. The interlace signal Sp is held.

  The non-interlaced signal horizontal synchronization signal HDp and the horizontal magnification factor Czh are input to the read control circuit 603. The read control circuit 603 cuts an arbitrary part of the line in the horizontal direction by setting the initial value of the address Arh1. The address Arh1 is held in a pixel unit in a predetermined pattern determined by the horizontal magnification coefficient Czh, and the address Arh1 is generated so that data of one line width is read in one non-interlaced line period, and the non-interlaced signal is generated from the line memory 601. Read SpB.

  The horizontal magnification coefficient Czh is input to the hold control circuit 605, and a hold control signal Chh is generated in a predetermined pattern determined by the horizontal magnification coefficient Czh. This pattern is the same as the pattern generated internally by the read control circuit 603.

  The non-interlace signal SpB is input to a delay element 604 capable of hold control, and the delay element 604 sequentially outputs a delay signal SpA in units of pixels while holding the non-interlace signal SpB according to the hold control signal Chh.

  Note that the read control circuit 603 and the hold circuit 605 activate the pixel-by-pixel hold function only when the enlargement process is performed in the horizontal direction.

The non-interlace signal SpB, the delay signal SpA and the horizontal magnification factor Czh are
Sph = (SpA−SpB) · k + SpB (k is the center of gravity value in Czh)
Is calculated by a subtractor 606, a multiplier 607, and an adder 608 so that an interpolated pixel signal Sph is output.

  The interpolated pixel signal Sph is input to a dual port line memory 609 having a capacity capable of holding at least one line of data and capable of independently controlling a clock and a read / write address.

  The horizontal synchronization signal HDp of the non-interlace signal and the horizontal magnification factor Czh are input to the write control circuit 610, and the write control circuit 610 holds the address Awh2 in a predetermined pattern determined by the horizontal magnification factor Czh, and the non-interlace 1 An address Awh2 is generated so that data of one line width is written in the line period, and the interpolation pixel signal Sph is held in the line memory 609.

  The horizontal synchronization signal HDp of the non-interlace signal is input to the read control circuit 611. The read control circuit 611 sequentially generates the address Arh2 so as to read the data of one line width in one non-interlace one line period, and from the line memory 609 The non-interlace signal Sph ′ is read out.

  Note that the write control circuit 610 activates the address hold function for each pixel only when the reduction process is performed in the horizontal direction.

  The non-interlace signal Sph 'is input to a memory 612 having a capacity capable of holding data for at least one field.

  The horizontal synchronization signal HDp of the non-interlace signal is input to the write control circuit 613, and the write control circuit 613 generates an address Awv1 so that one line of data is sequentially written in one non-interlace line period, and the memory 612 is non-interlaced. The signal Sph ′ is held.

  The non-interlaced signal horizontal synchronization signal HDp and the vertical magnification factor Czv are input to the read control circuit 614. The read control circuit 614 cuts out any part of the field in the vertical direction by setting the initial value of the address Arv1. The address Arv1 is held line by line in a predetermined pattern determined by the vertical scaling factor Czv, and the address Arv1 is generated so as to read out data of one field line in one field period of non-interlace. The non-interlace signal Sp2 is generated from the memory 612. Is read.

  The vertical magnification coefficient Czv is input to the hold control circuit 616, and a hold control signal Chv is generated in a predetermined pattern determined by the vertical magnification coefficient Czv. This pattern is the same as the pattern generated internally by the read control circuit 614.

  The non-interlace signal Sp2 is input to the line memory 615, and the line memory 615 sequentially outputs the delay signal Sp2 in units of pixels while holding the non-interlace signal Sp2 in units of lines according to the hold control signal Chv.

  Note that the read control circuit 614 and the hold circuit 616 activate the hold function in units of lines only when the enlargement process is performed in the vertical direction.

The non-interlace signal Sp2, the delay signal Sp1, and the horizontal magnification factor Czv are:
Spv = (Sp1-Sp2) · k + Sp2 (k is the center of gravity value in Czv)
Is calculated by a subtractor 617, a multiplier 618, and an adder 619 so that the interpolation pixel signal Spv is output.

  The interpolated pixel signal Spv is input to a memory 620 having a capacity capable of holding at least one field of data.

  The horizontal synchronization signal HDp of the non-interlace signal and the horizontal magnification coefficient Czv are input to the write control circuit 621, and the write control circuit 621 holds the address Awv2 in a predetermined pattern determined by the horizontal magnification coefficient Czv, and the non-interlace 1 An address Awv2 is generated so that data of one field line is written in the field period, and the interpolation pixel signal Spv is held in the memory 620.

  The non-interlaced signal horizontal synchronization signal HDp and the interlaced signal horizontal synchronization signal HDi are input to the read control circuit 622. When the output is non-interlace, the read control circuit 622 is one frame line of data in one frame period of non-interlace. The address Arv2 is generated sequentially so that the data is read out. If the output is interlaced, the address Arv2 is generated sequentially so that the data of one field line is read out in one field period of the interlace, and the interlace signal Sr is read out from the memory 620.

  Note that the write control circuit 621 activates the address hold function in units of lines only when the reduction process is performed in the vertical direction.

  In the case of a non-interlace signal, the video signal Sr obtained in this way is a non-interlace signal that has been subjected to high-definition IP conversion by motion adaptation and oblique adaptation processing, and at the same time has an enlargement / reduction ratio by electronic zoom. Accordingly, image quality deterioration due to IP conversion misjudgment that becomes conspicuous accordingly can be suitably suppressed, and as a result, a high-quality non-interlace signal can always be obtained.

  When the video signal Sr is an interlaced signal, high-definition IP conversion can be performed by shifting the vertical phase of the interpolated field image so that the non-interlaced signal is converted to an interlaced signal again by the enlargement / reduction circuit 6. The field image can be interpolated from the frame image while suitably suppressing deterioration in image quality due to IP conversion misjudgment, which becomes more conspicuous according to the enlargement / reduction ratio by electronic zoom, from the non-interlaced signal that has been performed. As a result, a high-quality interlace signal can always be obtained.

  The third embodiment of the present invention will be described. FIG. 14 is an example of a video signal processing block diagram suitable for the present invention.

  The present embodiment is an application system of the first and second embodiments described above, and is a video camera having a system configuration as shown in FIG. 14, for example.

  The image pickup device 141 such as a CCD outputs the accumulated electric charge as an electric signal at a video signal field rate (for example, 1/60 second), and converts it into a digital video signal through the CDS circuit 142, the AGC circuit 143, and the A / D converter 144. Converted.

  The camera signal processing circuit 145 performs camera signal processing such as color separation, white balance, contour compensation, and gamma processing on the input digital signal, and outputs an interlaced video signal.

  The IP conversion circuit 146 converts the input interlaced video signal into a non-interlaced video signal based on the above embodiment.

  The enlargement / reduction processing circuit 147 enlarges or reduces the input non-interlaced video signal or interlaced video signal based on the above-described embodiment, and converts it into a recording medium 148 represented by tape or semiconductor memory.

  The non-interlaced video signal or the interlaced video signal recorded in this way is subjected to high-definition IP conversion by motion adaptation and diagonal adaptation processing, and the image quality due to IP conversion misjudgment according to the enlargement / reduction ratio by electronic zoom. Deterioration can be suitably suppressed, and as a result, a high-quality video signal can always be recorded.

  The fourth embodiment of the present invention will be described. FIG. 15 is an example of a video signal processing block diagram suitable for the present invention.

  The present embodiment is an application system of the above-described first and second embodiments, and is a playback apparatus having a system configuration as shown in FIG. 15, for example.

  A recording medium 151 typified by a tape or a semiconductor memory outputs a digital signal of a recorded video signal at a video signal field rate (for example, 1/60 seconds) and inputs the digital signal to a reproduction signal processing circuit 152.

  The reproduction signal processing circuit 152 performs reproduction signal processing such as expansion processing and contour compensation on the input digital signal, and outputs an interlaced video signal.

  The IP conversion circuit 153 converts the input interlaced video signal into a non-interlaced video signal based on the above embodiment.

  The enlargement / reduction processing circuit 154 enlarges or reduces the input non-interlaced video signal or interlaced video signal based on the above-described embodiment, and converts it into a display medium 155 typified by a television monitor.

  The non-interlaced video signal or the interlaced video signal recorded in this way is subjected to high-definition IP conversion by motion adaptation and diagonal adaptation processing, and the image quality due to IP conversion misjudgment according to the enlargement / reduction ratio by electronic zoom. Deterioration can be suitably suppressed, and as a result, a high-quality video signal can always be displayed.

The figure which shows the 1st Example of this invention The figure which shows the example of the motion determination circuit of this invention The figure which shows the physical positional relationship of each signal of a motion determination circuit The figure which shows the example of the input / output characteristic of the offset circuit of the motion judgment circuit The figure which shows the example of the diagonal determination circuit of this invention The figure which shows the physical positional relationship of each signal of a diagonal determination circuit The figure which shows the example of the input / output characteristic of the offset circuit of the diagonal judgment circuit The figure which shows the example of the line interpolation circuit of 1st Example of this invention. The figure which shows the example of the line-sequentialization circuit of the line interpolation circuit of this invention Diagram showing an example of timing chart of line sequential circuit The figure which shows the example of the expansion / contraction circuit of this invention The figure which shows the 2nd Example of this invention The figure which shows the example of the line interpolation circuit of 2nd Example of this invention. The figure which shows the 3rd Example of this invention The figure which shows the 4th Example of this invention The figure which shows the example of the memory and memory control circuit of 2nd Example of this invention The figure which shows the example of the timing chart of a memory control circuit

Explanation of symbols

Si Interlace video signal input HDi Interlace signal horizontal synchronization signal HDp Non-interlace signal horizontal synchronization signal Czv Vertical magnification factor Czh Horizontal magnification factor Sp Non-interlace video signal output Sr Video signal after enlargement / reduction

Claims (4)

A memory having a capacity of at least one field that receives interlaced video signals interlaced and scanned in units of fields and sequentially delays the interlaced video signals in units of fields;
A motion determination circuit that performs motion determination of a video in a field in units of pixels from an input interlace signal and a video signal delayed by the memory, and outputs a motion determination coefficient;
A diagonal determination circuit that performs a pixel-by-pixel determination of a diagonal component of a video in a field from an input interlace signal and a video signal delayed by the memory, and outputs a diagonal determination coefficient;
A line interpolation circuit that performs an interpolating operation on a scanning line located between the scanning lines of the field in units of pixels from the motion determination coefficient and the oblique determination coefficient, and converts and outputs an interlaced video signal to a non-interlaced video signal;
An enlargement / reduction circuit that outputs the non-interlaced video signal output from the line interpolation circuit after being expanded or reduced in the horizontal and vertical directions;
In an image processing apparatus provided with a magnification coefficient generation circuit that generates horizontal and vertical magnification coefficients for interpolation calculation according to a magnification instructed from outside,
The enlargement / reduction circuit executes an enlargement / reduction process based on the horizontal and vertical magnification coefficients that are output from the magnification coefficient generation circuit, and the motion determination circuit and the oblique determination circuit correspond to the magnification coefficient. An image processing apparatus that outputs a motion determination coefficient and an oblique determination coefficient weighted to a determination result. A first memory having a capacity of at least one field that receives an interlaced video signal that is interlaced and operated in units of fields, and that sequentially delays the interlaced video signal in units of fields;
A motion determination circuit that performs motion determination of a video in a field in units of pixels from the input interlace signal and the video signal delayed in the first memory, and outputs a motion determination coefficient;
An oblique determination circuit for performing an oblique component determination of an image in a field from an input interlace signal and an image signal delayed in the first memory in units of pixels, and outputting an oblique determination coefficient;
A line interpolation circuit that performs an interpolating operation on a scanning line located between the scanning lines of the field in units of pixels from the motion determination coefficient and the oblique determination coefficient, and converts and outputs an interlaced video signal to a non-interlaced video signal;
A second memory having a capacity of at least one frame for holding a non-interlaced video signal output from the line interpolation circuit;
A memory control circuit for controlling writing and reading of the second memory;
An enlarging / reducing circuit for enlarging or reducing the non-interlaced video signal output from the second memory in the horizontal and vertical directions;
In an image processing apparatus provided with a magnification coefficient generation circuit that generates horizontal and vertical magnification coefficients for interpolation calculation according to a magnification instructed from outside,
The enlargement / reduction circuit executes an enlargement / reduction process based on the horizontal and vertical magnification coefficients that are output from the magnification coefficient generation circuit, and the motion determination circuit and the oblique determination circuit correspond to the magnification coefficient. The motion determination coefficient and the diagonal determination coefficient weighted to the determination result are output, and the memory control circuit writes or reads the second memory that holds the non-interlaced video signal that is line-interpolated according to the magnification coefficient. An image processing apparatus that performs control.   2. The motion determination circuit weights a motion determination result closer to the motion as the magnification coefficient is closer to an enlargement side, and increases intra-field interpolation processing by scanning line interpolation calculation in units of pixels. Or the image processing apparatus of 2.   The oblique determination circuit weights the oblique determination result closer to the vertical direction as the magnification coefficient is closer to the enlargement side, so that the interpolation processing in the vertical direction is increased by the scanning line interpolation calculation in pixel units. The image processing apparatus according to claim 1.

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