JP2007094603A - Programmable device control unit and programmable device control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a programmable device control unit and a programmable device control method which can easily perform addition or modification of a function block comprising a programmable device. <P>SOLUTION: The programmable device control method in this invention comprises; a read-out step which reads a classification code 31 which indicates a use of a plurality of FPGAs 5 connected to a control unit 1 (S4); a retrieval step which retrieves a program corresponding to the above classification code 31 (S5); and an individual program write step (S6) which writes a program retrieved by the above retrieval step (S5) in each FPGA 5. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a programmable device control apparatus and a programmable device control method, and more particularly to a programmable device control apparatus and a programmable device control method for automatically programming a programmable device.

  The programmable device is an LSI in which a circuit can be arbitrarily formed by a user writing a program. As programmable devices, there are a field programmable gate array (FPGA), a programmable logic device (PLD), and the like.

  A programmable device uses a volatile memory element, and it is necessary to write a program and form a circuit every time after power-on.

FIG. 9 is a block diagram of a conventional programmable device control apparatus.
As shown in FIG. 9, the conventional programmable device control apparatus arrange | positions ROM102 which memorize | stored the program to write with respect to each FPGA101. The conventional programmable device writes a program stored in the ROM 102 corresponding to each FPGA 101 after power-on. However, the above method has a problem that it is troublesome to change the ROM 102 corresponding to each FPGA 101 in order to change the program written in each FPGA 101.

  As a method of solving the above problem, there is a method of storing a program to be written in the FPGA 101 in a control device such as a processor or a host computer (for example, Patent Document 1).

  FIG. 10 is a block diagram of a conventional programmable device control apparatus that stores a program to be written in the FPGA 101 in a control apparatus such as a processor or a host computer.

  The programmable device control apparatus illustrated in FIG. 10 collectively stores a plurality of programs to be written in the plurality of FPGAs 101 in the ROM 105 in the processor 103. Thereby, it is possible to collectively manage programs to be written to the FPGAs 105.

As another method, there is a method of reading a program stored in a host computer or the like into the RAM 106 of the processor and writing it into the FPGA 101 via the external I / F 107.
JP 2002-342085 A

  However, in the method of storing a program to be written in the FPGA 101 in a control device such as a processor or a host computer, the control device needs to have information on which program to be written in which FPGA 101 connected to the control device. There is. Therefore, when adding or changing a functional block having the FPGA 101, the user needs to newly input information on a program to be written in the FPGA 101 to the control device. That is, the user needs to make a hardware change for adding or changing a functional block having the FPGA 101 connected to the control device and a software change for adding or changing program information to be written to the FPGA. Therefore, there is a problem that it is troublesome to add or change a functional block having the FPGA 101.

  Therefore, an object of the present invention is to provide a programmable device control apparatus and a programmable device control method capable of easily adding or changing a functional block having a programmable device such as the FPGA 101.

  In order to achieve the above object, a programmable device control method according to the present invention includes a reading step of reading a type code indicating a use of a plurality of programmable devices connected to a control device, and searching for program data corresponding to the type code. And a separate program writing step for writing the program data searched in the search step to each programmable device.

  Thereby, the program data to be written in each programmable device is retrieved from the identification code. That is, the control device automatically searches for program data to be written to each programmable device from the identification code, even if it does not have information on the program data to be written to each programmable device. Therefore, it is not necessary to change the program of the control device when changing or adding a programmable device connected to the control device. That is, it is not necessary to change the software of the control device only by changing (hardware changing) the programmable device connected to the control device. Moreover, even if it does not change a programmable device, a function change can be performed only by changing a classification code. Therefore, the programmable device control method of the present invention can easily add or change a programmable device.

  The programmable device control method further includes a common program write step for writing a common program to the plurality of programmable devices, and the read step is classified by a circuit formed in the programmable device by the written common program. The code may be read.

  Thereby, an identification code reading circuit is formed in each programmable device. Therefore, even when the functional block having each programmable device does not have an identification code reading function, the identification code can be read by using the identification code reading circuit formed in each programmable device.

  The programmable device control method further includes a number determination step for determining the number of the plurality of programmable devices, and in the reading step, a type code is read based on a determination result in the number determination step, and the common In the program writing step, a common program is written in a plurality of programmable devices based on the determination result in the number determination step, and in the individual program writing step, individual programs are written in the plurality of programmable devices based on the determination result in the number determination step. You may write.

  Thereby, the number of programmable devices connected to the control device can be determined. Therefore, even when the control device does not have information on the number of programmable devices connected to the control device, information on the number of programmable devices connected automatically can be determined.

  In addition, the programmable device control method further includes a function determination step of determining a specific specification of each programmable device by reading a function code indicating a specific specification of the programmable device that each of the plurality of programmable devices has. In the reading step, a type code is read based on the determination result in the function determination step, and in the common program writing step, a common program is written in a plurality of programmable devices based on the determination result in the function determination step. In the individual program writing step, the individual program may be written in a plurality of programmable devices based on the determination result in the function determination step.

  Thereby, the specific specifications (terminal information, operation speed, capacity, etc.) of the programmable device connected to the control device can be determined. Therefore, even when the control device does not have the information on the specific specification of the programmable device connected to the control device, the information on the specification specific to the programmable device connected to the control device can be automatically determined.

  In the number determination step, the number of programmable devices may be determined using a circuit in which first shift registers included in the plurality of programmable devices are connected in series.

  The circuit formed by the common program has a second shift register, and the plurality of second shift registers of the plurality of FPGAs are connected in series, and in the reading step, the circuits are connected in series. The type code may be read by a circuit formed by a plurality of second shift registers.

  The present invention can be realized not only as such a programmable device control method, but also as a program for causing a computer to execute characteristic steps included in the programmable device control method. Moreover, it is also realizable as a programmable device control apparatus which makes the characteristic step included in the programmable device control method a means.

  The present invention can provide a programmable device control apparatus and a programmable device control method capable of easily adding or changing a functional block having a programmable device such as the FPGA 101.

  Embodiments of a programmable device control apparatus according to the present invention will be described below in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a programmable device control apparatus according to the present embodiment.

  The programmable device control device shown in FIG. 1 includes a control device 1, a functional block 2, a functional block 3, and a termination device 4.

  The control device 1 is a processor or the like that controls the function block 2 and the function block 3.

The functional blocks 2 and 3 include an FPGA 5 and a type code storage unit 6.
The FPGA 5 is a programmable device that forms an arbitrary circuit configuration by a written program.

  The type code storage unit 6 stores a type code 31 indicating the usage of the functional blocks 2 and 3. The type code 31 is a code indicating information of a program written in the FPGA 5 of each functional block 2 and 3. For example, the type code storage unit 6 stores the type code 31 by a combination of wirings on the board.

  The termination device 4 loops back the signal output from the functional block 3 and outputs it to the functional block 3.

  The control device 1 is connected to the functional block 2. The functional block 2 is connected to the control block 3. The functional block 3 is connected to the termination device 4.

  The control device 1, the functional block 2, the functional block 3 and the termination device 4 have two signal paths 7 and 8. The signal paths 7 and 8 are connected in the order of the control device 1, the function block 2, the function block 3, and the termination device 4. The signal paths 7 and 8 are turned back at the terminating device 4 and are connected in the order of the functional block 3, the functional block 2, and the control device 1. Thus, each signal path 7 and 8 forms a loop.

The signal path 7 is used for writing a program to each FPGA 5.
The signal path 8 is used for reading the type code 31.

FIG. 2 is a block diagram of the control device 1 shown in FIG.
The control device 1 includes an I / O control unit 10 and 14, a number determination unit 11, a function determination unit 12, a common program writing unit 13, a type code reading unit 15, a type code data storage unit 16, and a program. A data storage unit 18, a program search unit 20, and an individual program writing unit 21 are provided.

  The I / O control unit 10 is an input interface that exchanges signals between the signal path 7 and the control device 1.

  The number determination unit 11 determines the number of functional blocks connected to the control device 1 and the connection order from the signal input from the signal path 7 via the I / O control unit 10.

  The function determination unit 12 determines specific specifications (terminal information, operation speed, capacity, etc.) of each functional block from the signal input from the signal path 7 via the I / O control unit 10.

  Based on the determination results of the number determination unit 11 and the function determination unit 12, the common program writing unit 13 sends a common program and a common program write command to the functional blocks 2 and 3 via the I / O control unit 10 and the signal path 7. send. Here, the common program is a program that forms a circuit for reading the type codes 31 of the functional blocks 2 and 3.

  The I / O control unit 14 is an input interface that exchanges signals between the signal path 8 and the control device 1.

  The type code reading unit 15 reads the type code 31 indicating the use of each functional block 2 and 3 from the signal path 8 via the I / O control unit 14.

  The type code data storage unit 16 is a hard disk or the like that stores type code data 17 indicating the relationship between the type code 31 and a program written in the FPGA 5.

  The program data storage unit 18 is a hard disk or the like that stores a plurality of program data 19 to be written in the FPGA 5.

  The program search unit 20 determines the function block 2 from the type code 31 of each functional block 2 and 3 read by the type code reading unit 15 and the type code data 17 stored in the type code data storage unit 16. And search for a program to write to 3.

  Based on the search result of the program search unit 20, the individual program writing unit 21 sends the write program data 19 to each functional block to each functional block via the I / O control unit 10 and the signal path 7.

  FIG. 3 is a block diagram showing a configuration of the functional block 2 shown in FIG. The functional block 3 has the same configuration.

  The functional block 2 includes an FPGA 5, a type code storage unit 6, an I / O control unit 32, and a program writing unit 33.

  The I / O control unit 32 exchanges signals between the functional block 2 and the signal path 7. Although not shown here, the I / O control unit 32 includes a shift register. The I / O control unit 32 stores a function code indicating the function of the function block. For example, the I / O control unit 32 is formed by a JTAG circuit or the like.

  The program writing unit 33 writes the program data 19 sent from the control device 1 via the I / O control unit 32 to the FPGA 5.

  The signal path 7 includes an I / O control unit 10 of the control device 1, an I / O control unit 32 of the functional block 2, an I / O control unit 32 of the functional block 3, an end device 4, and an I / O control of the functional block 3. The loop loop path | route electrically connected in series of the part 32, the I / O control part 32 of the functional block 2, and the I / O control part 10 of the control apparatus 1 is comprised. The signal path 8 includes the I / O control unit 14 of the control device 1, the FPGA 5 of the functional block 2, the FPGA 5 of the functional block 3, the termination device 4, the FPGA 5 of the functional block 3, the FPGA 5 of the functional block 2, and the control device 1. A folded loop path that is electrically connected in series in the order of the I / O control unit 14 is configured.

  In the signal path 7, the I / O control unit 32 of the functional block 2 and the shift register of the I / O control unit 32 of the functional block 3 are connected in series.

Next, the operation of the programmable device control apparatus in the present embodiment will be described.
FIG. 4 is a flowchart showing a program write operation of the programmable device control apparatus according to the present embodiment.

  When power is turned on to the programmable device control device, the program write operation of the FPGA connected to the control device 1 is started.

  FIG. 5 is a diagram schematically showing the circuit configuration of the functional blocks 2 and 3 when the power is turned on. As shown in FIG. 5, no program is written in the FPGA 5 of the functional blocks 2 and 3 when the power is turned on, and no circuit is formed in the FPGA 5. As shown in FIG. 5, the I / O control unit 32 includes a shift register 51.

  First, the number determination unit 11 of the control device 1 determines the number of functional blocks having the FPGA 5 connected to the control device 1.

  FIG. 6 is a diagram illustrating a timing chart of signals used for determining the number of connected functional blocks. An output signal 62 illustrated in FIG. 6 is a signal output from the number determination unit 11. Data 63 is data held by the shift register 51 of the I / O control unit 32 of the functional block 2. Data 64 is data held by the shift register 51 of the I / O control unit 32 of the functional block 3. The input signal 65 is a signal input to the number determination unit 11. Note that when the power is turned on, the data held in each shift register 51 of the I / O control unit 32 of the functional block 2 and the functional block 3 is at the L level.

  The number determination unit 11 outputs a clock signal 61 and an output signal 62 as shown in FIG. 6 to the signal path 7 via the I / O control unit 10. The clock signal 61 and the output signal 62 are sent to the shift register 51 provided in the I / O control unit 32 of the functional block 2. Thus, at time T1, the shift register 51 included in the I / O control unit 32 of the functional block 2 captures the signal level of the output signal 62 in synchronization with the rising edge of the clock signal 61. That is, the data 63 stored in the shift register 51 included in the I / O control unit 32 of the functional block 2 is at the H level. The data 63 is sent to the serial input of the shift register 51 provided in the I / O control unit 32 of the functional block 3. Thereby, at time T2, the shift register 51 included in the I / O control unit 32 of the functional block 3 captures the signal level of the data 63 in synchronization with the rising edge of the clock signal 61. That is, the data 64 held by the shift register 51 included in the I / O control unit 32 of the functional block 3 is at the H level. The data 64 is input to the number determination unit 11 via the terminal device 4, the function block 3, and the function block 2. The number determination unit 11 determines the number of connected functional blocks by counting the number of clocks from when the H level is output to the output signal 62 until the input signal 65 changes to the H level. That is, after the H level is output to the output signal 62, the input signal 65 changes to the H level in 2 clocks, so the number determination unit 11 determines that there are two connected functional blocks (S1). .

  Next, the function determination unit 12 of the control device 1 sends an instruction to output the function code stored in the I / O control unit 32 to the I / O control unit 32 of each functional block via the signal path 7. send. The I / O control unit 32 of each functional block outputs a function code in accordance with the sent instruction. The output function code is sent to the function determination unit 12 via the signal path 7. The function determination unit 12 determines the specific specifications (terminal information, operation speed, capacity, etc.) of each function block from the type code 31 sent and the table stored in the function determination unit 12 (S2). ).

  The common program writing unit 13 of the control device 1 sends a common program write command to each functional block based on the number of functional blocks determined in steps S1 and S2 and the specific specifications. That is, the common program writing unit 13 sends the common program and the write command to the signal path 7 via the I / O control unit 10. The I / O control unit 32 of each functional block sends the sent common program to the program writing unit 33. The program writing unit 33 writes the common program to the FPGA 5. Thereby, the FPGA 5 configures a circuit for reading the type code 31 stored in the type code storage unit 6 (S3). FIG. 7 is a diagram schematically showing the circuit configuration of the functional blocks 2 and 3 after writing the common program. As shown in FIG. 7, a shift register 71 is formed in the FPGA 5. The shift register 71 is connected to the signal path 8 and the type code storage unit 6. The shift register 71 has a function of taking the type code 31 stored in the type code storage unit 6 and outputting it to the signal path 8. The shift register 71 of each functional block is electrically connected in series via the signal path 8.

  The type code reading unit 15 of the control device 1 sends a read command of the type code 31 to each functional block based on the number of functional blocks determined in steps S1 and S2 and the specific specifications. That is, the type code reading unit 15 sends a type code reading command to the signal path 8 via the I / O control unit 14. The I / O control unit 32 of each functional block receives a type code read command from the signal path 8 and sends the sent command to the FPGA 5. The FPGA 5 reads the type code 31 stored in the type code storage unit 6 in accordance with the sent instruction. That is, the shift register 71 formed in the FPGA 5 takes in the type code 31 and sequentially outputs it to the signal path 8. The read type code 31 is sent to the type code reading unit 15 via the signal path 8 and the I / O control unit 14 (S4).

  The program search unit 20 of the control device 1 writes a program to each functional block from the type code 31 of each functional block sent to the reading unit 15 and the type code data 17 stored in the type code data storage unit 16. Data 19 is searched (S5).

  The individual program writing unit 21 acquires the program data 19 to be written to each functional block from the search result by the program search unit 20. The individual program writing unit 21 sends the acquired program data 19 to each functional block based on the number of functional blocks determined in steps S1 and S2 and the specific specifications. That is, the individual program writing unit 21 sends a program write command and program data 19 to be written to the FPGA 5 of each functional block to the signal path 7 via the I / O control unit 10. The I / O control unit 32 of each functional block sends the transmitted program data 19 to the program writing unit 33. The program writing unit 33 writes the program data 19 to the FPGA 5. Thereby, the FPGA 5 configures a circuit having a function corresponding to the type code 31 stored in the type code storage unit 6 (S6). FIG. 8 is a diagram schematically showing the circuit configuration of the functional blocks 2 and 3 after the program is written in step S6. As shown in FIG. 8, for example, an I / O control unit 81, a control unit 82, and processing units 83 and 84 are formed in the FPGA 5. The I / O control unit 81 exchanges signals with the control device 1 and other functional blocks via the signal path 85. The control unit 82 controls the processing units 83 and 84. The processing units 83 and 84 have arbitrary processing functions corresponding to the written program data 19. For example, the processing units 83 and 84 perform image processing or sound processing.

  As described above, the programmable device control apparatus according to the present embodiment determines the number of functional blocks connected to the control apparatus 1 in step S1. Thereby, even when the control device 1 does not have information on the number of functional blocks connected to the control device 1, the number of functional blocks connected to the control device 1 can be automatically determined. .

  In step S <b> 2, the unique specification of the functional block connected to the control device 1 is determined. Thereby, even when there is no information on the specific specification of the functional block connected to the control device 1, the information on the specific specification of the functional block connected automatically can be determined.

  In steps S3 to S5, a program for reading the type code 31 of each functional block is written, and the type code 31 is read. Thereby, even if the control apparatus 1 does not have the information of the program written in FPGA5 of each functional block, the program written in FPGA5 of each functional block can be determined automatically. Therefore, there is no need to change the program of the control device 1 when changing or adding a function block to be connected. That is, it is not necessary to change the software of the control device 1 simply by changing the function block connected to the control device 1 (hardware change). Even if the function block is not changed, the function of the programmable device control device can be changed only by changing the type code 31. Therefore, the programmable device control apparatus according to the present embodiment can easily add or change a functional block having a programmable device such as FPGA5.

  The programmable device control apparatus according to the embodiment of the present invention has been described above, but the present invention is not limited to this embodiment.

  For example, the programmable device control device in the above embodiment returns the signal via the termination device 4, but the termination device 4 may not be used. For example, the signal may be folded by wiring on the substrate.

  In the above description, two functional blocks are connected to the control device 1, but the number of functional blocks connected to the control device 1 is not limited to this.

  In the above description, the functional blocks 2 and 3 connected to the control device 1 include the FPGA 5, but may include a functional block that does not include the FPGA 5.

  In the above description, the signal path 7 and the signal path 8 are connected in the order of the control device 1, the function block 2, the function block 3, the termination device 4, the function block 3, the function block 2, and the control device 1. That is, a loop path that passes through each functional block is formed on both the upstream and downstream paths, but a loop path that passes through each functional block may be formed on either the upstream or downstream path. That is, the signal path may be formed in the order of the control device 1, the functional block 2, the functional block 3, the termination device 4 and the control device 1. Further, the signal path may be formed in the order of the control device 1, the termination device 4, the functional block 3, the functional block 2, and the control device 1.

  In the above description, each functional block includes one FPGA 5, but may include a plurality of FPGAs 5. When each functional block includes a plurality of FPGAs 5, a plurality of type codes 31 corresponding to the respective FPGAs are stored in the type code storage unit 6 of each functional block.

  Further, the type code data 17 is stored in the type code data storage unit 16 in the control device 1, but is not limited thereto. For example, the type code data 17 may be stored in a host computer or the like via a network, and the control device 1 may read and use the type code data 17.

  Further, the program data 19 is stored in the program data storage unit 18 in the control device 1, but is not limited thereto. For example, the program data 19 may be stored in a host computer or the like via a network, and the control device 1 may read and use the program data 19.

  In the above description, the program write operation is started when the power is turned on, but the program write operation may be started by an operation such as an external command input other than when the power is turned on.

  The present invention can be applied to a programmable device control apparatus and a programmable device control method, and in particular, a programmable device control apparatus such as industrial control electronic equipment, digital AV application equipment, wired communication equipment, wireless communication equipment, and satellite communication equipment using an FPGA. And can be applied to a programmable device control method.

It is a block diagram of the programmable device control apparatus in this invention. 2 is a block diagram of a control device 1. FIG. 3 is a block diagram of a function block 2. FIG. It is a flowchart which shows a program write operation. It is a figure which shows the circuit structure of the functional block 2 at the time of power activation. It is a figure which shows the timing chart of the signal used for number determination of a functional block. It is a figure which shows the circuit structure of the functional block 2 after writing a common program. It is a figure which shows the circuit structure of the functional block 2 after program writing. It is a block diagram of the conventional programmable device control apparatus. It is a block diagram of the conventional programmable device control apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Control apparatus 2, 3 Function block 4 Termination apparatus 5, 101 FPGA
6 Type code storage unit 7, 8, 85 Signal path 10, 14, 32, 81 I / O control unit 11 Number determination unit 12 Function determination unit 13 Common program writing unit 15 Type code reading unit 16 Type code data storage unit 17 Type Code data 18 Program data storage unit 19 Program data 20 Program search unit 21 Individual program writing unit 31 Type code 33 Program writing unit 51, 71 Shift register 61 Clock signal 62 Output signal 63, 64 Data 65 Input signal 82 Control unit 83, 84 Processing unit 102, 105 ROM
103 processor 104 CPU
106 RAM
107 External I / F

Claims (14)

A reading step of reading out a type code indicating the use of a plurality of programmable devices connected to the control device;
A search step for searching for program data corresponding to the type code;
A programmable device control method comprising: an individual program writing step of writing the program data searched by the searching step to each programmable device. The programmable device control method further includes:
A common program writing step of writing a common program to the plurality of programmable devices,
The programmable device control method according to claim 1, wherein in the reading step, a type code is read by a circuit formed in the programmable device by the written common program. The programmable device control method further includes:
A number determination step of determining the number of the plurality of programmable devices,
In the reading step, the type code is read based on the determination result in the number determination step,
In the common program writing step, based on the determination result in the number determination step, a common program is written in a plurality of programmable devices,
3. The programmable device control method according to claim 2, wherein in the individual program writing step, the individual program is written in a plurality of programmable devices based on a determination result in the number determination step. The programmable device control method further includes:
Each of the plurality of programmable devices has a function determination step of determining a specific specification of each programmable device by reading a function code indicating a specific specification of the programmable device,
In the reading step, the type code is read based on the determination result in the function determining step,
In the common program writing step, a common program is written in a plurality of programmable devices based on the determination result in the function determination step. In the individual program writing step, individual programs are written in a plurality of programmable devices based on the determination result in the function determination step. The method of controlling a programmable device according to claim 2 or 3, wherein: The programmable device control method according to claim 3, wherein in the number determination step, the number of programmable devices is determined using a circuit in which first shift registers included in the plurality of programmable devices are connected in series. The circuit formed by the common program has a second shift register,
A plurality of second shift registers of the plurality of FPGAs are connected in series;
The programmable device control method according to claim 2, wherein in the reading step, a type code is read by a circuit formed by the plurality of second shift registers connected in series. A reading step of reading out a type code indicating type information of a plurality of programmable devices connected to the control device;
A search step for searching for program data corresponding to the type code;
A program for causing a computer to execute an individual program writing step of writing program data searched by the searching step to each programmable device. A plurality of programmable devices connected to the controller;
Type code storage means for storing a type code indicating the use of each programmable device;
Reading means for reading out the type code;
Program data storage means for storing a plurality of program data to be written to the plurality of programmable devices;
Search means for searching program data corresponding to the read type code from the plurality of program data;
Programmable device control apparatus, comprising: individual program writing means for writing program data searched by the search means to each programmable device. The programmable device controller further includes:
A common program writing means for writing a common program to the plurality of programmable devices,
The programmable device control apparatus according to claim 8, wherein the reading unit reads a type code by a circuit formed in the programmable device by the written common program. The programmable device controller further includes:
Comprising a number determination means for determining the number of the plurality of programmable devices,
The reading means reads the type code based on the determination result by the number determining means,
The common program writing means writes a common program to a plurality of programmable devices based on the determination result by the number determination means,
The programmable device controller according to claim 9, wherein the individual program writing unit writes the individual program to a plurality of programmable devices based on a determination result by the number determination unit. Each programmable device comprises a function code storage means for storing a function code indicating a specific specification of each programmable device,
The programmable device controller further includes:
By reading the function code stored in the function code storage means of each programmable device, it comprises a function determination means for determining the specific specifications of each programmable device,
The reading means reads the type code based on the determination result by the function determining means,
The common program writing means writes a common program to a plurality of programmable devices based on the determination result by the function determining means. The individual program writing means is an individual program for a plurality of programmable devices based on the determination result by the function determining means. The programmable device control apparatus according to claim 9 or 10, wherein: Each of the programmable devices includes a first shift register,
The first shift register of each programmable device is electrically connected in series;
The programmable device control apparatus according to claim 11, wherein the number determination means determines the number of programmable devices using a circuit in which the first shift registers are connected in series. The circuit formed by the common program includes a second shift register,
A plurality of second shift registers of the plurality of programmable devices are electrically connected in series;
The programmable device control apparatus according to claim 9, 10, 11, or 12, wherein the reading unit reads a type code by a circuit formed by the plurality of second shift registers connected in series. The programmable device control apparatus according to claim 13, wherein the type code is formed by a combination of wirings on a substrate.

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