JP2003258609A - Noise-eliminating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problems that even a reset signal is delayed in passing through by using a delay means, when performing an operational test, etc., in an IC which embeds a noise-eliminating circuit using the delay means, and a conventional test pattern can no longer be used, because the reset timing of only a delay time is changed with respect to original reset timing. <P>SOLUTION: A noise-eliminating circuit for performing an AND calculation/ output of two signals given a time difference from an original signal by the delay means, etc., is provided with a selecting means for selecting freely signals which pass through the noise-eliminating circuit and signals not passing through the eliminating circuit. The eliminating circuit can cope over a wider range of applications by bringing the time widths of signals to be eliminated and considered as noises into free selections. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise removing circuit for removing pulse or spike noise in a computer device or the like.

[0002]

2. Description of the Related Art A conventional noise removal circuit for removing pulse or spike noise in a computer or the like is an AND circuit for a delayed signal passing through a delay means for delaying an input original signal and an original signal not passing through the delay means. To the number n by outputting the result of AND operation
If the noise has a width of (nano) seconds, the delay signal having a time difference larger than the noise width and the original signal are input to the AND circuit, and the AND operation is performed to output the noise. Was.

[0003]

However, in the case of an IC having a built-in noise removing circuit using a delay means, for example, a reset signal necessary for carrying out an operation test of the IC is subject to delay. However, the delay of the reset signal when passing through the delay means changes the reset timing from the original reset timing by the delay time of the reset signal.

Then, with reference to the timing of the reset signal necessary for performing the operation test of the IC,
For each time event, Hi (hereinafter referred to as “1”) of various signals output from the IC pin, or Lo
The test pattern defining the w (hereinafter referred to as “0”) output pattern cannot be used.

Therefore, according to the present invention, a general test pattern which cannot be used as it is in a conventional noise removing circuit which outputs an AND operation of two signals in which an original signal has a time difference by a delay means or the like can be used as it is. The purpose is to provide such a noise removal circuit.

If the time width of the signal is less than a predetermined value, it is regarded as noise and removed based on the operating principle of the noise removing circuit. If fixed, there was a drawback that the use of the noise removal circuit was limited.

Therefore, it is also an object to provide a noise removing circuit which can be more versatile by allowing the time width of a signal to be removed as noise to be arbitrarily selected.

[0008]

In order to achieve the above object, the present invention provides a delay means for delaying an input original signal, a delay signal passing through the delay means and an original signal not passing through the delay means. A noise removing circuit including an AND circuit that outputs a result of an AND operation includes a selecting unit that selectively selects a signal passing through the noise removing circuit and a signal not passing through the noise removing circuit. By doing so, even in the case of an IC having a built-in noise removing circuit using the delay means, the reset timing is changed from the original reset timing with respect to the reset signal necessary for the operation test of the IC. Since it can be retained, it can be used as it is even with the conventional test pattern.

Further, since the present invention is provided with the delay means whose function is increased / decreased by switching and connecting a plurality of stages, and the selector for effectively circuit-connecting only an arbitrary number of stages by the switching connection of the delay means, The delay time of the delay signal delayed by the delay means with respect to the original signal can be arbitrarily selected. Here, the time width of a signal that should be removed as noise is determined by the delay time. Therefore, by making it possible to arbitrarily select the time width of the signal to be removed as noise, it is possible to cope with more versatility.

Further, according to the present invention, the clock counting means for measuring the number of pulses of the reference frequency that can be included in the time width of the input signal, and the time width measured by the clock counting means is a threshold value set in advance. Since the input signal selection means that makes only the signals exceeding
By allowing the time width of a signal to be removed as noise to be removed to be arbitrarily selected, it is possible to cope with more versatility.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a noise removing circuit according to the present invention will be described below with reference to the drawings. In the present embodiment, a case will be described as an example where a noise removal circuit using a delay means is built in the reset terminal of the IC.

FIG. 1 is a first embodiment of the present invention and is a block diagram showing a relevant portion of an IC having a built-in noise elimination circuit. The input terminal 101 is generally called a PAD, and is electrically connected to the outside of an IC package (not shown) via a pin. The reset signal R is input from the input terminal 101 and branched into two paths. That is, the noise removing circuit 1
No. 02, and a second path passing through the noise removing circuit 2, and are respectively connected to the selecting means 103.

The selecting means 103 has a selector 30,
The first path and the second path respectively connected to the selector 30 are selectively selected, and only the signal passing through the selected path is output from the output terminal 104, and the internal reset of the circuit not shown. Are connected to be used. Detailed operation of the selection means 103 will be described later with reference to FIG. In addition,
The output terminal 104 is a name for convenience of description, and is not actually a terminal electrically connected to the outside of the IC package via a pin.

A decoder 31 and a register 3 for supplying a selection signal S for controlling the selector 30 to the selection means 103.
There are two, and each operates like a D flip-flop. However, since the decoder 31 is not a D flip-flop, its operation is as shown in the flowchart of FIG. The chip enable signal CE and the write signal WR are input to the decoder 31, and the decoder 31, the register 32, and the selector 30 perform a timing control operation described later with reference to FIG. In the figure, the chip enable signal CE and the write signal WR are drawn with an upper line meaning active Low, but the upper line is omitted in the specification.

FIG. 2 is a time chart showing the operation of the noise removing circuit. On the same time axis, the signal names are named address signal AD, data signal Data, chip enable signal CE, write signal WR, register WR signal W in order from the top.
R, a selection signal S, and six types of signals are shown. These signals will be described below by abbreviating the signals and using only the reference numerals.

AD is a signal which gives an address to the memory for reading or writing Data according to a predetermined cycle time. The timing for alternately designating addresses of 0Ah (the end h is hexadecimal representation) and FFh is formed by AD. CE is Low (hereinafter, “L” or “0”) at a timing corresponding to address 0Ah.
Is abbreviated), Data is assigned to address 0Ah.
Can read or write. D when WR is L
ata is written.

Now, when AD is input to the input terminal A1 of the decoder 31, CE is input to the input terminal A2, and the write signal WR is input to the trigger input terminal A3, a trigger pulse for determining the operation timing is added by L. , The decoder 31 operates similarly to the D flip-flop, and since CE is L, the same timing waveform as WR has the trigger input terminal C of the register 32.
The register WR signal WR is added as a trigger pulse at H. Data is input to the data input terminal D of the register 32, the register 32 performs a D flip-flop operation so as to match H and L of the data, and the selection signal S is shown in FIG. The selector 30 is controlled as described above.

The selector 30 selects the first path 111 when the selection signal S is 1, and selects the second path 112 when the selection signal S is 0. Then, the noise removal circuit 102 is used only during S = 0, and the noise removal circuit 102 is not used during S = 1. In this way, the selection means 103 performs a selection operation as needed.

The delayed signal when the noise removing circuit 102 is operated and the undelayed signal when the noise removing circuit 102 is not operated are
If they are mixed in an unstable manner, the reset operation or the like will be hindered. Therefore, the noise removal circuit 102 may be fixed so as not to operate when resetting.

FIG. 3A shows an example of a conventional test pattern for confirming the operation of an IC (not shown).
The output of the output terminal OUT in response to the input signals to the respective input terminals IN0, IN1, IN2, RESET is described in order of time events 1 to 10 from top to bottom.
An accurate test is realized by setting the reset signal to 1 at time events 1 to 3 to reset the circuit. To enable the test with this test pattern,
It is essential that there is no time lag in the reset signal that serves as the timing reference for the signals input to and output from each terminal.

However, when the noise removing circuit 102 using the delay means is built in the reset terminal of the IC like the circuit shown in FIG. 1, there is a delay time defined by the delay means while passing through the noise removing circuit 102. Reset signal is I
Acts on C. In that case, a time lag occurs in the reset signal serving as the timing reference of the signal input to and output from each terminal of the IC, and the time corresponding to the time events 1 to 3 of the test pattern shown in FIG. 3B is delayed. The test result is invalid for the time corresponding to the time events 1 to 3. Therefore, the conventional test pattern cannot be used. Then, the time events 4 to 1 of FIG.
3 required a new test pattern to match the time events 1-10 of FIG. 3 (a).

Therefore, even if the noise removing circuit 102 using the delay means is built in the reset terminal of the IC as in the circuit shown in FIG. 1, it is not necessary to prepare a new test pattern corresponding to the delay time. I am trying to do it.

FIG. 4A shows an example of a conventional noise removing circuit using a delay means and an AND circuit. A signal input from the input terminal 40 is directly input to the AND circuit 46 via the path 41. In addition, AND from the path 42 passing through the delay means 45 set to the delay time of 100 nS
Input to the circuit 46, ANDed, and output terminal 4
4 outputs a signal for internally resetting an IC (not shown). FIG. 4B is a time chart for explaining the operation principle of the noise removal circuit shown in FIG. 4A, and in the case where pulsed noise having a pulse width of 50 nS enters from the input terminal 40, each part This is a waveform observation of the signal. FIG. 4 (c) shows a delay circuit to which the time constant of the charging / discharging time by the resistor and capacitor used in the delay means 45 is applied, but the description thereof is omitted because it is well known.

With reference to FIG. 4B, it will be explained that there is a harmful effect that the operation of removing noise and the timing of a regular reset signal (not shown) are deviated during the noise removing operation. When the pulsed noise passes through the set delay means 45, a delay time of 100 nS is generated and the pulsed noise is input from the path 42 to the AND circuit 46. As shown, 50n
The pulsed noise having a pulse width of S is not output from the output terminal 44 as a result of being AND-processed with the delay signal of the path 42 which causes the delay time 100 nS which is longer than the pulse width, and the noise is removed. This means that the first 100 nS is removed even with a regular reset signal. Therefore, when 100 nS to be removed causes a malfunction, the delay time needs to be shorter than 100 nS. Further, it is not possible to remove noise having a pulse width larger than 100 nS.

Further, the noise removing circuit having a fixed delay time cannot remove noise having a time width exceeding the delay time of the delay means. On the contrary, the delay of the noise of the minute pulse becomes excessive, so that the time regulation of the input signal is excessively extended so as not to do so. Therefore, as a second embodiment, by switching the connection of a plurality of delay circuits,
By providing a register or the like capable of setting a desired optimum delay time in accordance with the noise removal width and appropriately changing the delay time setting, noise of any width can be reliably removed.

FIG. 5 is a second embodiment of the present invention, and is a block diagram showing a relevant part of an IC having a built-in noise eliminator circuit capable of selecting multistage delay times.
The noise removal circuit from 0 to the output terminal 62 basically operates in the same manner as the noise removal circuit shown in FIG. First, the signal input from the input terminal 50 is directly input to the AND circuit 46 via the path 43. Then, the delay means 56, 57, 58, and 59, which generate delay times of 100 nS, are connected in series to each other for convenience.
The path 55 that causes a delay time of 0 nS and the delay time 0 of each delay means
~ Routes 51, 5 that branch off every four passes
2, 53, 54 are set. Here, the input terminal 5
The signal input from 0 is branched, and one of the branched signals is input to the AND circuit 46 from the path 43 that does not cause a delay time. On the other hand, the signal input from the input terminal 50 passes through the paths 51, 52,
The signals of 53, 54, and 55 are selected by the selector 60 and input to the AND circuit 46 via the path 61. The selector 60 operates as a selection switch according to the selection signal S.

The AND circuit 46 also outputs an AND output, which is the result of the AND operation of the signal from the path 43 and the signal from the path 61, from the output terminal 62. Route 43
There is no delay time of the signal input from the AND circuit 46 to the AND circuit 46. On the other hand, the delay time of the signal input from the path 61 to the AND circuit 46 increases or decreases the number of stages of the serial connection of the delay means 56, 57, 58, 59 from 0 to 4 by the selection switch operation of the selector 60. it can.

Here, when the selector 60 selects the path 55, the signal input from the input terminal 50 passes through the four delay means 56, 57, 58 and 59 and has a delay time of 400n.
The signal S is connected to the path 61, and is input to one of the input terminals of the AND circuit 46 via the path 61. Further, an AND output with the non-delayed signal input from the path 43 to the other input terminal of the AND circuit 46 is output from the output terminal 62,
Since there is a time difference of 400 nS, noise is removed if the noise width is 400 nS or less.

However, as the noise is removed, the signal of the leading portion corresponding to the delay time of 400 nS is lost as described above, and the AND output is performed. That is, if the noise is removed over a wide range of noise width, there is a possibility that even the required signal may be lost. Therefore, if it is desired to limit the range of signal loss, it is necessary to limit the delay time.

Therefore, if the selector 60 selects the path 54 instead of the path 55 and connects it to the path 61, a signal having a delay time of 300 nS via the three delay means 56, 57 and 58 is routed. AND with the signal which is connected to 61 and is not delayed by the signal input from the path 43 to the AND circuit 46
Since the output has a time difference of 300 nS, the 300 nS
If the noise width is below, noise is removed.

If the selector 60 selects the path 53 and connects it to the path 61, the delay means 5
A signal having a delay time of 200 nS via two signals 6, 6 and 57 is connected to the path 61, and the AND output from the signal which is not delayed and is input from the path 43 to the AND circuit 46 has a time difference of 200 nS. If it is a noise width, noise is removed.

If the selector 52 selects the path 52 and connects it to the path 61, the delay means 5
A signal having a delay time of 100 nS passing through only 6 is routed to 6
Since the AND output of the signal connected to 1 and the non-delayed signal input from the path 43 to the AND circuit 46 has a time difference of 100 nS, the noise is removed if the noise width is 100 nS or less.

As described above, by controlling the selection signal S applied to the selector 60, the path connected to the path 61 is changed to the path 52.
By selecting any one of ˜55, the noise width capable of removing noise can be set appropriately. As described above, signal loss occurs at the same time as the noise width capable of removing noise, so the noise width capable of removing noise should be set to the minimum necessary. If the selector 51 selects the path 51 and connects it to the path 61, a signal that does not go through any delay means is connected to the path 61, and the signal from the path 43 to the AN
The AND output with the non-delayed signal input to the D circuit 46 is the original signal as it is, and noise is not removed.

The noise removing circuit shown in FIG. 5, that is, the noise removing circuit capable of properly setting the noise width capable of removing noise, is replaced by the noise removing circuit 102 shown in FIG. By switching, the function of the noise removing circuit 102 can be eliminated and the adverse effect of the delay time can be removed.

FIG. 6 shows a third embodiment of the present invention.
(A) is a block diagram of a signal selection means, (b) is a time chart explaining the operating principle. In FIG. 6A, the original signal input from the input terminal 65 is output from the output terminal 67 only as the signal selected by the signal selecting means 66. In the signal selection means 66, the time width of the original signal is measured by the clock counting means 69, and the measurement result is input to the threshold value setting means 70. If it is larger than the threshold value, the switch 68 is turned on and the original signal is output terminal 67. If the measurement result is smaller than the threshold value, the switch 68 is turned off and the original signal is not output from the output terminal 67. The threshold setting means 70 sets the threshold to, for example, 12
If nS is set, a signal of 12 nS or less is regarded as noise and removed, and a signal exceeding 12 nS is output so as to be valid, and functions as a noise removal circuit.

The detailed operation of the third embodiment will be described with reference to FIG. 6 (b). In FIG. 6B, the clock CL is a reference clock signal having a pulse width of 2 nS and one cycle of 4 nS. When the input signal D1 is input to the clock counting means 69, the clock counting means 69 recognizes one pulse of the clock count P0 in the clock CL and starts counting from the next pulse of the clock count P0 to the clock counts P1 to P6.
Including this, the signal width of 28 nS is measured as a result of counting clocks for a total of 7 cycles. The signal width of 28 nS is
The threshold setting means 70 set to 12 nS knows that the threshold value is equal to or higher than the threshold value. Therefore, the threshold setting means 70 turns on the switch 68 at the timing of the ON signal A and outputs the original signal from the output terminal 67. Note that for all input signals, the leading 12 nS includes noise that may be removed, so it will be removed uniformly, but the action is the same as that of the delay means application type in the first and second embodiments. It is similar to the noise removal circuit.

Next, in FIG. 6B, when the input signal D2 is inputted to the clock counting means 69, the clock counting means 69 recognizes one pulse of the clock count P0 in the clock CL and recognizes from the next pulse of the clock count P0. Since the clock counts P1 and P2 are started, when P0 is also included, the signal width of 12 nS is measured as a result of clock count of 3 cycles in total. 12
The signal width of nS is set to 12 nS, and the threshold setting means 7 is set.
From 0, it can be seen that the threshold value is equal to or less than the threshold value, so the threshold value setting means 70 maintains the switch 68 as the OFF signal B and does not output the original signal from the output terminal 67. Here, a signal having a time width of 12 nS or less is regarded as noise, and thus noise is removed.

As described above, the time width of the input signal is counted by the clock, and if the time width is less than or equal to the set threshold value, it is regarded as harmful noise, and the effective input signal is limited to the signal with the time width exceeding the threshold value. Therefore, the signal to be used and the noise to be removed are discriminated. In the embodiment shown in FIG. 6, a signal width of 12 nS or less is regarded as pulse noise, and a signal width of more than 12 nS is regarded as a valid signal and is output. The set value can be freely changed, and noise of an arbitrary width can be reliably removed by appropriately setting the clock count number as necessary. That is, more versatility can be dealt with by allowing the time width of the signal to be removed as noise to be arbitrarily selected.

[0039]

As described above, according to the present invention, even in the case of an IC having a built-in noise removing circuit using a delay means, a reset necessary for performing an operation test of the IC, etc. Since the reset timing of the signal can be maintained with respect to the original reset timing, the conventional test pattern can be used as it is. Also,
According to the present invention, it is possible to more versatilely support the time width of a signal to be removed as noise, which can be arbitrarily selected.

[Brief description of drawings]

FIG. 1 is a block diagram showing a relevant part of an IC having a built-in noise elimination circuit according to a first embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the noise removal circuit.

FIG. 3A is a conventional test pattern for confirming the operation of an IC. (B) A test pattern required when the reset signal is delayed by the noise removal circuit.

FIG. 4A is an example of a conventional noise removal circuit using a delay unit and an AND circuit. FIG. 4B is a time chart explaining the operation principle of the noise removal circuit shown in FIG. (C) An RC time constant circuit used as an example of the delay means.

FIG. 5 is a second embodiment of the present invention, which is an IC having a built-in noise removal circuit that allows multistage delay times to be freely selected.
It is a block diagram showing the corresponding part of.

FIG. 6 is a third embodiment of the present invention, in which (a) is a block diagram of a signal selection means. It is a time chart explaining the operation principle of (b).

[Explanation of symbols]

31, 32 registers 40, 50, 65, 101 input terminals 41-43,51-55,61 Route 44, 62, 67, 104 output terminals 45, 56-59 delay means 46 AND circuit 30,60 selector 66 signal selection means 68 switch Clock counting means to measure 69 time width 70 threshold setting means 102 Noise removal circuit 103 selection means 111 First route 112 Second route A ON signal A2, D data input terminal A3, C Trigger input terminal AD address signal B OFF signal CL clock CE chip enable signal D1, D2 input signal Data data signal P0, P1, P2 clock count Q data output terminal R reset signal S selection signal WR light signal

Claims (3)

[Claims] 1. A noise elimination circuit comprising: delay means for delaying an input original signal; and a circuit for outputting a delayed signal passed through the delay means and an operation result of the original signal not passed through the delay means. A noise removal circuit, comprising: a selection unit for selectively selecting a signal that has passed through the noise removal circuit and a signal that does not pass through the noise removal circuit. 2. A delay means for increasing or decreasing the function by switching and connecting a plurality of stages, and a selector for effectively circuit-connecting only an arbitrary number of stages by the switching connection of the delay means. The noise removal circuit according to claim 1. 3. A clock count means for measuring the number of pulses of a reference frequency that can be included in the time width of an input signal, and only a signal whose time width measured by the clock count means exceeds a preset threshold value. And an input signal selecting means for enabling the noise elimination circuit.