JP2007080956A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device including an offset-structured MOS transistor with improved reliability, and its manufacturing method. <P>SOLUTION: An offset insulation layer 24 is formed on a semiconductor layer except a channel formation region, a source formation region and a drain formation region, to form a gate insulation layer 102 and a gate electrode 104. A mask layer M3 is formed above the semiconductor layer 10, wherein the mask layer M3 has an opening 40 extending above the channel formation region, the source formation region and the drain formation region, and the end of the opening 40 is located above the offset insulation layer 24 at the same position as or inward from the end of the gate electrode 104 when the electrode 104 is viewed in the width direction. Impurities are introduced into the semiconductor layer by the use of the mask layer M3. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

In recent years, portable electronic devices have been reduced in weight and size, and research and development for reducing the size of ICs mounted on the electronic devices has been performed. In this IC, a plurality of transistors having different drive voltages are mounted depending on the application. As a transistor driven at a high voltage, a drain region and a channel region (in this case, a “channel region” is a semiconductor layer located below the gate electrode, and a region of the semiconductor layer having the same height as the drain region) MOS transistors having an offset gate structure are used which are separated from each other by an insulating layer formed in a semiconductor layer.
JP-A-64-51662

  An object of the present invention is to provide a semiconductor device including a MOS transistor having an offset structure, which has improved reliability, and a manufacturing method thereof.

(1) A manufacturing method of a semiconductor device of the present invention includes:
(A) preparing a semiconductor layer of a first conductivity type in which a transistor formation region is defined by an element isolation insulating layer;
(B) forming an offset insulating layer in the semiconductor layer other than at least the channel formation region, the source formation region, and the drain formation region in the transistor formation region;
(C) forming a gate insulating layer on at least the semiconductor layer to be the channel formation region;
(D) forming a gate electrode on at least the gate insulating layer;
(E) forming a source region and a drain region in the semiconductor layer,
The step (E)
(E-1) An opening continuous above at least the channel formation region, the source formation region, and the drain formation region above the semiconductor layer, and when the gate electrode is viewed in the width direction, A step of forming a mask layer having an end portion above the offset insulating layer and located on the same side as or inside the end portion of the gate electrode;
(E-2) introducing an impurity into the semiconductor layer using the mask layer.

  According to the method for manufacturing a semiconductor device of the present invention, when forming the source region and the drain region, the channel formation region, the mask layer having a continuous opening above the source formation region and the drain formation region, Impurities are introduced after a mask layer is formed in which the end of the opening is located at the same or the inside of the end of the gate electrode when viewed in the width direction. Therefore, impurities having the same conductivity type as those of the source region and the drain region are not introduced into the region outside the end portion of the gate electrode when the channel region is viewed in the width direction. For example, when the impurity is introduced using a mask layer having an opening from the end of the gate electrode to the outer region when the channel region is viewed in the width direction, the impurity may be offset insulated depending on the thickness of the offset insulating layer. In some cases, it penetrates the layer and is introduced into the semiconductor layer. As a result, the source region and the drain region are continuous, and current may flow even when no voltage is applied to the gate electrode of the transistor (when off). This is one of the factors that reduce the reliability of the semiconductor device. According to the method for manufacturing a semiconductor device according to the present invention, the impurity having the same conductivity type as that of the source region and the drain region is not introduced outside the end portion when the gate electrode is viewed in the width direction. It can suppress that an area | region continues. As a result, a semiconductor device with improved reliability can be manufactured.

  In the description of the present invention, the word “upper” is, for example, “forms another specific thing (hereinafter referred to as“ B ”)“ above ”a specific thing (hereinafter referred to as“ A ”)”. Etc. In the description according to the present invention, in the case of this example, the case where B is directly formed on A and the case where B is formed on A via another are included. The word “upward” is used.

  The method for manufacturing a semiconductor device of the present invention can further take the following aspects.

(2) In the method for manufacturing a semiconductor device of the present invention,
In the step (D), when the channel region is viewed in the width direction, the gate electrode whose end is located on the offset insulating layer is formed,
In the step (E-1), it is possible to form the mask layer whose end is located on the overlapping portion between the gate electrode and the offset insulating layer.

(3) In the method for manufacturing a semiconductor device of the present invention,
Further, the method may include a step of forming a guard ring region by introducing an impurity into a guard ring formation region located between the element isolation insulating layer and the offset insulating layer.

(4) In the method for manufacturing a semiconductor device of the present invention,
The element isolation insulating layer is formed by an STI method,
The offset insulating layer can be formed by a LOCOS method.

(5) The semiconductor device of the present invention
A semiconductor layer of a first conductivity type;
An element isolation insulating layer provided in the semiconductor layer and defining a transistor formation region;
A gate insulating layer provided on at least the channel region;
A gate electrode provided on at least the gate insulating layer;
A source region and a drain region provided in the semiconductor layer;
An offset insulating layer provided in the semiconductor layer other than at least the source region, the drain region, and the channel region,
The gate electrode is positioned at least above the channel region and at least the first conductivity type first polycrystalline silicon layer provided above the offset insulating layer when the channel region is viewed in the width direction. It consists of a second conductivity type second polycrystalline silicon layer.

(6) In the semiconductor device according to the present invention,
A contact layer connected to the gate electrode;
The contact layer may not be provided at a boundary between the first polycrystalline silicon layer and the second polycrystalline silicon layer.

  Embodiments relating to the present invention will be described below.

1. Semiconductor Device First, a semiconductor device according to this embodiment will be described with reference to FIGS. FIG. 1 is a plan view schematically showing the semiconductor device according to the present embodiment. FIG. 2 is a cross-sectional view taken along the line II of FIG. FIG. 3 is a cross-sectional view taken along line II-II in FIG.

  As shown in FIG. 1, the semiconductor device according to the present embodiment has an element formation region (transistor formation region) 10HV. A first transistor 100 (high voltage drive transistor) is provided in the element formation region 10HV. The transistor 100 is an MOS transistor having an offset structure between the drain region and the channel region and having a structure in which an offset insulating layer formed in the semiconductor layer 10 is provided. Here, the channel region is a semiconductor layer located below the gate electrode, and is a region where the height of the upper surface of the source region and the drain region is the same.

  In the transistor 100, a source region 110a and a drain region 110b are provided with a gate electrode 104 interposed therebetween. The channel region 108 located below the gate electrode 104 is separated from the source region 110a and the drain region 110b by the offset insulating layer 24 (see FIGS. 2 and 3). An offset impurity region 112a is provided so as to include the source region 110a, and similarly, an offset impurity region 112b is provided so as to include the drain region 110b. In the element formation region 10HV, a guard ring region 120 is provided so as to surround the transistor 100.

  Next, a cross-sectional structure of the semiconductor device according to the present embodiment will be described with reference to FIGS.

  As shown in FIG. 2, the element formation region 10HV is defined by the first element isolation insulating layer 20 provided in the semiconductor layer 10. The element forming region 10HV is provided with a well 12, and the well 12 is provided with a high voltage driving transistor 100. The transistor 100 includes a gate insulating layer 102 provided on the well 12, a gate electrode 104 provided on the gate insulating layer 102, a sidewall insulating layer 106, and a source region 110a and a drain region 110b. It becomes. The channel region 108 located in the semiconductor layer 10 below the gate electrode 104 is separated from the source region 110a and the drain region 110b by the offset insulating layer 24. That is, the offset insulating layer 24 is provided at both ends of the gate insulating layer 102. An offset impurity region 112 a is provided so as to include the source region 110 a and the offset insulating layer 24. Similarly, an offset impurity region 112b is provided so as to include the drain region 110b and the offset insulating layer 24.

  A guard ring region 120 is provided in the semiconductor layer 10 sandwiched between the element isolation insulating layer 20 and the offset insulating layer 24. An impurity region 122 having a low impurity concentration is provided so as to include the guard ring region 120.

  Next, a cross-sectional structure in the channel width direction of the transistor 100 is described with reference to FIGS. As shown in FIG. 3, the well 12 is formed in the semiconductor layer 10. A gate insulating layer 102 is formed on the well 12, and offset insulating layers 24 are provided on both ends of the gate insulating layer 102. A gate electrode 104 is provided on the gate insulating layer 102, and an end portion of the gate electrode 104 is provided on the offset insulating layer 24. A guard ring region 120 surrounding the transistor 100 is provided at a position sandwiched between the offset insulating layer 24 and the element isolation insulating layer 20. A low concentration impurity region 122 is provided so as to enclose the guard ring region 120.

2. Semiconductor Device Manufacturing Method Next, a semiconductor device manufacturing method according to the present embodiment will be described with reference to FIGS. 4 to 10 and 12 are views showing the manufacturing process of the semiconductor device according to the present embodiment, and showing a cross section corresponding to FIG. FIG. 11 is a diagram illustrating a manufacturing process of the semiconductor device according to the present embodiment, and is a diagram illustrating a plane corresponding to FIG. FIG. 13 is a diagram illustrating a manufacturing process of the semiconductor device according to the present embodiment, and is a diagram illustrating a cross section corresponding to FIG. 3.

  (1) As shown in FIG. 4, first, the semiconductor layer 10 is prepared. A first element isolation insulating layer 20 and an offset insulating layer 24 are formed on the semiconductor layer 10. This step can be performed by a semi-recessed LOCOS method. Specifically, the sacrificial film 30 and the nitride film 32 are formed on the semiconductor layer 10. Thereafter, a mask layer (not shown) having an opening is formed on a region where the element isolation insulating layer 20 and the offset insulating layer 24 are to be formed. Using this mask layer, the sacrificial film 30 and the nitride film 32 are patterned as shown in FIG. Next, using the sacrificial film 30 and the nitride film 32 after patterning as a mask, the semiconductor layer 10 is etched to form the grooves 18.

  (2) Next, by performing thermal oxidation, the first element isolation insulating layer 20 and the offset insulating layer 24 can be formed in the semiconductor layer 10 as shown in FIG. Thereby, the element formation region 10HV is defined. The offset insulating layer 24 is formed in a region other than the channel formation region 108a, the source formation region 110, the drain formation region 110, and the guard ring formation region 120a. Here, the source formation region 110 and the drain formation region 110 are regions which are to be a source region and a drain region after impurities are introduced in a later step. Thereafter, the sacrificial film 30 and the nitride film 32 are removed by a removal method corresponding to each film quality. Note that in the drawings showing manufacturing steps subsequent to this step, the channel formation region 108a, the source formation region 110, the drain formation region 110, and the guard ring formation region 120a may be omitted from reference numerals.

  (3) Next, as shown in FIG. 6, the well 12 is formed in the element formation region 10HV. In the formation of the well 12, a mask layer (not shown) that covers the region other than the element formation region 10HV is formed, a first conductivity type impurity is introduced into the semiconductor layer 10 by a known technique, and a thermal diffusion process is performed. It is formed.

  (4) Next, as shown in FIG. 7, offset impurity regions 112a and 112b (see FIGS. 1 to 3) of the transistor 100 are formed in the element formation region 10HV. In the formation of the offset impurity regions 112a and 112b, as shown in FIG. 8, the mask layer M1 having a predetermined pattern is formed, and the impurity is introduced using the mask layer M1 as a mask to form the offset impurity regions 112a and 112b. can do. Moreover, you may perform thermal diffusion as needed.

  (5) Next, as shown in FIG. 8, an impurity region 122 (see FIGS. 2 to 3) that encloses the guard ring layer 120 of the transistor 100 is formed. The impurity region 122 is formed by forming a mask layer M2 having a predetermined pattern and then introducing impurities into the well 12 by a known method. Moreover, you may heat-process for diffusion as needed.

  (6) Next, as shown in FIG. 9, a gate insulating layer 102 (see FIGS. 2 and 3) of the transistor 100 is formed. In forming the gate insulating layer 102, first, a mask layer 36 for heat-resistant oxidation is formed. As the mask layer 36, for example, a laminated film of a sacrificial film and a nitride film can be used. Next, the gate insulating layer 102 is formed by thermal oxidation using the mask layer 36 as a mask. Next, the mask layer 36 is removed using a removal method according to the film quality.

  (7) Next, as shown in FIG. 10, the gate electrode 104 of the transistor 100 is formed. The gate electrode 104 can be formed by forming a conductive layer (not shown) on the entire surface and then patterning the conductive layer. Examples of the conductive layer include a polycrystalline polysilicon layer. Next, a sidewall insulating layer 106 is formed on the side surface of the gate electrode 104. The sidewall insulating layer 106 can be formed by forming an insulating layer (not shown) over the entire surface of the semiconductor layer 10 and performing anisotropic etching on the insulating layer.

  (8) Next, as shown in FIG. 2, the source region 110a and the drain region 110b of the transistor 100 are formed. In this step, first, a mask layer M3 having a predetermined pattern is formed, and then an impurity is introduced into the semiconductor layer 10 using the mask layer M3. The pattern of the mask layer M3 will be described with reference to FIGS. As shown in FIGS. 11 and 12, the mask layer M3 has an opening 40 that is continuous above a region to be a source region and a drain region and above a channel region. Specifically, the gray area shown in FIG. As shown in FIG. 13, the end of the opening 40 is located inside the end of the gate electrode 104 when viewed in the width direction of the channel region. That is, when viewed in the width direction of the channel region, the width of the opening 40 is smaller than the width of the gate electrode 104. Note that although the case where the end portion of the opening 40 is on the inner side than the end portion of the gate electrode 104 is described in this embodiment mode, each end portion may be in the same position (overlapping position). By introducing impurities into the semiconductor layer 10 using the mask layer M3, the source region 110a and the drain region 110b are formed.

  Next, as shown in FIG. 2, the guard ring region 120 is formed. In this step, in the element formation region 10HV, a mask layer (not shown) having an opening above the guard ring region is formed, and then impurities are introduced. Although not described in this embodiment, this step is the same as the formation of the source region and the drain region of a transistor that is mixedly mounted on the same semiconductor layer and has a channel conductivity type different from that of the first transistor. Can be done.

  Through the above steps, the semiconductor device according to the present embodiment can be manufactured.

  According to the method of manufacturing a semiconductor device according to the present embodiment, the mask layer having the opening 40 continuous above the channel formation region 108a, the source formation region, and the drain formation region 110 when the source region 110a and the drain region 110b are formed. After forming the mask layer M3, the end of the opening 40 being the same as or inside the end of the gate electrode 104 when the channel formation region 108a is viewed in the width direction, the impurity is introduced. Has been done. Therefore, impurities having the same conductivity type as those of the source region 110a and the drain region 110b are not introduced into the region outside the end portion of the gate electrode 104 when the channel region 108a is viewed in the width direction. For example, when the impurity is introduced using a mask layer having an opening from the end portion of the gate electrode 104 to the outer region when the channel region 108 is viewed in the width direction, the impurity depends on the thickness of the offset insulating layer 24. May penetrate the offset insulating layer 24 and be introduced into the semiconductor layer 10. As a result, the source region and the drain region are continuous, and a current may flow even when no voltage is applied to the gate electrode of the first transistor (when off). This is one of the factors that reduce the reliability of the semiconductor device. According to the manufacturing method of the semiconductor device according to the present embodiment, the same conductivity type impurity as that of the source region 110a and the drain region 110b is not introduced outside the end portion when the gate electrode 104 is viewed in the width direction. The source region 110a and the drain region 110b can be prevented from being continuous. As a result, a semiconductor device with improved reliability can be manufactured.

3. Modified Example Next, a semiconductor device according to this modified example will be described with reference to FIG. FIG. 14 is a cross-sectional view schematically showing a semiconductor device according to this modification, and is a cross-sectional view corresponding to FIG. The semiconductor device according to this modification is an example of a semiconductor device in which the gate electrode 104 is formed of a polycrystalline silicon layer. In the following description, detailed description of structures common to those of the semiconductor device according to the above-described embodiment is omitted.

  In the semiconductor device according to this modification, the gate electrode 104 is formed of a polycrystalline silicon layer. Specifically, a first polycrystalline silicon layer 104a located above the channel region 108 and a second polycrystalline silicon layer located outside the first polycrystalline silicon layer 104a and above the offset insulating layer 24. 104b. First polycrystalline silicon layer 104a has the same conductivity type as source region 110a and drain region 110b, and second polycrystalline silicon layer 104b is doped with an impurity having a conductivity type different from that of first polycrystalline silicon layer 104a. A polycrystalline silicon layer.

  Furthermore, the semiconductor device according to the present modification can take a form in which a contact layer is provided on the gate electrode 104 to be electrically connected to a wiring layer (not shown) provided above. In this embodiment, an interlayer insulating layer 50 is provided so as to cover the transistor 100, and a contact layer 52 is formed at a predetermined position of the interlayer insulating layer 50. The contact layer 52 is preferably provided above the channel region, preferably above the offset insulating layer 24. When no silicide layer is formed on the upper surface of gate electrode 104, contact layer 52 is preferably not provided at the boundary between first polycrystalline silicon layer 104a and second polycrystalline silicon layer 104b. . This is because the N-type impurity and the P-type impurity are offset at the PN junction portion, resulting in a non-doped region, which has the advantage of preventing the phenomenon that the contact resistance increases at that location.

  In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation is possible. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

8A and 8B illustrate a semiconductor device according to this embodiment. Sectional drawing along the II line | wire of FIG. Sectional drawing along the II-II line of FIG. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment. 8A and 8B illustrate a manufacturing process of a semiconductor device according to this embodiment. 6A and 6B illustrate a semiconductor device according to a modification.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor layer, 12 ... Well, 18 ... Groove, 20 ... Element isolation insulating layer, 30 ... Sacrificial film, 32 ... Nitride film, 36 ... Mask layer, 40 ... Opening, 50 ... Interlayer insulating layer, 52 ... Contact layer, DESCRIPTION OF SYMBOLS 100 ... Transistor 102 ... Gate insulating layer 104 ... Gate electrode 106 ... Side wall insulating layer 108 ... Channel region 108a ... Channel forming region 110 ... Source forming region, drain forming region 112a, 112b ... Offset impurity region, 110a ... source region 110b ... drain region 120 ... guard ring region 122 ... impurity region

Claims (6)

(A) preparing a semiconductor layer in which a transistor formation region is defined by an element isolation insulating layer;
(B) forming an offset insulating layer in the semiconductor layer other than at least the channel formation region, the source formation region, and the drain formation region in the transistor formation region;
(C) forming a gate insulating layer on at least the semiconductor layer to be the channel formation region;
(D) forming a gate electrode on at least the gate insulating layer;
(E) forming a source region and a drain region in the semiconductor layer,
The step (E)
(E-1) An opening continuous above at least the channel formation region, the source formation region, and the drain formation region above the semiconductor layer, and when the gate electrode is viewed in the width direction, A step of forming a mask layer having an end portion above the offset insulating layer and located on the same side as or inside the end portion of the gate electrode;
(E-2) A step of introducing an impurity into the semiconductor layer using the mask layer. In claim 1,
In the step (D), when the channel region is viewed in the width direction, the gate electrode whose end is located on the offset insulating layer is formed,
In the step (E-1), a method of manufacturing a semiconductor device, wherein the mask layer having an end portion located on an overlapping portion of the gate electrode and the offset insulating layer is formed. In claim 1 or 2,
Furthermore, the manufacturing method of a semiconductor device including the process of introduce | transducing an impurity into the guard ring formation area | region located between the said element isolation insulating layer and the said offset insulating layer, and forming a guard ring area | region. In any of claims 1 to 3,
The element isolation insulating layer is formed by an STI method,
The method of manufacturing a semiconductor device, wherein the offset insulating layer is formed by a LOCOS method. A semiconductor layer of a first conductivity type;
An element isolation insulating layer provided in the semiconductor layer and defining a transistor formation region;
A gate insulating layer provided on at least the channel region;
A gate electrode provided on at least the gate insulating layer;
A source region and a drain region provided in the semiconductor layer;
An offset insulating layer provided in the semiconductor layer other than at least the source region, the drain region, and the channel region,
The gate electrode is positioned at least above the channel region and at least the first conductivity type first polycrystalline silicon layer provided above the offset insulating layer when the channel region is viewed in the width direction. A semiconductor device comprising a second polycrystalline silicon layer of a second conductivity type. In claim 5,
A contact layer connected to the gate electrode;
The contact layer is not provided at a boundary between the first polycrystalline silicon layer and the second polycrystalline silicon layer.

Images