JP2006237584A - Memory device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory element manufactured in a reduced number of manufacturing processes at lower costs and a memory circuit having the element, which relates to a memory element to be mounted in a semiconductor device typified by an RFID. <P>SOLUTION: A memory element, which is sandwiched between electrodes and has an organic compound, is characterized in that an electrode connected to a semiconductor element controlling the memory element functions as an electrode of the memory element. In addition, an extremely thin semiconductor film formed on an insulated surface is used for the memory element. Thus, lower costs is achieved. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention describes a memory element including an organic compound, a memory device including the memory element, and a manufacturing method thereof.

Currently, RFID (Radio Frequency Identification) is being developed and studied as a technology for recognizing and identifying objects and people. Such RFID is used for preventing counterfeiting of securities and for personal authentication, and is expected to have many uses.

A conventional RFID uses an IC (Integrated Circuit) chip formed from a silicon wafer, and forms a storage circuit such as a ROM and a RAM and a control circuit such as a CPU (see Patent Document 1).
JP 2000-20665 (FIG. 2)

As described above, chips formed from RFID silicon wafers are non-translucent, and there is a tendency to reduce the chip size in order to improve impact resistance. When mounted for, it often stands out.

Such RFID is also being used in the field of product tags, and it is desired to reduce the cost to such an extent that it can be disposable. For this reason, the silicon wafer base is fabricated from a silicon wafer having a circular shape by using multi-faced chamfering, but a limit has begun to appear in order to increase the extraction rate and reduce the cost.

In view of the above, an object of the present invention is to provide a memory element and a memory circuit including the element, in which the manufacturing process is reduced and the cost is reduced. It is another object of the present invention to provide a memory element including the circuit and a semiconductor device including the memory element.

In view of the above problems, the present invention is a memory element having an organic compound sandwiched between electrodes, and an electrode connected to a semiconductor element that controls the memory element, that is, a source electrode or a drain electrode, is connected to the memory element. It functions as a lower electrode. As a result, an electrode for a memory element is not necessary, and the number of processes can be reduced.

The insulator included in the memory element is formed in an opening for forming an electrode electrically connected to the semiconductor element. As a result, there is no formation of an insulating film, so-called isolation layer, which is necessary for the separate production of organic compounds.

Further, since the present invention uses an extremely thin semiconductor film formed on an insulating surface, cost can be reduced. The insulating surface refers to a surface on a synthetic resin substrate such as a glass substrate or plastic other than a silicon wafer.

Specific embodiments of the present invention are shown below.

A memory device of the present invention includes a semiconductor film having an impurity region formed over an insulating surface, an insulating film in contact with the semiconductor film and having an opening provided on the impurity region, an impurity region provided in the opening, A conductive film functioning as a source or drain electrode and a lower electrode that are electrically connected to each other, an insulator provided over the conductive film in an opening, and an upper electrode provided over the insulator It is characterized by that.

A memory device according to another embodiment of the present invention includes a semiconductor film having an impurity region formed over an insulating surface, a first insulating film in contact with the semiconductor film, and a first opening provided on the impurity region; A first conductive film that is provided in the first opening and functions as a source electrode or a drain electrode electrically connected to the impurity region, and is provided so as to cover an end portion of the conductive film. A second insulating film provided with two openings, a second conductive film connected to the first conductive film and functioning as a lower electrode, and a second conductive film in the first and second openings. It has an insulator provided on the film and an upper electrode provided on the insulator.

In the present invention, the insulator is a material whose properties change due to an optical action or a thermal action, so that the lower electrode and the upper electrode can be short-circuited. In order to change properties by optical action or thermal action, the film thickness is 5 nm to 100 nm, preferably 10 nm to 60 nm. In the case where an organic compound material is used for the insulator, the glass transition temperature thereof is 80 ° C. to 300 ° C., preferably 100 ° C. to 250 ° C.

In the method for manufacturing a memory device of the present invention, an impurity region is formed in a semiconductor film over an insulating surface, an insulating film is formed in contact with the semiconductor film, and an opening is formed in the insulating film so that the impurity region is exposed. In the opening, a conductive film functioning as a source or drain electrode and a lower electrode electrically connected to the impurity region is formed, an insulator is formed over the conductive film, and an upper electrode is formed over the insulator. It is characterized by forming.

In another embodiment of the present invention, a method for manufacturing a memory device includes forming an impurity region in a semiconductor film over an insulating surface, forming the insulating film in contact with the semiconductor film, and opening the insulating film so that the impurity region is exposed. A conductive film functioning as a source electrode or a drain electrode that is electrically connected to the impurity region and a lower electrode in the opening, and an insulator is formed on the conductive film. An upper electrode is formed and surface modification is performed on the conductive film and the insulating film.

In another embodiment of the present invention, a method for manufacturing a memory device includes forming an impurity region in a semiconductor film over an insulating surface, forming the insulating film in contact with the semiconductor film, and opening the insulating film so that the impurity region is exposed. A conductive film functioning as a source electrode or a drain electrode that is electrically connected to the impurity region and a lower electrode in the opening, and an insulator is formed on the conductive film. An upper electrode is formed and surface modification is performed on the conductive film by a sputtering method.

As described above, since the insulator is formed very thin, adhesion of the insulator can be improved by surface modification.

In another embodiment of the present invention, a method for manufacturing a memory device includes forming an impurity region in a semiconductor film over an insulating surface, forming the insulating film in contact with the semiconductor film, and opening the insulating film so that the impurity region is exposed. A conductive film functioning as a source electrode or a drain electrode that is electrically connected to the impurity region and a lower electrode in the opening, and an insulator is formed on the conductive film. An upper electrode is formed, surface modification is performed only on the upper surface of a conductive film provided around the opening, and then an insulator is formed by a droplet discharge method.

According to the present invention, there is provided a memory element and a memory circuit including the element, which are reduced in manufacturing process because an electrode for a memory is unnecessary, and cost is reduced.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment, a manufacturing process of a memory element will be described.

As shown in FIG. 1A, a base film 101 is formed over a substrate 100 having an insulating surface. As the substrate 100, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a stainless steel (SUS) substrate, or the like can be used. In addition, substrates made of plastics such as PET (polyethylene terephthalate), PEN (polyethylene naphthalate), and PES (polyethersulfone) and flexible synthetic resins such as acrylic are generally different from other substrates. Although the heat resistant temperature tends to be low as compared, it can be used as long as it can withstand the processing temperature in the manufacturing process.

The base film 101 is provided to prevent alkali metal such as Na or alkaline earth metal contained in the substrate 100 from diffusing into the semiconductor film and adversely affecting the characteristics of the semiconductor element. Therefore, an insulating film such as silicon oxide, silicon nitride, or silicon nitride oxide that can suppress diffusion of alkali metal or alkaline earth metal into the semiconductor film is used.

In the case of using a substrate containing an alkali metal or an alkaline earth metal, such as a glass substrate, a stainless steel substrate, or a plastic substrate, it is effective to provide a base film from the viewpoint of preventing impurity diffusion. On the other hand, the base film is not necessarily provided when the diffusion of impurities such as a quartz substrate is not a problem.

Next, a semiconductor film having an amorphous structure (referred to as an amorphous semiconductor film) is formed over the base film 101. As the amorphous semiconductor film, not only silicon but also silicon germanium can be used. When silicon germanium is used, the concentration of germanium is preferably about 0.01 to 4.5 atomic%. In the embodiment, a semiconductor film containing 66 nm silicon as a main component (also referred to as an amorphous silicon film or amorphous silicon) is used.

Next, the amorphous semiconductor film is crystallized to form a semiconductor film having a crystal structure (referred to as a crystalline semiconductor film). As a method for crystallization, a heating furnace, laser irradiation, irradiation with light emitted from a lamp (referred to as lamp annealing), or a combination thereof can be used.

For example, a crystalline semiconductor film is formed by adding a metal element to an amorphous semiconductor film and performing heat treatment using a heating furnace. Thus, it is preferable to add a metal element because crystallization can be performed at a low temperature. Here, the addition means that a metal element is formed on the surface of the amorphous semiconductor film so that at least crystallization of the amorphous semiconductor film is promoted. For example, a Ni solution (including an aqueous solution and an acetic acid solution) is applied on an amorphous semiconductor film by a coating method such as a spin coating method or a dip method, and a film containing Ni (however, it may be unobservable as a film because it is extremely thin). ) Is included. At this time, since the solution is spread over the entire surface of the amorphous semiconductor film, the wettability of the surface of the amorphous semiconductor film is preferably improved. For example, wettability can be improved by forming an oxide film of 1 nm to 5 nm by irradiation with UV light in an oxygen atmosphere, thermal oxidation, treatment with ozone water containing hydroxyl radicals or hydrogen peroxide, and the like. .

Thereafter, the amorphous semiconductor film is heated at 500 to 550 ° C. for 2 to 20 hours to crystallize the amorphous semiconductor film to form a crystalline semiconductor film. At this time, it is preferable to gradually change the heating temperature. In addition, hydrogen and the like of the amorphous semiconductor film come out by the low-temperature heating process, so that so-called hydrogen extraction that reduces film roughness during crystallization can be performed. For example, crystallization can be performed by performing heat treatment at 500 ° C. for 1 hour and then heat treatment at 550 ° C. for 4 hours using a vertical furnace.

When crystallization using a metal element is performed as described above, a gettering step is performed in order to reduce or remove the metal element. For example, a metal element can be captured by forming an amorphous semiconductor film as a gettering sink and heating.

Thereafter, heat treatment is performed at 550 ° C. for 4 hours in a nitrogen atmosphere to reduce or remove the metal element. Then, the amorphous semiconductor film and the oxide film which have become gettering sinks are removed with hydrofluoric acid or the like, so that a crystalline semiconductor film from which the metal element is reduced or removed can be obtained.

As another crystallization method, there is a method of irradiating a laser beam (laser beam) to an amorphous semiconductor film. Examples of such lasers include Ar laser, Kr laser, excimer laser, YAG laser, Y ₂ O ₃ laser, YVO ₄ laser, YLE laser, YAlO ₃ laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, One or a plurality of copper vapor lasers or gold vapor lasers can be used. As the laser oscillation type, there are a continuous oscillation type (also referred to as a CW laser) and a pulse oscillation type (also referred to as a pulse laser), which can be used. Still further, the fundamental wave of the laser or the second to fourth harmonics of the fundamental wave can be irradiated alone or in combination.

The laser beam shape is preferably linear. As a result, throughput can be improved. Further, the laser is preferably irradiated with an incident angle θ (0 ° <θ <90 °) with respect to the semiconductor film. This is because laser interference can be prevented.

The crystalline semiconductor film thus formed is processed into a predetermined shape (also referred to as patterning) as shown in FIG. 1A to form an island-shaped semiconductor film 102. At the time of patterning, a photoresist is applied on the crystalline semiconductor film, a predetermined mask shape is exposed, and a mask is formed. Using this mask, the crystalline semiconductor film can be patterned by a dry etching method.

After that, a gate insulating film 104 is formed so as to cover the semiconductor film 102. The gate insulating film 104 may be a single layer or a stacked layer. The insulating material used for the gate insulating film 104 may be an inorganic material or an organic material. For example, silicon oxide, silicon nitride, or silicon oxynitride can be used. Note that the surface of the island-shaped semiconductor film is preferably cleaned with hydrofluoric acid or the like before the gate insulating film 104 is formed. This is because interface contamination between the semiconductor film and the gate insulating film affects the electrical characteristics of the thin film transistor. Therefore, the semiconductor film and the gate insulating film may be continuously formed without being exposed to the atmosphere, and then the semiconductor film and the gate insulating film may be patterned into a predetermined shape at the same time.

A conductive film to be the gate electrode 105 is formed over the semiconductor film 102 with the gate insulating film 104 interposed therebetween. The gate electrode 105 may be a single layer or a stacked layer, and the end of the gate electrode 105 may have a tapered shape. For the conductive film to be the gate electrode 105, an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component can be used.

The impurity region 103 is formed in a self-aligning manner using the gate electrode 105 as a mask. In the case of forming an n-type thin film transistor, an impurity region to which phosphorus (P) is added is formed by doping phosphine (PH ₃ ). In the case of forming a p-type thin film transistor, diborane (B ₂ H ₆ ) is doped to form an impurity region to which boron (B) is added.

The impurity region 103 can be divided into a high concentration impurity region or a low concentration impurity region depending on the impurity concentration. For example, since the addition amount of the impurity element is reduced in the tapered portion of the gate electrode 105, a low-concentration impurity region can be formed, and a high-concentration impurity region can be formed in a region without the gate electrode 105. A structure in which the gate electrode overlaps with part of the impurity region is referred to as a GOLD (Gate Overlapped Drain) structure.

A so-called offset structure in which an insulator is provided on the side surface of the gate electrode 105 can also be used. In the offset structure, the distance between the channel formation region and the impurity region 103 can be set depending on the width of the insulator.

A first insulating film 106 is formed so as to cover the gate insulating film 104 and the gate electrode 105. The first insulating film can be formed from any of silicon oxide, silicon nitride, and silicon oxynitride. In particular, the first insulating film is preferably an insulating film containing hydrogen; therefore, the first insulating film is preferably formed by a CVD method.

After that, heat treatment is preferably performed to activate the impurity region 103. The heat treatment is performed, for example, at 400 ° C. to 550 ° C. in a nitrogen atmosphere using a heating furnace. As a result, dangling bonds and the like of the semiconductor film 102 can be reduced by hydrogen from the first insulating film 106.

Next, as illustrated in FIG. 1B, a second insulating film 108 is formed so as to cover the first insulating film 106. The second insulating film 108 can improve flatness. The second insulating film 108 can be formed using an organic material or an inorganic material. As the organic material, polyimide, acrylic, polyamide, polyimide amide, resist benzocyclobutene, siloxane, or polysilazane can be used. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Polysilazane is formed using a liquid material containing a polymer material having a bond of silicon (Si) and nitrogen (N) as a starting material. As the inorganic material, silicon oxide, silicon nitride, silicon oxynitride, or the like can be used. The second insulating film 108 may have a single layer structure or a stacked structure. In particular, when the second insulating film is formed using an organic material, flatness is improved, but moisture and oxygen are absorbed by the organic material. In order to prevent this, a stacked structure in which an inorganic material is formed over an organic material is preferable.

After that, openings, so-called contact holes 110 are formed in the gate insulating film 104, the first insulating film 106, and the second insulating film 108. The contact hole 110 can be formed by a dry etching method or a wet etching method. As an etchant used for such an etching method, the gate insulating film 104, the first insulating film 106, the second insulating film 108, and the semiconductor film 102 can be selected when the contact hole 110 is formed. If it is. At this time, the end portion of the second insulating film 108 around the contact hole 110 is preferably rounded. As a result, disconnection of a conductive film to be formed next can be prevented.

In the present invention, since the memory element is formed using the contact hole 110, its diameter, depth, taper angle, and the like are determined. For example, the contact hole 110 on the side where the memory element is formed has a larger diameter than the contact hole on the side where the memory element is not formed. For example, the diameter is set to 1 μm to 3 μm.

Thereafter, a conductive film to be the electrodes 109 and 109 ′ is formed in the contact hole 110. The electrodes 109 and 109 ′ can have a single layer structure or a stacked structure. The conductive film may be formed using an element of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), or silicon (Si) or an alloy using these elements. For the conductive film, a light-transmitting material such as indium tin oxide (ITO), indium tin oxide containing silicon oxide, or indium oxide containing 2 to 20% zinc oxide can be used. Such a conductive film is formed by a sputtering method, a droplet discharge method, or the like, and becomes an electrode 109 by patterning into a predetermined shape. Note that the electrodes 109 and 109 ′ connected to the impurity region 103 function as a source electrode or a drain electrode and function as a lower electrode of the memory element. In the present invention, since it is not necessary to newly form a conductive film as a lower electrode, the number of steps can be reduced and the cost can be reduced.

A top view of the steps so far is shown in FIG. As can be seen from FIG. 2A, the semiconductor film 102 may be patterned into a rectangle in order to ensure a large diameter of the contact hole 110 on the side where the memory element is formed. Further, as shown in FIG. 2A, the conductive film is patterned so that wirings connected to the electrodes are formed at the same time. For example, a word line is formed simultaneously with the gate electrode 105. A selection signal is input to the word line from the control circuit. In addition, a signal line is formed simultaneously with the source electrode and the drain electrode.

Thus, the thin film transistor 107 can be completed by forming the source electrode and the drain electrode.

Next, as illustrated in FIG. 1C, an insulator 112 that forms a memory element is formed in the contact hole 110. The insulator 112 may have a thickness of 5 nm to 100 nm, preferably 10 nm to 60 nm.

The insulator 112 can be formed of an inorganic material or an organic material. Further, the insulator 112 can be formed using such materials by a vapor deposition method, a spin coating method, a droplet discharge method, or the like. The insulator 112 may be formed using a material whose properties change due to an optical action, a thermal action, or the like. For example, any material may be used as long as its properties change due to melting due to Joule heat, dielectric breakdown, and the like, and the electrode 109 functioning as the lower electrode and the upper electrode formed thereafter can be short-circuited.

Examples of the inorganic material include silicon oxide, silicon nitride, and silicon oxynitride. Even if such an inorganic material is used, dielectric breakdown is caused by controlling the film thickness, so that the lower electrode and the upper electrode can be short-circuited.

Examples of the organic material include 4,4′-bis [N- (1-naphthyl) -N-phenylamino] biphenyl (abbreviation: α-NPD) and 4,4′-bis [N- (3-methylphenyl). ) -N-phenylamino] biphenyl (abbreviation: TPD), 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) triphenylamine (abbreviation: TDATA), 4,4 ′, 4 ″ -Tris [N- (3-methylphenyl) -N-phenylamino] triphenylamine (abbreviation: MTDATA) or 4,4'-bis (N- (4- (N, N-di-m-tolylamino) phenyl ) -N-phenylamino) biphenyl (abbreviation: DNTPD) and other aromatic amine-based compounds (that is, having a benzene ring-nitrogen bond), polyvinylcarbazole (abbreviation: PVK), and phthalocyanine (abbreviation: H ₂ Pc). ), Copper phthalocyanine (abbreviation: CuPc), vanadyl phthalocyanine (abbreviation: VOPc), and the like can be used. These materials are substances having a high hole transporting property.

As other organic compound materials, for example, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [ h] Quinolinato) Beryllium (abbreviation: BeBq ₂ ), Bis (2-methyl-8-quinolinolato) (4-phenylphenolato) aluminum (abbreviation: BAlq), etc. And bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) ₂ ) Materials such as metal complexes with oxazole and thiazole ligands such as You can. These materials are materials having a high electron transporting property.

In such an organic material, its glass transition temperature (Tg) is 80 ° C. to 300 ° C., preferably 100 ° C. to 250 ° C., in order to change its properties by thermal action or the like.

In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (P-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- ( 4-biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2, Compounds such as 4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), and the like can be used.

As a single-layer structure or a stacked structure with the above materials, 4-dicyanomethylene-2-methyl-6- [2- (1,1,7,7-tetramethyljulolidin-9-yl) ethenyl]- 4H-pyran (abbreviation: DCJT), 4-dicyanomethylene-2-t-butyl-6- [2- (1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] -4H-pyran, Periflanthene, 2,5-dicyano-1,4-bis [2- (10-methoxy-1,1,7,7-tetramethyljulolidin-9-ylethenyl] benzene, N, N′-dimethylquinacridone (abbreviation: DMQd), coumarin 6, coumarin 545T, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), 9,9′-bianthryl, 9,10-diphenylanthracene (abbreviation: DPA) Alternatively, a light-emitting material such as 9,10-bis (2-naphthyl) anthracene (abbreviation: DNA), 2,5,8,11-tetra- (tert-butyl) perylene (abbreviation: TBP) may be used.

As a base material for forming a layer in which the light emitting material is dispersed, an anthracene such as 9,10-di (2-naphthyl) -2-tert-butylanthracene (abbreviation: t-BuDNA) is used. Derivatives, carbazole derivatives such as 4,4′-bis (N-carbazolyl) biphenyl (abbreviation: CBP), bis [2- (2-hydroxyphenyl) pyridinato] zinc (abbreviation: Znpp ₂ ), bis [2- (2 Metal complexes such as -hydroxyphenyl) benzoxazolate] zinc (abbreviation: ZnBOX) can be used. In addition, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), 9,10-bis (2-naphthyl) anthracene (abbreviation: DNA), bis (2-methyl-8-quinolinolato) (4-phenylphenolato) Aluminum (abbreviation: BAlq) or the like can be used.

Alternatively, a material in which a metal oxide is mixed with the organic material or the light emitting material may be used. Note that the mixed material includes a mixed state or a stacked state. Specifically, it refers to a state formed by a co-evaporation method using a plurality of evaporation sources.

When a metal oxide is mixed with a substance having a high hole transporting property, the metal oxide is vanadium oxide, molybdenum oxide, niobium oxide, rhenium oxide, tungsten oxide, ruthenium oxide, titanium oxide. Further, chromium oxide, zirconium oxide, hafnium oxide, and tantalum oxide can be used.

In the case where a substance having a high electron transporting property and a metal oxide are mixed, lithium oxide, calcium oxide, sodium oxide, potassium oxide, or magnesium oxide can be used as the metal oxide.

The insulator 112 may be made of a material whose properties change due to optical action or thermal action. For example, the insulator 112 is doped with a compound that generates an acid by absorbing light (photo acid generator). Conjugated polymers can also be used. As the conjugated polymer, polyacetylenes, polyphenylene vinylenes, polythiophenes, polyanilines, polyphenylene ethynylenes, and the like can be used. As the photoacid generator, arylsulfonium salts, aryliodonium salts, o-nitrobenzyl tosylate, arylsulfonic acid p-nitrobenzyl esters, sulfonylacetophenones, Fe-allene complex PF6 salts and the like can be used.

A top view of the state where the insulator 112 is formed is shown in FIG. Although the insulator 112 can be formed as a whole as shown in FIG. 2B, it may be selectively formed in the contact hole 110 region so as to cover the lower electrode. The present invention is characterized in that a memory element is formed in the region of the contact hole 110, and can function as a memory element if the lower electrode and the upper electrode are not short-circuited.

In this embodiment mode, description is made focusing on one contact hole 110 region. However, a memory element may be formed using the other contact hole, or a memory element may be formed in both contact holes. Good. That is, both the electrodes 109 and 109 'can be applied as the lower electrode of the memory element. On the other hand, when a memory element is formed in any one of the contact holes, a memory material may be selectively formed. In the contact hole where the memory material is not formed, a lower electrode and an upper electrode are stacked, and this can be applied as a source electrode or a drain electrode.

Thereafter, a conductive film to be the upper electrode 113 is formed so as to cover the insulator 112. The conductive film can be formed in a manner similar to that of the electrode 109; however, the conductive film is not necessarily formed using the same material and the same process. The upper electrode 113 is electrically connected to a control circuit, and the control circuit can perform a writing operation or a reading operation on the memory element based on a change in the state of the insulator 112. Specifically, the memory element can have a state where the lower electrode and the upper electrode are not short-circuited (referred to as an initial state) and a state where a short-circuited state (referred to as a short-circuited state). It can have information of “0” or “1”. In the short circuit state, the upper electrode and the lower electrode may be short-circuited on the side surface side or the upper surface side of the contact hole, in addition to the short circuit between the upper electrode and the lower electrode on the bottom surface side of the contact hole. In the contact hole side surface or the boundary region between the side surface and the upper surface, the film thickness of the insulator is often reduced due to film formation, and the upper electrode and the lower electrode can be easily short-circuited.

In addition, when a memory element is formed in one contact hole, compared with a case where a memory element is formed in both contact holes, an applied voltage for causing the memory element to be in a short circuit state is increased. In this case, the source / drain breakdown voltage of the thin film transistor may be set higher. In order to increase the source / drain breakdown voltage, there is a method of increasing the gate length of the thin film transistor. Note that the memory element of the present invention can reduce the film thickness of the insulator serving as a memory material on the side surface side or the upper surface side of the contact hole, so even if the memory element is formed in both contact holes. Compared with the conventional structure, it is possible to achieve a short-circuit state with a low applied voltage.

FIG. 15 shows voltage-current characteristics of the memory element. Initial state: A current does not flow to the memory element in A unless a voltage (V _B ) or higher is applied. On the other hand, in the short-circuit state: B, a current flows only by applying a slight voltage (V _A : V _B <V _A ) to the memory element. Based on this difference in voltage value, information of “0” or “1” can be provided. Note that the voltage V _A is a voltage value at the intersection of the voltage-current characteristic C of the thin film transistor 107 and the initial state A. The voltage V _B is a voltage value at the intersection of the voltage-current characteristic C of the thin film transistor 107 and the short-circuit state. By reading this voltage value, the control circuit can provide information of “0” or “1”. Details of these operations will be described in the following embodiments.

Thereafter, preferably, a passivation film 115 is formed as shown in FIG. The passivation film 115 can be formed from a single layer structure or a stacked structure, and an inorganic material is preferably used. In particular, silicon nitride or silicon oxynitride is preferably used. This is because the insulating film containing nitrogen has an effect of preventing entry of alkali metal.

Note that in order to short-circuit the lower electrode and the upper electrode, when the thin film transistor 107 is turned on based on a selection signal input from the word line, a current flows between the source electrode and the drain electrode, and the current flows so that insulation is achieved. The property of the object 112 is changed. For example, the property, that is, the state of the insulator 112 changes due to Joule heat generated by the flow of the current. Further, when the current flows, dielectric breakdown occurs in the insulator 112, and the state changes. By utilizing such a change in the state, the lower electrode and the upper electrode can be short-circuited.

As described above, a memory element controlled by the thin film transistor 107 can be formed. According to the present invention, a memory element is formed in a contact hole and a source electrode or a drain electrode functions as a lower electrode of the memory element. Therefore, the number of steps can be reduced and cost can be reduced.

Although the case where a circular shape is used as the contact hole has been described above, the shape is not limited to this, and may be an elliptical shape as shown in FIG. 16A and a rectangular shape as shown in FIG. .

(Embodiment 2)
In this embodiment mode, a mode in which a plurality of memory elements are formed in a contact hole will be described.

As in the first embodiment, contact holes 110a and 110b are formed in the second insulating film 108 as shown in FIG. The contact holes 110a and 110b can be formed by a dry etching method or a wet etching method.

A top view of this state is shown in FIG. As shown in FIGS. 3 and 4, in the present embodiment, the diameters, depths, taper angles, and the like of the contact holes 110a and 110b are equal, but the present invention is not necessarily limited thereto. That is, the present invention is characterized in that a memory element is formed in a contact hole, and the source electrode or the drain electrode functions as a lower electrode of the memory element, and is not limited to the shape or the number of contact holes. . This is because a memory element is formed in the contact hole and the source electrode or the drain electrode functions as a lower electrode of the memory element, whereby the number of steps can be reduced and the cost can be reduced.

Thereafter, as in Embodiment Mode 1, an insulator 112, an upper electrode 113, and a passivation film 115 are formed.

According to the present invention, a memory element is formed in a contact hole and a source electrode or a drain electrode functions as a lower electrode of the memory element. Therefore, the number of steps can be reduced and cost can be reduced.

(Embodiment 3)
In this embodiment, a mode in which surface modification is performed on a surface to be formed before the insulator 112 is formed will be described.

As shown in FIG. 5A, the electrodes 109 are formed in the same manner as in Embodiment Mode 1. Then, surface modification is performed on the entire surface of the electrode 109 and the second insulating film 108. In order to perform surface modification as a whole as described above, plasma treatment (oxygen plasma treatment) in an oxygen atmosphere may be performed. As a result, the surface as indicated by 125 is modified in its state (this is referred to as surface modification).

The film thickness of the insulator 112 is preferably thinner in order to simplify the short circuit between the lower electrode and the upper electrode. For example, in order to use an inorganic material for the insulator 112 and cause dielectric breakdown, it is preferable that the thickness of the insulator 112 be 5 nm to 100 nm, preferably 10 nm to 60 nm. For this reason, when forming the insulator 112 in the contact hole 110 or the like, there is a concern that the end face of the contact hole 110 may be cut off. Therefore, as in this embodiment mode, by performing oxygen plasma treatment on the surface on which the insulator 112 is formed, adhesion can be improved, and it is preferable to prevent disconnection. That is, it is preferable to perform surface modification on the surface on which the insulator 112 is formed because the insulator 112 is easily manufactured.

As a means for performing such surface modification, a film having high adhesion to each of the insulator 112 and the electrode 109 may be formed in addition to the oxygen plasma treatment. This is because any means for improving the adhesiveness of the insulator 112 can provide an effect of preventing disconnection of the insulator 112.

In order to prevent the disconnection, the insulator 112 is preferably formed by a vapor deposition method. This is because when the insulator 112 is formed by an evaporation method, the film formation accuracy on the side surface of the contact hole 110 is higher than that of the spin coating method.

Thereafter, as shown in FIG. 5B, an upper electrode 113 and a passivation film 115 are formed as in the first embodiment.

According to the present invention, a memory element is formed in a contact hole and a source electrode or a drain electrode functions as a lower electrode of the memory element. Therefore, the number of steps can be reduced and cost can be reduced.

(Embodiment 4)
In this embodiment mode, unlike the above embodiment mode, a mode in which surface modification is selectively performed before the insulator 112 is formed will be described.

As shown in FIG. 6A, surface modification is performed only on at least the electrode 109. For example, a conductive film to be the electrode 109 is formed, and the surface of the conductive film is scratched and subjected to surface modification by a sputtering method. For example, an element substrate in which a conductive film is formed is placed in the film formation chamber, and the process is performed under such a condition as to scratch the surface of the conductive film. For example, the processing is performed with the pressure from 0.6 Pa (0.6 / 133 Torr) to 1.0 Pa (1/133 Torr), the power from 200 W to 400 W, and the processing time from 3 minutes to 15 minutes. After that, by patterning the conductive film so as to have a predetermined shape, the electrode 109 in which only the surface 126 is subjected to surface modification can be formed. Thus, the adhesion of the insulator 112 can be ensured by the surface-modified electrode 109.

In this embodiment mode, it suffices that the insulator 112 be formed without being disconnected in the contact hole 110, so that the surface on which the insulator 112 is formed may be selectively modified. In order to prevent the disconnection, the insulator 112 is preferably formed by a vapor deposition method. This is because when the insulator 112 is formed by an evaporation method, the film formation accuracy on the side surface of the contact hole 110 is higher than that of the spin coating method.

In addition to scratching the surface on which the insulator 112 is formed using a sputtering method, a film is formed under conditions where the surface is rough at the time of forming the conductive film, or an unevenness is formed on the surface on which the conductive film is formed, and the conductive film is formed along the unevenness. A film may be formed, or the film may be physically damaged using a dry etching method, a frost processing method, a sand blasting method, or the like. In the case where a sputtering method is used for manufacturing the conductive film, the process can be simplified by performing sputtering treatment for scratching in the same deposition chamber.

Thereafter, as shown in FIG. 6B, an upper electrode 113 and a passivation film 115 are formed as in the first embodiment.

According to the present invention, a memory element is formed in a contact hole and a source electrode or a drain electrode functions as a lower electrode of the memory element. Therefore, the number of steps can be reduced and cost can be reduced.

(Embodiment 5)
In this embodiment, a mode in which the insulator 112 is formed by a droplet discharge method will be described.

As shown in FIG. 7A, an electrode 109 is formed in the contact hole 110 as in the first embodiment. Then, a droplet (dot) 151 having the material of the insulator 112 is dropped from the predetermined nozzle 150 into the contact hole 110. Such a droplet discharge method is also called an inkjet method. The droplet 151 may be only the material of the insulator 112 or the material may be dispersed in a solvent.

Note that before the insulator 112 is formed, surface modification may be performed on a surface on which the insulator 112 is formed as described in Embodiment 3 or 4.

Thereafter, as shown in FIG. 7B, an insulator 112 is formed in the contact hole 110. At this time, an insulator 112 is formed in the contact hole 110 so that the electrode 109 and an upper electrode to be formed later are not short-circuited. Therefore, it is not necessary to fill the contact hole 110 with the insulator 112. Further, by using the surface tension, the insulator 112 can be thinly formed at the end portion of the electrode 109. As a result, the end of the electrode 109 can be easily short-circuited with the upper electrode.

Furthermore, the wettability with respect to the droplet 151 may be reduced around the end of the electrode 109. As a result, the droplet 151 can be selectively dropped on the electrode 109. As a method for reducing such wettability, a silane coupling agent may be selectively applied. As the silane coupling agent, a fluorine-based silane coupling agent having a fluoroalkyl group (fluoroalkylsilane (FAS)) is used. As typical FAS, heptadefluorotetrahydrodecyltriethoxysilane, heptadecafluorotetrahydrodecyl is used. There are fluoroalkylsilanes such as trichlorosilane, tridecafluorotetrahydrooctyltrichlorosilane, and trifluoropropyltrimethoxysilane.

The insulator 112 formed by a droplet discharge method may be preferably fired. In particular, when the droplet 151 includes a solvent, the solvent is preferably removed by heat treatment and then baked.

Next, as shown in FIG. 7C, the upper electrode 113 is formed. Using the nozzle 152, droplets (dots) 153 having a material for the upper electrode 113 are dropped to form the upper electrode 113. When the upper electrode 113 is formed by a droplet discharge method, the materials include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), nickel (Ni ), Tantalum (Ta), bismuth (Bi), lead (Pb), indium (In), tin (Sn), zinc (Zn), titanium (Ti), or aluminum (Al), alloys made of these, It is preferable to use dispersible nanoparticles or silver halide fine particles.

In this embodiment mode, the upper electrode 113 is formed by a droplet discharge method; however, the present invention is not limited to this, and a sputtering method or an evaporation method may be used. Further, the electrode 109 may be formed by a droplet discharge method.

In some cases, the upper electrode 113 formed by a droplet discharge method is preferably fired. In particular, when the droplet 153 includes a solvent, the solvent is preferably removed by heat treatment and then baked.

When the droplet discharge method is used in this manner, the utilization efficiency of the material is improved as compared with the photolithography process, and the cost can be reduced, the manufacturing time can be shortened, and the waste liquid processing amount can be reduced. As a result, the manufacturing cost of the memory element can be reduced.

Thereafter, a passivation film 115 is formed.

According to the present invention, a memory element is formed in a contact hole and a source electrode or a drain electrode functions as a lower electrode of the memory element. Therefore, the number of steps can be reduced and cost can be reduced.

(Embodiment 6)
In this embodiment mode, a mode of a contact hole structure different from the above embodiment mode will be described.

As shown in FIG. 8, as in the first embodiment, a contact hole is formed and an electrode 109 is formed. At this time, a word line is also formed at the same time as described above, but other wirings 209 can be formed. In order to increase the added value of the memory element, many wirings 209 are necessary. In that case, the formation of the third insulating film 130 can increase the degree of freedom in layout area such as wiring, contact hole arrangement, and memory element arrangement. Needless to say, the third insulating film 130 may be provided even when the wiring 209 is not formed.

The third insulating film 130 can be manufactured using the same material or the same method as the second insulating film 108 described in Embodiment 1.

Then, a contact hole 210 is formed in the third insulating film 130 in accordance with the position of the contact hole formed in the second insulating film 108. After that, as in Embodiment Mode 1, the insulator 112, the upper electrode 113, and the passivation film 115 are formed in the contact hole 210, and the memory element is completed. At this time, the end portion of the third insulating film 130 around the contact hole 210 may be rounded. This is because the contact hole 210 is considered to be deeper than the contact hole 110, and therefore, an effect of preventing disconnection of the insulator 112 and the upper electrode 113 can be expected.

This embodiment can be freely combined with the above embodiment. For example, surface modification may be performed before the insulator 112 is formed, or the insulator 112, the upper electrode 113, and the like may be formed by a droplet discharge method.

According to the present invention, a memory element is formed in a contact hole and a source electrode or a drain electrode functions as a lower electrode of the memory element. Therefore, the number of steps can be reduced and cost can be reduced.

(Embodiment 7)
In this embodiment mode, a mode in which an amorphous semiconductor film is used for a thin film transistor will be described.

As shown in FIG. 9, a bottom gate type in which a gate electrode is provided below can be applied to a thin film transistor using an amorphous semiconductor film. A conductive film to be the gate electrode 205 is formed over the substrate 100 and patterned into a predetermined shape. After that, an insulating film to be the gate insulating film 204 is formed so as to cover the gate electrode 205. Next, an amorphous semiconductor film 206 and an n-type semiconductor film 208 are sequentially formed and patterned into a predetermined shape. Then, a conductive film to be the source or drain electrode 211 is formed and patterned into a predetermined shape. The n-type semiconductor film 208 is etched using the source and drain electrodes 211. At this time, part of the amorphous semiconductor film 206 is also etched. Such a structure of a thin film transistor in which part of an amorphous semiconductor film is etched can be referred to as a channel etch type. In this manner, the thin film transistor 207 including an amorphous semiconductor film can be formed.

Thereafter, a first insulating film 212 functioning as a protective film is preferably formed. In the channel etch type structure, since the amorphous semiconductor film 206 is partly exposed, the first insulating film 212 is preferably provided to prevent entry of an impurity element, moisture, or the like. The first insulating film 212 having such a function is preferably formed using an insulating film containing nitrogen, typically silicon nitride.

Next, as in Embodiment Mode 1, a second insulating film 108 is formed, and a contact hole 110 is formed. Then, an electrode 109 is formed in the contact hole 110. In this embodiment mode, the electrode 109 functions as a lower electrode.

Thereafter, as in Embodiment Mode 1, an insulator 112, an upper electrode 113, and a passivation film 115 are formed.

This embodiment can be freely combined with the above embodiment. For example, surface modification may be performed before the insulator 112 is formed, or the insulator 112, the upper electrode 113, and the like may be formed by a droplet discharge method.

In the present invention, since a memory element is formed in the contact hole and the electrode 109 functions as a lower electrode of the memory element, a crystallization process is unnecessary, and the number of processes can be reduced and cost can be reduced.

(Embodiment 8)
In this embodiment, a structure of a device (memory device) including the memory element manufactured according to the above embodiment will be described.

As illustrated in FIG. 10, the memory device 508 includes a memory cell array 506 and a control circuit. The control circuit includes a column decoder 501, a row decoder 502, a read circuit 504, a write circuit 505, and a selector 503.

The memory cell array 506 includes a bit line Bm (m = 1 to x), a word line Wn (n = 1 to y), and a memory element 507 at each intersection of the bit line and the word line. The memory element is manufactured according to the above embodiment mode. The bit line is controlled by the selector 503 and the word line is controlled by the row decoder 502.

The column decoder 501 receives an address signal designating a column of the memory cell array, and gives a signal to the selector 503 of the designated column. The selector 503 receives a signal from the column decoder 501 and selects a bit line in a specified column. The row decoder 502 receives an address signal designating a row of the memory cell array and selects a word line in the designated row. Through the above operation, one memory element 507 corresponding to the address signal is selected. The reading circuit 504 reads data included in the selected memory element, and preferably amplifies and outputs the data. The writing circuit 505 generates a voltage necessary for writing and applies a voltage to the selected memory element, thereby setting a short circuit state and writing data.

FIG. 11 shows a configuration of the writing circuit 505. The write circuit 505 includes a voltage generation circuit 701, a timing control circuit 702, switches SW0 and SW1, and an output terminal Pw. The voltage generation circuit 701 is composed of a booster circuit or the like, generates a voltage V1 necessary for writing, and outputs it from the output Pa. The timing control circuit 702 generates signals S0 and S1 for controlling the switches SW0 and SW1, respectively, from a write control signal (described as WE), a data signal (described as DATA), a clock signal (described as CLK), and the like. , Output from outputs P0 and P1, respectively. The switch SW0 is connected to the ground, SW1 is connected to the output Pa of the voltage generation circuit 701, and the output voltage Vw from the output Pw of the write circuit can be switched depending on which connection state the switch is in.

Next, the writing operation when the initial state in which the conductivity of the memory element is not changed is “0” and the short-circuit state in which the conductivity of the memory element is changed is “1” will be described. First, when WE becomes Hi (a high voltage enabling writing), the column decoder 501 receiving the address signal designating the column gives a signal to the selector 503 of the designated column, and the selector 503 sends the bit line of the designated column to the writing circuit. Connect to output Pw. The unspecified bit line is not connected (described as floating), and the output voltage Vw of the write circuit is V1. Similarly, the row decoder 502 that has received an address signal designating a row applies a voltage V2 to the word line of the designated row, and applies 0 V to an undesignated word line. Through the above operation, one memory element 507 corresponding to the address signal is selected. At this time, 0 V is applied to the upper electrode.

By simultaneously receiving DATA = Hi, the voltage generation circuit 701 can generate the voltage V1 and output it from the output Pa. The timing control circuit 702 can generate signals S0 and S1 for controlling the switches SW0 and SW1 from WE, DATA, CLK, power supply voltage (VDD), and the like, and can output them from the outputs P0 and P1. The switches SW0 and SW1 are switched by the signal, and the writing circuit 505 can output the voltage V1 as the output voltage Vw from the output Pw.

In the selected memory element, the voltage V2 is applied to the word line, the voltage V1 is applied to the bit line, and 0 V is applied to the upper electrode by the above operation. Then, the impurity regions of the thin film transistors 107 and 207 are turned on, and the voltage V1 of the bit line is applied to the lower electrode of the memory element. As a result, the conductivity of the memory element changes, and a short circuit state is established, and “1” is written.

When WE becomes Lo (a low voltage at which writing is not permitted), all the word lines become 0 V, and all the bit lines and the upper electrodes are in a floating state. At this time, the timing control circuit generates Lo as the signals S0 and S1, respectively, and outputs them from the outputs P0 and P1, and the output Pw enters a floating state. With the above operation, writing is not performed.

Next, writing of “0” will be described. Writing “0” is writing that does not change the conductivity of the memory element, and this is realized by applying no voltage to the memory element, that is, maintaining the initial state. First, when WE becomes Hi as in the case of writing “1”, the column decoder 501 receiving the address signal designating the column gives a signal to the selector of the designated column, and the selector 503 outputs the bit line of the designated column to the output of the write circuit. Connect to Pw. At this time, the unspecified bit line is in a floating state. Similarly, the row decoder 502 that has received an address signal designating a row applies a voltage V2 to the word line of the designated row, and applies 0 V to an undesignated word line. Through the above operation, one memory element 507 corresponding to the address signal is selected. At this time, 0 V is applied to the upper electrode.

At the same time, DATA = Lo is received, and the timing control circuit 702 generates control signals S0 = Hi and S1 = Lo, and outputs the control signals from the outputs P0 and P1, respectively. The switch SW0 is turned on and SW1 is turned off by the control signal, and 0V is output from the output Pw as the output voltage Vw.

In the selected memory cell, V2 is applied to the word line by the above operation, and 0 V is applied to the bit line and the common electrode. Then, no voltage is applied to the memory element, and the conductivity does not change, so the initial state “0” is maintained.

When WE becomes Lo, all the word lines are set to 0 V, and all the bit lines and the upper electrodes are in a floating state. At this time, the timing control circuit generates Lo as the signals S0 and S1 and outputs them from the outputs P0 and P1, respectively, and the output Pw is in a floating state.

In this way, “1” or “0” can be written.

Next, the reading operation will be described. FIG. 12 shows a storage device from which a part necessary for explaining reading is extracted, and the other configurations are the same as those in FIG. A reading circuit 504 included in the memory device includes a voltage generation circuit 307, a sense amplifier 308, a resistance element 309, a data output circuit 310, and an input / output terminal Pr. The sense amplifier 308 is provided between the resistance element 309 and the input / output terminal Pr. Let α be the point input to.

The voltage generation circuit 307 generates voltages Vread and Vref necessary for the read operation and outputs them from P1 and P2, respectively. Since reading data uses a low voltage, the power supply voltage (VDD) can be used as the voltage Vread. The voltage Vref is lower than the voltage Vread, and is generated by resistance division between the power supply voltage and the ground voltage. Therefore, the voltage generation circuit 307 included in the reading circuit 504 has a configuration different from that of the voltage generation circuit included in the writing circuit 505. The sense amplifier 308 compares the voltage at the point α with the voltage Vref and outputs the result. The data output circuit 310 is controlled by a read control signal (described as RE), acquires data included in the memory element from the output of the sense amplifier 308, amplifies the data, and outputs the data.

Next, an operation of reading data included in the memory element 517 in the m-th column and the n-th row will be described. First, the column decoder 501 receiving an address signal designating a column gives a signal to the m-column selector 503, and the selector 503 connects the m-column bit line Bm to the input / output terminal Pr of the read circuit 504. At this time, the unspecified bit line is in a floating state. Similarly, the row decoder 502 that has received an address signal designating a row applies a voltage Vread to the n word lines Wn, and applies 0 V to an undesignated word line. At the same time, voltages Vread and Vref are output from the outputs P1 and P2 of the voltage generation circuit 307, respectively, and 0 V is applied to the upper electrode 113. By the above operation, the voltage Vread is applied to the series resistance of the resistance element 309 and the memory element 517, and the voltage at the point α takes a value obtained by resistance division by these two elements.

Here, FIG. 15 will be referred to again to explain the voltage that can be taken at the point α. The voltage that can be taken by the point α corresponds to the voltage value on the horizontal axis. A characteristic A in FIG. 15 is an IV characteristic of the memory element to which “1” is written, a characteristic B is an IV characteristic of the memory element to which “0” is written, and a characteristic C is the thin film transistor. It is an IV characteristic. Regarding the characteristic A of the memory element in which “1” is written, since the upper electrode and the lower electrode are short-circuited and the electric resistance of the memory element is small, the current value increases rapidly even if the voltage at the point α is small. To do. On the other hand, the characteristic B of the memory element in which “0” is written indicates that the memory element exhibits a diode characteristic, so that the current value starts to increase only when the voltage at the point α exceeds a certain value. In the characteristic C of the thin film transistor, the current value decreases as the voltage at the point α increases, and the current value becomes 0 when the voltage at the point α is Vread.

From FIG. 15, the voltage that can be taken by the point α can be explained as follows. When "1" is written in the memory element, "1" write voltage V _A of the I-V characteristic A and the thin film transistor of the I-V characteristic C and the intersection A of the storage elements of the point α performing the Voltage. When “0” is written in the memory element, the voltage V _{B at} the intersection B between the IV characteristic B of the memory element in which “0” is written and the IV characteristic C of the thin film transistor is the point α. Voltage.

The sense amplifier 308 has a function of comparing the voltage at the point α with the magnitude of Vref. Here, the voltage Vref is a voltage larger than the voltage V _A and smaller than the voltage V _B , and is preferably (VA + VB) / 2. By setting the voltage in this manner, when the sense amplifier 308 determines that the voltage at the point α is smaller than Vref, the voltage at the point α is determined to be the voltage _VA , and “1” is stored in the storage element. It can be seen that is written. Conversely, when it is determined that the voltage at the point α is higher than Vref, it is determined that the voltage at the point α is the voltage V _B , and it is understood that “0” is written in the memory element.

When the voltage at the point α is smaller than Vref, the sense amplifier 308 outputs a signal indicating “1”, and when the voltage at the point α is larger than Vref, the sense amplifier 308 outputs a signal indicating “0”.
The data output circuit 310 has a function of capturing data from the output signal of the sense amplifier 308 based on an RE input from the outside, amplifying the data, and outputting the data. Reading can be performed by the above operation.

Note that in this embodiment mode, the resistance value of the memory element is read as a voltage value, but the present invention is not limited to this. For example, it is possible to adopt a method of reading the resistance value of the memory element by replacing it with the magnitude of current, or a method of precharging the bit line.

The control circuit including the memory cell array 506, the column decoder 501, the row decoder 502, the reading circuit 504, the writing circuit 505, and the selector 503 can be formed using transistors formed over the same substrate. For example, a memory cell array and a control circuit can be formed using a thin film transistor formed over a glass substrate. Further, the control circuit can be formed using an integrated circuit (hereinafter referred to as an IC chip) made of a silicon wafer. In this case, the IC chip is preferably mounted on a substrate on which a memory cell array is formed. In particular, when a memory cell array is formed using a thin film transistor using an amorphous semiconductor film, the control circuit is preferably formed from an IC chip.

(Embodiment 9)
In this embodiment, a structure of a circuit including a memory element will be described.

As illustrated in FIG. 13A, one cell of a circuit including a memory element includes a transistor 401 and a memory element 402. The transistor 401 has a gate electrode connected to the word line Wn, one of a source electrode and a drain electrode connected to the bit line Bm, and the other connected to the memory element 402. The thin film transistors 107 and 207 described in the above embodiment can be used for the transistor 401, and the conductive film which is the other of the source electrode and the drain electrode functions as the lower electrode of the memory element 402. As described above, the memory element 402 has a structure in which an insulator and an upper electrode are sequentially stacked on a lower electrode. The upper electrode 403 of the memory element 402 can be shared with the upper electrode of the memory element of each cell, and a constant voltage is applied during writing and reading of the memory device.

The memory element 402 that can be selected by the transistor 401 can have an initial state and a short-circuit state, and can represent “0” and “1” depending on the state.

As described above, the memory element 402 may have an insulator exhibiting different diode characteristics before and after voltage application. Therefore, a memory circuit may be formed using a cell in which the memory element 412 is connected to the diode element 411 as illustrated in FIG. Since the diode element 411 can employ a structure in which one of a source electrode and a drain electrode of a transistor and a gate electrode are connected, the conductive film that is the other of the source electrode and the drain electrode is formed under the memory element 402. It can function as an electrode.

According to the present invention, a memory element is formed in a contact hole and a source electrode or a drain electrode functions as a lower electrode of the memory element. Therefore, the number of steps can be reduced and cost can be reduced.

(Embodiment 10)
In this embodiment mode, a semiconductor device that includes a memory device, a control circuit, and an antenna and transmits and receives information wirelessly, a so-called RFID mode is described.

FIG. 14 shows the structure of the semiconductor device of the present invention. The semiconductor device 601 includes a resonance circuit 602 having an antenna and a resonance capacitor, a power supply circuit 603, a clock generation circuit 604, a demodulation circuit 605, a control circuit 606, a storage device 607, an encoding circuit 608, and a modulation circuit 609. Note that the semiconductor device is not limited to the above configuration, and may include a central processing unit (CPU), a congestion control circuit, and the like. In addition, the semiconductor device 601 is not limited to a structure including an antenna, and may include only wiring for connecting the antenna. In this case, when transmitting / receiving information to / from the semiconductor device, an antenna provided separately is connected to the wiring. That is, it is a contact type semiconductor device.

Since the semiconductor device 601 of the present invention includes the resonance circuit 602 having an antenna, the semiconductor device 601 can receive power from electromagnetic waves emitted from the reader / writer 610 and can transmit and receive information to and from the reader / writer 610 wirelessly. The reader / writer 610 is connected to the computer 612 via the communication line 611, and supplies power to the semiconductor device 601 and transmits / receives information to / from the semiconductor device 601 under the control of the computer 612.

The resonance circuit 602 receives an electromagnetic wave emitted from the reader / writer 610 and generates an induced voltage. This induced voltage becomes power of the semiconductor device 601 and includes information transmitted from the reader / writer 610. The power supply circuit 603 rectifies the induced voltage generated in the resonance circuit 602 with a diode, stabilizes it using a capacitor, and supplies it to each circuit. The clock generation circuit 604 generates a clock signal having a necessary frequency based on the induced voltage generated in the resonance circuit 602. The demodulation circuit 605 demodulates data from the induced voltage generated in the resonance circuit 602. The control circuit 606 controls the storage device 607. Therefore, the control circuit 606 includes an information determination circuit for reading data from the reader / writer 610 in addition to the generation of the memory control signal. The storage device 607 includes a writing circuit, a reading circuit, and the like. The storage device 607 holds data unique to the semiconductor device 601. Here, the memory device 607 is manufactured as described in the above embodiment mode. The encoding circuit 608 converts data included in the storage device 607 into an encoded signal. The modulation circuit 609 modulates a carrier wave based on the encoded signal.

Although this embodiment mode shows an example in which the semiconductor device 601 receives power supply from the reader / writer 610, the present invention is not limited to this embodiment mode. For example, the semiconductor device 601 includes a battery or the like inside, can receive power from the battery, and can transmit and receive information wirelessly with a reader / writer.

By continuously applying voltages in a plurality of stages to the memory element, it is possible to change the conductivity even with a small size memory element with a low voltage and a short voltage application time. In addition, the current consumption at the time of writing can be reduced by the means of the present invention, and the time for which the current consumption can be maximized can be shortened. Therefore, the voltage generating circuit included in the writing circuit and the semiconductor device can be downsized. can do. In addition, when a high pulse voltage is applied to the memory element, variations in conductivity change occur, which reduces the reliability of the semiconductor device. However, by continuously applying a plurality of stages of voltages as in the present invention, the amount of change in conductivity of the memory element becomes constant, and the reliability of the semiconductor device can be improved. Furthermore, since the present invention uses an organic compound as a material for a memory element, it can be manufactured on a large glass substrate or a flexible substrate by a low temperature process, and an inexpensive semiconductor device can be provided.

Note that this embodiment mode can be freely combined with the above embodiment modes.

In the present invention, a memory element is formed in a contact hole and a source electrode or a drain electrode functions as a lower electrode of the memory element, so that the number of steps can be reduced and the cost of a semiconductor device can be reduced.

It is a figure showing a manufacturing process of a memory element It is a top view showing a manufacturing process of a memory element It is a figure showing a manufacturing process of a memory element It is a top view showing a manufacturing process of a memory element It is a figure showing a manufacturing process of a memory element It is a figure showing a manufacturing process of a memory element It is a figure showing a manufacturing process of a memory element It is a figure showing a manufacturing process of a memory element It is a figure showing a manufacturing process of a memory element It is the figure which showed the structure of the memory | storage device It is the figure which showed the structure of the writing circuit. It is the figure which showed the structure of the read-out circuit. It is the figure which showed the circuit structure of the memory element. It is the figure which showed the structure of the semiconductor device It is the figure which showed the IV characteristic of the memory element. It is a top view showing a manufacturing process of a memory element

Claims (13)

A semiconductor film having an impurity region formed over the insulating surface;
An insulating film in contact with the semiconductor film and provided with an opening on the impurity region;
A conductive film that is provided in the opening and functions as one of a source electrode or a drain electrode and a lower electrode electrically connected to the impurity region;
In the opening, an insulator provided on the conductive film;
And a top electrode provided on the insulator. A semiconductor film having an impurity region formed over the insulating surface;
A first insulating film in contact with the semiconductor film and provided with a first opening on the impurity region;
A first conductive film provided in the first opening and functioning as one of a source electrode or a drain electrode electrically connected to the impurity region;
A second insulating film provided to cover an end of the first conductive film and having a second opening on the impurity region;
A second conductive film connected to the first conductive film and functioning as a lower electrode;
An insulator provided on the second conductive film in the first opening and the second opening;
And a top electrode provided on the insulator. In claim 1 or 2,
The insulator is a material whose properties are changed by an optical action or a thermal action, and the lower electrode and the upper electrode can be short-circuited, and has silicon oxide, silicon nitride, or silicon oxynitride A storage device. In claim 1 or 2,
The insulator is a material whose properties are changed by optical action or thermal action, and the lower electrode and the upper electrode can be short-circuited,
4,4′-bis [N- (1-naphthyl) -N-phenylamino] biphenyl (abbreviation: α-NPD) and 4,4′-bis [N- (3-methylphenyl) -N-phenylamino] Biphenyl (abbreviation: TPD), 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) triphenylamine (abbreviation: TDATA), 4,4 ′, 4 ″ -tris [N- (3 -Methylphenyl) -N-phenylamino] triphenylamine, 4,4'-bis (N- (4- (N, N-di-m-tolylamino) phenyl) -N-phenylamino) biphenyl, polyvinylcarbazole, A storage device comprising phthalocyanine, copper phthalocyanine, or vanadyl phthalocyanine. In any one of Claims 1 thru | or 4,
2. A memory device, wherein a plurality of openings of an insulating film provided on the one impurity region are provided. In any one of Claims 1 thru | or 5,
The memory device, wherein the semiconductor film has a crystalline structure or an amorphous structure. An impurity region is selectively formed in the semiconductor film formed on the insulating surface,
Forming an insulating film in contact with the semiconductor film;
Forming an opening in the insulating film so that the impurity region is exposed;
Forming a conductive film functioning as one of a source electrode or a drain electrode and a lower electrode electrically connected to the impurity region in the opening;
Forming an insulator on the conductive film;
A method for manufacturing a memory device, wherein an upper electrode is formed over the insulator. An impurity region is selectively formed in the semiconductor film formed on the insulating surface,
Forming an insulating film in contact with the semiconductor film;
Forming an opening in the insulating film so that the impurity region is exposed;
Forming a conductive film functioning as one of a source electrode or a drain electrode and a lower electrode electrically connected to the impurity region in the opening;
Surface modification is performed on the conductive film and the insulating film,
Forming an insulator on the conductive film;
A method for manufacturing a memory device, wherein an upper electrode is formed over the insulator. An impurity region is selectively formed in the semiconductor film formed on the insulating surface,
Forming an insulating film in contact with the semiconductor film;
Forming an opening in the insulating film so that the impurity region is exposed;
Forming a conductive film functioning as one of a source electrode or a drain electrode and a lower electrode electrically connected to the impurity region in the opening;
Forming an insulator on the conductive film;
Forming an upper electrode on the insulator;
A method for manufacturing a memory device, wherein surface modification is performed on the upper electrode by a sputtering method. Forming an impurity region in the semiconductor film on the insulating surface;
Forming an insulating film in contact with the semiconductor film;
Forming an opening in the insulating film so that the impurity region is exposed;
Forming a conductive film functioning as one of a source electrode or a drain electrode and a lower electrode electrically connected to the impurity region in the opening;
Surface modification is performed around the opening and the upper surface of the conductive film,
Dropping an insulator on the conductive film in the opening by a droplet discharge method,
Forming an upper electrode on the insulator;
A method for manufacturing a memory device. In any one of Claims 7 thru | or 10,
The method for manufacturing a memory device, wherein the semiconductor film has a crystalline structure or an amorphous structure. In any one of Claims 7 thru | or 11,
The insulator is a material whose properties are changed by an optical action or a thermal action, and the lower electrode and the upper electrode can be short-circuited, and has silicon oxide, silicon nitride, or silicon oxynitride A method for manufacturing a memory device. In any one of Claims 7 thru | or 11,
The insulator is a material whose properties are changed by an optical action or a thermal action, and the lower electrode and the upper electrode can be short-circuited,
4,4′-bis [N- (1-naphthyl) -N-phenylamino] biphenyl (abbreviation: α-NPD) and 4,4′-bis [N- (3-methylphenyl) -N-phenylamino] Biphenyl (abbreviation: TPD), 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) triphenylamine (abbreviation: TDATA), 4,4 ′, 4 ″ -tris [N- (3 -Methylphenyl) -N-phenylamino] triphenylamine, 4,4'-bis (N- (4- (N, N-di-m-tolylamino) phenyl) -N-phenylamino) biphenyl, polyvinylcarbazole, A method for manufacturing a memory device, comprising phthalocyanine, copper phthalocyanine, or vanadyl phthalocyanine.

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