JP2001148471A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely prevent a semiconductor integrated circuit device equipped with a DRAM and a logic circuit from malfunctionings due to high-frequency noises. SOLUTION: A noise reduction capacitor element Cn of the same shape and size with a data storage capacitor element Cs located on a memory cell selection MISFET is provided to a part of a substrate. An N+-type semiconductor region 6, where the lower electrode 49 of the capacitor element Cn is connected, is formed in an active region which is wider in area than an active region, where the source and drain (N--type semiconductor region 11) of a memory cell selection MISFET Qs are provided. A through-hole 43 and a contact hole 21, which connect the lower electrode 49 of the noise reduction capacitor Cn to an N+-type semiconductor region 6 are wider in opening area than a through-hole 43 and a contact hole 21 which connect the data storage capacitor element Cs to either of the source and drain (N--type semiconductor region 11) of the memory cell selection MISFET Qs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device and, more particularly, to a DRAM (Dynamic Random Access Memory).
(Mory) and a logic circuit.

[0002]

2. Description of the Related Art In recent DRAMs, an information storage capacitor has been replaced with a memory cell selection MISF in order to compensate for a decrease in the amount of charge stored in the information storage capacitor accompanying the miniaturization of memory cells.
A so-called stacked / capacitive element structure arranged above the ET is adopted.

[0003] JP-A-10-74908 discloses a DRA.
As a measure to reduce power supply noise generated during the operation of the sense amplifier that amplifies a minute read signal from M, a noise reduction capacitor element formed simultaneously in the process of forming the information storage capacitor element of the memory cell is used as a sense amplifier. Discloses a technique of arranging between power supplies.

[0004]

SUMMARY OF THE INVENTION The present inventor has proposed a semiconductor integrated circuit device in which a storage unit is constituted by a DRAM.
As a method for speeding up the read operation of AM, SRA
A buffer memory using M (Static Random Access Memory) is provided, and multi-bit data is collectively read from the storage unit to the buffer memory, and is externally communicated with the outside via the buffer memory. We are considering to input and output data.

In order to collectively read multi-bit data from a DRAM, it is necessary to provide a large number of main amplifiers corresponding to each bit. The main amplifier amplifies the amplified signal of the sense amplifier, and the amplitude of the input signal is larger than that of the sense amplifier. Further, in order to perform high-speed operation, it is required to flow a larger current than a sense amplifier.

However, when attempting to perform batch reading of multi-bit memory cells for inputting / outputting data at high speed to / from the outside, peripheral noise such as an address selection circuit and buffers due to power supply noise during operation of the main amplifier. A malfunction occurs in the logic circuit portion forming the memory.

As a countermeasure, the present inventor is studying the arrangement of a noise-reducing capacitive element formed at the same time as the step of forming the information-storing capacitive element of the memory cell between the power supplies of the sense amplifiers. However, as the size of the capacitive element decreases with the miniaturization of the memory cell, the series parasitic resistance of the lower electrode terminal increases, and the cutoff frequency proportional to the reciprocal of the product of the capacitance and the resistance decreases. It has been found that it is difficult to reliably prevent malfunction of the circuit.

An object of the present invention is to provide a technique capable of reliably preventing a malfunction of a circuit due to high frequency noise in a semiconductor integrated circuit device having a DRAM and a logic circuit.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) In a semiconductor integrated circuit device according to the present invention, a memory cell selecting MIS is provided in a first region on a main surface of a semiconductor substrate.
Forming a memory cell comprising an FET, a first bit line connected to one of a source and a drain of the memory cell selecting MISFET, and a first capacitor connected to the other of the source and the drain; A second bit line and a second capacitance element having the same structure as the first capacitance element are formed in a second region of the main surface of the substrate, and
The bit line is connected to one of a source and a drain of the memory cell selecting MISFET through a first contact hole formed in a first insulating film above the memory cell selecting MISFET, and is connected to the first capacitive element. One electrode is connected to the memory cell selecting MIS through a second contact hole formed in the first insulating film and a first through hole formed in the second insulating film above the first insulating film.
Connected to the other of the source and drain of the FET,
The bit line is connected to a first diffusion layer of the semiconductor substrate via a third contact hole formed in the first insulating film, and one electrode of the second capacitor is formed in the first insulating film. The active region in which the first diffusion layer is formed is connected to the first diffusion layer of the semiconductor substrate via the formed fourth contact hole and the second through hole formed in the second insulating film. The area is equal to the MIS for memory cell selection.
The area is larger than the area of the active region in which the source and the drain of the FET are formed.

(2) In the semiconductor integrated circuit device of the present invention, the memory cell selecting MIS is provided in the first region on the main surface of the semiconductor substrate.
Forming a memory cell comprising an FET, a first bit line connected to one of a source and a drain of the memory cell selecting MISFET, and a first capacitor connected to the other of the source and the drain; A second bit line having an area larger than that of the first bit line and a second bit line having the same structure as the first capacitance element are formed in a second region of the main surface of the substrate.
A first bit line is connected to one of a source and a drain of the memory cell selecting MISFET through a first contact hole formed in a first insulating film above the memory cell selecting MISFET; Connected to
One electrode of the first capacitive element is connected via a second contact hole formed in the first insulating film and a first through hole formed in the second insulating film above the first insulating film. One electrode of the second capacitor is connected to the other of the source and the drain of the memory cell selecting MISFET, and one electrode of the second capacitor is connected to the second bit line via a second through hole formed in the second insulating film. Have been.

(3) In the semiconductor integrated circuit device of the present invention, the memory cell selecting MIS is provided in the first region on the main surface of the semiconductor substrate.
Forming a memory cell comprising an FET, a first bit line connected to one of a source and a drain of the memory cell selecting MISFET, and a first capacitor connected to the other of the source and the drain; A second capacitive element having the same structure as the first capacitive element is formed in a second region of the main surface of the substrate, and the first bit line is connected to a first insulating layer above the memory cell selecting MISFET. A first contact hole formed in the film is connected to one of a source and a drain of the memory cell selecting MISFET, and one electrode of the first capacitor is connected to a second electrode formed in the first insulating film. Connected to the other of the source and the drain of the memory cell selecting MISFET via a contact hole and a first through hole formed in a second insulating film above the first insulating film. And one electrode of the second capacitive element is connected to a fourth contact hole formed in the first insulating film and a second through hole formed in the second insulating film through a second electrode of the semiconductor substrate. The area of the active region connected to the first diffusion layer and having the first diffusion layer formed therein is larger than the area of the active region of the memory cell selecting MISFET in which the source and drain are formed.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

Embodiment 1 FIG. 1 is an overall plan view of a semiconductor substrate (chip) showing a schematic layout of a semiconductor integrated circuit device of the present embodiment.

On the main surface of the substrate (chip) 1, a storage section constituted by a DRAM is formed. The storage unit is
The substrate 1 is divided into an upper part (storage part 1) and a lower part (storage part 2), and each storage part is further divided into a plurality of memory arrays (MARY1 to MARY4). In an area adjacent to these memory arrays (MARY1 to MARY4), peripheral circuits such as an X-system address selection circuit for performing a word line selection operation and a Y-system address selection circuit for performing a bit line selection operation are formed. .

At the center of the main surface of the substrate 1, a plurality of SRAM macros serving as buffer memories are formed. Although not shown, areas (logic circuit sections) adjacent to these SRAM macros include logic circuits for controlling input / output of data between the SRAM macro and the memory array (MARY), and external terminals. An input / output circuit for controlling the input / output of data between them is formed.

FIG. 2 is an enlarged layout diagram showing a part of the memory array (MARY) (a region surrounded by a dashed line in FIG. 1). The memory array (MARY) is divided into a number of subarrays (SARY), and sense amplifiers (S) are arranged above and below each subarray (SARY).
A) is formed, and a sub-word driver (SW) is provided on the left and right.
D) is formed. In addition, the memory array (MAR
In a region adjacent to Y), a main amplifier (MA), a write amplifier (WA), and a control circuit (RWC) thereof are formed.

In a region adjacent to the main amplifier (MA), the write amplifier (WA) and its control circuit (RWC), a noise countermeasure capacitive element (Cn) of the main amplifier (MA) is formed. The noise countermeasure capacitive element (Cn) is connected to a power supply line (Vdd,
Vss) to reduce noise generated in the power supply line during the amplification operation of the main amplifier (MA). As shown in FIG. 1, in addition to the no-capacitance element (Cn) formed in a region adjacent to the main amplifier (MA), a noise countermeasure capacitance element (Cn) includes a DRAM peripheral circuit (Y-system address selection circuit). ) And the SRAM macro are arranged as control noise countermeasure capacitance elements (Cn), and the input / output circuit and the SRA
It is arranged as an I / O noise countermeasure capacitance element (Cn) between the M macro. As described above, the semiconductor integrated circuit device according to the present embodiment includes the capacitive element (C) for noise suppression at the boundary between the storage unit, the SRAM macro, and the input / output circuit.
By arranging n), the propagation of noise generated in each power supply line is reduced, and the stable operation of the circuit is ensured.

FIG. 3 is a sectional view of a main part of the substrate 1.
The left part of the figure shows a part of the storage part (memory array), the center part shows a part of the logic circuit part, and the right part shows a part of the area (capacitance element part) in which the capacitive element for noise suppression is formed. ing.

The DRAM constituting the storage section comprises a memory cell selecting MISFET (Qs) and an information storage capacitor (Cs) connected in series to the MISFET (Qs). The information storage capacitor (Cs) is a memory cell selection MISF.
A lower electrode 49, a capacitor insulating film 50, and an upper electrode (plate electrode) 51 which are formed above ET (Qs) and constitute a storage node. The logic circuit is configured by a CMOS circuit combining an n-channel MISFET (Qn) and a p-channel MISFET (Qp).

The capacitance element (Cn) for noise suppression is provided by the D
It has the same shape and the same dimensions as the information storage capacitor (Cs) of the RAM. That is, the capacitance element (Cn) for noise suppression is composed of the electrode (lower electrode) 49 constituting the storage node, the capacitance insulating film 50, and the plate electrode (upper electrode) 51. The capacitive element (Cn) for noise suppression has a lower electrode 49 of another capacitive element (Cn) (not shown in FIG. 3) via the diffusion layer (n ⁺ type semiconductor region 6) of the substrate 1. One electrode is formed by being connected in parallel with the lower electrode 49, and the other electrode is formed by forming the upper electrode 51 correspondingly. Like the upper electrode 51 of the information storage capacitor (Cs) of the DRAM, the upper electrode 51 has a voltage (for example, Vdd) that is half the operating voltage of the sense amplifier (SA).
/ 2) is supplied. The lower electrode 49 is connected to the plug 4
4, 22, n ⁺ type semiconductor regions 6 and 14, plug 33, bit line BL and plug 55 are connected to lead wiring 59. That is, the capacitance element (Cn) for noise suppression can absorb power supply noise by connecting in parallel a capacitance element (Cn) having the same small capacitance value as the information storage capacitance element (Cs) of the DRAM. This constitutes a capacitive element having a possible large capacitance value.

Next, a method of manufacturing the semiconductor integrated circuit device of the present embodiment provided with the above-described noise countermeasure capacitive element (Cn) will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 4, an element isolation groove 2 is formed on a main surface of a substrate 1 made of, for example, p-type single crystal silicon. The element isolation groove 2 is formed by etching the substrate 1 in the element isolation region to form a groove having a depth of about 350 μm, then depositing a silicon oxide film 7 on the substrate 1 by a CVD method, and then forming a silicon oxide outside the groove. The film 7 is formed by removing the film 7 by a CMP (chemical mechanical polishing) method.

Next, a p-type impurity (for example, boron) is ion-implanted into a part of the substrate 1 and an n-type impurity (for example, phosphorus) is ion-implanted into another part, so that the p-type well 3 and the n-type well 4 are ion-implanted. , 5 are formed in the p-type well 3 of the capacitive element portion.
An n ⁺ type semiconductor region 6 having a high impurity concentration is formed by ion implantation of a type impurity (for example, arsenic). The dose of the impurity implanted into the n ⁺ type semiconductor region 6 is, for example, 2
It should be about × 10 ¹⁵ / cm ⁻² .

As described above, by forming the n ⁺ -type semiconductor region 6 having a high impurity concentration in the p-type well 3 of the capacitive element portion, the capacitive element (C
Since the sheet resistance of the diffusion layer (n ⁺ type semiconductor region 6) connected to n) is reduced, the series parasitic resistance of the capacitive element (Cn) can be reduced. The n ⁺ type semiconductor region 6
Is formed using a step of forming another diffusion layer on the substrate 1, for example, a step of forming a diffusion resistance element or the like, thereby suppressing an ion implantation step and an increase in a photomask.

FIG. 5 is a schematic plan view of the substrate 1 showing a part of the storage section in which the element isolation grooves 2 are formed. As shown in the drawing, the active region (Lm) of the storage section is constituted by a plurality of elongated island-shaped patterns whose periphery is surrounded by the isolation trenches 2. As will be described later, two MISFETs (Qs) for memory cell selection are formed in each active region (Lm).

FIG. 6 is a sectional view of the substrate 1 showing a part of the capacitive element portion. As shown in the drawing, the active region (Lc) of the capacitive element section is different from the active area (Lm) of the storage section, and has a large area pattern common to a large number of capacitive elements (Cn). Thereby, the sheet resistance of the diffusion layer (n ⁺ type semiconductor region 6) connected to the capacitance element (Cn) is reduced, so that the series parasitic resistance of the capacitance element (Cn) can be reduced.

Next, as shown in FIGS. 7 and 8 (schematic plan views of the substrate 1 showing a part of the storage unit), a MISFET (Qs) for selecting a memory cell is formed in the storage unit, and n-channel type MISFET (Qn) and p-channel type M
An ISFET (Qp) is formed. MIS for memory cell selection
The FET (Qs), the n-channel MISFET (Qn) and the p-channel MISFET (Qp) are formed, for example, by the following method.

First, by heat-treating the substrate 1, p
Gate oxide film 8 is formed on each surface of type well 3 and n-type well 4. Next, a conductive film (not shown) for a gate electrode is formed on the gate oxide film 8, and a silicon nitride film 10 is deposited on the conductive film by a CVD method.
The gate electrode 9A (word line WL) is formed in the storage unit by patterning the silicon nitride film 10 and the conductive film for the gate electrode by dry etching using the photoresist film as a mask, and the gate electrode 9B is formed in the logic circuit unit. , 9
Form C. The conductive film for a gate electrode is formed of, for example, a laminated film (polymetal film) of a polycrystalline silicon film deposited by a CVD method and a WN (tungsten nitride) film and a W (tungsten) film deposited by a sputtering method.

Next, an n-type impurity (for example, arsenic) is ion-implanted into the p-type well 3 to form the n ^- type semiconductor region 11 having a low impurity concentration, and the p-type impurity (boron) is formed in the n-type well 4.
Implanted into the p ^- type semiconductor region 12 having a low impurity concentration.
Is formed, a silicon nitride film 1 is formed on the substrate 1 by a CVD method.
3 is deposited.

Next, after the silicon nitride film 13 of the logic circuit portion is anisotropically etched to form sidewall spacers 13a on the side walls of the gate electrodes 9B and 9C, the p-type well 3 and the capacitor of the logic circuit portion are formed. the n-type impurity (e.g., arsenic) to form an n ⁺ -type semiconductor region 14 of the ion implantation to the high impurity concentration in the n ⁺ -type semiconductor region 6 parts, p-type impurity into the n-type well 4 of the logic circuit portion (boron) Is implanted to form a p ⁺ -type semiconductor region 15 having a high impurity concentration. The n ⁺ type semiconductor region 14 of the logic circuit portion is an n channel type MIS
The source and drain of the FET (Qn) are formed, and the p ⁺ type semiconductor region 15 is the source and drain of the p-channel MISFET (Qp).

Next, as shown in FIG.
Source and drain (n) of channel type MISFET (Qn)
⁺ Type semiconductor region 14), p-channel type MISFET (Q
p) a source and a drain (p ⁺ -type semiconductor region 15) and a silicide for reducing contact resistance with a wiring (to be described later) connected to each of the surfaces of the n ⁺ -type semiconductor region 14 of the capacitor element portion A layer 16 is formed. The silicide layer 16 is formed, for example, by depositing a Co (cobalt) film or a Ti (titanium) film on the substrate 1 by a sputtering method,
Subsequently, the substrate 1 (n ⁺ type semiconductor region 14,
After reacting the p ⁺ type semiconductor region 15) with the Co (or Ti) film to form a silicide layer 16 at the interface between them,
It is formed by removing an unreacted Co (or Ti) film by etching.

As described above, by forming the silicide layer 16 on the surface of the n ⁺ -type semiconductor region 14 in the capacitance element portion, the diffusion layers (n ⁺ -type semiconductor regions 6, 14) connected to the capacitance element (Cn) And the contact resistance with the plug (33) formed in the upper part of the n ⁺ type semiconductor region 14 in a later step, so that the series parasitic resistance of the capacitor (Cn) can be reduced. In order to prevent the refresh characteristics from deteriorating due to an increase in leak current, the silicide layer 16 is formed on the surfaces of the source and drain (n ⁻ -type semiconductor region 11) of the memory cell selecting MISFET (Qs) formed in the storage section.
Does not form.

Next, after depositing a silicon oxide film 17 on the substrate 1 by the CVD method, the MIS for selecting a memory cell in the storage section is formed.
FET (Qs) source, drain (n ^- type semiconductor region 1)
1) Silicon oxide film 17 and silicon nitride film 13 on the upper part
And dry etching the contact holes 18, 19
To form At this time, the silicon oxide film 17 and the silicon nitride film 1 on the n ⁺ type
3 and dry etching the contact holes 20 and 2
Form one.

Next, a plug 22 made of polycrystalline silicon doped with an n-type impurity (for example, phosphorus) is formed inside the contact holes 18 to 21. Plug 22
Is to deposit an n-type polycrystalline silicon film inside the contact holes 18 to 21 and on the silicon oxide film 17 by the CVD method, and then remove the n-type polycrystalline silicon film outside the contact holes 18 to 21 by the CMP method. It forms by doing.

As shown in FIG. 10, among the contact holes 18 and 19 of the storage section, the MISFE for selecting a memory cell is provided.
Source and drain of T (Qs) (n ⁻ type semiconductor region 11)
In order to secure a large contact area with the bit line BL, a contact hole 18 connecting the bit line BL and a bit line BL formed in a later step has an elongated pattern partially extending above the element isolation groove 2. It consists of.

As shown in FIG. 11, the contact holes 20 and 21 in the capacitive element portion have the same shape and the same dimensions as the contact holes 18 and 19 formed in the storage portion. Contact hole 2 formed in the capacitive element
0 and 21, the contact hole 21 connecting the lower electrode (49) of the capacitive element (Cn) for noise suppression and the diffusion layer (n ⁺ type semiconductor region 6) formed in a later step is shown in FIG. And a slit-like elongated pattern as shown in FIG. As a result, the contact area between the plug 22 buried in the contact hole 21 and the diffusion layer (the n ⁺ type semiconductor region 6) increases, and the contact resistance between the two decreases accordingly. The series parasitic resistance can be reduced.

Next, as shown in FIG. 13 and FIG. 14 (schematic plan views of the substrate 1 showing a part of the storage unit) and FIG. After depositing a silicon oxide film 23 on the silicon oxide film 17 by the CVD method, the silicon oxide film 23 on the storage portion contact hole 18 and the capacitance element portion contact hole 20 is etched to form a through hole 24. ,
25 are formed. The silicon oxide films 23 and 17 and the silicon nitride film 13 of the logic circuit portion and the capacitor portion are etched to form contact holes on the n ⁺ -type semiconductor region 14, the p ⁺ -type semiconductor region 15, and the gate electrode 9C. 26 to 31 are formed.

Next, plugs 33 are formed in the through holes 24 and 25 and the contact holes 26 to 31.
Is formed, the bit lines B are formed above the through holes 24 and 25 in the storage section and the contact holes 33 in the capacitor section.
L is formed, and the contact holes 26 to 30 of the logic circuit portion are formed.
Are formed on the first layer. The plug 33 is formed by depositing a laminated film composed of a TiN (titanium nitride) film and a W film on the inside of the through holes 24 and 25, the inside of the contact holes 26 to 31 and the upper part of the silicon oxide film 23 by a sputtering method. Hall 24, 25
Is formed by removing the above-mentioned laminated film (TiN film / W film) outside the contact holes 26 to 31 by the CMP method. In addition, the bit line BL and the wiring 34 to
38 is formed by depositing a W film on the silicon oxide film 23 by a sputtering method, and then patterning the W film by dry etching using a photoresist film as a mask.

Next, as shown in FIGS. 16 and 17 (a schematic plan view of the substrate 1 showing a part of the storage section), the bit line B
After depositing a silicon oxide film 41 over the L and the wirings 34 to 38 by the CVD method, the silicon oxide film 41 and the silicon oxide film 23 thereunder are deposited using the photoresist film as a mask.
Are etched to form a through hole 42 above the contact hole 19 in the storage section and a through hole 43 above the contact hole 21 in the capacitor section.

Next, a plug 44 made of n-type polycrystalline silicon is formed inside the through holes 42 and 43.
The plug 44 is formed by the same method as when the plug 22 is formed inside the contact holes 18 to 21.

As shown in FIG. 18, the through hole 43 in the capacitive element portion is formed in the through hole 4 formed in the storage portion.
2 and have the same dimensions. The through hole 43 of the capacitive element may be formed in a slit-like elongated pattern as shown in FIG. Thereby, the contact area between the plug 44 buried in the through hole 43 and the plug 22 buried in the contact hole 21 thereunder is increased, and the contact resistance of both is reduced accordingly, so that the capacitance element (Cn ) Can be reduced. Also, at this time, the contact resistance between the plug 44 and the plug 22 is further reduced by forming the contact hole 21 below the through hole 43 with a slit-like elongated pattern, so that the capacitance element (C
n) The series parasitic resistance can be further reduced.

Next, as shown in FIGS. 20 and 21 (a schematic plan view of the substrate 1 showing a part of the storage section) and FIG. 22 (a schematic plan view of the substrate 1 showing a part of the capacitor element section), After depositing a silicon nitride film 45 on the silicon oxide film 41 by a CVD method and subsequently depositing a silicon oxide film 46 on the silicon nitride film 45 by a CVD method, the silicon oxide film 46 is By etching the silicon nitride film 45 and the underlying silicon nitride film 45, a concave groove 47 is formed above the through hole 42 of the storage section, and a concave groove 48 is formed above the through hole 43 of the capacitive element section. In addition,
When etching the silicon oxide film 46, the underlying silicon nitride film 45 is used as an etching stopper so that the underlying silicon oxide film 41 is not etched deeply.

Next, as shown in FIG.
8, a lower electrode 49 is formed.
By forming a capacitive insulating film 50 and an upper electrode (plate electrode) 51 on the top of the device, an information storage capacitor Cs is formed in the storage unit, and an information storage capacitor Cn is formed in the capacitor unit. Capacitive element C for information storage in the capacitive element section
n is configured to have the same shape and the same dimensions as the information storage capacitive element Cs of the storage unit.

To form the information storage capacitance elements Cs and Cn, first, a polycrystalline silicon film doped with an n-type impurity (for example, phosphorus) is formed on the silicon oxide film 46 including the insides of the concave grooves 47 and 48. After depositing (not shown) by the CVD method, the polycrystalline silicon film outside the concave grooves 47 and 48 is removed by etching to form the lower electrode 49 along the inner walls of the concave grooves 47 and 48. The lower electrode 49
Is a conductive material other than polycrystalline silicon, for example, tungsten, high melting point metal such as ruthenium, ruthenium oxide,
It may be formed using a conductive metal oxide such as iridium oxide. Further, the surface area of the lower electrode 49 may be further increased by roughening the surface.

Next, a thin Ta ₂ O layer is formed on the lower electrode 49.
₅ (Tantalum oxide) film (not shown) is deposited by CVD method,
Subsequently, a TiN film is deposited on the Ta ₂ O ₅ film by using, for example, a CVD method and a sputtering method in combination, and then the TiN film and the TN film are etched by using a photoresist film as a mask.
The a ₂ O ₅ film is patterned. The capacitance insulating films 50 of the information storage capacitance elements Cs and Cn are, for example, BST and SST.
TO, BaTiO ₃ (barium titanate), PbTiO
₃ (Lead titanate), PZT (PbZr _x Ti
_{1- X O 3), PLT (} PbLa X Ti 1-X O 3), PL
It may be made of a high (ferro) dielectric material made of a metal oxide such as ZT. Further, the upper electrode 51 can be formed using a conductive material other than titanium nitride, for example, tungsten or the like. Further, the information storage capacitor C
s and Cn may be formed in a shape other than the above, for example, a fin shape.

Next, as shown in FIG. 24, second-layer wirings 56 to 59 mainly composed of an Al (aluminum) alloy film are formed on the information storage capacitors Cs and Cn. In order to form the wirings 56 to 59, first, a silicon oxide film 52 is deposited on the information storage capacitor elements Cs and Cn by the CVD method, and then the silicon oxide film 52 and the underlying layer are oxidized using a photoresist film as a mask. By etching the silicon film 46, the silicon nitride film 45, and the silicon oxide film 41, a through hole 53 is formed above the first-layer wiring 34 in the logic circuit portion, and the bit line B in the capacitor portion is formed.
A through hole 54 is formed above L.

Next, a TiN film and a W film are formed in the through holes 53 and 54 and on the silicon oxide film 52 by CVD.
After the films are deposited, these films outside the through holes 53 and 54 are removed by etching (or a CMP method) so that the plugs 5 are formed inside the through holes 53 and 54.
5 is formed. Next, a Ti film, an Al alloy film, a Ti film, and a Ti film are formed on the silicon oxide film 52 by a sputtering method.
After sequentially depositing N films, the films 56 to 59 are formed by patterning these films by dry etching using a photoresist film as a mask.

Through the steps so far, the semiconductor integrated circuit device of the present embodiment shown in FIG. 3 is substantially completed. Note that the actual semiconductor integrated circuit device has wirings 56 to 59 of the second layer.
About 1 to 2 layers of wiring are formed on the upper surface of the substrate via an interlayer insulating film, and a dense water-resistant passivation film (for example, a stack of a silicon oxide film and a silicon nitride film deposited by a plasma CVD method) is formed thereon. Film) is formed,
Their illustration is omitted.

According to the semiconductor integrated circuit device of the present embodiment configured as described above, the capacitance element for noise suppression (Cn)
, The cut-off frequency of the capacitive element (Cn) is improved. As a result, malfunction of the circuit due to high-frequency noise can be reliably prevented, so that the speed and performance of the semiconductor integrated circuit device can be promoted.

In the above configuration, the shapes and dimensions of the contact holes 20 and the through holes 25 connected to the bit lines BL of the capacitor element portion are changed to the bit lines B of the capacitor element portion.
The shape and dimensions of the contact hole 18 and the through hole 24 formed below the L are the same (FIGS. 10 to 1).
2 and FIGS. 17 to 19), for example, as shown in FIG. 25, the contact hole 20 connected to the bit line BL of the capacitor element portion may be formed in a slit-like elongated pattern. As a result, the contact area between the plug 22 buried in the contact hole 20 and the diffusion layer (n ⁺ type semiconductor region 6) increases, and the contact resistance between the two decreases, thereby reducing the capacitance of the capacitor (Cn). The series parasitic resistance can be further reduced. For example, as shown in FIG. 26, by forming each of the contact hole 20 and the through hole 25 above the contact hole 20 with a slit-like elongated pattern, the plug 33 embedded in the through hole 25 and the contact hole below the plug 33 are formed. Since the contact area with the plug 22 embedded in the capacitor 22 also increases, the series parasitic resistance of the capacitor (Cn) can be further reduced.

(Embodiment 2) FIG. 27 is a cross-sectional view of a main part of a substrate 1 showing a part of a capacitor element portion in a semiconductor integrated circuit device of this embodiment, and FIG. 28 is a plan view of the same.

In the first embodiment, the lower electrode 49 of the capacitor (Cn) includes the plugs 44, 22, the n ⁺ type semiconductor regions 6, 14, the plug 33, the bit line BL, and the plug 55
Is connected to the lead-out wiring 59 via the. On the other hand, in the present embodiment, the lower electrode 49 of the capacitive element (Cn)
Are connected to a lead wiring 59 via a plug 44, a bit line BL and a plug 55. That is, in the present embodiment, the bit line BL of the capacitive element portion is formed with a large area pattern common to a large number of capacitive elements (Cn), and the contact holes 20 and 21 and the diffusion layer (n ⁺ type) in the capacitive element section are formed. The formation of the semiconductor regions 6, 14) is omitted,
Lower electrode 49 of capacitive element (Cn) and lead-out wiring 59
Are connected without interposing the substrate 1.

As a result, the series parasitic resistance of the capacitive element (Cn) can be further reduced, and the manufacturing process can be simplified.

In this case, as shown in FIGS. 29 and 30, the through hole 43 connecting the lower electrode 49 of the capacitive element (Cn) and the bit line BL may be formed in a slit-like elongated pattern. As a result, the contact area between the plug buried in the through hole 43 and the bit line BL thereunder increases, and the contact resistance therebetween is reduced accordingly, so that the series parasitic resistance of the capacitive element (Cn) is reduced. It can be further reduced.

(Embodiment 3) FIG. 31 is a cross-sectional view of a main part of a substrate 1 showing a part of a capacitive element portion in a semiconductor integrated circuit device of this embodiment, and FIG. 32 is a plan view of the same.

In this embodiment, the formation of the bit line BL in the capacitive element portion is omitted. Accordingly, the formation of the through hole 25 and the contact hole 20 below the bit line BL is omitted. In this case, the lower electrode 49 of the capacitor (Cn) includes the plugs 44 and 22, the n ⁺ -type semiconductor regions 6, 14, the plug 33, and the bit line BL of the storage unit.
Are connected to a lead-out wiring 59 through a first-layer wiring 39 and a plug 55 formed in the same step as in FIG.

According to the present embodiment, since the structure of the capacitive element portion is simplified, the production yield can be improved.

In this case, in order to further reduce the series parasitic resistance of the capacitance element (Cn), as shown in FIGS. 33 and 34, for example, the lower electrode 49 of the capacitance element (Cn) and the diffusion layer (n ^The contact hole 21 connecting to the ⁺ type semiconductor region 6) is formed by a slit-like elongated pattern, or as shown in FIGS. 35 and 36, the through-hole 43 above the contact hole 21 is formed by a slit-like elongated pattern. Or may be configured. As shown in FIGS. 37 and 38, both the contact hole 21 and the through hole 43 may be formed in a slit-like elongated pattern.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the spirit of the invention. Needless to say, it can be changed.

In the above embodiment, the plug inside the contact hole or through hole connecting the lower electrode of the capacitive element and the diffusion layer of the substrate is made of polycrystalline silicon.
This plug may be made of metal. In this case, a silicide layer can be formed at the interface between the diffusion layer and the plug to further reduce the contact resistance.

[0063]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

According to the present invention, the series parasitic resistance of the noise suppression capacitor is reduced, and the cutoff frequency is improved. As a result, malfunction of the circuit due to high-frequency noise can be reliably prevented.
High performance can be promoted.

[Brief description of the drawings]

FIG. 1 is an overall plan view of a semiconductor substrate (chip) showing a schematic layout of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is an enlarged layout diagram showing a part of FIG. 1;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 5 is a plan view of a main part of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 6 is a fragmentary plan view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 8 is a plan view of a principal part of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 10 is a fragmentary plan view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 11 is a fragmentary plan view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 12 is an essential part plan view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

14 is a fragmentary plan view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention; FIG.

15 is a fragmentary plan view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention; FIG.

FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 17 is a fragmentary plan view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 18 is a fragmentary plan view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 19 is a fragmentary plan view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

20 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention; FIG.

FIG. 21 is a fragmentary plan view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 22 is a fragmentary plan view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 23 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 24 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 25 is a main-portion plan view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

26 is a fragmentary plan view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention; FIG.

FIG. 27 is a fragmentary cross-sectional view of a semiconductor substrate showing a semiconductor integrated circuit device according to a second embodiment of the present invention;

FIG. 28 is a plan view of a principal part of a semiconductor substrate showing a semiconductor integrated circuit device according to a second embodiment of the present invention;

FIG. 29 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a semiconductor integrated circuit device according to a second embodiment of the present invention;

FIG. 30 is a plan view of a principal part of a semiconductor substrate showing a semiconductor integrated circuit device according to a second embodiment of the present invention;

FIG. 31 is a fragmentary cross-sectional view of a semiconductor substrate showing a semiconductor integrated circuit device according to a third embodiment of the present invention;

FIG. 32 is a plan view of a principal part of a semiconductor substrate showing a semiconductor integrated circuit device according to a third embodiment of the present invention;

FIG. 33 is a fragmentary cross-sectional view of a semiconductor substrate showing a semiconductor integrated circuit device according to a third embodiment of the present invention;

FIG. 34 is a fragmentary plan view of a semiconductor substrate showing a semiconductor integrated circuit device according to Embodiment 3 of the present invention;

FIG. 35 is a fragmentary cross-sectional view of a semiconductor substrate showing a semiconductor integrated circuit device according to a third embodiment of the present invention;

FIG. 36 is a fragmentary plan view of a semiconductor substrate showing a semiconductor integrated circuit device according to a third embodiment of the present invention;

FIG. 37 is a fragmentary cross-sectional view of a semiconductor substrate showing a semiconductor integrated circuit device according to a third embodiment of the present invention;

FIG. 38 is a plan view of a principal part of a semiconductor substrate showing a semiconductor integrated circuit device according to a third embodiment of the present invention;

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate (chip) 2 element isolation groove 3 p-type well 4 n-type well 5 n-type well 6 n ⁺ type semiconductor region 7 silicon oxide film 8 gate oxide film 9A to 9C gate electrode 10 silicon nitride film 11 n ^- type semiconductor Region 12 p ⁻ type semiconductor region 13 silicon nitride film 13 a sidewall spacer 14 n ⁺ type semiconductor region 15 p ⁺ type semiconductor region 16 silicide layer 17 silicon oxide film 18 to 21 contact hole 22 plug 23 silicon oxide film 24, 25 through hole 26 to 31 Contact hole 33 Plug 34 to 39 Wiring 41 Silicon oxide film 42, 43 Through hole 44 Plug 45 Silicon nitride film 46 Silicon oxide film 47, 48 Groove 49 Lower electrode 50 Capacitive insulating film 51 Upper electrode (plate electrode) 52 Silicon oxide film 53, 5 Through hole 55 Plug 56-59 Wiring BL Bit line Cn, Cs Capacitance element Lc, Lm Active area MA Main amplifier MARY Memory array Qn N-channel MISFET Qp P-channel MISFET Qs MISFET RWC control circuit for memory cell selection SA Sense amplifier SARY Subarray SWD Subword driver WA Write amplifier WD Word driver WL Word line

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Toshihiko Takakura 6-16-16 Shinmachi, Ome-shi, Tokyo 3 Inside the Device Development Center, Hitachi, Ltd. (72) Yuji Yokoyama 6--16 Shinmachi, Ome-shi, Tokyo 3 F-term in Hitachi, Ltd. Device Development Center (reference) 5F083 AD24 AD31 GA12 JA06 JA14 JA15 JA35 JA39 JA40 JA53 LA12 LA16 LA29 MA06 MA17 MA20 NA01 PR36 PR43 PR44 PR46 PR53 PR54 PR56 ZA01 ZA06 ZA12 ZA14

Claims (12)

[Claims] A first region on a main surface of a semiconductor substrate, a memory cell selecting MISFET and the memory cell selecting MISFET;
A memory cell including a first bit line connected to one of a source and a drain of the SFET and a first capacitor connected to the other of the source and the drain is formed, and a second region on a main surface of the semiconductor substrate is formed. And a second bit line,
A second capacitance element having the same structure as the first capacitance element is formed; and the first bit line is connected to the memory cell selecting MISFE.
The memory cell selecting MISFET is connected to one of a source and a drain via a first contact hole formed in a first insulating film above T, and one electrode of the first capacitor element is connected to the first insulating film. Connected to the other of the source and the drain of the memory cell selecting MISFET via a second contact hole formed in the film and a first through hole formed in the second insulating film above the first insulating film. The second bit line includes a third bit line formed on the first insulating film.
One electrode of the second capacitor is connected to a first diffusion layer of the semiconductor substrate through a contact hole, and one electrode of the second capacitor is formed in a fourth contact hole formed in the first insulating film and in the second insulating film. A semiconductor integrated circuit device connected to the first diffusion layer of the semiconductor substrate via the second through hole formed, wherein the area of the active region in which the first diffusion layer is formed is determined by the memory cell selection. A semiconductor integrated circuit device having a larger area than an active region in which the source and drain of the MISFET are formed. 2. The semiconductor integrated circuit device according to claim 1, wherein a sheet resistance of said first diffusion layer is larger than a sheet resistance of said source and said drain of said memory cell selecting MISFET. Circuit device. 3. The semiconductor integrated circuit device according to claim 1, wherein a plug made of polycrystalline silicon is buried inside said first to fourth contact holes and inside said first and second through holes. A semiconductor integrated circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein an opening area of said third contact hole is larger than an opening area of said first contact hole. 5. The semiconductor integrated circuit device according to claim 1, wherein an opening area of said fourth contact hole is larger than an opening area of said second contact hole. 6. The semiconductor integrated circuit device according to claim 1, wherein an opening area of said second through hole is larger than an opening area of said first through hole. 7. A memory cell selecting MISFET and a memory cell selecting MISFET are provided in a first region on a main surface of a semiconductor substrate.
A memory cell including a first bit line connected to one of a source and a drain of the SFET and a first capacitor connected to the other of the source and the drain is formed, and a second region on a main surface of the semiconductor substrate is formed. A second bit line having an area larger than that of the first bit line and a second capacitance element having the same structure as the first capacitance element are formed. MISFE for
The memory cell selecting MISFET is connected to one of a source and a drain via a first contact hole formed in a first insulating film above T, and one electrode of the first capacitor element is connected to the first insulating film. Connected to the other of the source and the drain of the memory cell selecting MISFET via a second contact hole formed in the film and a first through hole formed in the second insulating film above the first insulating film. A semiconductor integrated circuit device, wherein one electrode of the second capacitor is connected to the second bit line via a second through hole formed in the second insulating film. 8. The semiconductor integrated circuit device according to claim 7, wherein an opening area of said second through hole is larger than an opening area of said first through hole. 9. A memory cell selecting MISFET and a memory cell selecting MIFET in a first region on a main surface of a semiconductor substrate.
A memory cell including a first bit line connected to one of a source and a drain of the SFET and a first capacitor connected to the other of the source and the drain is formed, and a second region on a main surface of the semiconductor substrate is formed. A second capacitance element having the same structure as the first capacitance element is formed, and the first bit line is connected to the memory cell selecting MISFE.
The memory cell selecting MISFET is connected to one of a source and a drain via a first contact hole formed in a first insulating film above T, and one electrode of the first capacitor element is connected to the first insulating film. Connected to the other of the source and the drain of the memory cell selecting MISFET via a second contact hole formed in the film and a first through hole formed in the second insulating film above the first insulating film. One electrode of the second capacitive element is connected to a first contact hole of the semiconductor substrate via a fourth contact hole formed in the first insulating film and a second through hole formed in the second insulating film. In a semiconductor integrated circuit device connected to a diffusion layer, an area of an active region in which the first diffusion layer is formed is an active region in which the source and the drain of the memory cell selection MISFET are formed. The semiconductor integrated circuit device being larger than the area of the. 10. The semiconductor integrated circuit device according to claim 9, wherein a sheet resistance of said first diffusion layer is larger than a sheet resistance of said source and drain of said memory cell selecting MISFET. Circuit device. 11. The semiconductor integrated circuit device according to claim 9, wherein an opening area of said fourth contact hole is larger than an opening area of said second contact hole. 12. The semiconductor integrated circuit device according to claim 9, wherein said second through-hole has an opening area of said first through-hole.
A semiconductor integrated circuit device having a larger opening area than a through hole.