JP2006221381A - Processor system and image forming device provided with this processor system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a processor system capable of reducing power consumption. <P>SOLUTION: The processor system 100 comprises a main processor 20, a sub-processor 30, and a system controller 40 performing device control according to commands from each processor. The system controller 40 includes a main controller 40a performing device control according to a command from the main processor 20, and a sub-controller 40b performing the device control according to a command from the sub-processor 30. Further, this system comprises a first power supply system α connected to the main processor 20 and the main controller 40a, a second power supply system β connected to the sub-processor 30 and the sub-controller 40b, and a power supply control circuit 90 capable of independently switching input of power to the first power supply system α and to the second power supply system β, respectively. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a processor system that performs device control and an image forming apparatus including the processor system.

  A high-performance processor has high processing performance, but energy saving performance is generally not high. Even a processor that implements a standby mode that suppresses power consumption by stopping the operation of most of the internal circuits has a large leakage current, and the power consumption cannot be reduced so much. Therefore, when a high-performance processor system is applied to an apparatus, the power consumption of the apparatus does not decrease unless power supply to the processor is completely stopped.

  However, in a processor system applied to an apparatus connected to an external device through a network or the like, an external interface controller unit that communicates with the external device must always be operated. Therefore, a processor that controls the controller unit, In addition, power supply to a DRAM or the like used as a work area or a data reception area cannot be stopped.

As such a processor system, for example, Patent Document 1 and Patent Document 2 shown below are disclosed.
Japanese Patent Laid-Open No. 9-109519 (Publication date: April 28, 1997) JP 2002-67449 (release date: March 5, 2002)

  In Patent Document 1 described above, in a device having a main CPU and a sub CPU, when the device enters an energy saving mode, the main CPU stops operating, and the sub CPU receives data from an external host computer. A technique for storing the data in the RAM is disclosed.

  However, in the configuration of Patent Document 1, the controller needs to be operated in order for the sub CPU to communicate with the external host computer in the energy saving mode. In the normal mode, this controller transmits and receives commands to and from the main CPU and controls the entire engine for image formation. Therefore, the controller is a circuit that requires a capability corresponding to the main CPU. Yes, power consumption is relatively high. Therefore, even in the energy saving mode, the configuration of Patent Document 1 that needs to supply power to such a controller has a limit in reducing power consumption.

  In the configuration of Patent Document 2, the power supply system A that supplies power to the main CPU, ROM, RAM, and the like in the normal mode, and the sub CPU and the external device I / F control unit in the normal mode and the energy saving mode A processor system having a power supply system B that supplies power to the power supply system is disclosed.

  In the processor system having this configuration, the main CPU, ROM, RAM, sub CPU, and external device I / F control unit described above are configured to transmit and receive data within the same printer controller. The printer controller controls the ROM, RAM, display unit and the like in accordance with commands from the main CPU in the normal mode. That is, this printer controller is a circuit that controls a device in accordance with a command from the main CPU in the normal mode, and requires a capability corresponding to the main CPU and a relatively high power consumption.

  However, in this configuration, since the printer controller is also provided with a sub CPU and a device to be controlled by the sub CPU, it is necessary to supply power to the printer controller even in the energy saving mode. Therefore, a printer controller that requires a capability corresponding to the main CPU must be operated even in the energy saving mode, and there is a limit in reducing power consumption.

  An object of this invention is to provide the processor system which can aim at reduction of power consumption more.

  In order to achieve the above object, a processor system according to the present invention includes a main processor, a sub processor, a main control circuit that performs device control in response to a command from the main processor, and a command from the sub processor. A sub-control circuit that performs device control, a main processor, a main control circuit, a first power supply system that supplies input power to the main processor and the main control circuit, a sub-processor, and a sub-control circuit; Power supply control capable of independently switching between a second power supply system for supplying input power to the sub-processor and sub-control circuit, power input to the first power supply system, and power input to the second power supply system And a circuit.

  According to the present invention, a main control circuit that performs device control according to a command from the main processor and a sub control circuit that performs device control according to a command from the sub processor are provided.

  With such a configuration, when power is saved by stopping the power supply to the main processor and operating the sub processor, the sub processor can connect the sub control circuit if the sub control circuit is operable. Since device control can be realized through this, the main control circuit for processing commands from the main processor does not need to be operating.

  Therefore, in the present invention, a first power supply system connected to the main processor and the main control circuit and a second power supply system connected to the subprocessor and the sub control circuit are further configured, and power to the first power supply system is configured. And a power supply control circuit capable of switching the power input to the second power supply system independently of each other.

  As a result, when power is saved by stopping the power supply to the main processor while operating the sub processor, the sub processor and the sub control circuit are operated if the power control circuit supplies power only to the second power supply system. The power supply to the main processor and the main control circuit can be stopped.

  Therefore, when the power supply to the main processor is stopped, the power supply to the main control circuit which is not necessary for the operation of the sub processor can be stopped, and the power can be further saved.

  On the other hand, according to the configuration of Patent Document 2, the main CPU and the sub CPU are configured as a single controller circuit (printer controller). In this controller circuit, a circuit portion necessary for the operation of the main CPU and a circuit portion necessary for the operation of the sub CPU are not distinguished. Therefore, even when the sub CPU is operated and the power supply to the main CPU is stopped, the power must be supplied to the entire controller circuit, and the power supply is stopped to the circuit portions unnecessary for the operation of the sub processor. I can't do that. Therefore, power saving cannot be achieved as much as the configuration of the present invention.

  In the processor system of the present invention, in addition to the above configuration, the power supply control circuit includes a normal mode for inputting power to the first power supply system and the second power supply system, and does not input power to the first power supply system. It is preferable to switch between a power saving mode in which power is input to the second power supply system.

  According to the above configuration, the main processor and the main control circuit and the sub processor and the sub control circuit are operated in the normal mode, and the power supply to the main processor and the main control circuit is stopped in the power saving mode. it can.

  Thus, even if energy saving is achieved by stopping the main processor and the main control circuit, since the sub processor and the sub control circuit are operated, the minimum necessary data processing can be performed.

  In addition to the above configuration, the processor system of the present invention includes a memory that is a data development area, and the memory includes a first memory area that is used only in the normal mode, the normal mode and Preferably, a second memory area used in the power saving mode is included, the first memory area is connected to a first power supply system, and the second memory area is connected to a second power supply system.

  According to the above configuration, the first memory area is connected to the first power supply system, and the second memory area is connected to the second power supply system. Therefore, in the normal mode, power is supplied to the first and second memory areas, but in the power saving mode, power is supplied only to the second memory area. That is, in the normal mode, the first and second memory areas can be used as development areas for data (including programs), and in the power saving mode, only the second memory area can be used as a data development area.

  As a result, in the power saving mode, the usable memory area is reduced, but the memory area to which power is supplied is also reduced, so that an energy saving effect can be achieved.

  In the processor system according to the present invention, in addition to the above configuration, the main processor or sub processor may store data stored in the first memory area in advance before shifting from the normal mode to the power saving mode. It is preferable to perform control to save the data in the second memory area.

  According to the above configuration, the data (including the program) stored in the first memory area is saved in the second memory area before shifting to the energy saving mode. Therefore, even if the power supply to the first memory area is stopped, the data stored in the first memory area is backed up to the second memory area, and the sub processor transfers to the second memory area. By accessing, it becomes possible to access the same data as the data stored in the first memory area.

  According to the above configuration, in the power saving mode, the power supply to the first memory area is stopped and the power is supplied only to the second memory area. DRAM is preferable as the memory area, and SRAM is preferable as the second memory area. With this configuration, a DRAM having a higher storage capacity than the SRAM can be used as a data development area in the normal mode, and power can be supplied to the DRAM having a higher power consumption than the SRAM in the power saving mode. The SRAM can be used as a data development area while blocking the above. Therefore, it is possible to build a system that emphasizes high performance in the normal mode and emphasizes low power consumption in the energy saving mode.

  Further, in the processor system of the present invention, in addition to the above configuration, an address storage that stores an address before saving and an address after saving in association with data saved from the first memory area to the second memory area. It is preferable that the sub processor includes a circuit and accesses the address where the data is stored with reference to the address storage circuit in the power saving mode.

  As a result, the sub processor can refer to the current address of the data saved in the second memory area from the first memory area even in the power saving mode. Can be done.

  In addition to the above configuration, the processor system of the present invention preferably includes a standby mode for setting the main processor to a standby state.

  The processor system configured as described above may include a standby mode for setting the main processor to a standby state. In this standby mode, since the main processor is in a standby state, there is no energy saving effect as when the power supply to the main processor is stopped, but it is possible to achieve an energy saving effect than when the main processor is in full operation. .

  In addition, when energy saving is attempted by stopping the power supply to the main processor (the above power saving mode), it takes time to restart the main processor, but energy saving can be achieved by setting the main processor to the standby state. In this case, it does not take time to restart the main processor.

  Accordingly, the standby mode is inferior to the power saving mode in terms of energy saving, but is superior to the power saving mode in terms of restart speed.

  For this reason, in the processor system, the power saving mode and the standby mode coexist, and each mode is selectively used according to the use state, whereby an efficient energy saving effect can be realized.

  In addition to the above configuration, the processor system of the present invention includes a memory that is a data development area. The memory includes a first DRAM and a second DRAM, and the main processor or sub-processor includes Preferably, the first DRAM is set to a self-refresh state before the standby state is set, and control for canceling the self-refresh state is performed after the standby state is released.

  According to the above configuration, the first DRAM and the second DRAM, which are development areas for data (including programs), are included. Of these memories, the first DRAM performs a self-refresh operation while the main processor is in a standby state.

  Therefore, not only the energy saving effect due to the standby state of the main processor but also the energy saving effect due to the self-refresh operation of the first DRAM can further save power. According to the above configuration, the sub processor can use the second DRAM as a work area while the main processor is in the standby state.

  In the processor system of the present invention, in addition to the above configuration, it is preferable that the main processor or the sub processor performs control to save data in the first DRAM to the second DRAM before setting the standby state.

  According to the above configuration, data (including the program) in the first DRAM is saved in the second DRAM before the standby state is set. Therefore, even while the first DRAM is in the self-refresh state, the sub processor can access the same data as the data stored in the first DRAM by accessing the second DRAM.

  In the processor system of the present invention, the first DRAM is preferably a DRAM having a higher access speed than the second DRAM.

  The first DRAM has higher power consumption than the second DRAM because the access speed is higher than that of the second DRAM. Therefore, when energy saving is achieved by setting only one of the first DRAM and the second DRAM to the self-refresh state, energy saving can be further achieved by setting the first DRAM with higher power consumption to the self-refresh state as described above. The effect becomes high.

  In addition to the above configuration, the processor system according to the present invention further includes an address storage circuit that stores an address before saving and an address after saving in association with data saved from the first DRAM to the second DRAM. Preferably, the sub-processor accesses the address where the data is stored with reference to the address storage circuit in the self-refresh state of the first DRAM.

  As a result, the sub-processor can access the saved data for the data saved from the first DRAM to the second DRAM even in the power saving mode, so that the current address of the data can be referred to. It becomes.

  In the processor system of the present invention, in addition to the above configuration, when the data saved from the first DRAM to the second DRAM is updated, the data synchronization stores the updated data and the address of the data in the first DRAM. Preferably, the main processor or sub-processor including the storage circuit for memory performs control to synchronize data in the first DRAM with the update data when the self-refresh state of the first DRAM is released.

  According to the above configuration, when the data saved from the first DRAM to the second DRAM is updated, the data synchronization storage circuit is provided for storing the update data and the address of the data in the first DRAM.

  Therefore, even when the data saved from the first DRAM to the second DRAM is updated, the main processor or sub-processor releases the contents stored in the synchronization circuit after releasing the self-refresh state of the first DRAM. By referring to the data, it becomes possible to synchronize the data held in the first DRAM with the data saved from the first DRAM to the second DRAM.

  The processor system of the present invention described above is preferably provided in an image forming apparatus. The reason for this will be described below.

  Image forming apparatuses such as printers, copiers, facsimile machines, and MFPs (Multi Function Printers) have a high load during image forming processing, but have a low load during standby when image forming processing is not performed. . Accordingly, in such a processor system that controls the image forming apparatus, if the same power is always supplied, it is necessary to supply the same amount of power as in the case of a high load even in the case of a low load. Absent.

  In this regard, if the processor system of the present invention described above is mounted on an image forming apparatus, it has a power saving mode in which power supply to the main processor can be stopped and a standby mode in which the main processor is in a standby state. Energy efficiency can be improved by switching modes between time and high load.

  As described above, the processor system of the present invention has a main processor, a sub processor, a main control circuit that performs device control in accordance with a command from the main processor, and device control in accordance with a command from the sub processor. A sub-control circuit to be connected, a main processor, a main control circuit, a first power supply system for supplying input power to the main processor and the main control circuit, and a sub-processor, sub-control circuit connected to the input power A second power supply system for supplying power to the sub processor and the sub control circuit; a power control circuit capable of independently switching between power input to the first power supply system and power input to the second power supply system; It is the composition which includes.

  Therefore, when the power supply to the main processor is stopped, it is possible to stop the power supply to the main control circuit that is not necessary for the operation of the sub processor, and it is possible to achieve further power saving. .

[Embodiment 1]
Hereinafter, a processor system according to an embodiment of the present invention will be described with reference to the drawings. Note that the processor system according to the present embodiment is applied to various devices that are controlled by a computer. Hereinafter, a device to which the processor system of the present embodiment is applied is referred to as a “target device”.

  FIG. 1 is a block diagram showing the configuration of the processor system of this embodiment. As shown in the figure, the processor system 100 includes a main processor 20, a sub processor 30, a system controller 40, and a power supply control circuit 90.

  The main processor 20 and the sub-processor 30 collectively control various configurations in the processor system 100 and various devices in the target device via the system controller 40. This control is performed based on the program code stored in the ROM (Read Only Memory) or HD (Hard Disc) (not shown) or the program code expanded in the volatile memory. This is realized by outputting a command signal and the peripheral circuit of the target device or the system controller 40 executing this command.

  The system controller 40 is a circuit that is connected to the main processor 20 and the sub processor 30, processes commands from the main processor 20 and the sub processor 30, and controls various devices in the processor system 100 in accordance with the commands.

  In the system controller 40 of the present embodiment, a main controller (main control circuit) 40a, which is a circuit portion that processes commands from the main processor 20 and controls various devices according to the commands, and a sub processor And a sub-controller (sub-control circuit) 40b, which is a circuit portion that processes commands from 30 and controls various devices according to the commands.

  In the processor system 100 of the present embodiment, as shown in FIG. 1, the first power supply system α connected to the main processor 20 and the main controller 40a, and the sub processor 30 and the sub controller 40b are connected. A second power supply system β is included. Here, the first power supply system α and the second power supply system β are wirings for inputting power from the commercial power supply via the power supply control circuit 90, respectively.

  The power supply control circuit 90 is a circuit capable of independently switching between power input to the first power supply system and power input to the second power supply system. The power supply control circuit 90 performs the switching control described above based on a command from the sub processor 30.

  In such a configuration, when the power control circuit 90 inputs power from the commercial power source to the first power system α, power is supplied to the main processor 20 and the main controller 40a. Further, when the power control circuit 90 inputs power from the commercial power source to the second power system β, power is supplied to the sub processor 30 and the sub controller 40b.

  Accordingly, in the processor system 100 described above, the power supply control circuit 90 may supply power to the first power supply system α and the second power supply system β during the normal operation of the target device.

  As a result, during normal operation, the main and sub-processors 20 and 30 can be operated, and the main controller 40a and the sub-controller 40b can be operated (that is, the system controller 40 can be operated). Therefore, the main and sub-processors 20 and 30 can perform control via the system controller 40.

  On the other hand, in the processor system 100 described above, when the target device performs energy saving, the power supply control circuit 90 stops power supply to the first power supply system α and supplies power only to the second power supply system β. Control may be performed as follows. Thereby, at the time of energy saving, the main processor 20 can be stopped by operating the sub processor 30 and the sub controller 40b and stopping the power supply to the main processor 20, thereby achieving energy saving.

  Here, in this embodiment, since the main processor 20 and the main controller 40a are connected to the first power supply system α, if the power supply to the first power supply system α is stopped, not only the main processor 20, The power supply to the main controller 40a is also stopped.

  Here, the reason for stopping the power supply not only to the main processor 20 but also to the main controller 40a will be described.

  The main controller 40a is a circuit part that processes commands from the main processor 20 in the system controller 40 and controls various devices in accordance with the commands, and the sub controller 40b is a sub processor in the system controller 40. 30 is a circuit portion that processes commands from 30 and controls various devices in accordance with the commands. That is, when the power supply to the main processor 20 is stopped and only the sub processor 30 is operated, it is not necessary that the main controller 40a is operating as long as only the sub controller 40b is operating.

  Therefore, in this embodiment, when the sub processor 30 is operated without operating the main processor 20, the power supply to the first power supply system α is stopped and the power is supplied to the second power supply system β. The processor 30 and the sub controller 40b necessary for the operation of the sub processor are operated, and the power supply is stopped for the main processor 20 and the main controller 40a unnecessary for the operation of the sub processor 30.

  Therefore, when the power supply to the main processor 20 is stopped, the power supply to the main controller 40a unnecessary for the operation of the sub processor 30 can also be stopped, and an energy saving effect can be obtained.

[Embodiment 2]
Hereinafter, an application example of the processor system described in the first embodiment will be described as a second embodiment. In this embodiment, for convenience of description, FIG. 1 used in the description of the first embodiment is used as it is, and the members described in the first embodiment are denoted by the same reference numerals and the description thereof is omitted. To do.

  As shown in FIG. 1, the processor system 100 in this embodiment includes a main processor 20, a sub processor 30, a system controller 40, a power supply control circuit 90, a high-speed DRAM (Dynamic Random Access Memory) 50, a low-speed DRAM 60, an SRAM ( Static Random Access Memory) 70 and an external interface controller 80.

  A high-speed DRAM (first memory area / first DRAM) 50 is a memory that is connected to the system controller 40 and functions as a work area for the main processor 20 and the sub-processor 30. A low-speed DRAM (first memory area / second DRAM) 60 is a memory that is connected to the system controller 40 and functions as a work area for the main processor 20 and the sub-processor 30.

  That is, the main processor 20 and the sub-processor 30 develop data (including a program) on the high-speed DRAM 50 and the low-speed DRAM 60 via the system controller 40, and control various devices in the target apparatus based on the data and the program. Realized.

  The high speed DRAM 50 is a memory having a higher access speed than the low speed DRAM 60. That is, the high speed DRAM 50 has higher power consumption than the low speed DRAM 60.

  The SRAM (second memory area) 70 is a memory connected to the system controller 40. The SRAM 70 functions as a work area for the sub processor 30. That is, the sub processor 30 develops data and programs on the SRAM 70 via the system controller 40, and realizes control of various devices in the target apparatus based on the data and programs.

  The external interface controller 80 is a control circuit connected to the system controller 40. The external interface controller 80 is also connected to a communication interface (not shown) in the target device.

  The external interface controller 80 is a controller circuit for the communication interface of the target device. The main processor 20 and the sub processor 30 perform communication control with the external device via the external interface controller 80.

  The high speed DRAM 50 and the low speed DRAM 60 are connected to the first power supply system α, and the SRAM 70 and the external interface controller 80 are connected to the second power supply system β.

  Next, the operation in the processor system 100 of the present embodiment described above will be described with reference to FIG. FIG. 2 is an explanatory diagram showing state transition of the processor system 100 of the present embodiment. Note that the full operation mode shown in the figure means a mode in which the main processor 20 and the sub processor 30 are operated, and the power saving mode means that the power supply to the main processor 20 is stopped and the sub processor 30 is operated. Meaning the mode to make.

  When the processor system 100 is in the power-off state shown in FIG. 2, the power supply control circuit 90 does not supply power to either the first power supply system α or the second power supply system β, and the main processor 20 and No power is supplied to any of the sub-processors 30.

  When the operator of the target device turns on the power, the processor system 100 shifts from the power-off state to the full operation mode as shown in FIG. 2 (S1). In this full operation mode, the power supply control circuit 90 inputs power to both the first power supply system α and the second power supply system β.

  Therefore, in this full operation mode, power is supplied to the system controller 40, the high speed DRAM 50, the low speed DRAM 60, the SRAM 70, and the external interface controller 80 including the main processor 20, the sub processor 30, the main controller 40a and the sub controller 40b shown in FIG. Will be supplied.

  Thereby, in the full operation mode, the main processor 20 and the sub processor 30 can be operated, and the main processor 20 and the sub processor 30 can use the high speed DRAM 50, the low speed DRAM 60, and the SRAM 70 as work areas.

  Next, in the full operation mode, when the work amount of the main processor 20 and the sub processor 30 decreases, the processor system 100 shifts from the full operation mode shown in FIG. 2 to the power saving mode (S2). Here, the transition from the full operation mode to the power saving mode (S2) will be described based on the flowchart of FIG.

  In the full operation mode, the sub processor 30 counts the number of commands per unit time output from the main processor 20 and the sub processor 30 (the work amount of the main processor 20 and the sub processor 30), and the number of commands per unit time. Is less than or equal to a predetermined amount a (S11). Specifically, the system controller 40 counts commands generated from the main processor 20 and the sub processor 30, and sets the count number in a counter register (not shown) in the sub controller 40b. Then, the sub processor 30 detects the number of commands per unit time output from the main processor 20 and the sub processor 30 by detecting the count number in the counter register at regular time intervals.

  Here, when the sub processor 30 determines that the number of commands per unit time output from the main processor 20 and the sub processor 30 has become equal to or less than the predetermined amount a (YES in S11), the sub processor 30 stores in the memory via the system controller 40. A save command, which is a save command for the information, is transmitted to the main processor 20 (S12).

  The main processor 20 that has received the save command performs control to save the data (including the program) stored in the SRAM 70 to a nonvolatile memory (not shown) via the system controller 40 (S13). Further, after S13, the main processor 20 performs control to save necessary data in the power saving mode to the SRAM 70 among the data (including programs) stored in the high-speed DRAM 50 and the low-speed DRAM 60 via the system controller 40. (S14). Note that the processing of S13 and S14 may be performed under the control of the sub-processor 30.

  Further, the main processor 20 that has finished the process of S14 transmits a mode transition command to the sub-processor 30 via the system controller 40 (S15).

  Then, the sub processor 30 that has received this mode transition command performs control to stop the power supply to the first power system via the power control circuit 90 (S16). As a result, the power supply control circuit 90 stops the power supply to the first power supply system α, and the power supply to the main processor 20, the main controller 40a, the high speed DRAM 50, and the low speed DRAM 60 shown in FIG. This completes the transition to the power saving mode.

  In this power saving mode, the sub processor 30, the sub controller 40b, the SRAM 70, and the external interface controller 80 can operate, and the sub processor 30 performs various device controls using the SRAM 70 as a work area.

  Here, as shown in FIG. 1, an address storage circuit 200 is provided in the sub-controller 40b. In S14 of FIG. 3, the main processor 20 relates to the data saved from the high speed DRAM 50 / low speed DRAM 60 to the SRAM 70 before saving. It is preferable to store the address and the address after saving in the address storage circuit 200 in association with each other.

  Thereby, the sub processor 30 can access the current address of the data saved in the SRAM 70 from the high speed DRAM 50 / low speed DRAM 60 even in the power saving mode, and thus accesses the saved data. It becomes possible.

  Next, in the processor system 100 in the power saving mode, when the work amount of the sub processor 30 increases, as shown in FIG. 2, the power saving mode returns to the full operation mode (S3). Here, the return from the saving operation mode to the full operation mode will be described based on the flowchart of FIG.

  In the power saving mode, the sub processor 30 counts the number of commands per unit time output from the sub processor 30 (the work amount of the sub processor 30), and whether or not the number of commands per unit time is equal to or greater than a predetermined amount a. Is determined (S21). The specific procedure for counting is the same as the procedure in S11.

  Here, when the sub processor 30 determines that the number of commands per unit time output from the sub processor 30 has exceeded a predetermined amount a (YES in S21), the first power system α is connected via the power control circuit 90. Control for starting the power supply to is performed (S22). As a result, the power supply control circuit 90 starts supplying power to the first power supply system α, and power is supplied to the main processor 20, the main controller 40a, the high-speed DRAM 50, and the low-speed DRAM 60 shown in FIG.

  When the power supply to the first power supply system α is started, a reset circuit (not shown) detects the start of the power supply and resets the main processor 20 (S23). This reset circuit may be provided in the system controller 40 or may be provided outside the system controller 40.

  After S23, the main processor 20 performs control to write (return) the data (including the program) saved in the SRAM 70 in S13 to the high-speed DRAM 50 and the low-speed DRAM 60 via the system controller 40 (S24).

  After S24, the main processor 20 performs control for writing (returning) the data (including the program) saved in the nonvolatile memory in S12 to the SRAM 70 via the system controller 40 (S25). The control in S24 and S25 described above may be executed not by the main processor 20 but by the sub processor 30.

  When the processing of S25 is completed, the return processing from the power saving mode to the full operation mode is completed.

  When the operator turns off the power of the target device in the full operation mode and the power saving mode, the processor system 100 shifts to a power off state (S4 and S5 in FIG. 2).

  According to the above configuration, the power supply control circuit 90 has the full operation mode in which power from the power supply is input to the first power supply system α and the second power supply system β, and the second power supply is not input to the first power supply system. The power supply mode is switched to a power saving mode in which power from the power supply is input.

  Therefore, the main processor 20 and the main controller 40a and the sub processor 30 and the sub controller 40b can be operated in the full operation mode, and the power supply to the main processor 20 and the main controller 40a can be stopped in the power saving mode. .

  Thereby, even in the power saving mode in which the main processor 20 and the main controller 40a are stopped, the sub-processor 30 and the sub-controller 40b are operated, so that the minimum necessary data processing can be performed.

  Further, the processor system 100 described above includes a high-speed DRAM 50, a low-speed DRAM 60, and an SRAM 70 as memories that are development areas for data (including programs). Among these, the high-speed DRAM 50 and the low-speed DRAM 60 are connected to the first power supply system α and used only in the full operation mode, and the SRAM 70 is connected to the second power supply system β, and operates in the full operation mode and Used in power saving mode.

  That is, in the full operation mode, power is supplied to the high-speed DRAM 50, the low-speed DRAM 60, and the SRAM 70, and the high-speed DRAM 50, the low-speed DRAM 60, and the SRAM 70 can be used as a development area for data and the like. Only the SRAM 70 is used as a data development area.

  As a result, in the power saving mode, the usable memory area is reduced, but the memory area to which power is supplied is also reduced, so that an energy saving effect can be achieved.

  Further, the main processor 20 performs control for saving data necessary for the power saving mode among the data stored in the high speed DRAM 50 and the low speed DRAM 60 in advance to the SRAM 70 before shifting from the full operation mode to the power saving mode. Is going.

  Therefore, even if the power supply to the high-speed DRAM 50 and the low-speed DRAM 60 is stopped, the data necessary for the power-saving mode among the data stored in the high-speed DRAM 50 and the low-speed DRAM 60 is backed up in the SRAM 70. . Thereby, in the power saving mode, the sub processor 30 accesses the SRAM 70 to access the same data as the data required in the power saving mode among the data stored in the high speed DRAM 50 and the low speed DRAM 60. Is possible.

  Further, according to the above configuration, in the full operation mode, not only the SRAM 70 but also the high-speed DRAM 50 and the low-speed DRAM 60 having a higher storage capacity than the SRAM 70 are used as the data expansion areas, and in the energy saving mode, the power consumption is higher than that of the SRAM 70 The SRAM 70 is used as a data development area while cutting off the power supply to the high-speed DRAM 50 and the low-speed DRAM 60. Therefore, a system in which high performance is emphasized in the normal mode and low power consumption is emphasized in the energy saving mode is constructed.

  In the processor system 100 described above, the external interface controller 80 is connected to the second power supply system β. Therefore, even in the power saving mode, power is supplied to the external interface controller 80, and the sub-processor 30 can control data communication with the outside via the external interface controller 80.

  Therefore, even when the processor system 100 is in the power saving mode in the target device, the target device can receive data with the external device. Further, the sub processor 30 can store the data by performing control to write the data received from the outside into the SRAM 70.

[Embodiment 3]
The processor system 100 according to the second embodiment includes a power saving mode in which power supply to the main processor 20 is stopped. Instead of this power saving mode, the processor system 100 includes a standby mode in which the main processor 20 is in a standby state. You may go out. Hereinafter, the processor system 100 including the standby mode will be described as a third embodiment. Note that the standby state in the present embodiment means that the power consumption of the processor is suppressed by operating only some of the internal circuits included in the processor and stopping the operation of other circuits. To do.

  Further, in this embodiment, for convenience of explanation, the drawings used in the explanation of the first embodiment and the second embodiment are used as they are, and the same reference is made to the members explained in the first embodiment and the second embodiment. Reference numerals are assigned and explanations thereof are omitted.

  FIG. 5 is an explanatory diagram showing state transitions in the processor system 100 of the present embodiment.

  Since the power-off state, the full operation mode, and the transition from the power-off state to the full operation mode (S1) shown in the figure are the same as those in the second embodiment, description thereof is omitted here.

  In the full operation mode shown in FIG. 5, when the work amount of the main processor 20 and the sub processor 30 decreases, the processor system 100 shifts from the full operation mode to the standby mode (S6). Here, the transition from the full operation mode to the standby mode will be described based on the flowchart of FIG.

  In the full operation mode, the sub processor 30 counts the number of commands per unit time output from the main processor 20 and the sub processor 30 (the work amount of the main processor 20 and the sub processor 30), and the number of commands per unit time. Is less than or equal to a predetermined amount b (S31). Note that the counting method is the same as that in S11 in the second embodiment, and thus the description thereof is omitted here.

  Here, when sub processor 30 determines that the number of commands per unit time output from main processor 20 and sub processor 30 has become equal to or less than predetermined amount b (YES in S31), it is stored in memory via system controller 40. A save command, which is a save command for the information, is transmitted to the main processor 20 (S32).

  Upon receiving this save command, the main processor 20 performs control for saving necessary data in the standby mode among the data (including programs) stored in the high-speed DRAM 50 to the low-speed DRAM 60 via the system controller 40. Perform (S33).

  Further, after S33, the main processor 20 controls the high-speed DRAM 50 to execute a self-refresh operation via the system controller 40 (S34). Note that S33 and S34 described above may be executed under the control of the sub-processor 30.

  After S34, the main processor 20 shifts to the standby state by setting the standby state in the standby setting register in the main processor 20 (S35). Thereby, in the processor system 100, the transition to the standby mode is completed.

  That is, this standby mode is a state in which power is supplied to each member shown in FIG. 1, but the main processor 20 is set to a standby state. Therefore, in this standby mode, energy saving cannot be achieved as much as in the power saving mode described in the second embodiment, but energy saving can be achieved compared to the full operation mode because the main processor 20 is in the standby state. it can.

  In this standby mode, since the main processor 20 is in a standby state, the main processor 20 hardly operates, and the data (including programs) developed by the sub processor 30 on the low-speed DRAM 60 or the SRAM 70 via the system controller 40. To perform various device controls.

  Here, as shown in FIG. 1, an address storage circuit 200 is provided in the sub-controller 40b. With respect to the data saved by the main processor 20 from the high-speed DRAM 50 to the low-speed DRAM 60 in S33 of FIG. It is preferable to store the address after saving in the address storage circuit 200 in association with each other.

  As a result, the sub-processor 30 can access the current address of the data saved from the high-speed DRAM 50 to the low-speed DRAM 60 even in the standby mode, so that the saved data can be accessed. It becomes.

  Further, in the processor system 100 in the standby mode, when the work amount of the sub processor 30 increases, as shown in FIG. 5, the standby mode returns to the full operation mode (S7). Here, the return from the standby mode to the full operation mode will be described with reference to the flowchart of FIG.

  In the standby mode, the sub processor 30 counts the number of commands per unit time output from the sub processor 30 (the work amount of the sub processor 30), and determines whether the number of commands per unit time is equal to or greater than a predetermined amount b. Judgment is made (S41). The specific procedure for counting is the same as the procedure in S11 described in the second embodiment.

  If the sub processor 30 determines that the number of commands per unit time output from the sub processor 30 has reached a predetermined amount b or more (YES in S41), the sub processor 30 transmits an interrupt signal to the main processor 20. Then, interrupt processing is performed (S42). Although not shown in the figure, the processor system 100 is provided with an interrupt wiring for connecting the main processor 20 and the sub processor 30, and the sub processor 30 transmits an interrupt signal via this wiring.

  The main processor 20 that has received the interrupt signal cancels the standby state setting and returns to the full operation mode (S43).

  Further, the main processor 20 that has returned from the standby state performs control to cancel the self-refresh operation in the high-speed DRAM 50 via the system controller 40 (S44). The process of S44 may be performed under the control of the sub processor 30.

  Thereafter, the main processor 20 performs a process of synchronizing (returning) the information saved in the low-speed DRAM 60 in S33 with the high-speed DRAM 50 via the system controller 40 (S45). The process of S45 is performed using the synchronization circuit (data synchronization storage circuit) 300 shown in FIG.

  This synchronization processing will be specifically described below. In the standby mode, when the data saved from the high-speed DRAM 50 to the low-speed DRAM 60 is updated, when the full operation mode is subsequently restored, the pre-save data and the updated data on the high-speed DRAM 50 for which self-refresh is canceled Then, it becomes different contents.

  Therefore, when the data saved in the low-speed DRAM 60 is updated in the standby mode, the corresponding data in the high-speed DRAM 50 is similarly updated after returning to the full operation mode and releasing the self-refresh operation of the high-speed DRAM 50. There is a need to.

  Therefore, in this embodiment, as shown in FIG. 1, when the data saved from the high speed DRAM 50 to the low speed DRAM 60 is updated in the standby mode, the update contents and the data on the high speed DRAM 50 corresponding to the update data are updated. Is provided in the sub-controller 40b. This writing is performed by the sub processor 30 with reference to the address storage circuit 200.

  In step S45, the main processor 20 refers to the content stored in the synchronization circuit 300 and updates the data in the high-speed DRAM 50 to perform the synchronization process. The process of S45 may be performed under the control of the sub processor 30.

  When the process of S45 described above is completed, the return process from the standby mode to the full operation mode is completed.

  When the operator turns off the power of the target device in the full operation mode and the standby mode, the processor system 100 shifts to the power off state (S5 and S8 in FIG. 5).

  The processor system 100 having the above configuration includes a standby mode for setting the main processor 20 to a standby state. In the standby mode, since the main processor 20 is in the standby state, the main processor 20 has no energy saving effect as in the case where power supply to the main processor 20 is stopped (“power saving mode” in the second embodiment). It is possible to achieve an energy saving effect compared to the full operation.

  Further, the processor system 100 having the above configuration includes a high-speed DRAM 50 and a low-speed DRAM 60 which are data development areas. Among these memories, the high-speed DRAM 50 performs a self-refresh operation while the main processor 20 is in a standby state.

  Therefore, not only the energy saving effect due to the standby state of the main processor 20 but also the energy saving effect due to the self-refresh operation of the high-speed DRAM 50 enables further power saving. According to the above configuration, during the self-refresh operation of the high-speed DRAM 50, the sub processor 30 can use the low-speed DRAM 60 / SRAM 70 as a work area.

  Further, in the processor system 100 having the above configuration, necessary data in the standby mode among the data (including programs) in the high speed DRAM 50 is saved in the low speed DRAM 60 before the self refresh operation of the high speed DRAM 50 is started. Therefore, even while the high-speed DRAM 50 is in the self-refresh state in the standby mode, the sub-processor 30 accesses the low-speed DRAM 60, so that in the standby mode of the data stored in the high-speed DRAM 50. It becomes possible to access the same data as necessary data.

  In the processor system 100 configured as described above, the high-speed DRAM 50 has higher power consumption than the low-speed DRAM 60 because the access speed is higher than that of the low-speed DRAM 60. Therefore, as in this embodiment, when energy saving is achieved by setting only one of the high-speed DRAM 50 and the low-speed DRAM 60 to the self-refresh state, the higher-speed DRAM 50 with higher power consumption is set to the self-refresh state. , Energy saving effect is higher.

  Further, the processor system 100 is configured to be able to switch between three modes of “full operation mode”, “power saving mode” described in the second embodiment, and “standby mode” in the present embodiment. Also good.

  In the case of this configuration, the predetermined amount b shown in S31 of FIG. 6 and S41 of FIG. 7 is set higher than the predetermined amount a shown in S11 of FIG. 3 and S21 of FIG.

  As a result, when the work amount of the main processor 20 and the sub processor 30 is reduced in the full operation mode, the processor system 100 first shifts to the standby mode through the steps shown in FIG. 6 (FIG. 8). S6).

  Then, in the processor system 100 in the standby mode, when the work amount of the main processor 20 and the sub processor 30 is further reduced, the process shifts to the power saving mode through each procedure shown in FIG. 3 (S10 in FIG. 8). In this case, the processing of S13 and S14 shown in FIG. 3 is executed by the sub processor 30.

  In this way, as shown in FIG. 8, if the work amount of the main processor 20 and the sub processor 30 decreases, it first shifts to the “standby mode”, and if the work amount further decreases, it shifts to the “power saving mode”. A processor system 100 that can be migrated can be constructed. Note that S1, S3, S5, S6, and S7 in FIG. 8 are the same steps as S1, S3, S5, S6, and S7 shown in FIG.

  Further, as an application target of the processor system 100 having the three-stage modes of “full operation mode”, “standby mode”, and “power saving mode” as shown in FIG. 8, image forming apparatuses (printers, copiers, MFPs, etc.) Is preferred. This is because the amount of load on the image forming apparatus varies greatly depending on the state of the apparatus. In such an apparatus, by applying a processor system capable of switching the power consumption to a plurality of stages, This is because efficient energy saving can be achieved. For example, many image forming apparatuses connected to a LAN in an office are monitored by a host computer. Such a load state of the image forming apparatus is monitored by (a) a high load state during the image forming operation, and (b) data transmission / reception with the host computer which is not performing the image forming operation. And (c) a low load state in which no image forming operation is performed and no data is transmitted to or received from the host computer.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and the invention can be obtained by appropriately combining the technical means disclosed in the above-described embodiments. Embodiments are also included in the technical scope of the present invention.

  The processor system of the present invention can be applied to all computer-controlled apparatuses, but is optimally applied to an image forming apparatus.

1 is a block diagram showing a schematic configuration of a processor system according to an embodiment of the present invention. It is explanatory drawing which showed the state transition of the processor system shown in FIG. 3 is a flowchart showing a processing procedure of the processor system when shifting from the full operation mode shown in FIG. 2 to a power saving mode. 3 is a flowchart showing a processing procedure of the processor system when returning from the power saving mode shown in FIG. 2 to the full operation mode. It is explanatory drawing which showed the state transition of the processor system which concerns on other embodiment of this invention. 6 is a flowchart showing a processing procedure of the processor system when shifting from the full operation mode shown in FIG. 5 to the standby mode. FIG. 6 is a flowchart showing a processing procedure of the processor system when returning from the standby mode shown in FIG. 5 to the full operation mode. It is explanatory drawing which showed the state transition of the processor system which concerns on further different embodiment of this invention.

Explanation of symbols

20 Main processor 30 Sub processor 40 System controller 40a Main controller (main control circuit)
40b Sub-controller (Sub-control circuit)
50 High-speed DRAM (first memory area, first DRAM)
60 Low speed DRAM (first memory area, second DRAM)
70 SRAM (second memory area)
90 power supply control circuit 200 address storage circuit 300 synchronization circuit (memory circuit for data synchronization)
α First power supply system β Second power supply system

Claims (13)

A main processor;
A sub-processor,
A main control circuit that performs device control in response to a command from the main processor;
A sub control circuit that performs device control in response to a command from the sub processor;
A first power supply system connected to the main processor and the main control circuit for supplying input power to the main processor and the main control circuit;
A second power source system connected to the sub processor and the sub control circuit, and supplying input power to the sub processor and the sub control circuit;
A power supply control circuit capable of independently switching between input of power to the first power supply system and input of power to the second power supply system;
A processor system comprising: The processor system according to claim 1, wherein
The power control circuit is
A processor that switches between a normal mode in which power is input to the first power supply system and the second power supply system and a power saving mode in which power is not input to the first power supply system and power is input to the second power supply system. system. The processor system according to claim 2, wherein
Including the memory that is the data expansion area,
The memory includes a first memory area used only in the normal mode and a second memory area used in the normal mode and the power saving mode,
The processor system, wherein the first memory area is connected to a first power supply system, and the second memory area is connected to a second power supply system. The processor system according to claim 3, wherein
The main processor or sub-processor is
A processor system characterized by performing control to save data stored in the first memory area in the second memory area in advance before shifting from the normal mode to the power saving mode. The processor system according to claim 3 or 4,
2. The processor system according to claim 1, wherein the first memory area is constituted by a DRAM and the second memory area is constituted by an SRAM. The processor system according to any one of claims 3 to 5,
An address storage circuit for storing an address before saving and an address after saving with respect to data saved from the first memory area to the second memory area;
In the power saving mode, the sub-processor accesses the address where the data is stored with reference to the address storage circuit. The processor system according to claim 1 or 2,
A processor system comprising a standby mode for setting the main processor to a standby state. The processor system according to claim 7, wherein
Including the memory that is the data expansion area,
The memory includes a first DRAM and a second DRAM,
The main processor or the sub-processor sets the first DRAM to a self-refresh state before setting the standby state, and performs control for releasing the self-refresh state after releasing the standby state. . The processor system according to claim 8, wherein
The main processor or sub-processor is
A processor system characterized by performing control to save data in the first DRAM to the second DRAM before setting the standby state. The processor system according to claim 8 or 9,
The processor system, wherein the first DRAM is a DRAM having a higher access speed than the second DRAM. The processor system according to claim 9, wherein
An address storage circuit for storing an address before saving and an address after saving with respect to data saved from the first DRAM to the second DRAM;
The processor system, wherein the sub-processor accesses the address where the data is stored with reference to the address storage circuit in the self-refresh state of the first DRAM. The processor system according to claim 9 or 11,
When the data saved from the first DRAM to the second DRAM is updated, the data synchronization storage circuit stores the update data and the address of the data in the first DRAM,
The processor system, wherein the main processor or sub-processor controls to synchronize data in the first DRAM with the update data when the self-refresh state of the first DRAM is released.   An image forming apparatus comprising the processor system according to claim 1.

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