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JP2006295057A - Semiconductor light emitting element and its manufacturing method - Google Patents

Semiconductor light emitting element and its manufacturing method Download PDF

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JP2006295057A
JP2006295057A JP2005117117A JP2005117117A JP2006295057A JP 2006295057 A JP2006295057 A JP 2006295057A JP 2005117117 A JP2005117117 A JP 2005117117A JP 2005117117 A JP2005117117 A JP 2005117117A JP 2006295057 A JP2006295057 A JP 2006295057A
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JP4751093B2 (en
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Ichiyo Tsutsumi
一陽 堤
Norikazu Ito
範和 伊藤
Takeshi Nakahara
健 中原
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Rohm Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a nitride semiconductor light emitting element capable of improving external quantum efficiency by effectively taking out light to prevent the light emitted by a light emitting layer from repeating total reflection in a semiconductor laminate and a substrate to attenuate, and to provide its manufacturing method. <P>SOLUTION: The semiconductor laminate 7 made of a nitride semiconductor and having an n-type layer 3 on the side of a substrate 1 and a p-type layer 5 on the side of the upper surface to form the light emitting layer is provided on the surface of the substrate 1. A p-side electrode 9 is provided in electric connection with the p-type layer 5 of the laminate 7, and an n-side electrode 10 is provided in electric connection with the n-type layer 3. The outermost p-type semiconductor layer of the semiconductor laminate 7 serves as a light take-out layer 6 formed to have a six-sided pyramid protrusion 6a or recess formed on a crystalline plane of ä1-101} side. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は基板上に、窒化物半導体が積層される青色系(紫外線から黄色)の光を発生する半導体発光素子およびその製法に関する。さらに詳しくは、発光層形成部で発光した光を効率よく外部に取りだし、外部量子効率を向上させることができる構造の半導体発光素子およびその製法に関する。   The present invention relates to a semiconductor light-emitting element that generates blue light (ultraviolet to yellow) on which a nitride semiconductor is stacked on a substrate, and a method for manufacturing the same. More specifically, the present invention relates to a semiconductor light emitting device having a structure capable of efficiently extracting light emitted from a light emitting layer forming portion to the outside and improving external quantum efficiency, and a manufacturing method thereof.

従来、青色系の光を発光する半導体発光素子は、たとえば図6に示されるように、サファイア基板31上に、GaNなどからなる低温バッファ層32、GaNなどからなるn形層33と、バンドギャップエネルギーがn形層33のそれよりも小さく発光波長を定める材料、たとえばInGaN系(InとGaの比率が種々変り得ることを意味する、以下同じ)化合物半導体からなる活性層(発光層)34と、GaNなどからなるp形層35とが積層されて半導体積層部36が形成され、その表面に透光性導電層37を介して、p側(上部)電極38が設けられ、積層された半導体積層部36の一部がエッチングされて露出したn形層33の表面にn側電極39が設けられることにより形成されている。なお、n形層33およびp形層35はキャリアの閉じ込め効果を向上させるため、活性層側にAlGaN系(AlとGaの比率が種々変り得ることを意味する、以下同じ)化合物などのさらにバンドギャップエネルギーの大きい半導体層が用いられることがある。   Conventionally, a semiconductor light emitting device that emits blue light includes, for example, a low temperature buffer layer 32 made of GaN, an n-type layer 33 made of GaN, and a band gap on a sapphire substrate 31, as shown in FIG. A material whose energy is smaller than that of the n-type layer 33 and determines the emission wavelength, for example, an active layer (light emitting layer) 34 made of an InGaN-based (meaning that the ratio of In and Ga can be changed variously, the same applies hereinafter) compound semiconductor; , A p-type layer 35 made of GaN or the like is laminated to form a semiconductor laminated portion 36, and a p-side (upper) electrode 38 is provided on the surface via a translucent conductive layer 37. The n-side electrode 39 is provided on the surface of the n-type layer 33 exposed by etching a part of the stacked portion 36. Note that the n-type layer 33 and the p-type layer 35 further improve the carrier confinement effect, so that the active layer side has a further band such as an AlGaN-based compound (meaning that the ratio of Al and Ga can be changed variously, the same applies hereinafter). A semiconductor layer having a large gap energy may be used.

一方、窒化物半導体も他の化合物半導体などと同様に、屈折率は2.5程度と空気の屈折率1よりはるかに大きい。そのため、窒化物半導体層の発光層で発光した光が、半導体積層部から空気中に出射する際に全反射を起こしやすく、半導体積層部から外に出ないで、半導体積層部内で全反射を繰り返して減衰する光が多く、光の取出し効率が10%のオーダとなり著しく低い。そのため、たとえばp形層の最表面を円筒状または半球状にドライエッチングして凹凸を形成したり(たとえば特許文献1参照)、半導体層を積層して表面側のp形層に支持基板を形成して半導体層を積層する際の基板を除去し、露出するn形層にアルミナ粒などの粒体を塗布して、またはマスクパターンを形成して熱処理をしてからRIE法によりn形層を部分的にエッチングしたり、ダイヤモンド粒などを用いて研磨したり、n形層を成長させた後に成長温度などを適宜調節してn形層を再成長させたり、n形層表面にSiO2などのマスクを形成して選択的にn形層を再成長させたりする方法(たとえば特許文献2参照)などが知られている。
特開2000−196152号公報 特開2003−318443号公報
On the other hand, the nitride semiconductor, like other compound semiconductors, has a refractive index of about 2.5, much higher than the refractive index 1 of air. For this reason, the light emitted from the light emitting layer of the nitride semiconductor layer is likely to cause total reflection when emitted from the semiconductor stacked portion into the air, and repeats total reflection within the semiconductor stacked portion without exiting from the semiconductor stacked portion. Therefore, the light extraction efficiency is on the order of 10%, which is extremely low. Therefore, for example, the top surface of the p-type layer is dry-etched into a cylindrical or hemispherical shape to form irregularities (for example, see Patent Document 1), or a semiconductor substrate is stacked to form a support substrate on the p-type layer on the surface side Then, the substrate when the semiconductor layer is laminated is removed, and the exposed n-type layer is coated with particles such as alumina grains, or a mask pattern is formed and heat-treated, and then the n-type layer is formed by RIE. Etching partially, polishing with diamond grains, etc., growing the n-type layer, adjusting the growth temperature etc. as appropriate, and re-growing the n-type layer, SiO 2 etc. on the n-type layer surface There is known a method of forming an n-type mask and selectively regrowing an n-type layer (see, for example, Patent Document 2).
JP 2000-196152 A JP 2003-318443 A

前述のように、窒化物半導体発光素子においても、他の化合物半導体発光素子と同様に光の取出し効率を向上させるため、表面側に凹凸を設ける工夫は種々なされている。しかしながら、窒化物半導体は化学的に安定で、ウェットエッチングで窒化物半導体層の表面を凸凹にすることはできない。そのため、前述のように、RIEなどのドライエッチングにより積層された半導体積層部の表面をエッチングマスクの形状に合せてエッチングしたり、シリコン基板上に窒化物半導体層を積層し、その表面のp形層表面に支持基板を形成した後に、シリコン基板をウェットエッチングにより除去して、露出するn形層表面に凹凸を形成したりする方法が試みられている。   As described above, in the nitride semiconductor light emitting device, various measures have been taken to provide unevenness on the surface side in order to improve the light extraction efficiency as in the case of other compound semiconductor light emitting devices. However, the nitride semiconductor is chemically stable, and the surface of the nitride semiconductor layer cannot be made uneven by wet etching. Therefore, as described above, the surface of the semiconductor laminated portion laminated by dry etching such as RIE is etched according to the shape of the etching mask, or a nitride semiconductor layer is laminated on the silicon substrate, and the p-type on the surface is formed. An attempt has been made to form a support substrate on the layer surface, and then remove the silicon substrate by wet etching to form irregularities on the exposed n-type layer surface.

しかしながら、窒化物半導体のp形層はとくに結晶性が悪く、その表面をドライエッチングなどによりエッチングすると、その界面のみならず、p形層内部までドライエッチングによる衝撃で結晶性がより一層悪化して、直列抵抗が大きくなったり、界面に光を吸収する準位を有する欠陥を与えたりして、発光特性を低下させたり、寿命を短くしたりするという問題がある。   However, the p-type layer of nitride semiconductor is particularly poor in crystallinity, and when the surface is etched by dry etching or the like, the crystallinity is further deteriorated by the impact of dry etching not only at the interface but also inside the p-type layer. There are problems that the series resistance increases, or that the interface has a defect having a level that absorbs light, thereby reducing the light emission characteristics and shortening the lifetime.

また、n形層の表面を加工するのは比較的容易であるが、n形層の表面を加工するためn形層を露出させる方法では、窒化物半導体のp形層の結晶性が悪いため、窒化物半導体層を積層する場合にn形半導体層から積層するのが普通で、n形層をそのまま直接露出させることはできず、前述の引用文献2では、一般的に窒化物半導体層を積層するサファイア基板やSiC基板を用いないで、シリコン基板上に窒化物半導体層を積層してから、p形層の表面に支持基板を形成し、シリコン基板をエッチングにより除去してn形層を露出させる必要があり、非常に製造工程が複雑であるのみならず、シリコン基板と窒化物半導体とは格子整合せず、シリコン基板上に形成した窒化物半導体層自身の結晶性が非常に悪いという問題がある。さらに、シリコン基板ではなく、現在窒化物半導体層の成長に実用化されているサファイア基板またはSiC基板上に積層してサファイア基板などを除去することを試みると、サファイア基板などは非常に安定な化合物であり、ウェットエッチングをすることができず、基板の除去が大変であると共に、除去する際に積層した窒化物半導体層の結晶性を悪化させるという問題がある。   In addition, although it is relatively easy to process the surface of the n-type layer, the method of exposing the n-type layer to process the surface of the n-type layer has poor crystallinity of the p-type layer of the nitride semiconductor. When a nitride semiconductor layer is laminated, it is usually laminated from an n-type semiconductor layer, and the n-type layer cannot be directly exposed as it is. Without using a sapphire substrate or SiC substrate to be stacked, a nitride semiconductor layer is stacked on a silicon substrate, a support substrate is formed on the surface of the p-type layer, and the silicon substrate is removed by etching to form an n-type layer. Not only is the manufacturing process very complicated, the silicon substrate and the nitride semiconductor do not lattice match, and the crystallinity of the nitride semiconductor layer itself formed on the silicon substrate is very poor. There's a problem. Furthermore, if you try to remove the sapphire substrate by stacking it on the sapphire substrate or SiC substrate that is currently put into practical use for growing the nitride semiconductor layer instead of the silicon substrate, the sapphire substrate is a very stable compound Therefore, there is a problem that wet etching cannot be performed, the removal of the substrate is difficult, and the crystallinity of the nitride semiconductor layer stacked upon the removal is deteriorated.

本発明はこのような問題を解決し、発光層で発光した光が半導体積層部と基板内で全反射を繰り返して減衰してしまうことのないように光を有効に取りだし、外部量子効率を向上させることができる構造の窒化物半導体発光素子およびその製法を提供することを目的とする。   The present invention solves such problems and effectively extracts the light so that the light emitted from the light emitting layer does not attenuate by repeated total reflection in the semiconductor laminate and the substrate, thereby improving the external quantum efficiency. It is an object of the present invention to provide a nitride semiconductor light emitting device having a structure that can be made and a method for manufacturing the same.

本発明者らは、窒化物半導体発光素子の半導体層部内で発光した光をできるだけ有効に外に取りだすことができるように、半導体積層部の最表面に凹凸を形成しながら、ドライエッチングなどによりp形層の表面および内部にダメージを与えたり、表面側に支持基板を形成して成長用基板を除去するという製造工程が非常に複雑な工程を用いたりすることなく、簡単に凹凸を形成するため、鋭意検討を重ねた結果、p形層はn形層よりもとくに成長の平坦性を得難いことに着目して、p形層の成長時に、成長温度を、たとえば通常の成長温度である950〜1100℃から、740〜900℃に低下させると共に、かつ、導入するガスのV族元素のIII族元素に対する割合を6000〜8000から100〜5000に下げて成長することにより、前記p形層の表面に{1−101}面の結晶面で形成される6角錐状の凸部または凹部を形成することができることを見出した。そして、このような{1−101}面のファセット面を有する6角錐状の凸部または凹部を形成することにより、光の取出し効率が大幅に向上して外部量子効率を向上させることができることを見出した。   The present inventors have made p by dry etching or the like while forming irregularities on the outermost surface of the semiconductor stacked portion so that the light emitted in the semiconductor layer portion of the nitride semiconductor light emitting element can be taken out as effectively as possible. To easily form irregularities without damaging the surface and the inside of the shape layer, or using a very complicated manufacturing process that removes the growth substrate by forming a support substrate on the surface side As a result of repeated studies, the p-type layer is more difficult to obtain the growth flatness than the n-type layer, and the growth temperature is set to, for example, a normal growth temperature of 950 to 950 when the p-type layer is grown. The temperature is lowered from 1100 ° C. to 740 to 900 ° C., and the ratio of the group V element to the group III element of the introduced gas is lowered from 6000 to 8000 to 100 to 5000 to grow. Found that it is possible to form the hexagonal pyramid shaped projections or recesses formed in the crystal plane of {1-101} plane on the surface of the p-type layer. And by forming such a hexagonal pyramid-shaped convex part or concave part having such a {1-101} facet surface, the light extraction efficiency can be greatly improved and the external quantum efficiency can be improved. I found it.

ここに{1−101}は、厳密には   Where {1-101} is strictly

Figure 2006295057
Figure 2006295057

を指すが、便宜的に上記のように略記する。また、{1−101}面は、結晶のもつ対称性により、(1−101)面と等価な面も含む総称であることを示している。 Is abbreviated as described above for convenience. Further, the {1-101} plane is a generic name including a plane equivalent to the (1-101) plane due to the symmetry of the crystal.

本発明による半導体発光素子は、基板と、窒化物半導体からなり基板側にn形層、上面側にp形層を有し、発光層を形成するように前記基板の一面上に設けられる半導体積層部と、該半導体積層部の前記p形層に電気的に接続して設けられるp側電極と、前記n形層に電気的に接続して設けられるn側電極とを具備する半導体発光素子であって、前記半導体積層部の最表面のp形半導体層が、{1−101}面の結晶面で形成される6角錐状の凸部または凹部を有するように形成されている。   A semiconductor light emitting device according to the present invention includes a substrate, a semiconductor laminated layer made of a nitride semiconductor, having an n-type layer on the substrate side and a p-type layer on the upper surface side, and is provided on one surface of the substrate so as to form a light emitting layer. A semiconductor light emitting device comprising: a portion; a p-side electrode electrically connected to the p-type layer of the semiconductor stacked portion; and an n-side electrode electrically connected to the n-type layer The p-type semiconductor layer on the outermost surface of the semiconductor stacked portion is formed to have a hexagonal pyramid-shaped convex portion or concave portion formed by a {1-101} crystal plane.

ここに窒化物半導体とは、III族元素のGaとV族元素のNとの化合物またはIII族元素のGaの一部または全部がAl、Inなどの他のIII族元素と置換したものおよび/またはV族元素のNの一部がP、Asなどの他のV族元素と置換した化合物(窒化物)からなる半導体をいう。   Here, the nitride semiconductor means a compound in which a group III element Ga and a group V element N or a part or all of a group III element Ga is substituted with another group III element such as Al and In, and / or Alternatively, it refers to a semiconductor made of a compound (nitride) in which a part of N of the group V element is substituted with another group V element such as P or As.

前記凸部または凹部が形成されたp形半導体層上に透光性導電層が設けられていても、その厚さが1μm程度以下であれば、p形層の表面に形成された凸部または凹部をそのまま維持することができ、電流を拡散させながら、光の取出し効率を向上させることができる。   Even if a translucent conductive layer is provided on the p-type semiconductor layer on which the convex portion or the concave portion is formed, if the thickness is about 1 μm or less, the convex portion formed on the surface of the p-type layer or The recess can be maintained as it is, and the light extraction efficiency can be improved while diffusing the current.

本発明による半導体発光素子の製法は、基板上に窒化物半導体からなるn形層と活性層とp形層をこの順で発光層を形成するようにMOCVD法により積層すると共に、前記p形層の最表面の層を、基板温度を950〜1100℃から740〜900℃に下げ、かつ、導入するガスのV族元素のIII族元素に対する割合を6000〜8000から100〜5000に下げて成長することにより、前記p形層の表面に{1−101}面の結晶面で形成される6角錐状の凸部または凹部を形成することを特徴とする。   The method of manufacturing a semiconductor light emitting device according to the present invention includes an n-type layer made of a nitride semiconductor, an active layer, and a p-type layer formed on a substrate by MOCVD so as to form a light emitting layer in this order. The outermost layer is grown by lowering the substrate temperature from 950 to 1100 ° C. to 740 to 900 ° C., and reducing the ratio of the introduced group V element to the group III element from 6000 to 8000 to 100 to 5000. Thus, a hexagonal pyramid-shaped convex part or concave part formed with a {1-101} crystal plane is formed on the surface of the p-type layer.

本発明の半導体発光素子によれば、p形層の表面に{1−101}面の結晶面で形成される6角錐状の凸部または凹部が形成されているため、p形層表面での全反射を抑制することができ、外に光が出やすくなって光の取出し効率が向上し、外部量子効率が向上する。しかも、{1−101}面の結晶面で形成される6角錐状の凸部または凹部であるため、半導体層を積層した後にドライエッチングなどの半導体層にダメージを与えるような処理を施すことなく、また、p形層の表面に形成されているため、半導体層を積層する基板を除去する必要はなく、半導体層を成長しながらその成長条件を制御するだけで表面に凸部または凹部を形成することができる。その結果、製造工程が非常に簡単で、しかも発光特性に何らの害を及ぼすことなく、光取出し効率を上げることができ、非常に外部量子効率を向上させた窒化物半導体発光素子を安価に得ることができる。   According to the semiconductor light emitting device of the present invention, the hexagonal pyramid-shaped convex part or concave part formed with the {1-101} crystal plane is formed on the surface of the p-type layer. Total reflection can be suppressed, light is easily emitted to the outside, light extraction efficiency is improved, and external quantum efficiency is improved. Moreover, since it is a hexagonal pyramid-shaped convex or concave formed with a {1-101} crystal plane, the semiconductor layer is laminated and processed without damaging the semiconductor layer such as dry etching. In addition, since it is formed on the surface of the p-type layer, it is not necessary to remove the substrate on which the semiconductor layer is laminated, and a convex or concave portion is formed on the surface simply by controlling the growth conditions while growing the semiconductor layer. can do. As a result, the manufacturing process is very simple, and the light extraction efficiency can be increased without causing any harmful effects on the light emission characteristics, and a nitride semiconductor light emitting device with a greatly improved external quantum efficiency can be obtained at a low cost. be able to.

また、本発明の製法によれば、基板上にまず結晶性のよいn形層を成長し、その上に活性層やp形層を成長して積層しながら、その成長条件を制御するだけで、p形層の最表面に凸部または凹部を形成しているため、半導体層にダメージを与えるドライエッチングの工程や、n形層を加工するため成長用基板を除去する工程などを必要とすることなく、非常に簡単に最表面に凸部または凹部を形成することができる。しかも、p形層で凸部または凹部を形成するように成長条件を制御しているため、元々結晶性の平坦性に劣るというp形層の成長特性を利用していることにより、成長条件を制御するだけで、確実に{1−101}面の結晶面で形成される6角錐状の凸部または凹部を形成することができ、一旦このような凸部または凹部が形成されると、その凸部または凹部がそのまま成長して大きくなるため、0.5〜数μmの厚さに成長すると、0.5〜2μm程度の凸部または凹部を形成することができる。なお、成長温度を900〜850℃にすることにより、凸部が形成されやすく、成長温度を850℃よりさらに低くすることにより、凹部も形成されやすくなるが、光の取出し効率という面からは、凸部の方が凹部よりも好ましい。   In addition, according to the manufacturing method of the present invention, an n-type layer having good crystallinity is first grown on a substrate, and an active layer and a p-type layer are grown and stacked on the substrate while controlling the growth conditions. Since the convex portion or the concave portion is formed on the outermost surface of the p-type layer, a step of dry etching that damages the semiconductor layer or a step of removing the growth substrate to process the n-type layer is required. Without this, it is possible to form a convex portion or a concave portion on the outermost surface very easily. Moreover, since the growth conditions are controlled so as to form convex portions or concave portions in the p-type layer, the growth conditions are controlled by utilizing the growth characteristics of the p-type layer, which is originally inferior in crystallinity flatness. Only by controlling, a hexagonal pyramid-shaped convex part or concave part formed with a {1-101} crystal plane can be surely formed. Once such a convex part or concave part is formed, Since the convex portion or the concave portion grows as it is and grows large, when it is grown to a thickness of 0.5 to several μm, a convex portion or concave portion of about 0.5 to 2 μm can be formed. In addition, by setting the growth temperature to 900 to 850 ° C., convex portions are easily formed, and by making the growth temperature lower than 850 ° C., concave portions are also easily formed, but from the aspect of light extraction efficiency, The convex portion is preferable to the concave portion.

つぎに、図面を参照しながら本発明の半導体発光素子およびその製法について説明をする。図1に、青色系の発光に適した窒化物半導体層がサファイア基板上に積層される本発明による半導体発光素子の一実施形態の斜視説明図、凸部の拡大説明図および断面説明図が示されるように、基板1の表面上に、窒化物半導体からなり基板1側にn形層3、上面側にp形層5を有し、発光層を形成するように、半導体積層部7が設けられ、半導体積層部7のp形層5に電気的に接続してp側電極9が設けられ、n形層3に電気的に接続してn側電極10が設けられている。本発明では、半導体積層部7の最表面のp形半導体層が、{1−101}面の結晶面で形成される6角錐状の凸部6aまたは凹部を有するように形成された、光取出し層6とされている。   Next, the semiconductor light emitting device of the present invention and the manufacturing method thereof will be described with reference to the drawings. FIG. 1 shows a perspective explanatory view of an embodiment of a semiconductor light emitting device according to the present invention in which a nitride semiconductor layer suitable for blue light emission is stacked on a sapphire substrate, an enlarged explanatory view of a convex portion, and a cross sectional explanatory view. As shown in the figure, the semiconductor laminate portion 7 is provided on the surface of the substrate 1 so as to form a light emitting layer having an n-type layer 3 on the substrate 1 side and a p-type layer 5 on the upper surface side. In addition, a p-side electrode 9 is provided in electrical connection with the p-type layer 5 of the semiconductor stacked portion 7, and an n-side electrode 10 is provided in electrical connection with the n-type layer 3. In the present invention, the p-type semiconductor layer on the outermost surface of the semiconductor multilayer portion 7 is formed so as to have a hexagonal pyramid-shaped convex portion 6a or a concave portion formed by a {1-101} plane crystal plane. Layer 6 is designated.

図1に示される例では、基板1に絶縁性基板であるサファイア基板が用いられている。そのため、半導体積層部7の一部がエッチングにより除去され、下層の導電形層であるn形層3を露出させ、その表面にn側電極10が形成されている。しかし、後述する図5に示されるように、基板1としては、SiCのような半導体基板を用いることもできる。この場合でも、同様に最表面のp形層に{1−101}面の結晶面で形成される6角錐状の凸部6aまたは凹部を形成することにより、光の取出し効率が向上しながら、p形層を始め窒化物半導体層にダメージを与えることがないと共に、簡単な工数で凸部または凹部を形成することができる。   In the example shown in FIG. 1, a sapphire substrate that is an insulating substrate is used for the substrate 1. Therefore, a part of the semiconductor laminated portion 7 is removed by etching, the n-type layer 3 which is a lower conductive type layer is exposed, and an n-side electrode 10 is formed on the surface thereof. However, as shown in FIG. 5 to be described later, a semiconductor substrate such as SiC can also be used as the substrate 1. Even in this case, by similarly forming the hexagonal pyramid-shaped convex part 6a or concave part formed of the {1-101} crystal plane on the outermost p-type layer, the light extraction efficiency is improved. The p-type layer and the nitride semiconductor layer are not damaged, and the convex portion or the concave portion can be formed with a simple man-hour.

半導体積層部7は、たとえばつぎのような構造に形成される。たとえばGaNからなる低温バッファ層2が0.005〜0.1μm程度、SiをドープしたGaNまたはAlGaN系化合物からなるn形層3が1〜10μm程度、たとえば1〜3nmのIn0.13Ga0.87Nからなるウェル層と10〜20nmのGaNからなるバリア層とが3〜8ペア積層される多重量子井戸 (MQW)構造の活性層4が0.05〜0.3μm程度、p形のGaNまたはAlGaN系化合物半導体からなるp形層5が0.2〜1μm程度、それぞれ順次積層されることにより構成されている。本発明では、このp形層の最表面に{1−101}面の結晶面で形成される6角錐状の凸部6aが形成された、たとえばAlxGa1-xN(0≦x≦0.2、たとえばx=0)からなる光取出し層6が形成されていることに特徴がある。 The semiconductor laminated portion 7 is formed in the following structure, for example. For example, the low-temperature buffer layer 2 made of GaN is about 0.005 to 0.1 μm, and the n-type layer 3 made of Si-doped GaN or AlGaN-based compound is about 1 to 10 μm, for example, from In 0.13 Ga 0.87 N of 1 to 3 nm. Active layer 4 having a multiple quantum well (MQW) structure in which 3 to 8 pairs of well layers and 10 to 20 nm GaN barrier layers are stacked, is about 0.05 to 0.3 μm, p-type GaN or AlGaN The p-type layer 5 made of a compound semiconductor is formed by sequentially laminating about 0.2 to 1 μm. In the present invention, a hexagonal pyramid-shaped convex portion 6a formed of a {1-101} crystal plane is formed on the outermost surface of the p-type layer, for example, Al x Ga 1-x N (0 ≦ x ≦ It is characterized in that a light extraction layer 6 made of 0.2 (for example, x = 0) is formed.

なお、図1に示される例では、n形層3は1層で、p形層はp形層5と光取出し層6とで構成する例で示されているが、たとえばn形層3およびp形層5の活性層側にAlGaN系化合物からなるキャリアを閉じ込めやすい障壁層(バンドギャップエネルギーの大きい層)と、活性層4と反対側にキャリア濃度を上げやすいGaNコンタクト層との複層にすることもでき、さらに低温バッファ層上にアンドープまたはn形などの高温バッファ層や、各層間の歪みを緩和する超格子層などの他の層を介在させることができる。またこれらを他の窒化物半導体層で形成することもできる。さらに、この例では、n形層3とp形層5とで活性層4が挟持されたダブルヘテロ接合構造であるが、n形層とp形層とが直接接合するpn接合構造のものでもよい。また、活性層4も、前述のMQW構造に限らず、単一量子井戸構造(SQW)またはバルク構造にすることもできる。   In the example shown in FIG. 1, the n-type layer 3 is one layer and the p-type layer is composed of the p-type layer 5 and the light extraction layer 6. The p-type layer 5 is composed of a barrier layer (a layer having a large bandgap energy) that easily traps an AlGaN-based carrier on the active layer side, and a GaN contact layer that easily raises the carrier concentration on the side opposite to the active layer 4. Furthermore, another layer such as an undoped or n-type high-temperature buffer layer or a superlattice layer that relieves strain between layers can be interposed on the low-temperature buffer layer. They can also be formed of other nitride semiconductor layers. Further, in this example, the active layer 4 is sandwiched between the n-type layer 3 and the p-type layer 5, but a pn junction structure in which the n-type layer and the p-type layer are directly joined is also used. Good. Further, the active layer 4 is not limited to the MQW structure described above, but may be a single quantum well structure (SQW) or a bulk structure.

光取出し層6は、たとえばAlxGa1-xN層により形成され、表面に{1−101}面の結晶面で形成される6角錐状の凸部6aが形成され、0.1〜1μm程度の厚さtに形成されている。その結果、この凸部6aの高さh(図1(c)参照)は、0.1〜1μm程度の高さに形成される。この凸部6aの高さは、光取出し層6の厚さに依存し、厚く形成するほど凸部6aの高さは高くなる。なお、光取出し層6の厚さtとは、凸部6aの頂上までの厚さを意味する。このような凸部6aを形成するには、前述のように、光取出し効率を改善するため、本発明者らが鋭意検討を重ねた結果見出されたもので、p形層の成長の際に、たとえば成長温度を下げて、さらにV族元素のIII族元素に対する割合を減らすことにより、p形層の平坦性が害されて、{1−101}面の結晶面で形成される6角錐状の凸部6aまたは凹部が形成される。この凸部または凹部を形成するための成長条件の詳細については、後述する。 The light extraction layer 6 is formed of, for example, an Al x Ga 1-x N layer, and has a hexagonal pyramid-shaped convex portion 6 a formed of a {1-101} crystal plane on the surface, and is 0.1 to 1 μm. It is formed to a thickness t. As a result, the height h (see FIG. 1C) of the convex portion 6a is formed to a height of about 0.1 to 1 μm. The height of the convex portion 6a depends on the thickness of the light extraction layer 6, and the height of the convex portion 6a increases as the thickness increases. The thickness t of the light extraction layer 6 means the thickness up to the top of the convex portion 6a. In order to form such a convex portion 6a, as described above, the inventors of the present invention have made extensive studies in order to improve the light extraction efficiency. In addition, for example, by reducing the growth temperature and further reducing the ratio of the group V element to the group III element, the flatness of the p-type layer is impaired, and the hexagonal pyramid formed by the crystal plane of the {1-101} plane A convex portion 6a or a concave portion is formed. Details of the growth conditions for forming the convex portion or the concave portion will be described later.

図1に示される例では、光取出し層6に凸部を形成したが、図2に示されるように、{1−101}面の結晶面で形成される6角錐状の凹部6bを形成しても、同様に光取出し効率が向上する。このような凹部6bを形成するには、成膜温度を850℃以下にすることにより、形成しやすくなるが、凸部と凹部が混合して形成されてもよい。   In the example shown in FIG. 1, a convex portion is formed in the light extraction layer 6. However, as shown in FIG. 2, a hexagonal pyramid-shaped concave portion 6b formed by a {1-101} crystal plane is formed. However, the light extraction efficiency is similarly improved. In order to form such a recess 6b, the film formation temperature is set to 850 ° C. or less, so that the recess 6b can be easily formed.

そして、積層された半導体積層部7の一部がエッチングにより除去されて露出するn形層3上に、オーミックコンタクト用のn側電極10が、0.01μm程度の厚さのTi膜と0.25μm程度の厚さのAl膜とを積層した後600℃程度でシンターすることにより合金層として形成され、光取出し層7の上の一部に、0.1μm程度厚のTi膜と0.3μm程度厚のAu膜との積層構造によりp側電極9が形成されている。そして、p側電極9およびn側電極10の表面を除いて、全面に図示しないSiO2などのパシベーション膜を設けられている。 Then, an n-side electrode 10 for ohmic contact is formed on the n-type layer 3 exposed by removing a part of the laminated semiconductor laminated portion 7 by etching, and a Ti film having a thickness of about 0.01 μm and a thickness of 0.1 μm. An Al film having a thickness of about 25 μm is laminated and then sintered at about 600 ° C. to form an alloy layer. A Ti film having a thickness of about 0.1 μm and 0.3 μm are formed on a part of the light extraction layer 7. The p-side electrode 9 is formed by a laminated structure with a moderately thick Au film. A passivation film such as SiO 2 ( not shown) is provided on the entire surface except for the surfaces of the p-side electrode 9 and the n-side electrode 10.

つぎに、前述の{1−101}面の結晶面で形成される6角錐状の凸部6aの形成法を含めて、図1に示される半導体発光素子の製法について説明をする。たとえば有機金属化学気相成長法(MOCVD法)により、キャリアガスのH2 と共にトリメチリガリウム(TMG)、アンモニア(NH3)、トリメチルアルミニウム(TMA)、トリメチルインジウム(TMIn)などの反応ガスおよびn形にする場合のドーパントガスとしてのSiH4 、p形にする場合のドーパントガスとしてのシクロペンタジエニルマグネシウム(Cp2 Mg)またはジメチル亜鉛(DMZn)などの必要なガスを供給して順次成長する。 Next, a method for manufacturing the semiconductor light emitting device shown in FIG. 1 will be described, including the method for forming the hexagonal pyramid-shaped convex portion 6a formed by the crystal plane of the {1-101} plane described above. For example, by a metal organic chemical vapor deposition method (MOCVD method), a reactive gas such as trimethylethylene gallium (TMG), ammonia (NH 3 ), trimethylaluminum (TMA), trimethylindium (TMIn) and n together with H 2 as a carrier gas SiH 4 as a dopant gas when forming a p-type, and a necessary gas such as cyclopentadienylmagnesium (Cp 2 Mg) or dimethylzinc (DMZn) as a dopant gas when forming a p-type are sequentially grown. .

まず、たとえばサファイアからなる基板1上に、たとえば400〜600℃程度の低温で、GaN層からなる低温バッファ層2を0.005〜0.1μm程度成膜した後、温度を600〜1200℃程度の高温に上げて、n形GaNからなるn形層(障壁層)3を1〜10μm程度成膜する。つぎに、成長温度を400〜600℃の低温に下げて、たとえば1〜3nmのIn0.13Ga0.87Nからなるウェル層と10〜20nmのGaNからなるバリア層とが3〜8ペア積層される多重量子井戸 (MQW)構造の活性層4を0.05〜0.3μm程度成膜する。ついで、成長装置内の温度を950〜1100℃程度に上げ、GaNからなるp形層5を0.2〜1μm程度それぞれ積層する。その後、成長温度を740〜900℃に下げ、かつ、導入するガスのV族元素のIII族元素に対する割合が6000〜8000から100〜5000に下げてAlxGa1-xN(たとえばx=0)からなる光取出し層6を0.2〜1μm程度形成する。なお、この場合の成膜速度は1μm/h〜3μm/h程度となり、p形層5の成膜速度0.7〜1μm/h程度と比較して速くなり、ドーパントのMgの供給量をp形層5の成長の場合より多くして、Mg/Gaが1×10-3〜1×10-2程度となるようにドーパントガスの供給を行う。 First, on the substrate 1 made of sapphire, for example, a low-temperature buffer layer 2 made of a GaN layer is formed at a low temperature of about 400 to 600 ° C., for example, about 0.005 to 0.1 μm, and then the temperature is about 600 to 1200 ° C. The n-type layer (barrier layer) 3 made of n-type GaN is formed to a thickness of about 1 to 10 μm. Next, the growth temperature is lowered to a low temperature of 400 to 600 ° C., and, for example, 3 to 8 pairs of well layers made of In 0.13 Ga 0.87 N of 1 to 3 nm and barrier layers made of GaN of 10 to 20 nm are stacked. An active layer 4 having a quantum well (MQW) structure is formed to a thickness of about 0.05 to 0.3 μm. Next, the temperature in the growth apparatus is raised to about 950 to 1100 ° C., and the p-type layer 5 made of GaN is laminated to about 0.2 to 1 μm. Thereafter, the growth temperature is lowered to 740 to 900 ° C., and the ratio of the group V element to the group III element of the introduced gas is lowered from 6000 to 8000 to 100 to 5000 to reduce Al x Ga 1-x N (for example, x = 0). The light extraction layer 6 is formed with a thickness of about 0.2 to 1 μm. In this case, the film formation rate is about 1 μm / h to 3 μm / h, which is faster than the film formation rate of the p-type layer 5 of about 0.7 to 1 μm / h. The dopant gas is supplied so that the Mg / Ga is about 1 × 10 −3 to 1 × 10 −2 more than the growth of the shape layer 5.

すなわち、前述のように、本発明者らは、光の取出し効率を向上させるため、鋭意検討を重ねた結果、窒化物半導体層の結晶成長は、緻密で平坦な膜を成長しにくいという問題に着目し、あえて、成長温度を通常よりも低くし、さらにV族元素の原料ガスのIII族元素の供給ガスに対する割合を上記のように減ずることにより、{1−101}面の結晶面を有し、図1(b)に示されるような6角錐状の凸部が規則的に生成されることを見出した。また、成長温度を850℃程度以下とすることにより、図2に示されるような{1−101}面の結晶面を有する6角錐状の凹部6bが規則的に生成されることを見出した。なお、850℃以下の温度で成長すると、凸部と凹部が混合して形成されることもあるが、両者が混合していても何ら支障はない。内部で発生した光の入射角が変って臨界角度より小さくすることが目的であるため、傾斜面が形成されればよいからである。しかし、凹部よりも凸部が形成された方が、その上に透光性導電層や保護膜を形成した場合でも、凹部のように中が埋められてしまうということが起こり難いため好ましい。   That is, as described above, the present inventors have made extensive studies in order to improve the light extraction efficiency, and as a result, the crystal growth of the nitride semiconductor layer is difficult to grow a dense and flat film. Focusing on the fact that the growth temperature is lower than usual and the ratio of the group V element source gas to the group III element supply gas is reduced as described above, the crystal plane of the {1-101} plane is obtained. Then, it has been found that hexagonal pyramid-shaped convex portions as shown in FIG. Further, it has been found that by setting the growth temperature to about 850 ° C. or less, hexagonal pyramid-shaped recesses 6b having a {1-101} plane crystal plane as shown in FIG. In addition, when it grows at the temperature of 850 degrees C or less, although a convex part and a recessed part may be formed and mixed, even if both are mixed, there will be no trouble. This is because the incident angle of the light generated inside is changed to be smaller than the critical angle, so that an inclined surface may be formed. However, it is preferable that the convex portion is formed rather than the concave portion because even if a light-transmitting conductive layer or a protective film is formed on the concave portion, it is unlikely that the inside is buried like the concave portion.

その後、表面にSiNなどの保護膜を設けてp形ドーパントの活性化のため、400〜800℃程度で10〜60分程度のアニールを行い、ホトレジストを全面に塗布して、ホトリソグラフィ工程によりパターニングをして半導体積層部7のエッチングする部分(チップ周囲およびn側電極形成部分)を露出させ、たとえば塩素ガスと四塩化珪素ガスを導入してRFパワーを印加することによりエッチングする。その結果、マスクに覆われないで露出しているチップ周囲およびn側電極10の形成場所の半導体積層部7がエッチングされ、n形層3が露出する。   After that, a protective film such as SiN is provided on the surface, and in order to activate the p-type dopant, annealing is performed at about 400 to 800 ° C. for about 10 to 60 minutes, a photoresist is applied to the entire surface, and patterning is performed by a photolithography process. Then, the portion to be etched (the periphery of the chip and the n-side electrode forming portion) of the semiconductor laminated portion 7 is exposed, and etching is performed, for example, by introducing chlorine gas and silicon tetrachloride gas and applying RF power. As a result, the periphery of the chip that is exposed without being covered with the mask and the semiconductor laminated portion 7 at the place where the n-side electrode 10 is formed are etched, and the n-type layer 3 is exposed.

その後、リフトオフ法により、前述のエッチングにより露出したn形層3の表面に0.01μm厚のTi膜と0.25μm厚のAl膜を形成し、600℃程度の熱処理をすることによりシンターして合金化し、n側電極10とする。また、光取出し層6上の一部に同様にリフトオフ法により、Ti膜を0.1μm厚、Au膜を0.3μm成膜してp側電極9を形成する。そしてチップ化することにより、図1に示される構造のLEDチップが形成される。   After that, by lift-off method, a 0.01 μm thick Ti film and a 0.25 μm thick Al film are formed on the surface of the n-type layer 3 exposed by the etching described above, and sintered by heat treatment at about 600 ° C. The n-side electrode 10 is formed by alloying. Similarly, a Ti film is formed to a thickness of 0.1 μm and an Au film is formed to a thickness of 0.3 μm on a part of the light extraction layer 6 by the lift-off method to form the p-side electrode 9. Then, by making the chip, the LED chip having the structure shown in FIG. 1 is formed.

このように製造した発光素子に電圧を印加して、その電圧を変化させることにより電流Iに対する輝度L(相対値)の変化Aを、光取出し層のない従来構造のものの同様の変化Bと対比して図3に示す。図3から明らかなように、通常の動作点である電流が20mAのときの出力で、本発明による発光素子では、従来構造のものと比べて、1.2〜1.5倍程度に向上している。   By applying a voltage to the light emitting device manufactured in this way and changing the voltage, the change A of the luminance L (relative value) with respect to the current I is compared with the same change B of the conventional structure without the light extraction layer. This is shown in FIG. As is apparent from FIG. 3, the light-emitting element according to the present invention is an output when the current, which is a normal operating point, is 20 mA. ing.

本発明によれば、半導体積層部の表面に凸部または凹部が形成されているため、発光した光が直接、または半導体積層部および基板内で全反射して表面側に来た光が外部に出やすくなり、図3に示されるように、外部量子効率が大幅に向上する。しかも、その凸部や凹部を形成するのに、ドライエッチングなどの半導体層にダメージを受ける加工を一切施す必要がないため、半導体層にダメージが加わることがなく、発光特性を低下させることがないと共に、長時間の使用に対しても非常に安定した特性を維持することができ、信頼性も大幅に向上する。さらに、半導体層の積層工程で、その成長条件を変えるだけで凸部や凹部を形成することができるため、ドライエッチングのような特別な工程を挟むことなく、また、半導体積層部の下層となるn形層を露出させるため、半導体層を積層するために用いた基板を除去する必要もなく、余計な工程を一切追加する必要がないため、非常に簡単な製造工程で得ることができる。その結果、非常に高性能で信頼性が高く、外部量子効率の高い窒化物半導体発光素子が非常に安価に得られる。   According to the present invention, since the convex portion or the concave portion is formed on the surface of the semiconductor laminated portion, the light that has been emitted is reflected directly or totally reflected within the semiconductor laminated portion and the substrate, and the light that has come to the surface side is exposed to the outside. As shown in FIG. 3, the external quantum efficiency is greatly improved. In addition, it is not necessary to perform any processing that damages the semiconductor layer, such as dry etching, in order to form the projections and recesses, so that the semiconductor layer is not damaged and the light emission characteristics are not deteriorated. At the same time, very stable characteristics can be maintained even after long-term use, and the reliability is greatly improved. Furthermore, in the semiconductor layer stacking process, convex portions and concave portions can be formed only by changing the growth conditions, so that it becomes a lower layer of the semiconductor stacked portion without interposing a special process such as dry etching. Since the n-type layer is exposed, it is not necessary to remove the substrate used for stacking the semiconductor layers, and it is not necessary to add any extra steps, so that it can be obtained by a very simple manufacturing process. As a result, a nitride semiconductor light emitting device with very high performance, high reliability, and high external quantum efficiency can be obtained at a very low cost.

なお、図1に示される例では、p形層である光取出し層6上に直接p側電極9が形成されていたが、図4に示されるように、たとえば0.1〜2μm程度以下の厚さのZnOもしくはITO、またはNiとAuとの2〜100nm程度の薄い合金層からなる透光性導電層8が設けられても、その表面の凸部6aまたは凹部6bを維持することができ、光取出し効率を上げながら、電流をチップの全体に拡散させる効果を奏する。すなわち、p形層5やp形の光取出し層6は、キャリア濃度を上げ難いため、p側電極9からの電流がチップ全体に広がり難いが、このような透光性導電層8が設けられることにより、電流をチップの全体に広げやすいため好ましい。具体的には、たとえばGaドープのZnO層をMBE、スパッタ、真空蒸着、PLD、イオンプレーティングなどの方法により、この凸部6aが形成された半導体積層部7上に、たとえば比抵抗を5×10-4Ω・cm程度としたZnOからなる透光性導電層8が0.1〜2μm程度、たとえば0.5μm程度設けることもできる。なお、凹部には埋まりやすいため、凹部の効果が多少落ちるが、凸部6aであれば、あまり厚くしない限り、その凸部6a上に沿って透光性導電層8が形成されるため、凸部の形状を維持することができる。 In the example shown in FIG. 1, the p-side electrode 9 is formed directly on the light extraction layer 6 that is a p-type layer. However, as shown in FIG. 4, for example, about 0.1 to 2 μm or less. Even if the light-transmitting conductive layer 8 made of ZnO or ITO having a thickness or a thin alloy layer of about 2 to 100 nm of Ni and Au is provided, the convex portion 6a or the concave portion 6b on the surface can be maintained. This has the effect of diffusing the current throughout the chip while increasing the light extraction efficiency. That is, since the p-type layer 5 and the p-type light extraction layer 6 are difficult to increase the carrier concentration, the current from the p-side electrode 9 is difficult to spread over the entire chip, but such a translucent conductive layer 8 is provided. This is preferable because the current can be easily spread over the entire chip. Specifically, for example, a Ga-doped ZnO layer is formed on the semiconductor laminated portion 7 on which the convex portions 6a are formed by a method such as MBE, sputtering, vacuum deposition, PLD, ion plating, etc. The translucent conductive layer 8 made of ZnO having a thickness of about 10 −4 Ω · cm can be provided on the order of 0.1 to 2 μm, for example, about 0.5 μm. Note that the effect of the recesses is somewhat reduced because the recesses tend to be buried. However, if the projections 6a are used, the translucent conductive layer 8 is formed along the projections 6a unless the projections 6a are too thick. The shape of the part can be maintained.

さらに、前述の各例では、基板として絶縁性基板であるサファイア基板の例であったため、n側電極10を形成するのに、半導体積層部7の一部をエッチングしてn形層3を露出させたが、基板がSiCのような半導体基板の場合でも、同様に半導体積層部7の表面に凸部または凹部を形成することができる。その例が、図5に示されている。この例では、基板が絶縁性基板ではなく、半導体であるため、半導体積層部の一部をエッチングにより除去して露出するn形層3に電極を形成するのではなく、半導体基板1の裏面にn側電極10が形成されているだけで、後は前述の例と同じである。   Further, in each of the above-described examples, since the substrate is an example of a sapphire substrate that is an insulating substrate, in order to form the n-side electrode 10, a part of the semiconductor stacked portion 7 is etched to expose the n-type layer 3. However, even when the substrate is a semiconductor substrate such as SiC, a convex portion or a concave portion can be similarly formed on the surface of the semiconductor laminated portion 7. An example is shown in FIG. In this example, since the substrate is not an insulating substrate but a semiconductor, an electrode is not formed on the n-type layer 3 exposed by removing a part of the semiconductor stacked portion by etching, but on the back surface of the semiconductor substrate 1. Only the n-side electrode 10 is formed, and the rest is the same as the above example.

すなわち、SiCからなる基板1上に、前述と同様に、低温バッファ層2、n形層3、活性層4、p形層5、p形の光取出し層6からなる半導体積層部7が形成されている。この場合、p側電極9はチップのほぼ中央部の光取出し層6の表面に前述の材料で形成され、n側電極10は、SiCからなる基板1裏面の全面に、たとえばNi膜を成膜することにより形成される。   That is, on the substrate 1 made of SiC, the semiconductor laminated portion 7 made of the low-temperature buffer layer 2, the n-type layer 3, the active layer 4, the p-type layer 5 and the p-type light extraction layer 6 is formed as described above. ing. In this case, the p-side electrode 9 is formed of the above-described material on the surface of the light extraction layer 6 in the substantially central portion of the chip, and the n-side electrode 10 is formed, for example, by depositing a Ni film on the entire back surface of the substrate 1 made of SiC. It is formed by doing.

本発明による半導体発光素子の一実施形態の斜視、部分および断面の説明図である。It is explanatory drawing of the perspective view of the one Embodiment of the semiconductor light-emitting device by this invention, a part, and a cross section. 凹部の例を示す図である。It is a figure which shows the example of a recessed part. 図1の構造の半導体発光素子における電流と輝度(相対値)の特性を従来の凹凸を有しない構造の同様の特性と対比して示した図である。It is the figure which showed the characteristic of the electric current and brightness | luminance (relative value) in the semiconductor light-emitting device of the structure of FIG. 1 contrasted with the same characteristic of the structure without the conventional unevenness | corrugation. 図1の光取出し層の表面に透光性導電層が形成された例を示す図である。It is a figure which shows the example in which the translucent conductive layer was formed in the surface of the light extraction layer of FIG. 基板にSiCを用いた図1と同様の例を示す断面説明図である。It is sectional explanatory drawing which shows the example similar to FIG. 1 which used SiC for the board | substrate. 従来の窒化物半導体を用いたLEDの斜視説明図である。It is perspective explanatory drawing of LED using the conventional nitride semiconductor.

符号の説明Explanation of symbols

1 基板
3 n形層
4 活性層
5 p形層
6 光取出し層
7 半導体積層部
8 透光性導電層
9 p側電極
10 n側電極
DESCRIPTION OF SYMBOLS 1 Substrate 3 N-type layer 4 Active layer 5 P-type layer 6 Light extraction layer 7 Semiconductor laminated portion 8 Translucent conductive layer 9 P-side electrode 10 N-side electrode

Claims (3)

基板と、窒化物半導体からなり基板側にn形層、上面側にp形層を有し、発光層を形成するように前記基板の一面上に設けられる半導体積層部と、該半導体積層部の前記p形層に電気的に接続して設けられるp側電極と、前記n形層に電気的に接続して設けられるn側電極とを具備する半導体発光素子であって、前記半導体積層部の最表面のp形半導体層が、{1−101}面の結晶面で形成される6角錐状の凸部または凹部を有するように形成されてなる半導体発光素子。   A semiconductor laminated portion made of a nitride semiconductor, having an n-type layer on the substrate side and a p-type layer on the upper surface side, and provided on one surface of the substrate so as to form a light emitting layer; A semiconductor light emitting device comprising a p-side electrode provided in electrical connection with the p-type layer and an n-side electrode provided in electrical connection with the n-type layer, wherein A semiconductor light emitting device in which the p-type semiconductor layer on the outermost surface has a hexagonal pyramid-shaped convex portion or concave portion formed by a {1-101} crystal plane. 前記凸部または凹部が形成されたp形半導体層上に透光性導電層が設けられてなる請求項1記載の半導体発光素子。   The semiconductor light emitting element according to claim 1, wherein a translucent conductive layer is provided on the p-type semiconductor layer on which the convex portion or the concave portion is formed. 基板上に窒化物半導体からなるn形層と活性層とp形層をこの順で発光層を形成するようにMOCVD法により積層すると共に、前記p形層の最表面の層を、基板温度を950〜1100℃から740〜900℃に下げ、かつ、導入するガスのV族元素のIII族元素に対する割合を6000〜8000から100〜5000に下げて成長することにより、前記p形層の表面に{1−101}面の結晶面で形成される6角錐状の凸部または凹部を形成することを特徴とする半導体発光素子の製法。   An n-type layer made of a nitride semiconductor, an active layer, and a p-type layer are stacked on the substrate by MOCVD so as to form a light emitting layer in this order, and the outermost layer of the p-type layer is set to a substrate temperature. The temperature is lowered from 950 to 1100 ° C. to 740 to 900 ° C., and the ratio of the introduced group V element to the group III element is lowered from 6000 to 8000 to 100 to 5000, thereby growing on the surface of the p-type layer. A method of manufacturing a semiconductor light emitting device, comprising forming a hexagonal pyramid-shaped convex portion or concave portion formed of a {1-101} crystal plane.
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JP2007150259A (en) * 2005-11-02 2007-06-14 Sharp Corp Nitride semiconductor light-emitting element, and method for manufacturing same
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