JP2006270372A - Locked-state determination circuit for digital pll - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a locked-state determination circuit capable of surely executing determination of a locked state of a digital PLL to which a signal with a longer inversion interval and a signal with a shorter inversion interval are inputted. <P>SOLUTION: An input signal of the PLL is inputted by a discrete value sampled by an output signal from a digital control oscillator 25. A voltage comparison means 311 detects whether or not a signal level of the discrete value obtained by the repetition of an oscillation frequency of the digital control oscillator 25 is in the range of the preset threshold. When detected by the voltage comparison means 311 that the detected voltage is out of the range of the threshold, a first positive number is assigned by a selector 312. When detected that it is in the range of the threshold, a second negative number is assigned by the selector 312. The assigned number is added and accumulated with an accumulation means 321. It is determined by a lock determination means 323 whether or not the PLL 2 is in the locked state corresponding to the magnitude of the accumulated number. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a digital PLL lock state determination circuit that is used together with a digital PLL (Phase Locked Loop) circuit and determines whether or not the PLL is locked to an input signal.

  Recently, an optical disk that converts an information signal such as a video signal or an audio signal into a digital signal, compresses and encodes it, and digitally modulates and records it on a medium has been introduced into the market. The reproduction of the optical disc is performed by reading the recorded digital modulation signal, extracting a clock signal for decoding the digital modulation signal, and using the extracted clock signal to demodulate and compress-encode the digital modulation signal. Decode the signal. That is, a signal reproduced from an optical disk is input to a digital PLL to generate a clock signal, and an information signal recorded using the clock signal is reproduced.

  If the lock detection circuit can quickly detect that the digital PLL is in synchronization with the input signal (locked state) or out of synchronization with the input signal (unlocked state), In some cases, the PLL loop gain is increased to increase the response speed for locking to the locked state, or in the locked state, the PLL loop gain is decreased to reduce the influence of interference caused by the input noise signal component. It is difficult to receive and a clock signal with a stable frequency can be obtained. An optical disc reproducing apparatus capable of starting reproduction of a recorded information signal in a short time or performing highly stable reproduction on a demodulation input signal obtained by reading from an optical disc containing a large amount of phase fluctuation components Can be realized.

FIG. 14 shows a configuration of a PLL and a lock / lock detector according to a conventional example, and the operation thereof will be described with reference to the drawings.
The PLL 8 shown in the figure includes a phase comparison circuit 81, a loop filter 82, a voltage control oscillator 83, a phase difference detection circuit 91, and a lock detection circuit 92. The lock detection unit 9 includes a phase difference detection circuit 91 and a lock detection circuit 92.

  First, an input signal including a noise component and a phase fluctuation component is supplied to one input terminal of each of the phase comparison circuit 81 and the phase difference detection circuit 91. An oscillation output oscillated by the voltage controlled oscillator 83 is supplied to the other input terminal of each of the phase comparison circuit 81 and the phase difference detection circuit 91. The phase comparison circuit 81 detects the phase difference between the input signal and the signal input from the voltage controlled oscillator 83, and outputs an error signal corresponding to the phase difference. The error signal is input to the loop filter 82, where the low frequency component of the error signal is enhanced by integration processing. The error signal with the enhanced low frequency component is input to the voltage controlled oscillator 83. The voltage controlled oscillator 83 oscillates at a frequency controlled according to the input error signal, and an oscillation output is obtained. The oscillation output is used to generate a clock signal for driving a digital modulation signal demodulating circuit, a compression coded signal decoding circuit, etc. (not shown).

  The phase difference detection circuit 91 detects the phase difference between the two input signals by synchronous detection. That is, when the PLL circuit is locked (synchronized) with the input signal, a phase error signal with a small level is output, but when the PLL circuit is not locked and there are many noise components and phase fluctuation components included in the input signal. Sometimes a large level phase error signal is output. The lock detection circuit 92 compares the magnitude of the absolute value of the phase error signal with a preset reference set value, and detects that the phase error signal is in an unlocked state when it is larger than the reference set value. An optical disk reproducing apparatus in which the PLL 8 and the lock detecting unit 9 are incorporated is configured to perform demodulation of a digital modulation signal reproduced based on a detected lock state signal and decode a compression-coded information signal. ing.

  Patent Document 1 discloses a technique for detecting PLL unlock by detecting that an average of a predetermined period of a phase error signal, which is an output of a phase comparator of a PLL, exceeds a predetermined set value. Yes. By detecting the unlocking of the PLL, it is possible to detect the instability of the phase synchronization of the PLL. The phase synchronization state of the PLL is detected, and when the instability is detected, the circuit operation of the error correction unit is stopped. As a result, a regenerator that reduces the power consumption of the circuit is realized.

Further, Patent Document 2 compares the phase error signal and the lock determination reference set value, and only when the number of times the phase error signal continuously falls below the determination reference set value exceeds the set number, the PLL is A lock detection method in a PLL lock circuit configured to output a phase error signal for determining that the lock state is established is disclosed.
JP 2002-35839 A Japanese Patent No. 3028955

  However, in the data reproduction method disclosed in Patent Document 1, even if the PLL is locked during reproduction of the optical disk, it is detected when a signal with a large phase variation is input, such as a signal with a short inversion interval. It cannot be distinguished whether a phase error signal with a large level is generated based on an input signal with a short inversion interval or because the PLL is in an unlocked state. In particular, it is difficult to distinguish when the input signal input to the PLL is attenuated by high frequencies due to the influence of the deterioration of the transfer characteristic that occurs between recording and reproduction. Further, when the PLL loop gain is increased so as to greatly compensate the attenuated high frequency component in order to change the PLL from the unlocked state to the locked state, the phase error signal detected by the phase difference detection circuit 91 is input. It is difficult to distinguish and judge whether it is caused based on the phase fluctuation of the signal to be generated or because the PLL is in the unlocked state.

  The detection of lock and unlock shown in the example of Patent Document 2 will be described for an input signal obtained by reproducing an optical disc. When reproducing an optical disc, an input signal with a long inversion interval is not easily affected by the deterioration of the transfer characteristic, so that the PLL can be easily locked and the locked state can be easily determined. However, in the case of an input signal with a short inversion interval, it is easy to be affected by high frequency degradation of the transfer characteristics, so that phase error is detected greatly by applying high frequency emphasis to compensate for high frequency degradation. Often, a phase error exceeding is detected. Signals with a short inversion interval are often included in random input signals. When a signal with a short inversion interval is continuously input, it may be erroneously determined that the PLL is unlocked although the PLL is locked. In other words, the PLL lock determination disclosed in Patent Document 2 often includes erroneous determination, so that the PLL lock determination cannot be performed accurately.

  Accordingly, the present invention has been made to solve the above-described problems. A signal having a short inversion interval including a large level of phase fluctuation component and a signal having a long inversion interval and a small phase fluctuation component are provided. Is connected to a digital PLL that generates an oscillation output signal that oscillates at a frequency that is phase-synchronized with a signal that is randomly mixed, so that the determination of the locked state and the unlocked state of the PLL can be quickly performed without error. An object of the present invention is to provide a lock state determination circuit for a digital PLL that can be performed in a simple manner.

According to a first aspect of the present invention, in the digital PLL lock state determination circuit for detecting whether or not the PLL circuit is locked, a reference signal for determining whether or not the predetermined PLL circuit is locked The phase error signal output from the PLL circuit is compared. When the reference signal is larger than the phase error signal, the signal “0” is output, and when the reference signal is smaller, the signal “1” is output. A selector that outputs a positive number when a signal “0” is input from the comparator and a negative number when a signal “1” is input from the comparator A limiter unit that limits an input positive / negative number between a predetermined upper limit value and a lower limit value, and a feedback unit that outputs a feedback signal that feeds back a number within a range limited by the limiter unit; Based on the feedback signal, an adder that adds and outputs one of positive and negative numbers output from the selector unit to a number within a range limited by the limiter unit fed back from the feedback unit; and A lock determination unit that determines a locked state when the integrated value of the number within the range limited by the limiter unit is positive, and determines an unlocked state when it is negative. A lock state determination circuit for a digital PLL is provided.
According to a second aspect of the present invention, there is provided a digital PLL lock state determination circuit for detecting whether or not a PLL circuit is locked, and a reference signal for determining whether or not the predetermined PLL circuit is locked and the PLL circuit A comparator that outputs a signal “0” when the reference signal is larger than the phase error signal and outputs a signal “1” when the reference signal is smaller than the phase error signal output from A selector that outputs a positive number when a signal “0” is input from the comparator, and a negative number when a signal “1” is input from the comparator; A limiter unit that limits an input positive / negative number between a predetermined upper limit value and a lower limit value; a feedback unit that outputs a feedback signal that feeds back a number within a range limited by the limiter unit; An adder for adding one of positive and negative numbers output from the selector unit to a number within a range limited by the limiter unit fed back from the feedback unit based on the feedback signal, and the addition A lock determining unit that determines that the integrated value of the positive and negative values added by the device is positive, and determines that the integrated state is unlocked when the negative integrated value is negative. A lock state determination circuit for a digital PLL is provided.
A third invention is the digital PLL lock state determination circuit according to the first or second invention, wherein the absolute value of the positive number output from the selector unit is greater than the absolute value of the negative number. And a digital PLL lock state determination circuit characterized in that the number is a small number.

According to the present invention, a reference signal for determining whether or not a predetermined PLL circuit is locked is compared with a phase error signal output from the PLL circuit, and the reference signal is compared to the phase error signal. When the signal is large, the signal “0” is output. When the signal is small, the comparator outputs the signal “1”. When the signal “0” is input from the comparator, a positive number is output. When a signal “1” is input from the comparator, a selector unit that outputs a negative number, and a limiter that limits the input positive / negative number between a predetermined upper limit value and a lower limit value. A feedback unit that outputs a feedback signal that feeds back a number within the range limited by the limiter unit, and a range within the range limited by the limiter unit fed back from the feedback unit based on the feedback signal. To number If the adder that adds and outputs any of the positive and negative numbers output from the selector unit and the integrated value of the number within the range limited by the limiter unit are positive, it is determined as a locked state. If negative, there is a lock determination unit that determines an unlocked state, so that a signal with a short inversion interval including a large level phase fluctuation component and a signal with a long inversion interval and a small phase fluctuation component Is connected to a digital PLL that generates an oscillation output signal that oscillates at a frequency that is phase-synchronized with a signal that is randomly mixed, so that the determination of the locked state and the unlocked state of the PLL can be quickly performed without error. It is possible to realize a digital PLL lock state determination circuit that can be performed in a short time.
In addition, when the absolute value of the positive number output from the selector unit is set to a number smaller than the absolute value of the negative number, the determination of unlocking can be performed more quickly even after the locked state continues for a long time. Thus, a digital PLL lock state determination circuit can be realized.

A digital PLL (Phase Locked Loop) lock state determination circuit according to an embodiment of the present invention will be described below with reference to FIGS.
FIG. 1 is a block diagram illustrating a configuration example of a digital PLL device equipped with a lock state determination unit according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration example of a main part of the digital PLL according to the embodiment of the present invention.
FIG. 3 is a diagram illustrating an operation example of the digital PLL according to the embodiment of the present invention.
FIG. 4 is a diagram illustrating an operation example of the digital PLL according to the embodiment of the present invention.
FIG. 5 is a diagram illustrating an operation example of the digital PLL according to the embodiment of the present invention.
FIG. 6 is a diagram illustrating an operation example of the digital PLL according to the embodiment of the present invention.
FIG. 7 is a diagram showing an example of waveforms input to the digital PLL according to the embodiment of the present invention.
FIG. 8 is a diagram for explaining the operation of the lock state determination unit according to the embodiment of the present invention.
FIG. 9 is a diagram illustrating a configuration example of a main part of the lock state determination unit according to the embodiment of the present invention.
FIG. 10 is a diagram showing a modified configuration example of the digital PLL according to the embodiment of the present invention.
FIG. 11 is a diagram illustrating a modified configuration example of the lock state determination unit according to the embodiment of the present invention.
FIG. 12 is a diagram illustrating an operation of the lock state determination unit configured to be modified according to the embodiment of the present invention.
FIG. 13 is a diagram illustrating a change example of the integrated weighting signal according to the embodiment of the present invention.

  The digital PLL lock state determination circuit unit converts a signal having a short inversion interval including a phase fluctuation component of a large level and a signal that is a random mixture of a signal having a long inversion interval and a small phase fluctuation component. Connected to a digital PLL that generates an oscillation output signal that oscillates at a phase-synchronized frequency, so that the lock state of the digital PLL can be quickly determined without errors in the lock state of the PLL. For the purpose of realizing the circuit, a reference signal for determining whether or not a predetermined PLL circuit is locked is compared with a phase error signal output from the PLL circuit, and the reference signal is the phase error signal. Is greater than the output of the signal “0”, and if smaller, the comparator outputs the signal “1” and the signal “1” is output from the comparator. ”Is input, a positive number is output. When a signal“ 1 ”is input from the comparator, a selector that outputs a negative number and a positive / negative number to be input are set in advance. A limiter unit that limits between a predetermined upper limit value and a lower limit value; a feedback unit that outputs a feedback signal that feeds back a number within a range limited by the limiter unit; and the feedback unit based on the feedback signal An adder that adds one of positive and negative numbers output from the selector unit to the number within the range limited by the limiter unit fed back from the limiter unit, and a number within the range limited by the limiter unit When the integrated value is positive, the lock state is determined, and when the negative integrated value is negative, the lock determination unit is determined to determine the unlocked state.

The configuration of a digital PLL device equipped with a lock state determination circuit unit will be described.
A digital PLL device equipped with a lock state determination circuit unit shown in FIG. 1 includes an input circuit unit 1 including an analog-to-digital (A / D) converter 11 and a clock signal generator 12, a phase comparator 23, and a loop filter 24. The digital PLL 2 is composed of a digitally controlled oscillator 25, and the lock state determination circuit unit 3 is composed of a lock determination unit 32 in which positive and negative numbers inputted to the weighting allocator are predetermined.
The phase comparator 23 of the digital PLL 2 shown in FIG. 2 includes a sampling point interpolation circuit 23a, a zero cross detection circuit 23b, and a phase difference detection circuit 23c.
The lock state determination circuit unit 3 shown in FIG. 9 includes a weighted assigner 31 including a predetermined number of positive and negative inputs to the comparison circuit and a selector 312, an adder circuit 321, a limiter 322, a flip-flop (FF) 323, And a lock determination unit 32 including an unlock determination unit 329.
10 includes a zero-cross detection circuit 22b, a phase difference detection circuit 22c, a loop filter 24, a D / A (digital-to-analog) converter 27, and a voltage-controlled oscillator 28.
The lock determination unit 32a illustrated in FIG. 11 includes more flip-flops 324, a selector 325, an AND gate 326, a counter 327, and a comparison circuit 328 than the lock determination unit 32 illustrated in FIG. Instead of the unlock determination circuit 329, an unlock determination circuit 329a is provided.

The operation of the digital PLL device with the lock state determination circuit section will be described.
The input circuit unit 1, the digital PLL 2, and the lock state determination circuit unit 3 will be described with reference to FIG.
First, an input signal having a long inversion interval and an input signal having a short inversion interval and including a phase variation component obtained by reproducing an optical disc (not shown) are input to the A / D converter 11 of the input circuit unit 1. In the A / D converter 11, the input signal is sampled at the timing of the clock signal output from the clock signal generator 12, and a digitized input signal is obtained. The phase comparator 23 of the digital PLL 2 receives a digital input signal and interpolation phase information (described later) related to the digitally controlled oscillation frequency input from the digitally controlled oscillator 25, and the digital input signal is resampled later. Based on the value of the sample point obtained by the resampling, an error signal related to the phase error between the digital input signal and the digitally controlled oscillation frequency is generated. The loop filter 24 removes the high frequency component of the error signal. The digitally controlled oscillator 25 generates interpolation phase information related to the digitally controlled oscillation frequency in accordance with the error signal from which the high frequency component has been removed.

  The phase comparator 23 outputs a phase error signal related to the locked state in accordance with the phase difference between the phase of the digital input signal and the interpolation phase information related to the digitally controlled oscillation frequency. The phase error signal related to the lock state is input to the weighting assigner 31 of the lock state determination circuit unit 3. The phase error signal related to the lock state is output as a signal having a small voltage when the digital PLL 2 is in a lock state with respect to an input signal having a long inversion interval. When the digital PLL 2 is not in the locked state, it is output as a large voltage signal. On the other hand, for an input signal having a short inversion interval, a signal with a larger voltage is output when the digital PLL 2 is not in the locked state than when the digital PLL 2 is in the locked state, but the phase error signal when the digital PLL 2 is in the locked state. And the voltage difference between the phase error signal when not in the locked state is small. That is, the phase error signal is likely to contain an error in the determination between the locked state and the unlocked state of the input signal when the inversion interval is short. Further, when the input signal includes many phase fluctuation components, a phase error signal having a large voltage may be output even when the digital PLL 2 is in a locked state. The lock state determination circuit unit 3 can accurately determine the lock state of the digital PLL 2 by performing predetermined signal processing on the phase error signal.

  First, when the digital PLL 2 is in the locked state, that is, when a phase error signal of a predetermined value or less is detected, the weighting assigner 31 of the lock state determination circuit unit 3 outputs a weighting signal of +1, for example. When the phase error signal is detected as a voltage exceeding a predetermined value and not in the locked state, a weighting signal of −2 is output. The lock determination unit 32 adds weighted signals that are sequentially input. The weighting signal obtained by the sequential addition is limited to a predetermined value so that the added weighting signal does not become too large. For example, the addition value is limited so as not to exceed 5. The lock determiner 32 determines that the digital PLL 2 is in the locked state when the added value is positive, and determines that it is in the unlocked state when the added value becomes negative. When it is determined that the digital PLL 2 is in the locked state, a clock signal is generated based on the interpolation phase information output from the digital control oscillator 25, and the digital modulation reproduced from the optical disk (not shown) using the clock signal. Demodulate the signal.

  As described above, since the synchronization state of the digital PLL 2 can be determined by the lock state determination circuit unit 3 in a predetermined time, the PLL loop gain is increased in the unlocked state to increase the response speed for locking, By reducing the loop gain of the PLL, the flywheel effect is increased, and it is possible to obtain a clock signal with a stable frequency that is not easily disturbed by the input phase fluctuation component and noise signal component. Accordingly, it is possible to realize an optical disc reproducing apparatus that can start reproduction of a recorded information signal in a short time and continuously perform high-quality decoding operation after the reproduction is started.

The digital PLL 2 will be described in detail with reference to FIG.
First, the digital input signal converted into a digital signal by the input circuit unit 1 is input to the sampling point interpolation circuit 23 a of the phase comparator 23. The sampling clock related to the frequency oscillated by the digitally controlled oscillator 25 is not synchronized with the frequency sampled by the A / D converter 11. In the sampling point interpolation circuit 23a, the resampling calculation is performed based on the above-described interpolation phase information related to the oscillation frequency output from the digital control oscillator 25. The resampling operation is performed when sampling data obtained by A / D conversion using the clock signal input from the clock signal generator 12 is sampled at the oscillation frequency output from the digital control oscillator 25. This is an operation for obtaining a sampling value. That is, the resampling value is obtained using the interpolation phase information relating to the phase difference of the output signal of the digital control oscillator 25 with respect to the output signal of the clock signal generator 12. There are two methods for obtaining the resampling value: a method using linear interpolation and a method using high-order interpolation. High-order interpolation includes a method of obtaining an approximate value using a high-order function, a method of performing a combination of a sinX / x interpolation function and a window function.

  The interpolation phase information indicates how much the phase of the oscillation frequency oscillated by the digital control oscillator 25 differs from the phase of the clock generated by the clock signal generator 12 and operating the A / D converter 11. It is information which shows. The digitally controlled oscillator 25 is a virtual oscillator, and outputs information relating to the phase difference between the oscillation frequency and the signal generated by the clock signal generator 12 as interpolation phase information. The phase comparator 23 of the digital PLL 2 calculates a phase error from the input signal input from the input circuit unit 1 based on the input interpolation phase information. The digital PLL 2 performs an operation in which the oscillation frequency of the virtual oscillator is phase-synchronized with the input signal.

FIG. 3 shows the phase relationship of signals related to resampling performed by the signal sampled by the A / D converter 11 at the oscillation frequency output from the digital control oscillator 25.
In the figure, the horizontal direction is the time axis, and the signal amplitude is shown in the vertical direction. The discrete data sampled by the A / D converter 11 is indicated by white circles (◯). Data indicated by black circles (● marks) is discrete data (sample values) obtained by resampling based on the interpolation phase information output from the digitally controlled oscillator 25 by the sampling point interpolation circuit 23a.

  The zero cross detection circuit 23b detects a zero cross state of the resampled input signal. There, there is a sample value at which the waveform of the input voltage crosses the zero level, and if there is a sample value that crosses the zero level, the value of the zero cross sample point (zero cross level value) is detected. When the PLL is in a stable locked state, a sample point with a level of zero can be detected as a zero cross sample point. In the actual detection of the zero-cross sample point, as described later, the zero-cross sample point is determined from two sample points before and after the signal polarity of the sample point changes.

  FIG. 4 shows discrete value data obtained by resampling at a time position based on the interpolation phase information output from the digital control oscillator 25 of the digital PLL 2 in the locked state. Among the plurality of resampled discrete value data, there is discrete value data that exists at the zero-cross position. This is because the oscillation frequency position of the digital control oscillator 25 of the digital PLL 2 in the locked state is phase-controlled so that the discrete value data is at the zero cross position. This is a case where the voltage at the zero-cross sample point detected by the zero-cross detection circuit 23b is detected as “0”.

  The resampled discrete values shown in FIG. 5 are discrete value data in the case of phase synchronization including a phase error. In this case, the absolute value of the signal level B of the discrete value data b on the left side (past) of the zero-cross position and the right side (future) of the zero-cross position among the discrete value data in which the polarity of the signal at the sample point changes. The absolute value of the signal level A of the discrete value data a is compared, and the smaller discrete value data a is set as the zero cross point. The voltage at the zero cross sample point is detected as A.

  The resampled discrete values shown in FIG. 6 are discrete value data when a large phase fluctuation component is input and a phase error is included. This is a case where the resampling position relating to the oscillation frequency of the digitally controlled oscillator 25 does not include the zero cross sample position. In that case, the points indicated by Δ in the figure are regarded as zero cross points. That is, the points indicated by Δ are the midpoints of the two points before and after the change in the polarity of the data, and the midpoint is regarded as the zero cross point and the zero cross sample position and the zero cross level are specified.

  In the phase difference detection circuit 23c, the time position of the zero cross obtained based on the voltage value of the input zero cross sample point and the time position of the interpolated phase information related to the oscillation frequency input from the digital control oscillator 25 are compared. The An error signal is generated according to the phase difference which is a time position shift. The error signal is supplied to the loop filter 24, where the low frequency components are integrated based on the loop characteristics of the PLL that can pull in the frequency, and is generated as an enhanced control signal of the low frequency signal.

  The error signal filtered for the PLL loop characteristic is input to the digitally controlled oscillator 25. The digital control oscillator 25 obtains interpolation phase information related to the oscillation output oscillated at a frequency corresponding to the input signal, and outputs the interpolation phase information.

  Here, in the case of the method shown in FIG. 5 described above, which of the two points where the polarity of the discrete value data has changed is the zero cross point is not after the absolute values of the two discrete values are compared. It cannot be detected. In the case of FIG. 6, since the midpoint of the two points is simply detected as the zero cross point, it is preferable because the phase fluctuation information at the zero cross point can be detected in a short time. In the digital PLL 2 that is operated using the midpoint value, the level of the error signal is also reduced, so that the phase synchronization operation with the increased flywheel effect is continued. However, the digital PLL 2 in this case is different from the operation that is phase-synchronized with the actually input signal. It is preferable to obtain a large level phase error signal. Here, as a phase error signal input to the lock state determination circuit unit 3, there are a method using a discrete value at a midpoint between two points before and after the polarity change and a method using a discrete value at a position away from the zero level. . In the method using a discrete value at a position away from the zero level, the absolute values of the two discrete values are similar values, and any of the discrete values may be input to the lock state determination circuit unit 3. Regardless of which discrete value is used, it is possible to increase the detection sensitivity of the unlocked state when the digital PLL 2 transitions from the locked state to the unlocked state.

  The waveform shown in FIG. 7 is an example of a digitally modulated waveform diagram obtained by reproducing an optical disc. The digitally modulated signal is composed of signal components whose inversion intervals with respect to time T are 3T to 11T. The signal level with the shortest inversion interval is 2 div. The level of a signal having a long inversion interval is 6 div.P-P. The level of the high frequency component is smaller than the level of the low frequency component. This signal is a signal in which a high frequency component is somewhat enhanced in order to lock the PLL, and is input to the input circuit unit 1 to operate the digital PLL 2. The waveform diagram shows that the high frequency components contain many signal components with large phase fluctuations under the influence of the deterioration of the transfer characteristics.

  Of the black circles (● marks) shown in the figure, the central black circle indicates a zero cross point. Each black circle (● mark) on the left and right of the zero cross point is a past and future adjacent sample point. The up and down arrows shown together with the black circle of the zero cross point schematically indicate that the zero cross point is generated by shifting up and down due to a zero cross error.

  FIG. 8 shows a characteristic example of the level (vertical axis) of the phase error signal with respect to the inversion interval (horizontal axis) of the input signal. This shows the level of the phase error signal when the digital PLL 2 is in the locked state and in the unlocked state when the inversion interval of the input signal is 3T to 11T. As shown in FIG. 4, when the digital PLL 2 is in the locked state, the level of the sample value at the zero cross sampling point is zero. Here, the signal level given by the sampling point adjacent to the zero cross point is defined as the maximum amplitude value. The maximum amplitude value is defined as 100% jitter. FIG. 8 is a graph showing the zero cross error (amplitude value) at each inversion interval as a ratio to 100% jitter.

  The bar graph shown at the bottom of FIG. 8 indicates the level of the phase error signal when the digital PLL 2 is in the locked state. The level indicates a value distributed with a probability of 90% among the level values observed in a varying manner. A black circle (● mark) and a dotted line shown in the upper part of FIG. 8 indicate the level of the maximum value of the phase error signal given when the digital PLL 2 is unlocked. A white triangle (Δ mark) shown in FIG. 8 is an average zero cross error given when the digital PLL 2 is unlocked. Since the phase error signal is detected based on the value of the sample point adjacent to the zero cross sample point, the average value is almost half of the maximum value. In the case of an input signal with a short inversion interval, the signal in the vicinity of the zero cross is not a straight line but close to a sine wave, and thus becomes a value slightly larger than half of the maximum value. As can be seen from FIG. 8, in the case of an input signal with a short inversion interval, the phase error signal level in the locked state is higher and the phase error signal level in the unlock state is lower than that of the input signal with a long inversion interval. . Therefore, it is difficult to determine the locked state and the unlocked state.

  When the 25% point is used as the lock determination criterion as the jitter converted value of the phase error signal level, the lock state and the unlock state can be determined on average, but a determination error is likely to be included. In the case where a point with a jitter converted value of 30% is used as a determination criterion, a determination with little error is made for an input signal whose inversion interval is, for example, 5T or more. However, for a short input signal with a determination interval of 3T, the average value when the PLL is unlocked is below this reference, so that it is erroneously determined as “locked”.

  The use of the characteristics indicated by the white triangles in the determination corresponds to the case where the weighting for the phase error signal in the locked state and the unlocked state is set to 1: 1. When the weight ratio between the locked state and the unlocked state is 1: 1, a margin of less than 3% can be ensured when the jitter conversion value of the best criterion is 25% point. The signal reproduced from the optical disc has a different high-frequency attenuation state depending on the state of the disc. A reproduction signal having a short inversion interval and containing a lot of high frequency components is affected by the deterioration of the transfer characteristics, so that the level of the phase error signal is likely to fluctuate and erroneous determination is likely to occur.

Next, a case where the weighting for the phase error signal in the locked state and the unlocked state is set to 1: 2.
A curve indicated by a white circle (◯ mark) in FIG. 8 is a value of the weighting voltage that the digital PLL 2 gives in the unlocked state when the weighting is set to 1: 2. In the case of the inversion interval 3T, a margin of 7% or more is obtained even when the determination criterion is set to a jitter conversion value of 30%. By setting a large weight in the unlocked state, it is possible to set a determination criterion that secures a margin against fluctuations in the high frequency reproduction level of the input signal.

  Although the weighting can be set to a larger ratio of 1: 3 or more, the level of the phase error signal when the digital PLL 2 is in the locked state is also distributed to the upper part of the bar graph. Increasing cases of misjudgment of being locked.

The lock state determination circuit unit 3 will be described with reference to FIG.
The value of the discrete value data (which is also a signal giving a phase error) at the zero-cross sample point detected by the zero-cross detection circuit 23b is input to the terminal A of the comparison circuit 311 of the weighting allocator 31 of the lock state determination circuit 3. . A reference value relating to a determination criterion for the locked state and the unlocked state is input to the terminal B. The comparator 311 compares the values input to the respective terminals A and B. When the value input to the terminal B is large, the signal “0” is displayed. When the value input to B is small, the signal “1” is output. Is output. The result obtained by the comparison is input to the selector 312.

  In the selector 312, + N (N is a positive number, for example, 1) when the input signal is “0”, and −M (−M is a negative number, for example −2) when the input signal is “1”. Weighting signals are generated. The weighting signal is input to the input terminal A of the adder 321 of the lock determination unit 32. The integrated value of the weighting signal obtained by adding the past weighting signals output from the flip-flop 323 is input to the input terminal B of the adder 321. The adder circuit 321 adds the currently input weighting signal and the integrated value obtained by adding a plurality of previously input weighting signals to obtain a new integrated weighting signal.

  In the limiter 322, when the absolute value of the integrated weight signal exceeds 31, for example, the absolute value of the integrated weight signal is limited to 31. In the flip-flop 323, the integrated weighting signal whose value is limited is input to the D terminal. When an enable signal (zero cross detection signal) is supplied to the enable terminal (EN), a signal input to the D terminal is output to the Q terminal. That is, each time the zero cross detection circuit 23b detects that the input signal has a sample value that crosses the zero level, an integration weighting signal is output to the Q terminal. The unlock determination circuit 329 receives an integrated weighting signal within a limited voltage range. When the polarity of the integrated weighting signal is positive, it is determined that the digital PLL2 is in the locked state, and when the polarity of the integrated weighting signal is detected as negative, it is determined that the digital PLL2 is in the unlocked state.

  Here, the determination of the locked state and the unlocked state is made based on the polarity of the integrated weighting signal operated within a limited range of values. If the amplitude value of the integrated weight signal is not limited, the value of the integrated weight signal increases when the locked state or unlocked state continues for a long time. By limiting the value range of the integrated weighting signal, a change from the unlocked state to the locked state or from the locked state to the unlocked state can be detected with a small number of additions. The detection accurately detects the locked state and the unlocked state, and when the transition is made from the locked state to the unlocked state or from the unlocked state to the locked state, the transition of the state can be detected in a short time. Further, overflow of signals handled by the adder circuit 321 and the flip-flop 323 can be prevented.

Although the positive number and the negative number output from the selector 312 are described as integers, the positive number and the negative number may be decimal values.
Further, it has been described that the lock determination unit 32 determines the locked state and the unlocked state based on the polarity of the signal output from the limiter 322. The determination can be made in the same manner by determining the polarity of the signal output from the adder circuit 321 at the time of zero-cross input. A similar operation can be performed by inserting a limiter 322 inserted between the adder circuit 321 and the flip-flop 323 between the output terminal of the flip-flop 323 and the input terminal B of the adder circuit 321.

  Further, instead of determining based on the polarity of the signal, a threshold value is set, and the locked state and the unlocked state are determined depending on whether the signal output from the adder circuit 321 or the limiter 322 is equal to or greater than the threshold value. I can do it. In that case, either the locked state or the unlocked state can be detected quickly by changing the threshold level.

Further, the operation of the lock state determination can be performed in the same manner by using the opposite sign to the sign of the number of weighting results performed based on the state output from the comparator 311.
Further, although the signal error at the zero cross point is used as the phase error signal obtained by the phase comparison in the above, the phase amount may be calculated and used based on the values of the preceding and following sample points. The same applies to the phase error signal used in lock detection.

With reference to FIG. 10, a modified PLL and a lock state determination circuit connected to the PLL will be described with respect to differences from the digital PLL 2 shown in FIG.
The PLL 2a shown in the figure is different from the digital PLL 2 shown in FIG. 2 in that the sampling point interpolation circuit 23a is not provided. That is, a signal that is A / D converted by a bit clock signal obtained by oscillating by the voltage controlled oscillator 28 is input to the PLL 2a as a digital input signal. Data resampled with the PLL clock shown in FIG. 3 is input as a digital input signal.

  The zero-cross detection circuit 22b receives a digital input signal and an analog oscillation output signal obtained by oscillating by the voltage controlled oscillator 28. The zero cross detection circuit 22b outputs a similar signal when it is output from the zero cross detection circuit 23b. The phase difference detection circuit 22c receives the output signal of the zero cross detection circuit 22b and the analog oscillation output signal, and outputs a signal similar to the signal output from the phase difference detection circuit 23c. The signal output from the loop filter 24 and from which the high frequency component has been removed is converted into an analog signal by the D / A converter 27. From the voltage controlled oscillator 28, an oscillation output signal oscillated at a frequency corresponding to the level of the error signal converted into analog is output.

The above is the case where the PLL 2a is configured using the voltage controlled oscillator 28 that operates with an analog signal.
The loop filter 24 is constituted by a digital circuit. However, when the loop filter 24 is constituted by an analog circuit, the analog loop filter may be installed after the D / A converter 27.
Which method is used to configure the digital PLL is a matter of design.

With reference to FIG. 11, an application example of the lock determination device 32 used in the lock state determination circuit unit 3 will be described with respect to parts different from the lock determination device 32 shown in FIG. 9.
The lock determination unit 32 shown in FIG. 9 is set in advance as compared with the case where the lock determination of the weighting signal output from the weighting assigner 31 is continuously operated. The difference is that the operation of lock determination is performed while being initialized every predetermined number of times for each cumulative set number of times.

  For example, when the cumulative number is set to 128 (0 to 127), 127 is input to the input terminal B of the comparison circuit 328. The counter 327 increments the count by one each time there is a zero cross input signal detected by the zero cross detection circuit 23b at the EN terminal. The count number incremented by one is compared with 127 input to the terminal B by the comparison circuit 328. When the count number is less than 127, “0” is output from the comparison circuit 328 and the count for each zero-cross input signal is continued. When the count number reaches 127, “1” is output from the comparison circuit 328. The AND gate 326 outputs a signal “1” when the signal input from the comparison circuit 328 is “1” and the zero-cross input signal is “1”.

  The count number of the counter 327 is cleared to “0” by “1” output from the AND gate 326. The counter 327 starts counting the zero-cross input signal, and “1” output from the AND gate 326 is input to the selector 325 and the EN terminal of the flip-flop 324. From the Q terminal of the flip-flop 324, the integrated weighting signal input to the D terminal immediately before the data is cleared is output. In the unlock determination circuit 329a, the locked state or the unlocked state is determined according to the polarity of the signal output to the Q terminal of the flip-flop 324, and according to the level of the signal output to the Q terminal of the flip-flop 324. Then, a soft decision is made to determine the degree related to the unlocked state.

  When the signal input from the AND gate 326 to the selector 325 is “0”, the circuit composed of the adder circuit 321, the limiter 322, the flip-flop 323, and the selector 325 is the same as the circuit shown in FIG. A similar operation is performed. That is, when the signal input to the selector 325 is “0”, the integration weighting signal output from the terminal Q of the flip-flop 323 is selected and input to the terminal B of the adder circuit 321.

  When the signal input to the selector 325 from the AND gate 326 is “1”, the data “0” input to the input terminal 1 is selected by the selector 325. The data “0” is input to the terminal B of the adder circuit 321. When the data “0” is input to the terminal B, the above integrated weighting signal is changed to data “0”. That is, it is reset. Then, calculation of a new integrated weight signal is started.

With reference to FIG. 12, the signal flow of the modified lock state determination unit will be described.
(A) shown in the figure shows the waveform of the zero cross detection signal output from the zero cross detection circuit 23b, that is, the detection signal of the zero cross sample point. The lock determiner 32a operates in synchronization with the change of the zero cross detection signal. The counter 327 counts the zero cross detection signal. The comparison circuit 328 detects whether or not the count value is equal to or greater than a set cumulative number value. When it is detected that the count value A is 127 or more, which is the cumulative number value, an A ≧ B comparison output shown in (c) is output.

(D) is a weighting signal W that is sequentially output from the selector 312 of the weighting assigner 31. A subscript attached to W is a count value counted by the counter 327. The integration weight signal shown in (e) is an integration weight signal value output from the flip-flop 323. Σ ₁₂₇ indicates the value of the integrated weighting signal when the count value is 127.
When A ≧ B comparison output is input to the AND gate 326 and (a) the zero cross detection signal is input, Σ ₁₂₇ is replaced with data “0” output from the selector 325. Σ ₀ next to Σ ₁₂₇ is W ₀ obtained by adding the weighting signal W ₀ to the data “0”. Later, Σ ₁ is W ₀ + W _1, Σ ₂ is _{W 0 + W 1 + W 2} , sequentially obtained until Σ ₁₂₇ as ....
(F) shows the integrated weighting signal output from the flip-flop 324. Integrated weighting signal sigma ₁₂₇ at the time the counter output is cleared, is output as a current cumulative weighted signal sigma _127, its output is maintained until the counter output is cleared at the next.

The integrated weighting signal will be described with reference to FIG.
The horizontal axis is the count value of the counter 327, and the vertical axis is the value of the integrated weighting signal.
The counter 327 repeats counting from 0 to 127. The value of the integrated weighting signal is limited to a value of −31 to +31 by the limiter 322.
(1) shown in the figure is the value of the integrated weighting signal when the digital PLL 2 is in the locked state. The selector 312 selects + N = 1, and the integrated weighting signal is incremented by one each time a zero cross detection signal is generated. When the count value is 31, the integrated weighting signal is 31. Thereafter, the upper limit of the integrated weighting signal is limited to 31.
(2) shows the value of the integrated weighting signal when the digital PLL 2 is in the unlocked state. -M = -2 is selected by the selector 312, and the integrated weighting signal decreases by two each time a zero-cross detection signal is generated. The cumulative weighting signal is limited to -31 after the count number of 15.

  (3a) shows a change in the integrated weighting signal when the digital PLL 2 repeats the locked state and the unlocked state. The slope of the change in the locked state is parallel to the first part of (1), and the slope of the change in the unlocked state is parallel to the first part of (2). The broken line (3a) continues until the count value 127. (3c) is the value of the integrated weighting signal obtained when the count value is 127, and the value is output from the flip-flop 324.

  Compared with the unlock determination circuit 329 illustrated in FIG. 9, the unlock determination circuit 329 a performs an operation of determining the lock state and the unlock state according to the polarity of the value of the integrated weighting signal output from the flip-flop 324. In addition, the lock state of the digital PLL 2 is softly determined based on the value of the integrated weighting signal that is output. By clearing the accumulated value to 0 each time the accumulation count is reached, the influence of the accumulated weighting signal accumulated in the past is made less likely to be affected, and the determination of the lock state of the digital PLL 2 is made according to the value of the accumulated weighting signal, that is, unlocking. This can be done according to the frequency of occurrence of the condition.

  The lock determination unit 32a obtains the value of the integrated weighting signal for each set count of the counter as a lock determination result according to the frequency of occurrence of the unlocked state. Based on the obtained result, for example, the PLL loop gain in the unlocked state Increases the response speed for locking by increasing the value, or decreases the loop gain of the PLL in the locked state to set operating parameters to obtain a clock signal with a stable frequency for the input noise signal component Can be appropriately performed according to the lock state of the digital PLL 2 that is softly determined at each time point.

As described above, in this embodiment, the PLL lock operation and the unlock operation are weighted differently as compared with the conventional PLL lock determination based on a simple average value or simple 1: 1 weighting. In the lock state determination method, detection times when the operation of the PLL changes from the locked state to the unlocked state or from the unlocked state to the locked state can be individually set. Depending on the determination result of the lock state, a hold process of the adaptive equalization circuit operation in the demodulation operation of the recording signal (not shown), a command to move to the interpolation process of the information signal obtained by demodulation, etc. can be given to the demodulation circuit, etc. It can be used as a signal for performing playback control of an optical disc, and a suitable optical disc playback apparatus can be realized.
Furthermore, if the input signal contains a lot of phase errors and both of the discrete data sandwiching the zero cross are separated from the zero cross point, the midpoint of both discrete data is interpolated and regarded as the zero cross point, and the digital PLL Continue phase synchronization. In this case, the detection sensitivity of the unlocked state of the digital PLL 2 can be increased if the phase error signal is obtained using discrete data that is distant from the zero cross point.

  According to the digital PLL lock state determination circuit shown in the embodiment, a reference signal for determining whether or not a predetermined PLL circuit 2 is locked is compared with a phase error signal output from the PLL circuit 2. When the reference signal is larger than the phase error signal, the signal “0” is output. When the reference signal is smaller, the comparator 311 that outputs the signal “1” and the signal “0” from the comparator 311 are output. ”Is input, a positive number is output, and when the signal“ 1 ”is input from the comparator, a selector unit 312 that outputs a negative number and the input positive / negative number are A limiter unit 322 that limits between a predetermined upper limit value and a lower limit value; a feedback unit 323 that outputs a feedback signal that feeds back a number within the range limited by the limiter unit 322; and the feedback signal An adder 321 for adding one of the positive and negative numbers output from the selector unit 312 to the number within the range limited by the limiter unit fed back from the feedback unit 323, and the limiter; If the integrated value of the number within the range limited by the unit 322 is positive, it is determined to be in the locked state, and if it is negative, there is a lock determining unit 329 that determines to be in the unlocked state. Generates an oscillation output signal that oscillates at a frequency that is phase-synchronized with a signal that is mixed with a signal that has a short inversion interval including a level phase error component and a signal that has a long inversion interval and a small phase error component The digital PLL lock is connected to the digital PLL, and the lock state of the PLL can be determined without error and the determination of the lock state and the unlock state can be performed quickly. State determination circuit can be realized.

  Further, when the absolute value of the positive number output from the selector unit 312 is set to a number smaller than the absolute value of the negative number, it is further determined whether the lock is released even after the lock state continues for a long time. It is possible to realize a lock state determination circuit for a digital PLL that is quickly performed.

  When demodulating an input signal, even if the input signal contains a lot of noise and phase fluctuation components, the input signal is demodulated by a digital PLL and the input signal decoding circuit is operated. It can be used to determine whether or not the clock signal is normally generated, and to determine whether to lock the digital PLL for controlling the operation of the decoding circuit based on the determined result.

It is a block diagram which shows the structural example of the digital PLL system carrying the lock state determination part which concerns on implementation of this invention. It is a figure which shows the structural example of the principal part of the digital PLL which concerns on implementation of this invention. It is a figure which shows the structural example of the principal part of the lock state determination part which concerns on implementation of this invention. It is a figure which shows the operation example of the digital PLL which concerns on implementation of this invention. It is a figure which shows the operation example of the digital PLL which concerns on implementation of this invention. It is a figure which shows the operation example of the digital PLL which concerns on implementation of this invention. It is a figure which shows the operation example of the digital PLL which concerns on implementation of this invention. It is a figure which shows the example of a waveform input into the digital PLL which concerns on implementation of this invention. It is a figure explaining operation | movement of the lock state determination part which concerns on implementation of this invention. It is a figure which shows the modification structural example of the digital PLL which concerns on implementation of this invention. It is a figure which shows the modification structural example of the lock state determination part which concerns on implementation of this invention. It is a figure which shows operation | movement of the lock state determination part comprised by deformation | transformation which concerns on implementation of this invention. It is a figure which shows the example of a change of the integrating | accumulating weighting signal which concerns on implementation of this invention. It is a block diagram which shows the structural example of the conventional analog PLL and a lock | rock detection part.

Explanation of symbols

1 Input circuit section 2 Digital PLL
2a, 8 PLL
DESCRIPTION OF SYMBOLS 3 Lock state determination circuit part 9 Lock detection part 11 A / D converter 12 Clock signal generator 22b, 23b Zero cross detection circuit 22c, 23c Phase difference detection circuit 23 Phase comparator 23a Sampling point interpolation circuit 24 Loop filter 25 Digitally controlled oscillator 27 D / A converter 28, 83 Voltage controlled oscillator 31 Weighted assigner 32, 32 a Lock determination device 81, 91 Phase comparison circuit 82 Loop filter 92 Lock detection circuit 311 Comparison circuit 312 Selector 321 Adder circuit 322 Limiter 323, 324 Flip-flop 325 selector 326 AND gate 327 counter 328 comparison circuit 329, 329a unlock determination circuit

Claims (3)

In the digital PLL lock state determination circuit for detecting whether or not the PLL circuit is locked,
A reference signal for determining whether or not the predetermined PLL circuit is locked is compared with a phase error signal output from the PLL circuit, and when the reference signal is larger than the phase error signal, A comparator that outputs a signal “0” and, if small, a signal “1”;
A selector that outputs a positive number when the signal “0” is input from the comparator, and outputs a negative number when the signal “1” is input from the comparator;
A limiter unit that limits an input positive / negative number between a predetermined upper limit value and a lower limit value;
A feedback unit that outputs a feedback signal that feeds back a number within a range limited by the limiter unit;
Based on the feedback signal, an adder that adds and outputs one of positive and negative numbers output from the selector unit to a number within a range limited by the limiter unit fed back from the feedback unit;
When the integrated value of the number within the range limited by the limiter unit is positive, it is determined as a locked state, and when it is negative, a lock determining unit is determined as an unlocked state;
A circuit for determining a lock state of a digital PLL. In the digital PLL lock state determination circuit for detecting whether or not the PLL circuit is locked,
A reference signal for determining whether or not the predetermined PLL circuit is locked is compared with a phase error signal output from the PLL circuit, and when the reference signal is larger than the phase error signal, A comparator that outputs a signal “0” and, if small, a signal “1”;
A selector that outputs a positive number when the signal “0” is input from the comparator, and outputs a negative number when the signal “1” is input from the comparator;
A limiter unit that limits an input positive / negative number between a predetermined upper limit value and a lower limit value;
A feedback unit that outputs a feedback signal that feeds back a number within a range limited by the limiter unit;
Based on the feedback signal, an adder that adds and outputs one of positive and negative numbers output from the selector unit to a number within a range limited by the limiter unit fed back from the feedback unit;
When the positive / negative integrated value added by the adder is positive, it is determined as a locked state, and when it is negative, a lock determining unit is determined as an unlocked state;
A circuit for determining a lock state of a digital PLL. A digital PLL lock state determination circuit according to claim 1 or 2,
The digital PLL lock state determination circuit, wherein the absolute value of the positive number output from the selector unit is smaller than the absolute value of the negative number.