JP2006113162A - Electrooptical apparatus, driving circuit and method for same, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To keep operation stability for applying a voltage corresponding to a grayscale data to a data line in a structure in which a plurality of grayscale voltages are changed for each color in a time sharing system. <P>SOLUTION: A voltage generation circuit 32 outputs grayscale voltages Vref0 to Vref7 corresponding to each different grayscale for each display color in the time sharing system. A D/A converting circuit 51 selects one of the grayscale voltages Vref0 to Vref7 according to the grayscale data D. A sample and hold circuit 53 includes a sampling switch 531 and a capacitive element 533. The capacitive element 533 holds a voltage Vout which is selected by the D/A converting circuit 51. The sampling switch 531 which is located between the D/A converting circuit 51 and the capacitive element 533, is in an OFF state from a starting point of a period in which the voltage generation circuit 32 outputs the grayscale voltage corresponding to each color till a predetermined time later, and thereafter, it becomes an ON state. An output circuit 55 outputs a voltage which is held in the capacitive element 533, to the data line 13. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique for displaying an image using an electro-optical element such as an OLED (Organic Light Emitting Diode) element.

  An electro-optical device that displays a color image with a plurality of pixels each assigned a different color is widely used. Each pixel is arranged at each intersection of the scanning line and the data line, and has a gradation corresponding to the voltage applied to the data line. As a configuration for applying a voltage corresponding to data indicating the gradation of each pixel (hereinafter referred to as “gradation data”) to the data line, a plurality of voltages corresponding to different gradations (hereinafter referred to as “gradation data”). A configuration including a voltage generation circuit that generates a “voltage” and a D / A conversion circuit that selects any one of these voltages according to gradation data and applies the selected voltage to a data line is employed.

On the other hand, it is known that an electro-optical element such as an OLED element has different electrical or optical characteristics for each display color. In order to compensate for such a difference in characteristics and maintain good display quality (particularly white balance), it is desirable to separately generate a plurality of gradation voltages for each display color. However, under this configuration, the total number of gradation voltages generated by the voltage generation circuit (the number of gradations of each display color × the total number of display colors) increases, and as a result, the voltage generation circuit changes to the D / A conversion circuit. There is a problem that the number of wirings for supplying gradation voltage increases. In order to solve this problem, for example, Patent Document 1 discloses a configuration in which a plurality of gradation voltages corresponding to each color of a pixel are generated in a time division manner and output to a D / A conversion circuit. According to this configuration, wiring for supplying a plurality of gradation voltages corresponding to each color to the D / A conversion circuit (hereinafter referred to as “voltage supply line”) can be shared for a plurality of colors. There is an advantage that the total number of the is reduced.
JP 2003-98998 A (paragraph 0011 and FIG. 2)

  However, since each of the voltage supply lines is accompanied by a capacitance, under the configuration of Patent Document 1 in which the reference voltage supplied to the D / A conversion circuit is sequentially changed, according to the amount of change. The charging / discharging of the voltage supply line is repeated. As a result of such charge and discharge, noise and ripple are superimposed on the gradation voltage, which causes a problem that the stability of the operation of the D / A conversion circuit is impaired. The present invention has been made in view of such circumstances. In the configuration in which a plurality of gradation voltages are changed in a time-sharing manner for each color, an operation of applying a voltage corresponding to gradation data to a data line is performed. It aims to maintain stability.

In order to solve this problem, a first feature of the drive circuit according to the present invention is that a voltage generation circuit that outputs a plurality of gradation voltages corresponding to different gradations in a time-sharing manner for each drive condition; A D / A conversion circuit that selects one of a plurality of gradation voltages output from the voltage generation circuit according to gradation data that indicates the gradation of each pixel, and holds the voltage selected by the D / A conversion circuit Among the periods in which the voltage generation element outputs the gradation voltage corresponding to each driving condition, and is interposed between the voltage holding element, the D / A conversion circuit, and the voltage holding element, a predetermined time from the start point of the period A sampling switch that is in an off state until after a lapse of time elapses, and an output circuit that outputs a voltage held in the voltage holding element to the data line. The “electro-optical device” in the present invention is a device that realizes various functions such as image display using the electro-optical action of the electro-optical element. The electro-optical element means an element having a property of converting one of electric energy and optical energy into the other. A typical example of such an element is an organic light emitting diode (OLED) element such as an organic EL (ElectroLuminescent) or a light emitting polymer, but the scope to which the present invention can be applied is not limited thereto.
In this configuration, the sampling switch is turned off until a predetermined time elapses from the starting point of the period during which the voltage generation circuit outputs the gradation voltage corresponding to each driving condition (the voltage selection period in the embodiment). As a result, the output circuit and the D / A conversion circuit are electrically disconnected, and therefore the operation of the D / A conversion circuit and the electro-optical device becomes unstable due to noise accompanying fluctuations in the gradation voltage. Is prevented.

A second feature of the drive circuit according to the present invention is that a voltage generation circuit that outputs a plurality of gradation voltages corresponding to different gradations in a time-sharing manner for each drive condition, and a plurality of output voltages output from the voltage generation circuit A D / A conversion circuit that selects any one of the gradation voltages according to gradation data that indicates the gradation of each pixel, and first and second voltages that hold the voltage selected by the D / A conversion circuit Any voltage generating circuit is interposed between the holding element, the D / A conversion circuit, and the first voltage holding element (corresponding to the capacitor element 533 of the sample hold circuit 53a shown in FIGS. 7 and 9). The first sampling switch (shown in FIGS. 7 and 9) that is in an off state until a predetermined time elapses from the start point of the period and outputs an on state after the period is output. The sample hold circuit 53a shown Between the D / A converter circuit and the second voltage holding element (corresponding to the capacitor element 533 of the sample hold circuit 53b shown in FIGS. 7 and 9), and the voltage Among the periods in which the generation circuit outputs the grayscale voltages corresponding to other driving conditions, the second sampling switch (see FIG. 7) is turned off until a predetermined time elapses from the start point of the period and then turned on. And corresponding to the sampling switch 531 of the sample-and-hold circuit 53b shown in FIG. 9), and outputs the voltage of the second voltage holding element to the data line during the period in which the first sampling switch is in the ON state. And an output circuit that outputs the voltage of the first voltage holding element to the data line during a period in which the switch is on.
Also with this configuration, the same operation and effect as the drive circuit according to the first feature can be obtained. Furthermore, according to the drive circuit according to the second feature, the voltage of the other voltage holding element is output when one of the first voltage holding element and the second voltage holding element is charged. A sufficient period for applying a voltage corresponding to the gray level of the pixel to the data line can be secured. Note that the fact that only the first sample hold circuit and the second sample hold circuit are specified does not mean that the configuration in which other sample hold circuits are provided is excluded. That is, even if the configuration includes three or more sample and hold circuits, it is included in the scope of the present invention if two of the sample and hold circuits are understood as the first and second sample and hold circuits in the present invention. It is.

In a specific aspect of the drive circuit according to the second feature, the output circuit includes a first output unit interposed between the first voltage holding element and the data line, a second voltage holding element, and the data line. A first output unit interposed between the buffer circuit having an input terminal connected to the first voltage holding element and the output terminal of the buffer circuit and the data line. The second output unit includes a buffer circuit whose input terminal is connected to the second voltage holding element, and a switch interposed between the output terminal of the buffer circuit and the data line. A specific example of this aspect will be described later as a second embodiment (FIG. 7).
In another aspect, the output circuit includes a buffer circuit interposed between the first voltage holding element and the second voltage holding element and the data line, an input terminal of the buffer circuit, and the first voltage holding element. Is interposed between the input terminal of the buffer circuit and the second voltage holding element, and the first sampling switch is in the off state. And a switch which is turned on in a certain period. A specific example of this aspect will be described later as a third embodiment (FIG. 9). According to this aspect, since one buffer circuit is shared to output the voltage of each voltage holding element, the configuration is simplified and the circuit scale is compared with the configuration in which the buffer circuit is provided for each voltage holding element. Can be reduced.
In addition, in the above-described driving circuit, the driving condition may be determined corresponding to the display color of the pixel. For example, when the pixel has a light emitting element such as an OLED element corresponding to the display color, the driving condition of the pixel may be different for each display color. In such a case, the drive circuit described above can be driven in a time-sharing manner corresponding to the display color.

  A first feature of the electro-optical device according to the present invention is that a voltage generation circuit that outputs a plurality of gradation voltages corresponding to different gradations in a time-sharing manner for each driving condition, and a plurality of outputs that the voltage generation circuit outputs. A D / A conversion circuit that selects any one of the gradation voltages in accordance with gradation data that indicates the gradation of each pixel, a voltage holding element that holds the voltage selected by the D / A conversion circuit, and D A sampling switch interposed between the A / A conversion circuit and the voltage holding element, an output circuit for outputting the voltage held in the voltage holding element to the data line, and the voltage generation circuit for generating a gradation voltage corresponding to each driving condition. A control circuit that controls the sampling switch so as to be in an off state until a predetermined time elapses from the start point of the period during the output period and to be in an on state after the lapse of the predetermined period. According to this electro-optical device, the same operation and effect as the drive circuit according to the first feature are exhibited.

A second feature of the electro-optical device according to the present invention is that a voltage generation circuit that outputs a plurality of gradation voltages corresponding to different gradations in a time-sharing manner for each driving condition, and the voltage generation circuit outputs A D / A conversion circuit that selects any one of the plurality of gradation voltages according to gradation data designating the gradation of each pixel, and a first and a first that hold the voltage selected by the D / A conversion circuit 2 voltage holding elements, a first sampling switch interposed between the D / A conversion circuit and the first voltage holding element, and a first sampling switch interposed between the D / A conversion circuit and the second voltage holding element. The voltage of the second voltage holding element is output to the data line during the period in which the two sampling switches and the first sampling switch are in the on state, and the first voltage holding element in the period in which the second sampling switch is in the on state Output time to output the voltage of In the period in which the voltage generation circuit outputs the gradation voltage corresponding to any driving condition, the voltage generation circuit is turned off until a predetermined time elapses from the start point of the period, and is turned on after that time. While controlling one sampling switch, the voltage generation circuit is in an off state until a predetermined time elapses from the start point of the period in which the voltage generation circuit outputs a gradation voltage corresponding to another driving condition. And a control circuit for controlling the second sampling switch. According to this electro-optical device, the same operation and effect as the drive circuit according to the second feature are exhibited. The electro-optical device according to the present invention is typically employed as a display device for various electronic devices.
Further, in the electro-optical device described above, it may be determined corresponding to the display color of the pixel. For example, when the pixel has a light emitting element such as an OLED element corresponding to the display color, the driving condition of the pixel may be different for each display color. In such a case, the electro-optical device described above can be driven in a time-sharing manner corresponding to the display color.

The present invention is also specified as a method of driving an electro-optical device. That is, the first feature of the driving method according to the present invention is that a plurality of gradation voltages each corresponding to a different gradation are output in a time-sharing manner for each driving condition, and any one of the plurality of gradation voltages is While selecting the gradation of each pixel according to the gradation data instructing, the gradation data is output after a predetermined time has elapsed from the start point of the gradation voltage output period corresponding to each driving condition. The corresponding gradation voltage is held in the voltage holding element, and the voltage held in the voltage holding element is output to the data line.
A second feature of the driving method according to the present invention is that a plurality of gradation voltages each corresponding to a different gradation are output in a time-sharing manner for each driving condition, and any one of the plurality of gradation voltages is While the grayscale voltage corresponding to one of the driving conditions is generated, the grayscale voltage corresponding to any driving condition is selected after the grayscale data indicating each pixel is designated. In a period in which a grayscale voltage corresponding to grayscale data is held in the first voltage holding element and a grayscale voltage corresponding to another driving condition is generated, a predetermined time from the start point of the period is generated. The grayscale voltage corresponding to the grayscale data is held in the second voltage holding element in the period after the elapse of time, and the second voltage is held in the period in which the grayscale voltage is held in the first voltage holding element. The voltage of the element is output to the data line, and the gradation voltage is held in the second voltage holding element. It is to output a voltage of the first voltage storage element to a data line.
In addition, in the driving method described above, the driving condition may be determined corresponding to the display color of the pixel. For example, when the pixel has a light emitting element such as an OLED element corresponding to the display color, the driving condition of the pixel may be different for each display color. In such a case, the driving method described above can be driven in a time division manner corresponding to the display color.

<1. First Embodiment>
First, a first embodiment in which the present invention is applied to an electro-optical device using an OLED element as an electro-optical element will be described. FIG. 1 is a block diagram illustrating a configuration of the electro-optical device according to the present embodiment. As shown in the figure, the electro-optical device A includes an electro-optical panel 1 for displaying an image, a scanning line driving circuit 2 and a data line driving circuit 3 for driving the electro-optical panel 1, and an electro-optical device A. And a control circuit 4 for controlling the whole. Among these, the electro-optical panel 1 includes a total of m scanning lines 121 extending in the X direction (row direction), a light emission control line 122 extending in the X direction in pairs with each scanning line 121, and the X direction. And 3n data lines 13 extending in the Y direction (column direction) orthogonal to (m and n are natural numbers).

  A pixel P is disposed at each intersection of the pair of scanning line 121 and light emission control line 122 and the data line 13. Therefore, these pixels P are arranged in a matrix form in the X direction and the Y direction. Each pixel P has an OLED element that emits light in one of red (R), green (G), and blue (B) display colors. In the present embodiment, a configuration in which pixels P of the same color are arranged in the Y direction (so-called stripe arrangement) is illustrated. The three pixels P of red, green, and blue arranged in the X direction form a dot that is the minimum unit of the display image. Hereinafter, the arrangement of dots extending in the Y direction is referred to as a “column”. Accordingly, the electro-optical panel 1 has a total of n rows of dots, and each row includes m vertical pixels × 3 horizontal pixels P.

  Each scanning line 121 and the light emission control line 122 are connected to the scanning line driving circuit 2. The scanning line driving circuit 2 is a circuit for sequentially selecting each scanning line 121 and the light emission control line 122. More specifically, the scanning line driving circuit 2 outputs the scanning signals Ya1, Ya2,..., Yam that sequentially become active levels (H levels) for each horizontal scanning period to each scanning line 121, and these , Ybm are output to the respective light emission control lines 122. When the scanning signal Yai (i is an integer satisfying 1 ≦ i ≦ m) becomes an active level, it means that the i-th row has been selected.

  On the other hand, each data line 13 is connected to the data line driving circuit 3 via a total of n distribution circuits 11 arranged for each column of dots. The data line driving circuit 3 generates and outputs gradation signals x1, x2,..., Xn based on gradation data D input from an external device. The gradation signal xj (j is an integer satisfying 1 ≦ j ≦ n) is a voltage signal corresponding to the gradation to be displayed by the three pixels P in the j-th column belonging to each row. More specifically, the gradation signal xj constitutes a dot in the j-th column belonging to the i-th row in the first period among three periods equally divided by the horizontal scanning period in which the i-th row is selected. The voltage corresponds to the gradation of the red pixel P, becomes a voltage corresponding to the gradation of the green pixel P in the middle period, and becomes a voltage corresponding to the gradation of the blue pixel P in the last period. The distribution circuit 11 in the j-th column distributes each voltage of the gradation signal xj to each of the three data lines 13 corresponding to each color, and outputs it as data signals Xj-r, Xj-g, and Xj-b. (Details will be described later). The OLED element of each pixel P belonging to the row selected by the scanning line driving circuit 2 is supplied with a data signal Xj (any one of Xj-r, Xj-g, and Xj-b) supplied via the data line 13. It emits light at a luminance corresponding to the voltage.

  FIG. 2 is a block diagram illustrating a configuration of the pixel P. In the figure, only the red pixel P constituting the dot in the j-th column belonging to the i-th row is illustrated, but the other pixels P have the same configuration. As shown in the figure, the pixel P has three transistors T1 to T3, a capacitive element C, and an OLED element 100 whose cathode is grounded. Among these, the p-channel transistor T1 has its source electrode connected to the high potential Vdd of the power supply and its drain electrode connected to the drain electrode of the n-channel transistor T2. The transistor T2 has a source electrode connected to the anode of the OLED element 100 and a gate electrode connected to the emission control line 122 in the i-th row. On the other hand, the transistor T3 has its drain electrode connected to the gate electrode of the transistor T2, its source electrode connected to the data line 13 corresponding to the red color in the j-th column, and its gate electrode connected to the scanning line 121 in the i-th row. It is connected. One end of the capacitive element C is connected to the gate electrode of the transistor T1 and the drain electrode of the transistor T3, and the other end is connected to the source electrode of the transistor T1 (and further to the higher potential Vdd).

  Under this configuration, when the scanning signal Yai becomes H level in the i-th horizontal scanning period among the vertical scanning periods, the transistor T3 is turned on. Therefore, if the H level of the scanning signal Yai is sufficiently high, The potential of the gate electrode of the transistor T1 becomes equal to the potential of the data signal Xj-r supplied to the data line 13 at that time. Therefore, the capacitive element C is charged to a voltage corresponding to the data signal Xj-r. At this time, since the light emission control signal Ybi is maintained at the L level, the transistor T2 is turned off. Next, when the i-th horizontal scanning period elapses, the scanning signal Yai becomes L level and the transistor T3 is turned off, while the light emission control signal Ybi transits to H level and the transistor T2 is turned on. At this time, since the voltage stored in the capacitive element C is applied to the gate electrode of the transistor T1, a current corresponding to the data signal Xj-r is supplied to the OLED element 100 via the transistor T2, and the current corresponding to this current is supplied. The OLED element 100 emits light with luminance. Of course, the configuration of the pixel P is not limited to the configuration of FIG.

  Next, a specific configuration of the data line driving circuit 3 will be described. As shown in FIG. 1, the data line driving circuit 3 includes an S / P (Serial to Parallel) conversion circuit, a voltage generation circuit 32, and a total of n processing units 33 corresponding to the total number of columns. The S / P conversion circuit 31 is means for distributing gradation data D serially input from an external device to the processing units 33. Gradation data D specifying the gradations of three (red, green and blue) pixels P belonging to the jth column is supplied to the processing unit 33 in the jth column. In the present embodiment, it is assumed that any of a total of 8 gradations is designated by the 3-bit gradation data D. On the other hand, the voltage generation circuit 32 is means for generating eight types of gradation voltages Vref0 to Vref7 corresponding to these eight gradations. Each processing unit 33 selects one of the gradation voltages Vref0 to Vref7 generated by the voltage generation circuit 32 according to the gradation data D, and outputs it as a gradation signal xj.

  FIG. 3 is a block diagram showing a specific configuration of the voltage generation circuit 32 and each processing unit 33. In the figure, only the processing unit 33 in the j-th column is illustrated, but the configuration of the other processing units 33 is the same. In the same figure, the specific configuration of the distribution circuit 11 in the j-th column is also shown.

  As shown in the figure, the voltage generation circuit 32 includes a voltage generation unit 321 and a voltage selection unit 322. Among these, the voltage generator 321 includes eight types of voltages Vr0 to Vr7 corresponding to the red pixel P, eight types of voltages Vg0 to Vg7 corresponding to the green pixel P, and eight types corresponding to the blue pixel P. Means for generating voltages Vb0 to Vb7. On the other hand, the voltage selection unit 322 is means for selecting the voltage generated by the voltage generation unit 321 as the gradation voltages Vref0 to Vref7 and supplying each to the voltage supply line 35. The voltage selected by the voltage selection unit 322 is determined by the voltage selection signals SELr, SELg, and SELb supplied from the control circuit 4. In other words, the voltage selection unit 322 outputs the voltages Vr0 to Vr7 during the period when the voltage selection signal SELr is at the H level, the voltages Vg0 through Vg7 when the voltage selection signal SELg is at the H level, and the voltage selection signal SELb is at the H level. During the level period, the voltages Vb0 to Vb7 are selected as the gradation voltages Vref0 to Vref7, respectively. In the present embodiment, as shown in FIG. 4, a period corresponding to one horizontal scanning period is divided into three periods (hereinafter referred to as “voltage selection period”), and among these, voltage is applied in the first voltage selection period Tr. The selection signal SELr becomes H level, the voltage selection signal SELg becomes H level in the central voltage selection period Tg, and the voltage selection signal SELb becomes H level in the last voltage selection period Tb. Therefore, as shown in FIG. 4, the voltages Vr0 to Vr7 are in the voltage selection period Tr, the voltages Vg0 to Vg7 are in the voltage selection period Tg, and the voltages Vb0 to Vb7 are in the voltage selection period Tb. Vref0 to Vref7 are selected and supplied to the voltage supply line 35. As described above, the voltage supply line 35 can be shared for all colors by changing the gradation voltages Vref0 to Vref7 output from the voltage generation circuit 32 by time division for each color (that is, the voltage supply line 35). Therefore, the space required for the arrangement of the data line driving circuit 3 can be reduced.

  On the other hand, the processing unit 33 includes a D / A conversion circuit 51, a sample hold circuit 53, and an output circuit 55. Among these, the D / A conversion circuit 51 selects any one of eight kinds of gradation voltages Vref0 to Vref7 based on the gradation data D (3 bits of bits D0 to D2) supplied from the S / P conversion circuit 31. And output as the voltage Vout. As shown in FIG. 4, the gradation data D that designates the gradation of the pixel P of each color belonging to the jth column is sequentially supplied to the D / A conversion circuit 51 in each voltage selection period T (Tr, Tg, Tb). Is input. In other words, the gradation data D corresponding to red is in the voltage selection period Tr, the gradation data D corresponding to green is in the voltage selection period Tg, and the gradation data D corresponding to blue is in the voltage selection period Tb. Input from the P conversion circuit 31 to the D / A conversion circuit 51.

  FIG. 5 is a circuit diagram showing a configuration of the D / A conversion circuit 51. As shown in the figure, three n-channel type transistors 511 are inserted in each of the eight voltage supply lines 35, and the ends of all the voltage supply lines 35 are output of the voltage Vout. The terminal 515 is connected in common. On the other hand, there are a total of six systems of signals consisting of three systems of three bits D0 to D2 constituting the gradation data D, and three systems of signals that are branched and then inverted by an inverter 513. It is generated and applied to the gate electrode of each transistor 511. More specifically, the combination of the gate electrodes of the three transistors 511 on each voltage supply line 35 is different for each voltage supply line 35 among the six systems of signals generated from the gradation data D. The three selected signals are respectively applied. FIG. 6 is a table showing the relationship between the gradation data D and the voltage Vout in the configuration of FIG. In FIG. 6, the decimal value of the gradation value indicated by the gradation data D is also shown. As shown in the figure, any one of Vref0 to Vref7 is output from the output terminal 515 as the voltage Vout according to the gradation value (bits D0 to D2) represented by the gradation data D. For example, when the gradation data D is [D2, D1, D0] = [0, 0, 0] (that is, when the gradation value is “0”), the gradation voltage Vref0 is output as the voltage Vout. When the gradation data D is [D2, D1, D0] = [0, 0, 1] (that is, when the gradation value is “1”), the gradation voltage Vref1 is output as the voltage Vout. And so on. Of course, the configuration of the D / A conversion circuit 51 is not limited to the configuration of FIG.

  Next, the sample hold circuit 53 shown in FIG. 3 is means for sampling and holding the voltage Vout output from the D / A conversion circuit 51, and includes a sampling switch 531 and a capacitive element 533. Among them, the sampling switch 531 has one end connected to the output terminal 515 of the D / A conversion circuit 51 and the other end connected to the output circuit 55 in the subsequent stage. The capacitor 533 is an element for holding the voltage Vout. One end of the capacitive element 533 is connected to the end (the other end) of the sampling switch 531 on the output circuit 55 side, and the other end is grounded. Therefore, the capacitor 533 holds the voltage Vout when the sampling switch 531 is turned on. Opening and closing of the sampling switch 531 is controlled by a sampling signal SAM supplied from the control circuit 4. As shown in FIG. 4, the sampling signal SAM has an active level when a predetermined time length Δt has elapsed from the time when the gradation voltages Vref0 to Vref7 change (that is, the start points of the voltage selection periods Tr, Tg, and Tb). The pulse signal falls to the inactive level until the next time when the gradation voltages Vref0 to Vref7 change. The sampling switch 531 is turned on only during a period in which the sampling signal SAM maintains an active level, and is turned off in other periods.

  The output circuit 55 shown in FIG. 3 is a unit for outputting the voltage Vout held in the capacitor 533 and includes a buffer circuit 551 and a switch 553. An input terminal of the buffer circuit 551 is connected to one end of the capacitor 533. On the other hand, one end of the switch 553 is connected to the output terminal of the buffer circuit, and the other end is connected to the distribution circuit 11. The opening / closing of the switch 553 is controlled by an output enable signal OE supplied from the control circuit 4. As shown in FIG. 4, the output enable signal OE has an active level (H) in a period from when the sampling signal SAM becomes inactive level (that is, after falling to L level) until it becomes active level. Level). When the output enable signal OE transits to the active level and the switch 553 is turned on, the voltage Vout held in the capacitor 533 of the sample hold circuit 53 is processed as the gradation signal xj through the buffer circuit 551 and the switch 553. Output from unit 33.

  With the above configuration, when the sampling signal SAM transitions to the active level in the voltage selection period Tr in which the voltage selection signal SELr is at the active level, the grayscale voltages Vref0 to Vref7 are supplied to the voltage supply line 35 at that time. Among the voltages Vr0 to Vr7, the voltage Vout selected according to the gradation data D is held in the capacitor 533. When the sampling signal SAM transits to the inactive level and the sampling switch 531 is turned off, the output enable signal OE transits to the active level and the switch 553 is turned on, whereby the voltage of the capacitor 533 is increased. Vout is output to the distribution circuit 11 as the gradation signal xj. The same operation is performed in the voltage selection period Tg corresponding to green and the voltage selection period Tb corresponding to blue. Therefore, the gradation signal xj output from the output circuit 55 is a voltage corresponding to the gradation of the red pixel P in the voltage selection period Tr, which is the first period among the three periods equally divided in the horizontal scanning period. (Vr0 to Vr7), and in the voltage selection period Tg which is the central period, the voltage (any one of Vg0 to Vg7) corresponds to the gradation of the green pixel P, and the voltage selection period which is the last period At Tb, a voltage (any one of Vb0 to Vb7) corresponding to the gradation of the blue pixel P is obtained.

  By the way, in the present embodiment, the gradation voltages Vref0 to Vref7 output from the voltage generation circuit 32 are changed in a time-sharing manner for each color, so that the voltage selection period T (Tr, Tg, Tb) starts and immediately after that. The potential of the voltage supply line 35 is not always stable. That is, at the start point of each voltage selection period T, noise is generated in the voltage supply line 35 as the gradation voltages Vref0 to Vref7 change, or the voltage supply line is due to a capacitance component associated with the voltage supply line 35. It takes some time for the 35 voltage to change completely. Therefore, if the voltage of the voltage supply line 35 is output to each data line 13 from the start point of each voltage selection period T or immediately after that, there is a problem that the stable operation of the electro-optical panel 1 is hindered. On the other hand, in the present embodiment, the D / A conversion circuit 51 and the output circuit 55 are electrically connected by turning off the sampling switch 531 until a predetermined time length Δt elapses from the start point of each voltage selection period T. The voltage Vout is held in the capacitor element 533 by turning on the sampling switch 531 when the potential of the voltage supply line 35 is stabilized after the time length Δt has elapsed, and the gradation signal xj Is output to the distribution circuit 11. According to this configuration, it is possible to avoid the influence of noise and ripple caused by fluctuations in the potential of the voltage supply line 35 on the electro-optical panel 1. As is clear from such an action, the time length Δt from the start point of each voltage selection period T to the rise of the sampling signal SAM is set to a length sufficient to stabilize the potential of the voltage supply line 35. It is desirable.

  Next, the configuration of the distribution circuit 11 will be described with reference to FIG. In the figure, only one distribution circuit 11 in the j-th column is shown, but the other distribution circuits 11 have the same configuration. As shown in the figure, the distribution circuit 11 includes three switches 111 corresponding to the pixels P of each color belonging to the j-th column, a buffer circuit 115 disposed at the subsequent stage of each switch 111, and each buffer circuit 115. And the capacitor 113 having one end connected to the input terminal. The output terminal of the buffer circuit 115 is connected to the corresponding data line 13, and the other end of each capacitive element 113 is grounded. The gradation signal xj output from the output circuit 55 is branched into three systems corresponding to each color, and then supplied to each switch 111. When any one of the switches 111 is turned on, the voltage of the gradation signal xj is held in the capacitor 113 and the data signal Xj (Xj-r, Xj-g) is sent to each data line 13 via the buffer circuit 115. , Xj-b).

  Opening and closing of each switch 111 is controlled by distribution signals Sr, Sg and Sb supplied from the control circuit 4. As shown in FIG. 4, the distribution signals Sr, Sg, and Sb are signals that become active level (H level) in a period that does not overlap each other. More specifically, the distribution signal Sr is a period during which the gradation signal xj having a voltage corresponding to red (any one of the voltages Vr0 to Vr7) is output from the output circuit 55 (that is, the output enable signal OE is at an active level). The distribution signal Sg becomes active level during the period when the gradation signal xj becomes a voltage corresponding to green (any one of voltages Vg0 to Vg7), and the distribution signal Sb becomes the gradation signal xj. Becomes an active level during a period when the voltage becomes a voltage corresponding to blue (any one of voltages Vb0 to Vb7). Therefore, the data signal Xj-r output to the red pixel P is any one of the voltages Vr0 to Vr7, and the data signal Xj-g output to the green pixel P is any one of the voltages Vg0 to Vg7. The data signal Xj-b output to the blue pixel P is one of the voltages Vb0 to Vb7. That is, the distribution circuit 11 plays a role of distributing the gradation signal xj as the data signal Xj (Xj-r, Xj-g, Xj-b) of each color.

  As described above, in the present embodiment, the voltage supply line 35 and the output circuit 55 are electrically disconnected at the timing when the gradation voltages Vref0 to Vref7 fluctuate. The electro-optical panel 1 is not affected by noise or ripple caused by the fluctuation. Accordingly, the electro-optical panel 1 can be stably operated.

<2. Second Embodiment>
Next, a second embodiment of the present invention will be described.
In the first embodiment, the configuration in which one sample hold circuit 53 samples the voltage Vout and outputs it to the output circuit 55 when the time length Δt has elapsed from the start point of each voltage selection period T has been exemplified. In this configuration, if the parasitic capacitance of the voltage supply line 35 is sufficiently small (that is, if the time length Δt required for stabilizing the potential of the voltage supply line 35 is sufficiently short), the sampling switch 531 is turned on to sample the voltage Vout. In addition, a sufficient holding period can be secured. However, when the parasitic capacitance of the voltage supply line 35 is relatively large, it takes a long time to stabilize the potential of the voltage supply line 35. Therefore, it is necessary to ensure a long time length Δt. In order to sufficiently secure the time length Δt, if the time length at which the sampling signal SAM is at the active level is relatively shortened, the voltage Vout may not be sufficiently held in the capacitor 533 in some cases. . On the other hand, if the time length during which the sampling signal SAM is at the active level is sufficiently secured, the time length during which the output enable signal OE is at the active level is shortened by the time length Δ, resulting in the data signal Xj. There is a problem that the time that can be output is limited. In the present embodiment, this problem is solved by arranging a plurality of sets of the sample hold circuit 53 and the output circuit 55 for one column. The configuration of the electro-optical device A according to this embodiment is the same as that of the first embodiment except for the configuration of the processing unit 33. Therefore, in the following, the configuration of the processing unit 33 will be described with emphasis, and description of other elements will be omitted as appropriate.

  FIG. 7 is a block diagram illustrating a configuration of the processing unit 33 in the j-th column in the present embodiment. As shown in the figure, the processing unit 33 has two sample and hold circuits 53a and 53b and two output circuits 55a and 55b. The configurations of the sample hold circuits 53a and 53b and the configurations of the output circuits 55a and 55b are the same as the sample hold circuit 53 and the output circuit 55 in the first embodiment, respectively. The sampling switch 531 of the sample and hold circuit 53a is controlled by the first sampling signal SAMa, and the sampling switch 531 of the sample and hold circuit 53b is controlled by the second sampling signal SAMb. The switch 553 of the output circuit 55a is controlled by the first output enable signal OEa, and the switch 553 of the output circuit 55b is controlled by the second output enable signal OEb.

  The first sampling signal SAMa and the second sampling signal SAMb, the first output enable signal OEa, and the second output enable signal OEb are supplied from the control circuit 4. As shown in FIG. 8, the first sampling signal SAMa and the second sampling signal SAMb are alternately at the active level for each voltage selection period T (Tr, Tg, Tb). For example, when the first sampling signal SAMa becomes an active level in the voltage selection period Tr corresponding to red, the first sampling signal SAMa maintains an inactive level and the second sampling signal SAMb is an active level in the subsequent voltage selection period Tg. Further, in the voltage selection period Tb immediately after that, the second sampling signal SAMb maintains the inactive level and the first sampling signal SAMa becomes the active level. The first output enable signal OEa and the second output enable signal OEb have the same relationship. That is, the first output enable signal OEa becomes active level immediately after the first sampling signal SAMa falls, and the second output enable signal OEb becomes active level immediately after the second sampling signal SAMb falls. With the above configuration, the operations of holding the voltage Vout output from the D / A conversion circuit 51 and outputting the gradation signal xj are the combination of the sample hold circuit 53a and the output circuit 55a, the sample hold circuit 53b, and the output circuit. It is executed alternately with the set of 55b. More specifically, it is as follows.

  First, when the first sampling signal SAMa transitions to the active level in the voltage selection period Tr, the voltage Vout is held in the capacitive element 533 of the sample hold circuit 53a. At this time, since the second sampling signal SAMb maintains the inactive level, the output circuit 55 b is electrically disconnected from the D / A conversion circuit 51. Next, the first sampling signal SAMa changes to the inactive level, the output circuit 55a and the D / A conversion circuit 51 are electrically disconnected, and the first output enable signal OEa changes to the active level. As a result, the voltage Vout previously held by the capacitive element 533 of the sample and hold circuit 53a is output from the output circuit 55a to the distribution circuit 11 as the gradation signal xj. On the other hand, when the second sampling signal SAMb transitions to the active level during the voltage selection period Tg, the voltage Vout is held in the capacitive element 533 of the sample hold circuit 53b. As described above, the output circuit 55a is electrically disconnected from the D / A conversion circuit 51 at this time. Next, after the second sampling signal SAMb transits to an inactive level, the second output enable signal OEb transits to an active level, whereby the voltage held in the capacitive element 533 of the sample hold circuit 53b is output from the output circuit 55b. The gradation signal xj is output to the distribution circuit 11. As a result of the above operation being repeated, the gradation signal xj output from the processing unit 33 has the same waveform as in the first embodiment.

  Thus, in the present embodiment, when the sample hold circuit 53a holds the voltage Vout, the output of the gradation signal xj by the output circuit 55a is stopped, and the sample hold circuit 53b becomes the D / A conversion circuit. The output circuit 55b outputs the gradation signal xj while being electrically disconnected from 51. On the other hand, when the sample hold circuit 53b holds the voltage Vout, the output of the gradation signal xj by the output circuit 55b is stopped, and the sample hold circuit 53a is electrically disconnected from the D / A conversion circuit 51. The output circuit 55a outputs the gradation signal xj. Therefore, the time length Δt is set to a length sufficient for stabilizing the potential of the voltage supply line 35, and the time length during which the sampling switch 531 is turned on (that is, the time length during which the sampling signal SAM is at the active level) is set to the first embodiment. Even if it is secured longer, the time length for outputting the voltage held in the capacitive element 533 to the distribution circuit 11 (that is, the time length for which the first output enable signal OEa and the second output enable signal OEb are at the active level) is sufficient. Can be secured.

<3. Third Embodiment>
Next, a third embodiment of the present invention will be described.
In the second embodiment, the configuration in which two output circuits 55a and 55b are arranged in one processing unit 33 is exemplified. On the other hand, in the present embodiment, one buffer circuit 551 is shared to output the voltage Vout output from each of the sample hold circuits 53a and 53b as the gradation signal xj. In the electro-optical device A according to this embodiment, elements similar to those in the first embodiment and the second embodiment are denoted by common reference numerals, and the description thereof is omitted as appropriate.

  FIG. 9 is a block diagram showing the configuration of the processing unit 33 in the j-th column in the present embodiment. As shown in the figure, one output circuit 55c is arranged at the subsequent stage of the sample hold circuits 53a and 53b. This output circuit 55 c has one buffer circuit 551 whose output terminal is connected to the distribution circuit 11, and two switches 535 and 536 each having one end connected to the input terminal of the buffer circuit 551. The other end of the switch 535 is connected to the capacitive element 533 of the sample and hold circuit 53b, and the other end of the switch 536 is connected to the capacitive element 533 of the sample and hold circuit 53a. Among them, the switch 535 is controlled to be opened and closed by the second output enable signal OEb supplied from the control circuit 4, and the switch 536 is controlled to be opened and closed by the first output enable signal OEa supplied from the control circuit 4.

  The waveform of each signal in this embodiment is the same as that in the second embodiment (FIG. 8). With this configuration, when the sample and hold circuit 53a holds the voltage Vout, the switch 536 is turned off, and the sample and hold circuit 53b is electrically disconnected from the D / A conversion circuit 51 and the sample. The voltage Vout of the capacitor 533 of the hold circuit 53b is output as the gradation signal xj through the switch 535 and the buffer circuit 551. On the other hand, when the sample hold circuit 53b holds the voltage Vout, the switch 535 is turned off, the sample hold circuit 53a is electrically disconnected from the D / A conversion circuit 51, and the sample hold circuit 53a The voltage Vout of the capacitor 533 is output as the gradation signal xj through the switch 536 and the buffer circuit 551. Therefore, also in this embodiment, the same effect as the second embodiment is produced. In addition, in the present embodiment, since one buffer circuit 551 is shared to output the voltage Vout output from each of the sample hold circuits 53a and 53b as the gradation signal xj, it is compared with the second embodiment. Thus, there is an advantage that complication of the configuration of the processing unit 33 and enlargement of the circuit scale can be suppressed.

<4. Modification>
Various modifications may be added to each embodiment. Specific modifications are as follows. In addition, the structure which combined each following aspect suitably is also employ | adopted.

(1) In the first to third embodiments, the configuration in which the gradation signal xj is distributed to the pixels P of each color by the distribution circuit 11 interposed between the pixels P and the data line driving circuit 3 is exemplified. The configuration for distributing the gradation signal xj is not limited to this. For example, as shown in FIG. 10, a configuration in which the gradation signal xj is distributed by a signal supplied to the light emission control line 122 is also employed. In the configuration shown in FIG. 10, the gradation signal xj output from the processing unit 33 is branched into three systems for each column and then supplied to the red, green, and blue pixels P. That is, the common gradation signal xj is supplied to the three data lines 13 belonging to each column. On the other hand, a total of three light emission control lines 122 corresponding to each color are formed for each row, and the three distribution signals Sr, Sg, and Sb shown in each embodiment are supplied to these light emission control lines 122, respectively. With this configuration, the distribution signal Sr is supplied to the pixel P corresponding to red, the distribution signal Sg is supplied to the pixel P corresponding to green, and the distribution signal Sb is supplied to the pixel P corresponding to blue via the light emission control line 122. And supplied to the gate electrode of the transistor T2 of each pixel P. Therefore, the capacitor C of each pixel P holds the same voltage regardless of the color of the pixel P in the horizontal scanning period, while the OLED element 100 of the pixel P of each color has a voltage corresponding to that color. Light is emitted with luminance corresponding to the voltage at the timing held in C. Even in this configuration, the same effects as those of the first to third embodiments can be obtained.

(2) In the first to third embodiments, the configuration in which the voltage selection unit 322 selects the voltage generated in advance by the voltage generation unit 321 as the grayscale voltages Vref0 to Vref7 is illustrated. However, the voltage generation unit 321 generates the voltage. The voltage itself may be changed sequentially for each color. That is, the voltage generator 321 in this configuration sequentially changes the gradation voltages Vref0 to Vref7 supplied to each voltage supply line 35 for each voltage selection period T in accordance with an instruction from the control circuit 4. . This configuration also provides the same effects as those of the first to third embodiments.

(3) In each embodiment, after the sampling switch 531 of the sample and hold circuit 53 is changed to the off state (that is, after the sampling signal SAM falls to the inactive level), the enable signal OE is set to the active level and the gradation signal Although the configuration for outputting xj is exemplified, the output circuit 55 may output the gradation signal xj before the sampling switch 531 is turned off. However, in this case, it is desirable that the voltage Vout be sufficiently held in the capacitor 533 before the sampling switch 531 is turned off.

(4) In the second embodiment, the configuration in which only two sets of the sample hold circuit 53 and the output circuit 55 are provided in one processing unit 33 is illustrated, but the total number of the sets is arbitrarily changed. For example, a configuration in which three sets including the sample hold circuit 53 and the output circuit 55 are provided in one processing unit 33 may be adopted. Similarly, the number of sample and hold circuits 53 in the third embodiment is arbitrarily changed.

(5) In each embodiment, the number of bits of the gradation data D is “3”, but it goes without saying that this number of bits is arbitrarily changed. Therefore, the total number of voltages generated by the voltage generation circuit is not limited to “8”, and is appropriately changed according to the number of bits of the gradation data D.

(6) In each embodiment, the pixel P (so-called voltage drive type) in which the luminance of the OLED element 100 is defined by the voltage of the data signal Xj is exemplified. However, a method for displaying a gradation on each pixel P is described below. It is not limited to this. For example, a configuration (so-called pulse width modulation driving) in which a data signal Xj whose time length (pulse width) at which the OLED element 100 emits light is adjusted according to the gradation data D is supplied to each pixel P is also employed. .

(7) In each embodiment, the electro-optical device A to which the OLED element 100 is applied as the electro-optical element is illustrated, but the present invention is also applied to other electro-optical devices. For example, liquid crystal display, field emission display (FED), surface-conduction electron emission display (SED), ballistic electron surface display (BSD), light emission The present invention can also be applied to various electro-optical devices such as a display device using a diode or a write head of an optical writing type printer or an electronic copying machine, as in the above embodiments. As described above, the electro-optical element in the present invention is an element having a property of converting one of electric energy and optical energy into the other, and all apparatuses including this type of electro-optical element. The present invention can be applied to.

<5. Application example>
Next, an electronic apparatus to which the electro-optical device according to the invention is applied will be described. FIG. 11 is a perspective view illustrating a configuration of a mobile personal computer in which the electro-optical device A according to the embodiment is applied to a display device. The personal computer 2000 includes an electro-optical device A as a display device and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002. Since the electro-optical device A uses the OLED element 100, it is possible to display an easy-to-see screen with a wide viewing angle.

  FIG. 12 shows a configuration of a mobile phone to which the electro-optical device A according to the above embodiment is applied. A cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and an electro-optical device A as a display device. By operating the scroll button 3002, the screen displayed on the electro-optical device A is scrolled.

  FIG. 13 shows a configuration of a portable information terminal (PDA: Personal Digital Assistants) to which the electro-optical device A according to the embodiment is applied. The information portable terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and an electro-optical device A as a display device. When the power switch 4002 is operated, various types of information such as an address book and a schedule book are displayed on the electro-optical device A.

  The electronic apparatus to which the electro-optical device according to the present invention is applied includes, in addition to those shown in FIGS. 11 to 13, a digital still camera, a television, a video camera, a car navigation device, a pager, an electronic notebook, electronic paper, Examples include calculators, word processors, workstations, videophones, POS terminals, printers, scanners, copiers, video players, devices equipped with touch panels, and the like.

1 is a block diagram illustrating an overall configuration of an electro-optical device according to a first embodiment of the invention. FIG. It is a block diagram which shows the structure of a pixel. It is a block diagram which shows the structure of the processing unit of an electro-optical apparatus, and a distribution circuit. 6 is a timing chart for explaining the operation of the electro-optical device. It is a circuit diagram which shows the structure of a D / A conversion circuit. It is a table | surface for demonstrating operation | movement of a D / A conversion circuit. FIG. 6 is a block diagram illustrating a configuration of a processing unit of an electro-optical device according to a second embodiment of the invention. 6 is a timing chart for explaining the operation of the electro-optical device. FIG. 10 is a block diagram illustrating a configuration of a processing unit of an electro-optical device according to a third embodiment of the invention. It is a block diagram which shows the other structure for distributing a gradation signal to the pixel of each color. It is a perspective view which shows the structure of the personal computer to which this invention is applied. It is a perspective view which shows the structure of the mobile telephone to which this invention is applied. It is a perspective view which shows the structure of the portable information terminal to which this invention is applied.

Explanation of symbols

A ... electro-optical device, P ... pixel, 100 ... OLED element, 1 ... electro-optical panel, 11 ... distribution circuit, 111 ... switch, 113 ... capacitance element, 115 ... buffer circuit, 121 ... scanning line, 122 ... light emission control line , 13 ... Data line, 2 ... Scan line drive circuit, 3 ... Data line drive circuit, 31 ... S / P conversion circuit, 32 ... Voltage generation circuit, 321 ... Voltage generation unit, 322 ... Voltage selection unit, 33 ... Processing unit , 51 D / A conversion circuit 53, 53 a, 53 b Sample hold circuit 531 Sampling switch 533 Capacitance element 55 Output circuit 551 Buffer circuit 553 Switch Yai Scan signal Ybi Light emission control signal, Xj (Xj-r, Xj-g, Xj-b) ... data signal, xj ... gradation signal, SELr, SELg, SELb ... voltage selection signal, Sr, Sg, Sb ... distribution signal, Vref0 to Vref7: gradation voltage, SAM, SAMa, SAMb: sampling signal, OE, OEa, OEb: output enable signal, D: gradation data.

Claims (13)

A circuit for driving an electro-optical device in which a plurality of pixels having different driving conditions have gradations according to the voltage of the data line,
A voltage generation circuit that outputs a plurality of gradation voltages each corresponding to a different gradation in a time-sharing manner for each of the driving conditions;
A D / A conversion circuit that selects any one of the plurality of gradation voltages output from the voltage generation circuit according to gradation data instructing the gradation of each pixel;
A voltage holding element for holding the voltage selected by the D / A conversion circuit;
A predetermined time elapses from the start point of the period among the periods in which the voltage generation circuit outputs the gradation voltage corresponding to each driving condition, interposed between the D / A conversion circuit and the voltage holding element. A sampling switch that is turned off until it is turned on, and after that,
An output circuit that outputs a voltage held in the voltage holding element to the data line. The drive circuit according to claim 1, wherein the output circuit includes a switch that is interposed between the voltage holding element and the data line and is turned on when the sampling switch is turned off. A circuit for driving an electro-optical device in which a plurality of pixels having different driving conditions have gradations according to the voltage of the data line,
A voltage generation circuit that outputs a plurality of gradation voltages each corresponding to a different gradation in a time-sharing manner for each of the driving conditions;
A D / A conversion circuit that selects any one of the plurality of gradation voltages output from the voltage generation circuit according to gradation data instructing the gradation of each pixel;
First and second voltage holding elements for holding a voltage selected by the D / A conversion circuit;
Among the periods in which the voltage generation circuit outputs a grayscale voltage corresponding to any driving condition and is interposed between the D / A conversion circuit and the first voltage holding element, the predetermined period from the start point of the period A first sampling switch that is turned off until the time elapses, and turned on after that time;
Among the periods in which the voltage generation circuit outputs grayscale voltages corresponding to other driving conditions, and is interposed between the D / A conversion circuit and the second voltage holding element, a predetermined value from the start point of the period A second sampling switch that is turned off until time has elapsed and then turned on;
The voltage of the second voltage holding element is output to the data line during a period when the first sampling switch is in an on state, and the first voltage holding element is output during a period when the second sampling switch is in an on state. An output circuit that outputs the voltage of the above to the data line. The output circuit includes: a first output unit interposed between the first voltage holding element and the data line; a second output unit interposed between the second voltage holding element and the data line; Including
The first output unit includes a buffer circuit whose input terminal is connected to the first voltage holding element, and a switch interposed between the output terminal of the buffer circuit and the data line,
The second output unit includes a buffer circuit whose input terminal is connected to the second voltage holding element, and a switch interposed between the output terminal of the buffer circuit and the data line. Drive circuit. The output circuit is
A buffer circuit interposed between the first voltage holding element and the second voltage holding element and the data line;
A switch that is interposed between an input terminal of the buffer circuit and the first voltage holding element and is turned on in a period in which the second sampling switch is turned on;
4. The drive circuit according to claim 3, further comprising: a switch that is interposed between an input terminal of the buffer circuit and the second voltage holding element and is turned on during a period in which the first sampling switch is turned off.   The drive circuit according to claim 1, wherein the drive condition is determined in accordance with a display color of the pixel. An electro-optical device in which a plurality of pixels having different driving conditions have gradations according to the voltage of the data line,
A voltage generation circuit that outputs a plurality of gradation voltages each corresponding to a different gradation in a time-sharing manner for each of the driving conditions;
A D / A conversion circuit that selects any one of the plurality of gradation voltages output from the voltage generation circuit according to gradation data instructing the gradation of each pixel;
A voltage holding element for holding the voltage selected by the D / A conversion circuit;
A sampling switch interposed between the D / A conversion circuit and the voltage holding element;
An output circuit for outputting the voltage held in the voltage holding element to the data line;
Of the period in which the voltage generation circuit outputs the gradation voltage corresponding to each driving condition, the sampling switch is turned off until a predetermined time elapses from the start point of the period, and the sampling switch is turned on after that period. An electro-optical device comprising a control circuit for controlling. A circuit for driving an electro-optical device in which a plurality of pixels having different driving conditions have gradations according to the voltage of the data line,
A voltage generation circuit that outputs a plurality of gradation voltages each corresponding to a different gradation in a time-sharing manner for each of the driving conditions;
A D / A conversion circuit that selects any one of the plurality of gradation voltages output from the voltage generation circuit according to gradation data instructing the gradation of each pixel;
First and second voltage holding elements for holding a voltage selected by the D / A conversion circuit;
A first sampling switch interposed between the D / A conversion circuit and the first voltage holding element;
A second sampling switch interposed between the D / A conversion circuit and the second voltage holding element;
The voltage of the second voltage holding element is output to the data line during a period when the first sampling switch is in an on state, and the first voltage holding element is output during a period when the second sampling switch is in an on state. An output circuit that outputs a voltage of
Among the periods in which the voltage generation circuit outputs the gradation voltage corresponding to any driving condition, the voltage generation circuit is in an off state until a predetermined time has elapsed from the start point of the period, and after that, the first state is turned on. While controlling one sampling switch, the voltage generation circuit is in an off state until a predetermined time elapses from the start point of the period in which the voltage generation circuit outputs a gradation voltage corresponding to another driving condition, and is turned on thereafter An electro-optical device comprising: a control circuit that controls the second sampling switch so as to be in a state.   9. The drive circuit according to claim 7, wherein the drive condition is determined in accordance with a display color of the pixel.   An electronic apparatus comprising the electro-optical device according to claim 7. A method of driving an electro-optical device in which a plurality of pixels having different driving conditions have gradations according to the voltage of a data line,
A plurality of gradation voltages, each corresponding to a different gradation, are output in a time-sharing manner for each driving condition, and any one of the plurality of gradation voltages is determined according to gradation data indicating the gradation of each pixel. While selecting
Of the period in which the gradation voltage corresponding to each driving condition is output, the gradation voltage corresponding to the gradation data is held in the voltage holding element after a predetermined time has elapsed from the start point of the period, and this voltage holding element A method of driving an electro-optical device that outputs the voltage held in the data line to the data line. A method of driving an electro-optical device in which a plurality of pixels having different driving conditions have gradations according to the voltage of a data line,
A plurality of gradation voltages, each corresponding to a different gradation, are output in a time-sharing manner for each driving condition, and any one of the plurality of gradation voltages is determined according to gradation data indicating the gradation of each pixel. While selecting
Among the periods in which the gradation voltage corresponding to any driving condition is generated, the gradation voltage corresponding to the gradation data is the first voltage in a period after a predetermined time has elapsed from the start point of the period. The grayscale voltage corresponding to the grayscale data in a period after a predetermined time elapses from the start point of the period among the periods in which the grayscale voltage held in the holding element and corresponding to other driving conditions is generated Is held in the second voltage holding element,
The voltage of the second voltage holding element is output to the data line during a period in which the first voltage holding element holds the gradation voltage, and the gradation voltage is held by the second voltage holding element. A method of driving an electro-optical device, wherein the voltage of the first voltage holding element is output to the data line during a period of time.   The method of driving an electro-optical device according to claim 11, wherein the driving condition is determined corresponding to a display color of the pixel.

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