JP2006186332A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the technology of manufacturing a semiconductor device in which the utilization efficiency of a material is improved and a manufacturing process is simplified, and technology capable of forming in a desired profile and with sufficient adhesiveness a pattern such as an interconnect line constituting the semiconductor device. <P>SOLUTION: A first insulating layer is formed on a first conductive layer. A second insulating layer is formed on the first insulating layer. A first mask layer having a first opening is formed on the second insulating layer. The first opening reaching the first conductive layer is formed by etching the first insulating layer and the second insulating layer. A second mask layer having a second opening whose opening area is larger than that of the first opening and whose wettability toward a composition comprising a conductive material is low is formed on the second insulating layer after removing the first mask layer. The second insulating layer is etched such that a part of the top surface of the first insulating layer is exposed. The second opening is formed. The first and second openings are filled with the composition comprising the conductive material. A second conductive layer is formed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  For connection between multilayer wiring and wiring layers in a conventional semiconductor device, a method of producing a buried wiring structure by using copper (Cu), which is a low resistance material, and removing unnecessary wiring material by CMP technology (see FIG. For example, see Patent Document 1). Examples of the embedded wiring include a damascene method in which only a wiring portion is filled with copper after a connection plug is formed from a lower layer wiring, and a dual damascene method in which a connection between wiring layers is also formed with copper. The dual damascene method will be described with reference to FIG.

  An insulating film 1002, a first wiring 1003, an interlayer insulating film 1004, an etching stop insulating film 1005, and an inter-wiring insulating film 1006 are formed over the semiconductor substrate 1001 (see FIG. 28A). A resist film 1007 having an opening is formed over the inter-wiring insulating film 1006, and a groove 1009 is formed in the inter-wiring insulating film 1006 using the resist film 1007 (see FIG. 28B). After removing the resist film 1007, a resist film 1010 having an opening is formed again, and the etching stop insulating film 1005 and the interlayer insulating film 1004 are etched and connected using the resist film 1010 until the first wiring is exposed. A hole 1012 is formed (see FIG. 28C).

Copper 1023 is formed over the inter-wiring insulating film 1006, the connection hole 1012 and the groove 1009 (see FIG. 28D). A portion of the copper 1023 other than that formed inside the groove 1009 and the inside of the connection hole 1012 is removed by polishing by CMP to form a connection plug portion 1024 and a second wiring 1025 (see FIG. 28E). .)
JP 9-306988 A

  The present invention simplifies the manufacturing process of a semiconductor device and a display device having complicatedly designed multilayer wiring, and can manufacture a substrate with a large area with one side exceeding 1 meter at a low cost with a high yield. The purpose is to provide.

  It is another object of the present invention to provide a technique capable of forming components such as wirings constituting the semiconductor device and the display device in a desired shape with good adhesion.

  Note that in this specification, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. A semiconductor device such as a multilayer wiring layer or a processor chip can be manufactured by using the present invention.

  The present invention can also be used for a display device that has a display function. The display device using the present invention includes an organic substance that emits light called electroluminescence (hereinafter also referred to as “EL”), or an organic substance. And a liquid crystal display device using a liquid crystal element having a liquid crystal material as a display element, and the like.

  In one embodiment of the method for manufacturing a semiconductor device of the present invention, a first conductive layer is formed, a first insulating layer is formed over the first conductive layer, and a second insulating layer is formed over the first insulating layer. Forming a first mask layer having a first opening on the second insulating layer, and etching the first insulating layer and the second insulating layer through the first mask layer; The second opening having a larger opening area than the first opening is formed at a position overlapping the first opening after forming the first opening reaching the first conductive layer and removing the first mask layer. And a second mask layer having low wettability with respect to the composition containing a conductive material is formed on the second insulating layer so that a part of the upper surface of the first insulating layer is exposed. The second insulating layer is etched to form a second opening, and the first opening and the second opening are filled with a composition containing a conductive material, and the second conductive layer Formed, characterized in that.

  According to one method for manufacturing a semiconductor device of the present invention, a first conductive layer is formed, a first insulating layer is formed over the first conductive layer, and a second hole having a hole over the first insulating layer is formed. An insulating layer is formed, a first mask layer having a first opening is formed over the second insulating layer, and the first insulating layer and the second insulating layer are etched through the first mask layer. Thus, after the first opening reaching the first conductive layer is formed and the first mask layer is removed, the first opening having a larger opening area than the first opening is formed at a position overlapping the first opening. A second mask layer having two openings and low wettability with respect to the composition containing a conductive material is formed on the second insulating layer, and a part of the upper surface of the first insulating layer is exposed. The second insulating layer is etched to form a second opening, and a conductive material is contained in the first opening, the second opening, and the hole of the second insulating layer. The composition was filled, and forming a second conductive layer.

  In one embodiment of the method for manufacturing a semiconductor device of the present invention, a first conductive layer is formed, a first insulating layer is formed over the first conductive layer, and a second insulating layer is formed over the first insulating layer. Forming a third insulating layer on the second insulating layer, forming a first mask layer having a first opening on the third insulating layer, and through the first mask layer, The first insulating layer, the second insulating layer, and the third insulating layer are etched to form a first opening reaching the first conductive layer, and after removing the first mask layer, A second mask layer having a second opening having a larger opening area than the first opening at a position overlapping with the first opening and having low wettability with respect to the composition containing a conductive material is provided. The second insulating layer is formed on the third insulating layer, and the third insulating layer is etched so that a part of the upper surface of the second insulating layer is exposed to form a second opening, and the first opening and the second Filled with a composition containing a conductive material in the opening, and forming a second conductive layer.

  In one embodiment of the method for manufacturing a semiconductor device of the present invention, a first conductive layer is formed, a first insulating layer is formed over the first conductive layer, and a second insulating layer is formed over the first insulating layer. Forming a third insulating layer having a hole on the second insulating layer, forming a first mask layer having a first opening on the third insulating layer, and forming a first mask layer on the second insulating layer; A first opening reaching the first conductive layer is formed by etching the first insulating layer, the second insulating layer, and the third insulating layer, and the first mask layer is removed After that, a second mask having a second opening having a larger opening area than the first opening at a position overlapping with the first opening and having low wettability with respect to the composition containing a conductive material. A layer is formed over the third insulating layer, the third insulating layer is etched so that a part of the upper surface of the second insulating layer is exposed, a second opening is formed, and the first opening is formed. , The second opening, and filled with a composition containing a conductive material in the holes of the second insulating layer, and forming a second conductive layer.

  In the above structure, the second mask layer is formed using a substance containing a fluorocarbon group.

  In the above structure, plasma treatment is performed on the surface of the second mask layer.

  In the above structure, the plasma treatment is performed in a gas atmosphere containing fluorine.

  According to the present invention, the conductive layer can be formed with good controllability, the material loss is small, and the cost can be reduced. Further, by using an insulating layer having holes, the conductive layers can be formed with good adhesion by the anchor effect. Therefore, a high-performance and highly reliable semiconductor device and display device can be manufactured with high yield.

  Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
An embodiment of the present invention will be described with reference to FIGS.

  The present invention provides at least one or more of components necessary for manufacturing a semiconductor device, a display device, and the like, such as a conductive layer for forming a wiring layer or an electrode, and a mask layer for forming a predetermined pattern. Are formed by a method that can be selectively formed into a desired shape, and a semiconductor device and a display device are manufactured. In the present invention, a component (also referred to as a pattern) refers to a conductive layer such as a wiring layer, a gate electrode layer, a source electrode layer, and a drain electrode layer, a semiconductor layer, a mask layer, an insulating layer, etc. that constitute a thin film transistor or a display device. Including all components formed with a predetermined shape. As a method that can selectively form a desired pattern with a desired pattern, droplets of a composition formulated for a specific purpose are selectively ejected (ejected) to form a conductive layer, insulating layer, etc. in a predetermined pattern A droplet discharge (ejection) method (also called an ink jet method depending on the method) can be used. In addition, a method in which the composition can be transferred or drawn in a desired pattern, for example, various printing methods (screen (stencil) printing, offset (flat plate) printing, letterpress printing, gravure (intaglio printing), etc.) ), A selective coating method, and the like can also be used.

  In this embodiment, a method is used in which a composition containing a constituent forming material that is a fluid is ejected (ejected) as droplets to form a desired pattern. A droplet containing a component forming material is discharged onto a region where the component is to be formed, and fixed by firing, drying, or the like to form a component having a desired pattern.

  One mode of a droplet discharge apparatus used for the droplet discharge method is shown in FIG. The individual heads 1405 and 1412 of the droplet discharge means 1403 are connected to the control means 1407, which can be drawn in a pre-programmed pattern under the control of the computer 1410. The drawing timing may be performed with reference to a marker 1411 formed on the substrate 1400, for example. Alternatively, the reference point may be determined based on the edge of the substrate 1400. This is detected by the imaging means 1404, converted into a digital signal by the image processing means 1409, is recognized by the computer 1410, a control signal is generated, and sent to the control means 1407. As the imaging unit 1404, an image sensor using a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) can be used. Of course, the information on the pattern to be formed on the substrate 1400 is stored in the storage medium 1408. Based on this information, a control signal is sent to the control means 1407, and each head 1405 of the droplet discharge means 1403 is sent. The heads 1412 can be individually controlled. The material to be discharged is supplied from the material supply source 1413 and the material supply source 1414 to the head 1405 and the head 1412 through piping.

  The inside of the head 1405 has a structure having a space filled with a liquid material as indicated by a dotted line 1406 and a nozzle that is a discharge port. Although not shown, the head 1412 has the same internal structure as the head 1405. When the nozzles of the head 1405 and the head 1412 are provided in different sizes, different materials can be drawn simultaneously with different widths. With one head, conductive material, organic material, inorganic material, etc. can be discharged and drawn respectively. When drawing in a wide area like an interlayer film, the same material is used from multiple nozzles to improve throughput. It is possible to discharge and draw at the same time. In the case of using a large substrate, the head 1405 and the head 1412 can freely scan on the substrate in the direction of the arrow to freely set a drawing area, and a plurality of the same pattern can be drawn on a single substrate. it can.

  The concept of the embodiment of the present invention will be described with reference to FIGS. 1 and 2 using a method for forming a wiring layer.

  A wiring layer 101 is formed on a substrate 100 such as a silicon substrate, a glass substrate, a quartz substrate, or a plastic substrate together with active elements (not shown) such as field effect transistors and thin film transistors. The wiring layer 101 is formed by forming a conductive material such as Al, Cu, or W by sputtering, vacuum deposition, CVD, or the like, and processing it into a desired shape using a photolithography method, an etching method, or the like. It is formed. Alternatively, a wiring layer may be formed by selectively forming a film obtained by dissolving or dispersing a conductive material in a solvent by a droplet discharge method and performing heat treatment.

  The insulating layer 102, the insulating layer 103, and the insulating layer 104 are formed. An insulating layer having a hole in an interlayer insulating layer such as the insulating layer 102, the insulating layer 103, or the insulating layer 104 can be used. In this embodiment mode, the insulating layer 102 and the insulating layer 104 are formed using an organic siloxane film including fine holes by a coating method. The organic siloxane composition containing the pore-forming material is applied and formed by a coating method such as spin coating or slit coating, and heat treatment is performed, so that the curing reaction of the organic siloxane proceeds, and the pore-forming material is decomposed and vaporized. Arise. As a result, a large number of fine holes are formed in the organosiloxane film. By introducing these fine holes, the dielectric constant of the interlayer insulating film is lowered, the parasitic capacitance between the wirings is lowered, and signal delay can be suppressed. The insulating layer 103 functions as an etching stopper when the insulating layer 104 is etched. The insulating layer 103 is not necessarily used if the etching selectivity between the insulating layer 102 and the insulating layer 104 is high. In this embodiment mode, the insulating layer 103 is formed using a silicon nitride film formed by a CVD method. The insulating layer 103 may be made of another material as long as it can function as an etching stop film when the insulating layer 104 is etched and can obtain the same effect.

  A mask layer 105a and a mask layer 105b made of a resist having an opening at a position to be connected to the wiring layer 101 are formed by a photolithography process. Using the mask layer 105a and the mask layer 105b as an etching mask, the insulating layer 102, the insulating layer 103, and the insulating layer 104 are etched until the wiring layer 101 is exposed to form an opening 106 (see FIG. 1B). ). Thereafter, the mask layer 105a and the mask layer 105b are removed.

  By a photolithography process, a mask layer 107a, a mask layer 107b, and a mask layer 107c each having an opening in a region where a wiring layer is to be formed are formed. The material of the mask layer is preferably a resist material or an organic material. In this embodiment, a dissolution inhibiting resist using a novolak resin as a polymer and diazonaphthoquinone as a photoreceptor is used. Using the mask layer 107a, the mask layer 107b, and the mask layer 107c as an etching mask, the insulating layer 104 is etched until part of the upper surface of the insulating layer 103 is exposed, so that an opening 108a and an opening 108b are formed.

Next, by performing plasma treatment in a gas atmosphere containing fluorine, the C—H bonds on the surfaces of the mask layer 107a, the mask layer 107b, and the mask layer 107c are replaced with C—F bonds. Reduce energy. In this embodiment mode, plasma treatment is performed in a mixed gas atmosphere of CF ₄ and O ₂ . After that, a solution in which a conductive material is dissolved or dispersed in a solvent (hereinafter also referred to as a composition containing a conductive material) is selectively formed in the opening 108a and the opening 108b by the droplet discharge devices 112a and 112b. To do. In this embodiment, a solution in which Ag nanoparticles are dispersed in a tetradecane solvent is used. In general, the droplet discharge method is inferior to the photolithography process in positional accuracy, but the resist film surface as a mask layer has a low wettability region 109a, a low wettability region 109b, and a composition containing a conductive material. Since it has a low wettability region 109c and has a low surface energy, even if the discharged solution adheres to the resist film, it is repelled by the resist film and formed in the opening 108a and the opening 108b.

  In the present embodiment, the surface energy of the mask layer is reduced by plasma treatment in a gas atmosphere containing fluorine. However, other methods may be used as long as they have similar effects. For example, a layer made of a material with low wettability may be formed, and a low resisting solution may be formed by applying, exposing, and developing a resist solution to which a surface modifier such as a monomer or oligomer having a fluorocarbon group is added. It is possible to form a surface energy resist film. Since fluorocarbon has a low surface energy, it tends to exist in a large amount on the surface, and even when added in a small amount of about 1%, a fluorocarbon group exists on the surface of the mask layer and exhibits a low surface energy.

As a substance having low wettability, a substance containing a fluorocarbon group or a substance containing a silane coupling agent can be used. The silane coupling agent is represented by a chemical formula of Rn—Si—X _(4-n) (n = 1, 2, 3). Here, R is a substance containing a relatively inert group such as an alkyl group. X is a hydrolyzable group such as halogen, methoxy group, ethoxy group or acetoxy group, which can be bonded by condensation with a hydroxyl group on the substrate surface or adsorbed water.

Further, as a representative example of the silane coupling agent, wettability can be further reduced by using a fluorine-based silane coupling agent (fluoroalkylsilane (FAS)) having a fluoroalkyl group in R. R of FAS has a structure represented by (CF ₃ ) (CF ₂ ) _x (CH ₂ ) _y (x: an integer of 0 or more and 10 or less, y: an integer of 0 or more and 4 or less), and a plurality of R Alternatively, when X is bonded to Si, R and X may all be the same or different. As typical FAS, fluoroalkylsilanes (hereinafter also referred to as FAS) such as heptadecafluorotetrahydrodecyltriethoxysilane, heptadecafluorotetrahydrodecyltrichlorosilane, tridecafluorotetrahydrooctyltrichlorosilane, and trifluoropropyltrimethoxysilane. ).

  Solvents for the solution that forms the low wettability region include n-pentane, n-hexane, n-heptane, n-octane, n-decane, dicyclopentane, benzene, toluene, xylene, durene, indene, tetrahydronaphthalene, deca A hydrocarbon solvent such as hydronaphthalene or squalane, or a solvent that forms a low wettability surface such as tetrahydrofuran is used.

  In addition, as an example of a composition of a solution that forms a low wettability region, a material having a fluorocarbon chain (fluorine-based resin) can be used. Examples of fluorine resins include polytetrafluoroethylene (PTFE; tetrafluoroethylene resin), perfluoroalkoxyalkane (PFA; tetrafluoroethylene perfluoroalkyl vinyl ether copolymer resin), and perfluoroethylene propene copolymer (PFEP; four fluoropolymer). Ethylene-hexafluoropropylene copolymer resin), ethylene-tetrafluoroethylene copolymer (ETFE; tetrafluoroethylene-ethylene copolymer resin), polyvinylidene fluoride (PVDF; vinylidene fluoride resin), polychlorotrifluoroethylene (PCTFE; trifluoroethylene chloride resin), ethylene-chlorotrifluoroethylene copolymer (ECTFE; trifluoroethylene chloride-ethylene copolymer resin), polytetrafluoroethylene-perfluorodioxide Rukoporima (TFE / PDD), polyvinyl fluoride (PVF; a vinyl fluoride resin), or the like can be used.

Alternatively, the low wettability region may be formed by using an organic material and subsequently performing treatment with CF ₄ plasma or the like. For example, a material in which a water-soluble resin such as polyvinyl alcohol (PVA) is mixed with a solvent such as H ₂ O can be used. Moreover, you may use combining PVA and another water-soluble resin. An organic material (organic resin material) (polyimide, acrylic), a siloxane resin, or the like may be used. In the siloxane resin, a skeleton structure is formed by a bond of silicon (Si) and oxygen (O), and a compound containing at least hydrogen as a substituent is used. A fluoro group may be used as a substituent. Alternatively, as a substituent, a compound containing at least hydrogen and a fluoro group may be used. Furthermore, even with a material having a low wettability surface, wettability can be further reduced by performing plasma treatment or the like.

  In the case where diffusion of the wiring material into the insulating layer becomes a problem, a conductive film functioning as a barrier may be formed before the wiring is formed. The conductive film only needs to cover the side wall of the opening in contact with the wiring material. For example, a catalytic material such as palladium (Pd) may be adsorbed on the side wall of the opening, and NiB may be formed by chemical plating.

  Next, the solution formed as the conductive layer 110a and the conductive layer 110b is dried by heat treatment. In this embodiment mode, tetradecane is evaporated by heat treatment at 150 ° C. for 10 minutes. After removing the mask layer 107a, the mask layer 107b, and the mask layer 107c, heat treatment at 230 ° C. for 1 hour is performed to advance the fusion of the silver nanoparticles, thereby forming the wiring layer 111a and the wiring layer 111b. The wiring layer 111 a is electrically connected to the wiring layer 101. If diffusion of the wiring material into the interlayer insulating film becomes a problem, a silicon nitride film may be formed by a CVD method. A multilayer wiring layer can be formed by repeating the above steps.

  In the case of forming a conductive layer by using a droplet discharge method, a conductive layer is formed by discharging a composition containing a conductive material processed into a particulate form and fusing or fusion-bonding and solidifying by firing. Since it adheres to a formation area by discharge, the composition containing a conductive material is formed including a solvent and conductive particles so as to have fluidity. In the conductive layer formed by discharging and baking the composition containing the conductive material in this manner, the conductive layer is not densely formed and has a defect, and an object to be formed (formable substance) In some cases, the adhesion to the insulating surface is low. Such poor adhesion causes a decrease in the reliability of a manufactured semiconductor device, display device, or the like.

  As the insulating layer used as the interlayer insulating layer, an insulating layer having holes (cavities, holes) in the layer or on the surface thereof can be used. The pores existing on the surface of the layer and inside the layer can fix the conductive material that has entered and filled with the particulate conductive material attached to the surface and solidified after firing. In this specification, a space in which such an insulating layer has a conductive material introduced into the surface of the layer or inside the layer and the solidified conductive layer can be fastened and fixed is generally referred to as a hole. The size of the hole is not limited as long as the particles of the conductive material discharged into the insulating layer can enter, and the effect that the conductive material is fixed to the surface of the insulating layer due to the presence of the hole (adhesion force, fixing force). (It may be called). Therefore, the size of the hole is a relative relationship between the opening of the hole and the particles of the conductive material to be discharged, and the size of the opening of the hole is the size of the particles contained in the conductive material. It should be larger than this. The shape of the hole may be irregular, and may be a shape having a curvature or a shape having a corner such as a needle as long as it has one or more openings through which the conductive material passes. A plurality of holes or a single hole may be included in the insulating layer, and some or all of the holes may be connected. The shape in which the particles of the conductive material filled in the holes are solidified reflects the shape of the holes. Therefore, in order for the solidified conductive layer to exert a wedge-like or wrinkle-like force on the insulating layer and to obtain an effect of improving the adhesion, the shape of the hole is more internal (from the hole opening). It is preferable that at least one place is larger toward the back. In addition, the hole has a complicated shape such as a constriction or a polygon having many surfaces, so that the conductive layer can be more firmly fixed, and the conductive layer can be prevented from being peeled off and removed.

  It is preferable that the insulating layer has a large number of holes because the ability to fix the conductive material is increased and the adhesion is also increased. Such a property having a large number of pores (voids) is referred to as porous, and a substance having a large number of pores is referred to as a porous material. The porous material is characterized by the proportion of the pores in the material (porosity), the pore size distribution, and the pore shape. The pore size differs depending on the substance, and those having a size of 2 nm or less are classified as micropores, those having a thickness of 2 to 50 nm are classified as mesopores, and those having a size of 50 nm or more are classified as macropores. The size of the hole may be selected to be larger than the particle of the conductive material to be attached so that the particle of the conductive material can enter the hole. In addition, the porous material includes a material called a microporous material to a porous material depending on the porosity. In the present invention, the insulating layer has a function of retaining a solidified conductive layer having pores. Any layer (film) can be used regardless of its porosity.

  There are two methods for the conductive material to enter the hole of the insulating layer: the case where the conductive material enters the hole in the insulating layer by capillary action, or the case where the ejected material is adsorbed depending on the electrical state of the layer surface. The invention is not limited to that method.

  FIG. 2B illustrates the case where an insulating layer having a hole is used for the insulating layer 124 which serves as an interlayer insulating layer and the insulating layer 122. Since the opening is formed by etching an interlayer insulating layer having fine holes, a large number of holes cross section appear on the side surface of the opening. The wiring layer formed in a later process enters the cross section of these holes and hardens, so that an anchor effect is generated, and the wiring layer has a high adhesion to the interlayer insulating layer.

  In the composition containing a liquid conductive material, the particles of the conductive material are filled in the plurality of holes of the insulating layer as indicated by the holes 123 and 125. The filled conductive material melts and aggregates inside the hole and solidifies in the shape of the hole in the subsequent drying and firing steps. The conductive layer inside the solidified hole plays a role like a wedge or a wrinkle with respect to the entire conductive layer 121a and the conductive layer 121b. Therefore, the conductive layer is in close contact with the insulating layer 124 and the insulating layer 122.

  In addition, as described above, the insulating layer having holes can keep the dielectric constant low. The porosity of the insulating layer having such holes is preferably 20 to 90%. When the dielectric constant is low, parasitic capacitance can be reduced, so that the semiconductor device can be driven at high speed.

  In this embodiment mode, the wiring layer 111a and the wiring layer 111b are formed using a droplet discharge unit. The droplet discharge means is a general term for a device having means for discharging droplets such as a nozzle having a composition discharge port and a head having one or a plurality of nozzles. The diameter of the nozzle provided in the droplet discharge means is set to 0.02 to 100 μm (preferably 30 μm or less), and the discharge amount of the composition discharged from the nozzle is 0.001 pl to 100 pl (preferably 0). .1pl or more and 40pl or less, more preferably 10pl or less). The discharge amount increases in proportion to the size of the nozzle diameter. In addition, the distance between the object to be processed and the nozzle outlet is preferably as close as possible in order to drop it at a desired location, preferably about 0.1 to 3 mm (preferably about 1 mm or less). Set.

  A composition in which a conductive material is dissolved or dispersed in a solvent is used as the composition discharged from the discharge port. The conductive material corresponds to one kind or plural kinds of fine particles or nanoparticles of a metal such as Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, and Al, and the conductive material includes Cd , Zn metal sulfides, oxides such as Fe, Ti, Si, Ge, Zr, and Ba, one or more kinds of fine particles such as silver halide, or dispersible nanoparticles may also be mixed. Further, it corresponds to indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), organic indium, organic tin, zinc oxide, titanium nitride, or the like used as a transparent conductive film. However, it is preferable to use a composition in which any of gold, silver and copper is dissolved or dispersed in a solvent in consideration of the specific resistance value, more preferably the composition discharged from the discharge port. It is preferable to use low resistance silver or copper. However, when silver or copper is used, a barrier film may be provided as a countermeasure against impurities. As the barrier film, a silicon nitride film or nickel boron (NiB) can be used.

  Alternatively, particles in which a conductive material is coated with another conductive material to form a plurality of layers may be used. For example, particles having a three-layer structure in which nickel boron (NiB) is coated around copper and silver is coated around it may be used. As the solvent, esters such as butyl acetate and ethyl acetate, alcohols such as isopropyl alcohol and ethyl alcohol, organic solvents such as methyl ethyl ketone and acetone are used. The viscosity of the composition is preferably 20 mPa · s or less, in order to prevent drying from occurring or to smoothly discharge the composition from the discharge port. The surface tension of the composition is preferably 40 mN / m or less. However, the viscosity and the like of the composition may be appropriately adjusted according to the solvent to be used and the application. As an example, the viscosity of a composition in which ITO, organic indium, or organic tin is dissolved or dispersed in a solvent is 5 to 20 mPa · s, the viscosity of a composition in which silver is dissolved or dispersed in a solvent is 5 to 20 mPa · s, The viscosity of the composition in which gold is dissolved or dispersed in a solvent is preferably set to 5 to 20 mPa · s.

  The conductive layer may be a stack of a plurality of conductive materials. Alternatively, first, silver may be used as a conductive material, and a conductive layer may be formed by a droplet discharge method, followed by plating with copper or the like. Plating may be performed by electroplating or chemical (electroless) plating. For plating, the substrate surface may be immersed in a container filled with a solution having a plating material, but the substrate is placed at an angle (or vertically) so that the solution having the material to be plated flows on the substrate surface. It may be applied. When plating is performed such that the solution is applied while standing the substrate, there is an advantage that the apparatus used in the process can be downsized even if the substrate is a large area.

  Although depending on the diameter of each nozzle and the desired pattern shape, the diameter of the conductor particles is preferably as small as possible for preventing nozzle clogging and producing a high-definition pattern. 1 μm or less is preferable. The composition is formed by a known method such as an electrolytic method, an atomizing method, or a wet reduction method, and its particle size is generally about 0.01 to 10 μm. However, when formed by a gas evaporation method, the nanomolecules protected by the dispersant are as fine as about 7 nm, and these nanoparticles are aggregated in the solvent when the surface of each particle is covered with a coating agent. And stably disperse at room temperature and shows almost the same behavior as liquid. Therefore, it is preferable to use a coating agent.

  When processing into a desired pattern shape by utilizing the difference in wettability between the composition having fluidity and the vicinity of the region to be formed, the composition has fluidity even when landing on the object to be treated. However, as long as the fluidity is not lost, the step of discharging the composition may be performed under reduced pressure. Further, it is preferable to perform under reduced pressure because an oxide film or the like is not formed on the surface of the conductor. After discharging the composition, one or both steps of drying and baking are performed. The drying and firing steps are both heat treatment steps. For example, drying is performed at 100 degrees (C) for 3 minutes, and firing is performed at 200 to 550 degrees (C) for 15 minutes to 60 minutes. Its purpose, temperature and time are different. The drying process and the firing process are performed under normal pressure or reduced pressure by laser light irradiation, rapid thermal annealing, a heating furnace, or the like. Note that the timing of performing this heat treatment and the number of heat treatments are not particularly limited. In order to carry out the drying and firing steps satisfactorily, the substrate may be heated, and the temperature at that time depends on the material such as the substrate, but is generally 100 to 800 ° C. (° C.) ( Preferably, it is set to 200 to 550 degrees (° C.). By this step, the solvent in the composition is volatilized or the dispersant is chemically removed, and the surrounding resin is cured and contracted to bring the nanoparticles into contact with each other, thereby accelerating fusion and fusion.

For the laser light irradiation, a continuous wave or pulsed gas laser or solid-state laser may be used. Examples of the former gas laser include an excimer laser and an ion laser, and examples of the latter solid-state laser include a laser using a crystal such as YAG, YVO ₄ , or GdVO ₄ doped with Cr, Nd, or the like. . Note that it is preferable to use a continuous wave laser because of the absorption rate of the laser light. In addition, a so-called hybrid laser irradiation method combining pulse oscillation and continuous oscillation may be used. However, depending on the heat resistance of the substrate, the heat treatment by laser light irradiation may be performed instantaneously within a few microseconds to several tens of seconds so that the substrate is not deformed or damaged. Instantaneous thermal annealing (RTA) uses an infrared lamp or a halogen lamp that irradiates ultraviolet light or infrared light in an inert gas atmosphere, and rapidly raises the temperature for several minutes to several microseconds. This is done by applying heat instantaneously. Since this treatment is performed instantaneously, only the outermost thin film can be heated substantially without affecting the lower layer film. That is, it does not affect a substrate having low heat resistance such as a plastic substrate.

  Alternatively, after the composition is discharged by a droplet discharge method to form a gate electrode layer or the like, the surface may be pressed and flattened by pressure in order to improve the flatness. As a pressing method, unevenness may be reduced by scanning a roller-like object on the surface, or the surface may be pressed vertically with a flat plate-like object. A heating step may be performed when pressing. Alternatively, the surface may be softened or melted with a solvent or the like, and the surface irregularities may be removed with an air knife. Further, polishing may be performed using a CMP method. This step can be applied when the surface is flattened when unevenness is generated by the droplet discharge method.

  According to the present invention, components can be formed with good controllability, material loss is small, and cost reduction can be achieved. Further, by using an insulating layer having holes, the conductive layers can be formed with good adhesion by the anchor effect. Therefore, a high-performance and highly reliable semiconductor device and display device can be manufactured with high yield.

(Embodiment 2)
In this embodiment mode, a process for forming a MOS transistor using a single crystal semiconductor substrate and a multilayer wiring structure including the MOS transistor will be described with reference to FIGS.

  An element isolation region 151a, an element isolation region 151b, and an element isolation region 151c are formed on the substrate 150. The substrate 150 is a single crystal semiconductor substrate or a compound semiconductor substrate, and is typically an n-type or p-type single crystal silicon substrate, GaAs substrate, InP substrate, GaN substrate, SiC substrate, sapphire substrate, ZnSe substrate, or the like. Is mentioned. An SOI substrate (Silicon On Insulator) can also be used. In this embodiment, a single crystal silicon substrate is used as the substrate 150. For the element isolation region 151a, the element isolation region 151b, and the element isolation region 151c, a known selective oxidation method (LOCOS (Local Oxidation of Silicon) method), a trench isolation method, or the like can be used as appropriate. Here, as the element isolation region 151a, the element isolation region 151b, and the element isolation region 151c, part of a silicon substrate is oxidized by a LOCOS method to form a silicon oxide film. Thereafter, well ion implantation, channel stop ion implantation, and threshold adjustment ion implantation are appropriately performed.

  Next, the surface of the substrate 150 is washed to expose the substrate surface 150. Next, an insulating film serving as a gate insulating layer is formed over the substrate 150, the element isolation region 151a, the element isolation region 151b, and the element isolation region 151c. A conductive film to be a gate electrode layer is formed over the insulating film. As the insulating film, a silicon oxide film or a silicon nitride film can be used. Alternatively, a stacked structure of a silicon oxide film, a silicon nitride film, or a stacked structure of a silicon oxide film, a silicon nitride film, a silicon oxide film, or the like may be used from the substrate 150 side. In this embodiment, a silicon oxide film and a silicon nitride film are stacked as the insulating film. The conductive film can be formed by a known method such as sputtering, vapor deposition, or CVD. The conductive film is an element selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), and neodymium (Nd). Or an alloy material or a compound material containing these elements as main components. Alternatively, a semiconductor film to which an impurity element is added can be used. The conductive film and the insulating film are processed into desired shapes, so that the gate electrode layer 153a, the gate electrode layer 153b, the gate insulating layer 152a, and the gate insulating layer 152b are formed.

  Next, after an insulating layer covering the gate electrode layer 153a, the gate electrode layer 153b, the gate insulating layer 152a, the gate insulating layer 152b, and the like is formed, this is anisotropically formed by RIE (Reactive Ion Etching). The gate electrode layer 153a, the gate electrode layer 153b, the gate insulating layer 152a, and the sidewalls of the gate insulating layer 152b are sidewalls (sidewall spacers) 154a, sidewalls 154b, sidewalls 154c, and sidewalls in a self-aligned manner. 154d is formed. Here, there is no particular limitation on the insulating layer, and the insulating layer may be silicon oxide with good step coverage formed by reacting TEOS (Tetra-Ethyl-Orso-Silicate) or silane with oxygen or nitrous oxide. preferable. The insulating layer can be formed by a method such as thermal CVD, plasma CVD, atmospheric pressure CVD, bias ECRCVD, or sputtering.

  Using the gate electrode layer 153a, the gate electrode layer 153b, the gate insulating layer 152a, the gate insulating layer 152b, the sidewall 154a, the sidewall 154b, the sidewall 154c, and the sidewall 154d as masks, an impurity element is added to the substrate 150 in a self-aligning manner. To do. Next, the impurity element is activated by heat treatment, a GRTA method, an LRTA method, or the like, so that a source region or drain region 155a, a source region or drain region 155b, a source region or drain region 155c, a source region or drain region 155d, A source or drain region 156a, a source or drain region 156b, a source or drain region 156c, and a source or drain region 156d are formed. The source region or drain region 155a, the source region or drain region 155b, the source region or drain region 155c, and the source region or drain region 155d are higher concentration impurity regions, and the source region or drain region 156a, the source region or drain region 156b The source or drain region 156c and the source or drain region 156d are lower concentration impurity regions. If p-type boron (B) or the like is an impurity element, it becomes a p-type impurity region, and if it is an impurity element such as phosphorus (P) that is an n-type impurity region, it becomes an n-type impurity region. In this embodiment mode, in order to manufacture an n-type MOS transistor, phosphorus which is an impurity element imparting n-type conductivity is doped to form an n-type impurity region.

  An insulating layer 157 is formed so as to cover the element isolation region, the gate electrode layer, the sidewall, and the like (see FIG. 3A). In this embodiment, the insulating layer 157 is formed using an insulating film containing silicon by a plasma CVD method or a sputtering method. The insulating layer 157 is not limited to a silicon nitride film, and may be a silicon nitride oxide (SiNO) film using plasma CVD, or an insulating film containing other silicon may be used as a single layer or a stacked structure.

  The insulating layer 157 includes silicon nitride, silicon oxide, silicon oxynitride (SiON), silicon nitride oxide (SiNO), aluminum nitride (AlN), aluminum oxynitride (AlON), and aluminum nitride oxide having a nitrogen content higher than the oxygen content. (AlNO) or aluminum oxide, diamond-like carbon (DLC), and a material selected from substances including a nitrogen-containing carbon film (CN). Further, a siloxane resin may be used. Note that the siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  Next, an insulating layer 180 to be an interlayer insulating film is formed. In the present invention, an interlayer insulating film provided for planarization is required to have high heat resistance and insulation and a high planarization rate. As a method for forming such an insulating layer, a coating method typified by a spin coating method is preferably used.

  In this embodiment, the material of the insulating layer 180 is a compound having a skeleton structure formed of a bond of silicon (Si) and oxygen (O) and containing at least hydrogen as a substituent (for example, an alkyl group or an aromatic hydrocarbon). ) Is used. A fluoro group may be used as a substituent. Alternatively, as a substituent, a compound containing at least hydrogen and a fluoro group may be used. The film after baking can be called a silicon oxide film (SiOx) containing an alkyl group. This silicon oxide (SiOx) film containing an alkyl group can withstand heat treatment at 300 ° C. or higher.

  The insulating layer 180 can employ dipping, spray coating, spin coating, doctor knife, roll coater, curtain coater, knife coater, CVD method, vapor deposition method, or the like. The insulating layer 180 may be formed by a droplet discharge method. When the droplet discharge method is used, the material liquid can be saved. Further, a method capable of transferring or drawing a pattern, such as a droplet discharge method, for example, a printing method (a method for forming a pattern such as screen printing or offset printing) or the like can be used. In addition, an inorganic material may be used. In that case, silicon oxide, silicon nitride, or silicon oxynitride can be used.

  The insulating layer 180 can be an inorganic material (silicon oxide) as long as it has high heat resistance and good planarity in addition to an insulating film having a skeleton structure formed of a bond of silicon (Si) and oxygen (O). , Silicon nitride, silicon oxynitride, silicon nitride oxide, PSG (phosphorus glass), BPSG (phosphorus boron glass), alumina film, etc.), photosensitive or non-photosensitive organic material (organic resin material) (polyimide, acrylic, polyamide) , Polyimide amide, resist, benzocyclobutene, etc.), a low dielectric constant material, or a film made of a plurality of types, or a laminate of these films.

  An insulating layer 181 and an insulating layer 182 are stacked over the insulating layer 180. In this embodiment mode, since the insulating layer 181 is used as an etching stopper when the insulating layer 182 is processed into a desired shape, it is desirable that the insulating layer 181 and the insulating layer 182 have a high selection ratio during etching. The insulating layer 181 may be formed using the same material and process as the insulating layer 157, and the insulating layer 182 may be formed using the same material and process as the insulating layer 181. As described in Embodiment 1, when an insulating layer having a hole is used for the insulating layer 180, the insulating layer 181, and the insulating layer 182, a part of the conductive layer attached to the insulating layer is formed inside the hole. Since it has a wedge-like effect on the insulating layer (anchor effect), the adhesion is improved.

  An opening reaching the source region or the drain region is formed in the insulating layer 157, the insulating layer 180, the insulating layer 181, and the insulating layer 182 by etching. In this embodiment, first, first openings are formed in the insulating layer 157, the insulating layer 180, the insulating layer 181, and the insulating layer 182, and then the mask layer 158a, the mask layer 158b, the mask layer 158c, the mask layer 158d, A mask layer 158e is formed, and a second opening is formed in the insulating layer 182 so as to widen the first opening by using the insulating layer 181 as an etching stopper. The cross section in the film thickness direction of the first opening and the second opening is like the opening 159a, the opening 159b, the opening 159c, and the opening 159d in FIG. The side surfaces of the insulating layer 181 and the insulating layer 182 facing each other are discontinuous and have a stepped shape.

Next, the surfaces of the mask layer 158a, the mask layer 158b, the mask layer 158c, the mask layer 158d, and the mask layer 158e are regions having low wettability with respect to the composition containing a liquid conductive material formed in the opening. Such processing is performed. In this embodiment mode, plasma treatment is performed in a gas atmosphere containing fluorine to replace the C—H bond on the surface of the mask layer with the C—F bond, thereby reducing the surface energy of the mask layer surface. In this embodiment mode, plasma treatment is performed in a mixed gas atmosphere of CF ₄ and O ₂ . The region with low wettability becomes a liquid repellent region depending on the liquid and repels the liquid, so that the droplet cannot adhere to the region with low wettability. The composition containing the liquid conductive material does not adhere to the mask surface having low wettability with respect to the composition, or does not become stable even if it adheres to the relatively wettable opening. Filled. Thus, since the composition containing the conductive material is filled, the wiring layer can be stably formed with good controllability, and loss of the material can be prevented. Therefore, the composition containing a conductive material discharged by the droplet discharge device 160 has a low wettability region 161a, a low wettability region 161b, a low wettability region 161c, a low wettability region 161d, and a low wettability on the mask layer surface. The conductive region 161e is repelled and does not adhere to the opening 159a, the opening 159b, the opening 159c, and the opening 159d, so that the conductive layer 162a, the conductive layer 162b, the conductive layer 162c, and the conductive layer 162d are formed. The conductive layer 162a, the conductive layer 162b, the conductive layer 162c, and the conductive layer 162d are solidified by drying and baking, and then a source or drain electrode layer 163a, a source or drain electrode layer 163b, a source or drain electrode layer 163c, A source or drain electrode layer 163d is formed. Accordingly, the MOS transistor 170a and the MOS transistor 170b are manufactured (see FIG. 3D).

  As described above, when a material having low wettability with respect to the composition is formed only in the non-formation region, and the region having lower wettability (hereinafter also referred to as the low wettability region) is formed, the formation region is relatively wetted. It becomes an area | region (henceforth a highly wettability area | region) with high property. The discharged composition containing the liquid conductive material is repelled in the low wettability region and is formed in a self-aligned manner only in the formation region with good controllability.

  A region having different wettability means that the contact angle of a composition containing a conductive material is different, a region having a large contact angle of a composition containing a conductive material is a low wettability region, and a region having a small contact angle is High wettability area. When the contact angle is large, the liquid composition having fluidity does not spread on the surface of the region and repels the composition, so that the surface is not wetted. However, when the contact angle is small, the composition has fluidity on the surface. Because it spreads out and wets the surface well. Therefore, regions having different wettability also have different surface energies. The surface energy of the surface in the region with low wettability is small, and the surface energy at the surface of the region with high wettability is large. In addition, a low wettability region for a certain liquid is a region in which it is difficult to stably keep the liquid in that region, and the behavior of the droplet surface changes depending on the degree of wettability. When the wettability is low and the region has high liquid repellency (the region with lower wettability with respect to droplets, also referred to as a liquid repellent region), the region completely repels liquid. In this specification, by selectively controlling the wettability between the non-formation region and the formation region, it is only necessary to obtain the effect of forming a stable conductive layer in the formation region. Of course, the non-formation region is preferably a complete liquid repellent region, and the conductive layer can be formed with better controllability. Further, the wettability may be only on the surface that is in contact with the liquid droplet and is retained, and it is not always necessary to have the same property throughout the film thickness direction.

  An example in which a multilayer wiring is formed on the MOS transistor formed in FIG. 3 will be described with reference to FIG. An insulating layer 165, an insulating layer 166, and an insulating layer 167 are stacked over the MOS transistor manufactured in FIG. 3, and a source or drain electrode layer 163a, a source or drain electrode layer 163b, and a source or drain electrode layer are stacked. 163c, an opening reaching the source or drain electrode layer 163d is formed. The insulating layer 165, the insulating layer 166, the insulating layer 167, and the opening may be formed in the same manner as the insulating layer 180, the insulating layer 181, the insulating layer 182, the opening 159a, the opening 159b, the opening 159c, and the opening 159d. . The surface of the mask layer for forming the opening is processed so as to be a low wettability region for the composition containing a liquid conductive material. In this embodiment mode, plasma treatment is performed in a gas atmosphere containing fluorine.

  The region with low wettability becomes a liquid repellent region depending on the liquid and repels the liquid, so that the droplet cannot adhere to the region with low wettability. The composition containing the liquid conductive material does not adhere to the surface of the mask layer having low wettability with respect to the composition, or does not become stable even if it adheres to the relatively wettable opening. And filled. Thus, since the composition containing the conductive material is filled, the wiring layer can be stably formed with good controllability, and loss of the material can be prevented. Therefore, the composition containing a conductive material discharged by the droplet discharge device 169 has a low wettability region 168a, a low wettability region 168b, a low wettability region 168c, a low wettability region 168d, and a low wettability on the mask layer surface. The conductive regions 168e are repelled and do not adhere to each other, and are filled in the respective openings to become a conductive layer 171a, a conductive layer 171b, a conductive layer 171c, and a conductive layer 171d (see FIG. 4A). The conductive layer 171a, the conductive layer 171b, the conductive layer 171c, and the conductive layer 171d are solidified by drying and baking, so that the wiring layer 172a, the wiring layer 172b, the wiring layer 172c, and the wiring layer 172d are formed. Accordingly, a multilayer wiring layer including the MOS transistor 170a and the MOS transistor 170b is manufactured (see FIG. 4B).

  In the present invention, the conductive layer is formed by attaching a composition containing a liquid conductive material to a formation region and then solidifying the composition. Therefore, the shape filled or attached in a liquid state still has fluidity, and the shape of the conductive layer may change when solidified later. This change in shape affects the place filled as a fluid and the firing temperature and time when solidifying. Therefore, when an insulating layer having holes is used for the insulating layer serving as an interlayer film, the conductive particles fill the holes and are solidified by fusion and solidification. The conductive layer filled and solidified inside these holes functions like a wedge and a wrinkle, increases the adhesion between the conductive layer and the insulating layer, and improves the adhesion. In this embodiment, the conductive layer 162a, the conductive layer 162b, the conductive layer 162c, and the conductive layer 162d are solidified to form a source or drain electrode layer 163a, a source or drain electrode layer 163b, and a source or drain electrode layer. In 163c, the source electrode layer or the drain electrode layer 163d, the solvent is dried, so that the central portion of the surface of the conductive layer is dented. However, such a change in shape can vary depending on the shape and size of the particles of the conductive material, the characteristics of the material such as the solvent, and the production conditions such as the temperature and time of formation. On the other hand, when the conductive layer 171a is solidified to become the wiring layer 172a, the surface of the wiring layer is almost flat, and the wiring layer surface may have a convex shape depending on conditions.

  According to the present invention, the wiring material can be formed only in the opening without a step of removing unnecessary wiring material such as CMP, and the multilayer wiring forming process can be further simplified. Further, since it is not necessary to remove the wiring material, the utilization efficiency of the wiring material is high and the cost can be reduced. In addition, a conductive material is formed in the opening by pouring a solution in which the conductive material is dissolved or dispersed in a solvent, drying the solvent by heat treatment, and fusing the conductive material to form the conductive material. Since a solution is used, it is possible to fabricate a highly reliable wiring structure with high embedding of connection holes and no voids. Therefore, by using such a wiring structure, a highly reliable semiconductor device can be manufactured with high productivity and low cost.

(Embodiment 3)
FIG. 25A is a top view illustrating a structure of a display panel according to the present invention. A pixel portion 2701 in which pixels 2702 are arranged in a matrix over a substrate 2700 having an insulating surface, a scan line side input terminal 2703, a signal A line side input terminal 2704 is formed. The number of pixels may be provided in accordance with various standards, and the number of pixels in the case of XGA and RGB full-color display may be 1024 × 768 × 3. Similarly, in the case of UXGA and RGB full-color display, it may be 1600 × 1200 × 3, and in the case of full-spec high vision and RGB full-color display, it may be 1920 × 1080 × 3.

  The pixels 2702 are arranged in a matrix by a scan line extending from the scan line side input terminal 2703 and a signal line extending from the signal line side input terminal 2704 intersecting. Each of the pixels 2702 includes a switching element and a pixel electrode connected to the switching element. A typical example of the switching element is a TFT. By connecting the gate electrode side of the TFT to a scanning line and the source or drain side to a signal line, each pixel can be controlled independently by a signal input from the outside. Yes.

  FIG. 25A shows the structure of a display panel in which signals input to the scan lines and signal lines are controlled by an external driver circuit. As shown in FIG. 22A, COG (Chip on The driver IC 2751 may be mounted on the substrate 2700 by a glass method. As another mounting mode, a TAB (Tape Automated Bonding) method as shown in FIG. 22B may be used. The driver IC may be formed on a single crystal semiconductor substrate or may be a circuit in which a TFT is formed on a glass substrate. In FIG. 22, the driver IC 2751 is connected to the FPC 2750.

  In the case where a TFT provided for a pixel is formed using a polycrystalline (microcrystalline) semiconductor with high crystallinity, a scan line driver circuit 3702 may be formed over the substrate 3700 as illustrated in FIG. it can. In FIG. 22B, reference numeral 2701 denotes a pixel portion, and the signal line side driver circuit is controlled by an external driver circuit as in FIG. In the case where a TFT provided for a pixel is formed using a polycrystalline (microcrystalline) semiconductor, a single crystal semiconductor, or the like with high mobility like the TFT formed in the present invention, as shown in FIG. The driver circuit 4702 and the signal line driver circuit 4704 can be formed over the glass substrate 4700 integrally. Note that in FIG. 25C, reference numeral 4701 denotes a pixel portion.

  FIG. 5 is a top view of a pixel region of a display device manufactured in this embodiment mode, and FIGS. 6 to 9 and FIG. 10B are cross sections taken along lines AC and BD in FIG. FIG. 6 to 9 is a cross-sectional view corresponding to a line IJ which is a peripheral driver circuit region of the display device in FIG.

  As the substrate 300, a glass substrate made of barium borosilicate glass, alumino borosilicate glass, or the like, a quartz substrate, a metal substrate, or a plastic substrate having heat resistance that can withstand the processing temperature in this manufacturing process is used. Further, polishing may be performed by a CMP method or the like so that the surface of the substrate 300 is planarized. Note that an insulating layer may be formed over the substrate 300. The insulating layer is formed as a single layer or a stacked layer using an oxide material or a nitride material containing silicon by a known method such as a CVD method, a plasma CVD method, a sputtering method, or a spin coating method. This insulating layer is not necessarily formed, but has an effect of blocking contaminants from the substrate 300.

  A conductive film is formed over the substrate 300 and processed into a desired shape using a resist mask, so that the gate electrode layer 301, the gate electrode layer 302, the gate electrode layer 303, the gate electrode layer 360a, and the gate electrode layer 360b are formed. The gate electrode layer 301, the gate electrode layer 302, the gate electrode layer 303, the gate electrode layer 360a, and the gate electrode layer 360b can be formed by a CVD method, a sputtering method, a droplet discharge method, or the like. The gate electrode layer 301, the gate electrode layer 302, the gate electrode layer 303, the gate electrode layer 360a, and the gate electrode layer 360b are formed of Ag, Au, Ni, Pt, Pd, Ir, Rh, Ta, W, Ti, Mo, Al, An element selected from Cu or an alloy material or compound material containing the element as a main component may be used. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used. Alternatively, a single-layer structure or a multi-layer structure may be used, for example, a two-layer structure of a tungsten nitride (WN) film and a molybdenum (Mo) film, a tungsten film with a thickness of 50 nm, aluminum with a thickness of 500 nm, and A three-layer structure in which a silicon alloy (Al—Si) film and a titanium nitride film with a thickness of 30 nm are sequentially stacked may be employed. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or aluminum instead of the aluminum and silicon alloy (Al-Si) film of the second conductive film. A titanium alloy film (Al—Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film.

When the gate electrode layer 301, the gate electrode layer 302, the gate electrode layer 303, the gate electrode layer 360a, and the gate electrode layer 360b need to be processed, a mask is formed and processed into a desired shape by dry etching or wet etching. That's fine. Using an ICP (Inductively Coupled Plasma) etching method, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the electrode temperature on the substrate side, etc.) are appropriately set. By adjusting, the electrode layer can be etched into a tapered shape. As an etching _gas, using Cl _2, BCl 3, SiCl ₄ or a chlorine-based gas typified by CCl _4, fluorine-based gas or _{O 2} and typified by CF 4, SF ₆ or NF ₃ as appropriate be able to.

  A mask for processing into a desired shape can be formed by selectively discharging a composition. When the mask is selectively formed in this way, there is an effect that the process of processing the shape of the mask is simplified. For the mask, a resin material such as an epoxy resin, a phenol resin, a novolac resin, an acrylic resin, a melamine resin, or a urethane resin is used. Also, using organic materials such as benzocyclobutene, parylene, flare, permeable polyimide, compound materials made by polymerization of siloxane polymers, composition materials containing water-soluble homopolymers and water-soluble copolymers, etc. And formed by a droplet discharge method. Alternatively, a commercially available resist material containing a photosensitizer may be used. For example, a novolak resin that is a typical positive resist and a naphthoquinonediazide compound that is a photosensitizer, a base resin that is a negative resist, diphenylsilanediol, and An acid generator or the like may be used. Whichever material is used, the surface tension and viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant or the like.

  In this embodiment mode, when a mask layer for processing into a desired shape is formed by a droplet discharge method, as a pretreatment, a region having different wettability may be formed in the vicinity of a formation region. Good. In the present invention, when forming a composition such as a conductive layer or an insulating layer by discharging a droplet by a droplet discharge method, a low wettability region or a high wettability region with respect to the forming material is formed in a region where the component is formed. And the shape of the formed product can be controlled. By performing this process on the formation region, there is a difference in wettability in the formation region, so that droplets remain only in the formation region with high wettability, and a formed product can be formed in a desired pattern with good controllability. it can. This step can be applied as a pretreatment of any formed material (insulating layer, conductive layer, mask layer, wiring layer, etc.) when a liquid material is used.

  In order to form a gate insulating layer over the gate electrode layer 301, the gate electrode layer 302, the gate electrode layer 303, the gate electrode layer 360a, and the gate electrode layer 360b, and to form a semiconductor layer over the gate insulating layer, an amorphous semiconductor film 306 is formed.

  The gate insulating layer may be formed of a material such as a silicon oxide material or a nitride material, and may be a stacked layer or a single layer. Alternatively, a single layer of silicon oxynitride film or a stacked layer including a plurality of layers may be used. A silicon nitride film having a dense film quality is preferably used. In addition, when silver or copper is used for a conductive layer formed by a droplet discharge method, if a silicon nitride film or a NiB film is formed thereon as a barrier film, diffusion of impurities can be prevented and the surface can be planarized. is there. Note that in order to form a dense insulating film with low gate leakage current at a low deposition temperature, a rare gas element such as argon is preferably contained in the reaction gas and mixed into the formed insulating film.

A semiconductor layer having one conductivity type may be formed as necessary. In addition, an n-type semiconductor layer is formed, an NMOS structure of an N-channel TFT, a PMOS structure of a P-channel TFT formed with a p-type semiconductor layer, and a CMOS structure of an N-channel TFT and a P-channel TFT. Can be produced. In order to impart conductivity, an element imparting conductivity is added by doping, and an impurity region is formed in the semiconductor layer, whereby an N-channel TFT or a P-channel TFT can be formed. Instead of forming an N-type semiconductor layer, conductivity may be imparted to the semiconductor layer by performing plasma treatment with a PH ₃ gas.

  As a material for forming the semiconductor layer, an amorphous semiconductor (hereinafter also referred to as “AS”) manufactured by a vapor deposition method or a sputtering method using a semiconductor material gas typified by silane or germane is used. A polycrystalline semiconductor crystallized using energy or thermal energy, a semi-amorphous (also referred to as microcrystal or microcrystal, hereinafter, also referred to as “SAS”) semiconductor, or the like can be used. The semiconductor layer can be formed by a known means (such as sputtering, LPCVD, or plasma CVD).

SAS is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal) and having a third state that is stable in terms of free energy and has a short-range order and a lattice. It includes a crystalline region with strain. A crystal region of 0.5 to 20 nm can be observed in at least a part of the film, and when silicon is a main component, the Raman spectrum is shifted to a lower wave number side than 520 cm ^−1. Yes. In X-ray diffraction, diffraction peaks of (111) and (220) that are derived from the silicon crystal lattice are observed. In order to terminate dangling bonds (dangling bonds), hydrogen or halogen is contained at least 1 atomic% or more. The SAS is formed by glow discharge decomposition (plasma CVD) of a gas selected from SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , and SiF ₄ . Further, to these gases may be mixed _{F 2, GeF 4, H 2} , or, _{H 2} and the He, Ar, Kr, diluted with one or more rare gas elements selected from Ne Also good. The dilution rate is in the range of 2 to 1000 times, the pressure is in the range of approximately 0.1 Pa to 133 Pa, and the power supply frequency is 1 MHz to 120 MHz, preferably 13 MHz to 60 MHz. The substrate heating temperature is preferably 300 ° C. or lower, and can be formed even at a substrate heating temperature of 100 to 200 ° C. Here, as an impurity element mainly taken in at the time of film formation, impurities derived from atmospheric components such as oxygen, nitrogen, and carbon are preferably 1 × 10 ²⁰ cm ⁻³ or less, and in particular, the oxygen concentration is 5 × 10 5. It is preferable to be ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ⁻³ or less. Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, stability is improved and a favorable SAS can be obtained. In addition, a SAS layer formed of a hydrogen-based gas may be stacked on a SAS layer formed of a fluorine-based gas as a semiconductor layer.

  A typical example of an amorphous semiconductor is hydrogenated amorphous silicon, and a typical example of a crystalline semiconductor is polysilicon. Polysilicon (polycrystalline silicon) is mainly made of so-called high-temperature polysilicon using polysilicon formed through a process temperature of 800 ° C. or higher as a main material, or polysilicon formed at a process temperature of 600 ° C. or lower. And so-called low-temperature polysilicon, and polysilicon crystallized by adding an element that promotes crystallization. Of course, as described above, a semi-amorphous semiconductor or a semiconductor including a crystal phase in a part of the semiconductor layer can also be used.

In the case where a crystalline semiconductor layer is used for the semiconductor layer, a method for manufacturing the crystalline semiconductor layer can be a known method (laser crystallization method, thermal crystallization method, or heat using an element that promotes crystallization such as nickel. A crystallization method or the like may be used. In addition, a microcrystalline semiconductor that is a SAS can be crystallized by laser irradiation to improve crystallinity. In the case where an element for promoting crystallization is not introduced, the amorphous silicon film is heated at 500 ° C. for 1 hour in a nitrogen atmosphere before irradiating the amorphous silicon film with laser light, whereby the concentration of hydrogen contained in the amorphous silicon film is set to 1 ×. Release to 10 ²⁰ atoms / cm ³ or less. This is because the film is destroyed when the amorphous silicon film containing a large amount of hydrogen is irradiated with laser light.

  The method of introducing the metal element into the amorphous semiconductor layer is not particularly limited as long as the metal element can be present on the surface of the amorphous semiconductor layer or inside the amorphous semiconductor layer. For example, sputtering, CVD, A plasma treatment method (including a plasma CVD method), an adsorption method, or a method of applying a metal salt solution can be used. Among these, the method using a solution is simple and useful in that the concentration of the metal element can be easily adjusted. At this time, in order to improve the wettability of the surface of the amorphous semiconductor layer and to spread the aqueous solution over the entire surface of the amorphous semiconductor layer, irradiation with UV light in an oxygen atmosphere, thermal oxidation method, hydroxy radical It is desirable to form an oxide film by treatment with ozone water or hydrogen peroxide.

  The crystallization of the amorphous semiconductor layer may be a combination of heat treatment and crystallization by laser light irradiation, or may be performed multiple times by heat treatment or laser light irradiation alone.

  Alternatively, the crystalline semiconductor layer may be directly formed over the substrate by a linear plasma method. Alternatively, the crystalline semiconductor layer may be selectively formed over the substrate by a linear plasma method.

  As a semiconductor, an organic semiconductor material can be used and formed by a printing method, a spray method, a spin coating method, a droplet discharge method, or the like. In this case, the number of processes can be reduced because the etching process is not necessary. As the organic semiconductor, a low molecular material, a polymer material, or the like is used, and materials such as an organic dye or a conductive polymer material can also be used. The organic semiconductor material used in the present invention is preferably a π-electron conjugated polymer material whose skeleton is composed of conjugated double bonds. Typically, a soluble polymer material such as polythiophene, polyfluorene, poly (3-alkylthiophene), a polythiophene derivative, or pentacene can be used.

  In addition, as an organic semiconductor material that can be used in the present invention, there is a material that can form a semiconductor layer by processing after forming a soluble precursor. Examples of the organic semiconductor material that passes through such a precursor include polythienylene vinylene, poly (2,5-thienylene vinylene), polyacetylene, a polyacetylene derivative, and polyarylene vinylene.

  When converting the precursor into an organic semiconductor, a reaction catalyst such as hydrogen chloride gas is added as well as heat treatment. Typical solvents for dissolving these soluble organic semiconductor materials include toluene, xylene, chlorobenzene, dichlorobenzene, anisole, chloroform, dichloromethane, γ-butyllactone, butyl cellosolve, cyclohexane, NMP (N-methyl-2 -Pyrrolidone), cyclohexanone, 2-butanone, dioxane, dimethylformamide (DMF), THF (tetrahydrofuran), or the like can be applied.

  In this embodiment, a gate insulating layer 305a made of silicon nitride and a gate insulating layer 305b made of silicon oxide are stacked as the gate insulating layer. As the amorphous semiconductor film 306, an amorphous silicon film is used. The gate insulating layer 305a, the gate insulating layer 305b, and the amorphous semiconductor film 306 are continuously formed by plasma CVD only by switching the gas type. By forming continuously, a process is simplified and it can prevent that the pollutant in air | atmosphere adheres to the film | membrane surface and an interface.

After removing the oxide film formed on the amorphous semiconductor film, the oxide film is made 1 by irradiation with UV light in an oxygen atmosphere, a thermal oxidation method, treatment with ozone water containing hydrogen radicals or hydrogen peroxide, and the like. Form ~ 5 nm. In this embodiment, an aqueous solution containing 30 ppm of Ni is applied to the amorphous semiconductor film 306 by a spin coating method to form a metal film 307 (see FIG. 6A). An aqueous solution containing 10 ppm to 100 ppm (preferably 10 ppm to 50 ppm) of Ni element may be applied by spin coating. Elements that promote crystallization include iron (Fe), nickel (Ni), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), and platinum. The metal film 307 can be formed using one or a plurality of types selected from (Pt), copper (Cu), and gold (Au). The metal film 307 has an extremely thin film thickness depending on the formation conditions, and does not have to maintain the form as a film. It may be formed in contact with the amorphous semiconductor film 306 so that an effect of promoting crystallization can be obtained.
Next, the amorphous semiconductor film 306 is heated to form a crystalline semiconductor film 309. In this case, in crystallization, silicide is formed in a portion of the semiconductor film in contact with a metal element that promotes crystallization of the semiconductor, and crystallization proceeds using the silicide as a nucleus. Here, after the heat treatment for dehydrogenation, heat treatment for crystallization (at 550 ° C. to 750 ° C. for 3 minutes to 24 hours) is performed. Further, crystallization may be performed by RTA or GRTA. Here, when crystallization is performed without laser light irradiation for heating, variation in crystallinity can be reduced, and variation in TFTs to be formed later can be suppressed. In this embodiment, heat treatment is performed at 550 ° C. for 8 hours, so that the crystalline semiconductor film 309 is formed.

The crystalline semiconductor film 309 thus obtained may be doped with a trace amount of an impurity element (boron or phosphorus) in order to control the threshold voltage of the thin film transistor. This doping of the impurity element may be performed on the amorphous semiconductor film before the crystallization process, or may be performed after the metal element in the crystalline semiconductor film 309 is reduced and removed by the gettering process. In this embodiment mode, boron is added by an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation. Note that an ion implantation method in which mass separation is performed may be used. When the impurity element is doped in the state of the amorphous semiconductor film, the impurity can be activated by heat treatment for subsequent crystallization. In addition, defects and the like generated during doping can be improved.

  A semiconductor film having an impurity element imparting one conductivity type is formed over the crystalline semiconductor film. As the impurity element, an impurity element imparting n-type conductivity, an impurity element imparting p-type conductivity, a rare gas element, or the like can be used. For example, phosphorus (P), nitrogen (N), arsenic (As), antimony (Sb) , Bismuth (Bi), boron (B), helium (He), neon (Ne), argon (Ar), Kr (krypton), or Xe (xenon) can be used. The n-type semiconductor layer containing an impurity element imparting n-type conductivity can be formed so as to contain a rare gas element such as argon.

In this embodiment, an n-type semiconductor film 308 is formed over the crystalline semiconductor film 309 (see FIG. 6B). In this embodiment, as the semiconductor film 308 having n-type, an amorphous silicon film containing phosphorus (P) as an impurity element imparting n-type is formed to a thickness of 100 nm by a plasma CVD method. Heat treatment is performed using the n-type semiconductor film 308 as a gettering sink, so that the metal element in the crystalline semiconductor film 309 is gettered (see FIG. 6C). In this embodiment, heat treatment is performed at 550 ° C. for 4 hours. The metal element in the crystalline semiconductor film 309 moves in the direction of the arrow by heat treatment, and is captured in the n-type semiconductor film 308. By this step, the concentration at which the element that promotes crystallization in the crystalline semiconductor film (in this embodiment, nickel element) does not affect the device characteristics, that is, the nickel concentration in the film is 1 × 10 ¹⁸ / cm ³ or less. Desirably, it can be 1 × 10 ¹⁷ / cm ³ or less. Therefore, the crystalline semiconductor film 309 becomes the crystalline semiconductor film 310 in which the metal element in the film is reduced, and the n-type semiconductor film 308 includes an impurity element imparting n-type (P in this embodiment). An n-type semiconductor film 311 containing a metal element (Ni in this embodiment) is formed. In addition, the n-type semiconductor film 308 to which the metal element after gettering has moved may be crystallized by heat treatment. Note that in this embodiment, an impurity element imparting n-type (donor-type element) in the n-type semiconductor film 308 is activated along with the gettering step.

  As for the semiconductor film having one conductivity type, a semiconductor film containing a low concentration of an impurity element, a semiconductor film containing a high concentration of an impurity element, and two semiconductor films having different impurity concentrations may be stacked from the crystalline semiconductor film side. In this case, the semiconductor film containing the impurity element at a low concentration functions as an LDD region, and the semiconductor film containing the impurity element at a high concentration functions as a source region or a drain region.

  The crystalline semiconductor film 310 and the n-type semiconductor film 311 are processed into a desired shape, and the semiconductor layer 312, the semiconductor layer 313, the semiconductor layer 314, the semiconductor layer 361, the n-type semiconductor layer 315, and the n-type semiconductor are processed. The layer 316, the n-type semiconductor layer 317, and the n-type semiconductor layer 362 can be formed (see FIG. 7A).

  As the photomask, a resist may be selectively formed by whole surface application by spin coating or the like, or a droplet discharge method, and a fine pattern mask may be formed by exposure by laser light irradiation. The semiconductor film can be finely and finely processed into a desired shape with a fine pattern mask.

  When the mask is formed by selectively discharging the composition without performing exposure processing, a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, or a urethane resin can be used. Also, using organic materials such as benzocyclobutene, parylene, flare, permeable polyimide, compound materials made by polymerization of siloxane polymers, composition materials containing water-soluble homopolymers and water-soluble copolymers, etc. And formed by a droplet discharge method. Whichever material is used, the surface tension and viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant or the like.

Either plasma etching (dry etching) or wet etching may be employed as the etching process when processing into a desired shape, but plasma etching is suitable for processing a large area substrate. As an etching gas, a fluorine-based gas such as CF ₄ , NF ₃ , SF ₆ , or CHF ₃ , a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl _4, CCl _4, or the like, or an O ₂ gas is used. An inert gas such as Ar or Ar may be added as appropriate. Further, if an atmospheric pressure discharge etching process is applied, a local electric discharge process is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

  Next, the semiconductor layer 312, the mask layer 318a covering the n-type semiconductor layer 315, the channel formation region of the semiconductor layer 313, and the mask layer 318b covering the channel formation region of the n-type semiconductor layer 316, the semiconductor layers 314 and n A mask layer 318c covering the semiconductor layer 317 having a type, a semiconductor layer 361, and a mask layer 318d covering the semiconductor layer 362 having an n-type are formed. An impurity element 319 imparting p-type conductivity is added to form a p-type impurity region 320a and a p-type impurity region 320b in the n-type semiconductor layer 316 (see FIG. 7B). In this embodiment, an impurity element imparting p-type conductivity (boron (B) in this embodiment) is added by an ion doping method. After that, heat treatment is performed at 550 ° C. for 4 hours to activate the impurity element addition region.

  In this embodiment mode, a CMOS structure is used in the drive circuit area to function as an inverter. In the case of only PMOS and NMOS only, the gate electrode layer of some TFTs and the source electrode layer or drain electrode layer are connected. By connecting the source or drain electrode layer 327b and the gate electrode layer 302, a thin film transistor 335 and a thin film transistor 336 to be formed later can function as an inverter even if they are NMOS transistors and PMOS transistors. As described above, in this embodiment mode, the thin film transistor 335 and the thin film transistor 336 have a CMOS structure, and thus can function as an inverter without using the above structure.

  After the mask layer 318a, the mask layer 318b, the mask layer 318c, and the mask layer 318d are removed, the n-type semiconductor layer 315, the n-type semiconductor layer 316, the n-type semiconductor layer 317, and the n-type semiconductor A conductive layer 321, a conductive layer 322, and a conductive layer 363 are formed over the layer 362. In this embodiment, the conductive layer 321, the conductive layer 322, and the conductive layer 363 are selectively formed by a droplet discharge method, so that material loss is reduced. Silver (Ag) is used as the conductive material, and a composition containing Ag is discharged from the droplet discharge device 380a, the droplet discharge device 380b, and the droplet discharge device 380c, and is baked at 300 ° C. A layer 322 and a conductive layer 363 are formed (see FIG. 7C). In the same step, a conductive layer 370 which serves as a source electrode layer or a drain electrode layer which also forms a capacitor is formed over the gate insulating layer 305b over the gate electrode layer 360a.

  As a conductive material for forming the conductive layer 321, the conductive layer 322, the conductive layer 363, and the conductive layer 370 to be the source electrode layer or the drain electrode layer, Ag (silver), Au (gold), Cu (copper), W ( A composition containing metal particles such as tungsten) or Al (aluminum) as a main component can be used. Further, light-transmitting indium tin oxide (ITO), ITSO made of indium tin oxide and silicon oxide, organic indium, organic tin, zinc oxide, titanium nitride, or the like may be combined.

  The conductive layer 321, the conductive layer 322, the conductive layer 363, and the conductive layer 370 are processed into desired shapes, and the source or drain electrode layer 327a, the source or drain electrode layer 327b, the source or drain electrode layer 327c, A source or drain electrode layer 328, a source or drain electrode layer 366a, a source or drain electrode layer 366b, and a source or drain electrode layer 366c are formed. In the same step, a source electrode layer or a drain electrode layer 386 is also formed (see FIG. 5). Source or drain electrode layer 327a, Source or drain electrode layer 327b, Source or drain electrode layer 327c, Source or drain electrode layer 328, Source or drain electrode layer 366a, Source or drain electrode layer 366a With the electrode layer 366b as a mask, the semiconductor layer 312, the semiconductor layer 313, the semiconductor layer 314, the semiconductor layer 361, the n-type semiconductor layer 315, the n-type semiconductor layer 316, the n-type semiconductor layer 317, and the n-type The semiconductor layer 362 is etched so that the semiconductor layer 371, the semiconductor layer 372, the semiconductor layer 373, the semiconductor layer 375, the n-type semiconductor layer 324a, the n-type semiconductor layer 324b, the p-type semiconductor layer 325a, and the p-type A semiconductor layer 325b having n-type, a semiconductor layer 326 having n-type, and an n-type Conductive layer 365a, a semiconductor layer 365b having a n-type. Etching can be dry etching or wet etching. In this embodiment mode, a dry etching method is used.

  Through the above steps, an n-channel thin film transistor 335, a p-channel thin film transistor 336, an n-channel thin film transistor 337, an n-channel thin film transistor 364, and a capacitor 338 which form a CMOS can be formed. In this embodiment mode, a CMOS configuration is used. However, the present invention is not limited to this, and a PMOS configuration or an NMOS configuration may be used.

  An insulating film 330 to be a passivation film is formed. In this embodiment, the insulating film 330 is formed using a stacked film of a silicon oxide film with a thickness of 150 nm and a silicon nitride film with a thickness of 200 nm from the side in contact with the semiconductor layer. The insulating film 330 may be formed using another silicon-containing film, or a silicon oxynitride film may be used instead of the silicon oxide film, and a silicon oxynitride film and a silicon nitride film may be stacked.

  The insulating film 330 is formed so as to contain hydrogen, and heat treatment is performed in a nitrogen atmosphere at a temperature of 300 to 500 ° C. to hydrogenate the semiconductor layer.

  An insulating layer 339 and an insulating layer 381 are formed over the insulating film 330 (see FIG. 8A). In this embodiment, as the insulating layer 381, a silicon oxide film including an alkyl group is formed using a slit coater. Although not illustrated in this embodiment mode, the insulating layer 339 is a stacked layer of a silicon oxide film containing an alkyl group and a silicon nitride film from the substrate 300 side, and the upper silicon nitride film is desired to be the insulating layer 381. It functions as an etching stopper when processing into the shape. The film functioning as an etching stopper is not necessary if the etching selectivity with the laminated insulating layer is high.

  An opening 340b reaching the source or drain electrode layer 328 and an opening 340d reaching the source or drain electrode layer 366b are formed in the insulating layer 339 and the insulating film 330 in the insulating layer 381, the insulating layer 339, and the insulating film 330. The gate insulating layer 305a, the opening 340a reaching the gate electrode layer 303, and the opening 340c reaching the gate electrode layer 360a are formed in the gate insulating layer 305b by performing an etching process twice as in Embodiment 2 (FIG. 8 (B)). The mask layer 382a, the mask layer 382b, the mask layer 382c, the mask layer 382d, the mask layer 382e, and the mask layer 382f are mask layers used in the second etching for the opening formed when the insulating layer 381 is selectively processed. It is.

The mask layer 382a, the mask layer 382b, the mask layer 382c, the mask layer 382d, the mask layer 382e, and the mask layer 382f have low wettability with respect to the composition containing a liquid conductive material formed in the opening. Processing is performed. In this embodiment mode, plasma treatment is performed in a gas atmosphere containing fluorine to replace the C—H bond on the surface of the mask layer with the C—F bond, thereby reducing the surface energy of the mask layer surface. In this embodiment mode, plasma treatment is performed in a mixed gas atmosphere of CF ₄ and O ₂ . The region with low wettability becomes a liquid repellent region depending on the liquid and repels the liquid, so that the droplet cannot adhere to the region with low wettability. The composition containing the liquid conductive material does not adhere to the surface of the mask layer having low wettability with respect to the composition, or does not become stable even if it adheres to the relatively wettable opening. And filled. Thus, since the composition containing the conductive material is filled, the wiring layer can be stably formed with good controllability, and loss of the material can be prevented.

  Therefore, a composition including a conductive material discharged by the droplet discharge method 385a, the droplet discharge method 385b, and the droplet discharge method 385c has a low wettability region 383a, a low wettability region 383b, and a low wettability region on the mask layer surface. The conductive region 383c, the low wettability region 383d, the low wettability region 383e, and the low wettability region 383f are repelled and do not adhere to the openings 340a, 340b, 340c, and 340d, and are electrically conductive. The layer 384a, the conductive layer 384b, and the conductive layer 384c are formed. The conductive layer 384a, the conductive layer 384b, and the conductive layer 384c are dried and solidified by baking at 300 ° C., so that the wiring layer 341, the gate wiring layer 342, and the gate wiring layer 367 are formed. In this embodiment mode, Ag is used for the gate wiring layer or the wiring layer. After that, the mask layer 382a, the mask layer 382b, the mask layer 382c, the mask layer 382d, the mask layer 382e, and the mask layer 382f are removed.

  Through the above steps, the gate wiring layer 367 that electrically connects the source or drain electrode layer 328 and the gate electrode layer 360a, the source or drain electrode layer 366b, and the first electrode layer 304 are electrically connected. A wiring layer 341 connected to each other and a gate wiring layer 342 electrically connected to the gate electrode layer 303 are formed (see FIG. 9B).

Subsequently, the first electrode layer 304 is formed by selectively discharging a composition containing a conductive material over the wiring layer 341. When light is emitted from the substrate 100 side, the first electrode layer 304 is made of indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), and indium zinc oxide containing zinc oxide (ZnO). A predetermined pattern is formed by a composition containing a material (IZO (indium zinc oxide)), zinc oxide (ZnO), ZnO doped with gallium (Ga), tin oxide (SnO ₂ ), etc. May be.

  Further, it is preferably formed of indium tin oxide (ITO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), or the like by a sputtering method. More preferably, indium tin oxide containing silicon oxide is used by a sputtering method using a target containing 2 to 10% by weight of silicon oxide in ITO. In addition, indium zinc oxide (IZO), which is a conductive material obtained by doping ZnO with gallium (Ga), and an oxide conductive material containing silicon oxide and indium oxide mixed with 2 to 20 wt% zinc oxide (ZnO). (Indium zinc oxide)) may be used. After the first electrode layer 304 is formed by a sputtering method, a mask layer may be formed by a droplet discharge method and formed into a desired pattern by etching. In this embodiment mode, the first electrode layer 304 is formed using a light-transmitting conductive material by a droplet discharge method, and specifically includes indium tin oxide, ITO, and silicon oxide. It is formed using ITSO.

  In this embodiment mode, the first electrode layer 304 can be formed in a flat formation region, so that the coverage is good and polishing treatment such as CMP can be sufficiently performed, so that the first electrode layer 304 can be formed with high flatness. Alternatively, an insulating layer serving as an interlayer insulating layer may be formed over the wiring layer 341 and electrically connected to the first electrode layer 304 with the wiring layer.

  In addition, when a structure in which emitted light is emitted to the side opposite to the substrate 100 side and a top emission type EL display panel is manufactured, Ag (silver), Au (gold), Cu (copper), A composition composed mainly of metal particles such as W (tungsten) and Al (aluminum) can be used. As another method, a transparent conductive film or a light reflective conductive film is formed by a sputtering method, a mask pattern is formed by a droplet discharge method, and the first electrode layer 304 is formed by combining etching processes. Also good.

  The first electrode layer 304 may be wiped with a CMP method or a polyvinyl alcohol-based porous material and polished so that the surface thereof is planarized. Further, after polishing using the CMP method, the surface of the first electrode layer 304 may be subjected to ultraviolet irradiation, oxygen plasma treatment, or the like.

  Through the above steps, a TFT substrate for a display panel in which a bottom gate type TFT and a first electrode layer are connected to the substrate 300 is completed. The TFT of this embodiment mode is an inverted stagger type.

  Next, an insulating layer 343 (also referred to as a partition wall or a bank) is selectively formed. The insulating layer 343 is formed so as to have an opening over the first electrode layer 304. In this embodiment, the insulating layer 343 is formed over the entire surface, and is etched into a desired shape by a mask layer such as a resist. In the case where the insulating layer 343 is formed using a droplet discharge method, a printing method, or the like that can be directly and selectively formed, etching processing is not necessarily required. The insulating layer 343 can also be formed into a desired shape by the pretreatment of the present invention.

  The insulating layer 343 is formed using silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, other inorganic insulating materials, acrylic acid, methacrylic acid, and derivatives thereof, polyimide, aromatic, or aromatic. Heat-resistant polymers such as polyamide, polybenzimidazole, or inorganic siloxanes containing Si—O—Si bonds among silicon, oxygen, and hydrogen compounds formed from siloxane-based materials as starting materials It can be formed of an organic siloxane insulating material in which hydrogen is substituted with an organic group such as methyl or phenyl. You may form using photosensitive and non-photosensitive materials, such as an acryl and a polyimide. The insulating layer 343 preferably has a shape in which the radius of curvature continuously changes, and the coverage of the electroluminescent layer 344 and the second electrode layer 345 formed thereon is improved.

  Alternatively, after the composition is discharged by a droplet discharge method to form the insulating layer 343, the surface may be flattened by pressing with a pressure in order to improve the flatness. As a pressing method, unevenness may be reduced by scanning a roller-like object on the surface, or the surface may be pressed vertically with a flat plate-like object. Alternatively, the surface may be softened or melted with a solvent or the like, and the surface irregularities may be removed with an air knife. Further, polishing may be performed using a CMP method. This step can be applied when the surface is flattened when unevenness is generated by the droplet discharge method. When flatness is improved by this step, display unevenness of the display panel can be prevented and a high-definition image can be displayed.

An electroluminescent layer 344 and a second electrode layer 345 are stacked over the first electrode layer 304. Although not shown, it is effective to provide a passivation film so as to cover the second electrode layer 345. The protective film provided when forming the display device may have a single layer structure or a multilayer structure. As the passivation film, silicon nitride (SiN), silicon oxide (SiO ₂ ), silicon oxynitride (SiON), silicon nitride oxide (SiNO), aluminum nitride (AlN), aluminum oxynitride (AlON), nitrogen content is oxygen It is made of an insulating film containing aluminum nitride oxide (AlNO) or aluminum oxide, diamond-like carbon (DLC), or nitrogen-containing carbon film (CN _X ) that is higher than the content, and a single layer or a combination of the insulating films is used. Can do. For example, a laminate such as a nitrogen-containing carbon film (CN _x ) or silicon nitride (SiN), or an organic material can be used, or a laminate of polymers such as styrene polymer may be used. In addition, a skeleton structure is formed by a bond of silicon (Si) and oxygen (O), and at least one of a material containing at least hydrogen as a substituent, or fluorine, an alkyl group, or an aromatic hydrocarbon as a substituent. You may use the material which has.

At this time, it is preferable to use a film with good coverage as the passivation film, and it is effective to use a carbon film, particularly a DLC film. Since the DLC film can be formed in the temperature range from room temperature to 100 ° C., it can be easily formed over the electroluminescent layer having low heat resistance. The DLC film is formed by a plasma CVD method (typically, an RF plasma CVD method, a microwave CVD method, an electron cyclotron resonance (ECR) CVD method, a hot filament CVD method, etc.), a combustion flame method, a sputtering method, or an ion beam evaporation method. It can be formed by laser vapor deposition. The reaction gas used for film formation was hydrogen gas and a hydrocarbon-based gas (for example, CH ₄ , C ₂ H ₂ , C ₆ H _6, etc.), ionized by glow discharge, and negative self-bias was applied. Films are formed by accelerated collision of ions with the cathode. The CN film may be formed using C ₂ H ₄ gas and N ₂ gas as reaction gases. The DLC film has a high blocking effect against oxygen and can suppress oxidation of the electroluminescent layer. Therefore, the problem that the electroluminescent layer is oxidized during the subsequent sealing process can be prevented.

  After that, the filler 346 is sealed with a sealing substrate 347 and sealed. Instead of the filler 346, an inert gas such as nitrogen may be filled. Further, by installing the desiccant in the display device, the light emitting element can be prevented from being deteriorated by moisture. The installation place of the desiccant may be on the sealing substrate 347 side or on the substrate 300 side where elements are formed, or may be installed in a region where the sealing material 348 is formed with a recess formed in the substrate. Further, when the sealing substrate 347 is installed in a location corresponding to a region that does not contribute to display, such as a drive circuit region or a wiring region, the desiccant is an opaque substance (a substance that does not transmit light in the visible light region). ) Does not reduce the aperture ratio. The filler 346 may be formed so as to include a hygroscopic material, and may have a function of a desiccant. Through the above steps, a display device having a display function using a light-emitting element is completed (see FIG. 9B).

  In addition, an FPC 354 is bonded to a terminal electrode layer 352 for electrically connecting the inside and the outside of the display device with an anisotropic conductive film 353 to be electrically connected to the terminal electrode layer 352.

  FIG. 10A shows a top view of the display device. As shown in FIG. 10A, the pixel region 390, the scan line drive region 391a, the scan line drive region 391b, and the connection region 393 are sealed between the substrate 300 and the sealing substrate 347 with a sealant 348. A signal line driver circuit 392 formed by an IC driver is provided on the substrate 300.

  Note that in this embodiment mode, a case where a light-emitting element is sealed with a glass substrate is shown; however, the sealing process is a process for protecting the light-emitting element from moisture and is mechanically sealed with a cover material. Either a method, a method of encapsulating with a thermosetting resin or an ultraviolet light curable resin, or a method of encapsulating with a thin film having a high barrier ability such as a metal oxide or a nitride is used. As the cover material, glass, ceramics, plastic, or metal can be used. However, when light is emitted to the cover material side, it must be translucent. In addition, the cover material and the substrate on which the light emitting element is formed are bonded together using a sealing material such as a thermosetting resin or an ultraviolet light curable resin, and the resin is cured by heat treatment or ultraviolet light irradiation treatment to form a sealed space. Form. It is also effective to provide a hygroscopic material typified by barium oxide in this sealed space. This hygroscopic material may be provided in contact with the sealing material, or may be provided on the partition wall or in the peripheral portion so as not to block light from the light emitting element. Further, the space between the cover material and the substrate on which the light emitting element is formed can be filled with a thermosetting resin or an ultraviolet light curable resin. In this case, it is effective to add a moisture absorbing material typified by barium oxide in the thermosetting resin or the ultraviolet light curable resin.

  In this embodiment mode, the switching TFT has a single gate structure, but a multi-gate structure such as a double gate structure may be used. In the case where a semiconductor is manufactured using a SAS or a crystalline semiconductor, an impurity region can be formed by adding an impurity imparting one conductivity type. In this case, the semiconductor layer may have impurity regions having different concentrations. For example, the vicinity of the channel region of the semiconductor layer and the region stacked with the gate electrode layer may be low-concentration impurity regions, and the outer region may be high-concentration impurity regions.

  In the display device in FIG. 10 described in this embodiment, the gate electrode layer 301, the gate electrode layer 302, the gate electrode layer 303, the gate electrode layer 360a, the gate electrode layer 360b, and the first electrode layer 304 are illustrated in a single layer structure. However, as described above, two or more gate electrode layers may be stacked.

  Through the above steps, an inverted staggered thin film transistor having a crystalline semiconductor film can be formed. Since the thin film transistor formed in this embodiment is formed using a crystalline semiconductor film, it has higher mobility than a thin film transistor formed using an amorphous semiconductor film. In addition, the source region and the drain region include a metal element in addition to the impurity element imparting one conductivity type. For this reason, a source region and a drain region with low resistivity can be formed. As a result, a display device that requires high-speed operation can be manufactured.

  Further, compared to a thin film transistor formed using an amorphous semiconductor film, threshold shift is less likely to occur, and variations in thin film transistor characteristics can be reduced.

  Further, since the metal element mixed in the semiconductor film in the film formation stage is also gettered by the gettering step, off current can be reduced. Therefore, the contrast can be improved by providing such a thin film transistor in the switching element of the display device.

  According to the present invention, the conductive layer can be formed with good controllability, the material loss is small, and the cost can be reduced. Further, by using an insulating layer having holes, the conductive layers can be formed with good adhesion by the anchor effect. Therefore, a high-performance and highly reliable light-emitting device can be manufactured with high yield.

(Embodiment 4)
An embodiment of the present invention will be described with reference to FIGS. More specifically, a method for manufacturing a display device including an inverted staggered thin film transistor formed in Embodiment 3 to which the present invention is applied will be described. 12 is a top view of the display device pixel portion, and FIG. 13 is a cross-sectional view taken along line EF, line GH in FIG. 12, and line I-J in FIG. 14A is also a top view of the display device, and FIG. 14B is a cross-sectional view taken along line OP (including U-W) in FIG. Note that an example of a liquid crystal display device using a liquid crystal material as a display element is shown. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

  An n-channel thin film transistor 235, a p-channel thin film transistor 236, and an n-channel thin film transistor 237 which form a CMOS can be formed over the substrate 200 (see FIG. 14B). Although the CMOS structure is used in this embodiment mode, the present invention is not limited thereto, and a PMOS structure or an NMOS structure may be used.

  An insulating film 230 to be a passivation film is formed. In this embodiment, the insulating film 230 is formed using a stacked film of a silicon oxide film with a thickness of 150 nm and a silicon nitride film with a thickness of 200 nm from the side in contact with the semiconductor layer. The insulating film 230 may be formed using another silicon-containing film, or a silicon oxynitride film may be used instead of the silicon oxide film, and a silicon oxynitride film and a silicon nitride film may be stacked.

  The insulating film 230 is formed so as to contain hydrogen, and heat treatment is performed in a nitrogen atmosphere at a temperature of 300 to 500 ° C. to hydrogenate the semiconductor layer.

  An insulating layer 222 and an insulating layer 223 are formed over the insulating film 230. In this embodiment, as the insulating layer 223, a silicon oxide film containing an alkyl group is formed using a slit coater. In this embodiment mode, although not illustrated, the insulating layer 222 is a stack of a silicon oxide film containing an alkyl group and a silicon nitride film from the substrate 200 side, and the upper silicon nitride film is desired to have the insulating layer 223. It functions as an etching stopper when processing into the shape. The film functioning as an etching stopper is not necessary if the etching selectivity with the laminated insulating layer is high. As described in Embodiment 1, when an insulating layer having a hole is used for the insulating layer 222 and the insulating layer 223, a part of the conductive layer attached to the insulating layer is filled in the hole. Since it is formed and exhibits a wedge-like effect (anchor effect) on the insulating layer, adhesion is improved.

  An opening reaching the source electrode layer or the drain electrode layer is formed in the insulating layer 223, the insulating layer 222, and the insulating film 230 by performing an etching process twice as in Embodiment Mode 2. A mask layer used in the second etching for the opening formed when the insulating layer 381 is selectively processed is formed so as to include a substance having a fluorocarbon group. By applying, exposing, and developing a resist solution to which a surface modifier such as a monomer or oligomer having a fluorocarbon group is added, a low surface energy mask layer can be formed. Since fluorocarbon has a low surface energy, it tends to exist in a large amount on the surface, and even when added in a small amount of about 1%, a fluorocarbon group exists on the surface of the mask layer and exhibits a low surface energy. Therefore, the mask layer surface becomes a low wettability region with respect to a composition containing a liquid conductive material.

  The region with low wettability becomes a liquid repellent region depending on the liquid and repels the liquid, so that the droplet cannot adhere to the region with low wettability. The composition containing the liquid conductive material does not adhere to the mask surface having low wettability with respect to the composition, or does not become stable even if it adheres to the relatively wettable opening. Filled. Thus, since the composition containing the conductive material is filled, the wiring layer can be stably formed with good controllability, and loss of the material can be prevented.

  Therefore, the composition containing the conductive material discharged by the droplet discharge method is repelled in the low wettability region on the surface of the mask layer and does not adhere to fill the opening. The wiring layer 224 is formed by baking the filled conductive layer at 300 ° C. In this embodiment, Ag is used as the wiring layer.

  FIG. 12 is a top view of a pixel region of a liquid crystal display device manufactured in this embodiment mode. The thin film transistor provided in the pixel region is a multi-gate type. In the pixel region, there are a gate wiring layer 233, a pixel electrode layer 225, a thin film transistor 237, a source or drain electrode layer 231, a wiring layer 224, and a capacitor wiring layer 232.

  Next, as illustrated in FIG. 13, an insulating layer 226 called an alignment film is formed by a printing method or a spin coating method so as to cover the pixel electrode layer 225. Note that the insulating layer 226 can be selectively formed by a screen printing method or an offset printing method. Thereafter, a rubbing process is performed. Subsequently, a sealant 251 is formed in a peripheral region where the pixels are formed.

  After that, the insulating layer 245 functioning as an alignment film, the colored layer 247 functioning as a color filter, the conductor layer 246 functioning as a counter electrode, the counter substrate 248 provided with the polarizing plate 250 and the substrate 200 having TFTs are separated by a spacer 275. And a liquid crystal layer 244 is provided in the gap, whereby a liquid crystal display device can be manufactured (see FIG. 13). A polarizing plate 221 is also formed on the side of the substrate 200 that does not have a TFT. A filler may be mixed in the sealing material, and a shielding film (black matrix) or the like may be formed on the counter substrate 248. Note that as a method for forming the liquid crystal layer, a dispenser type (dropping type) or a dip type (pumping type) in which liquid crystal is injected using a capillary phenomenon after the counter substrate 248 is attached can be used.

  A liquid crystal dropping injection method employing a dispenser method will be described with reference to FIG. In FIG. 23, 40 is a control device, 42 is an imaging means, 43 is a head, 33 is a liquid crystal, 35 and 45 are markers, 34 is a barrier layer, 32 is a sealing material, 30 is a TFT substrate, and 20 is a counter substrate. A closed loop is formed by the sealing material 32, and the liquid crystal 33 is dropped from the head 43 once or plural times therein. The head 43 includes a plurality of nozzles, and a large amount of liquid crystal material can be dropped at a time, thereby improving the throughput. When the viscosity of the liquid crystal material is high, the liquid crystal material is continuously discharged and adhered to the formation region while being connected. On the other hand, when the viscosity of the liquid crystal material is low, the liquid crystal material is ejected intermittently and droplets are dropped. At that time, a barrier layer 34 is provided to prevent the sealing material 32 and the liquid crystal 33 from reacting. Subsequently, the substrates are bonded together in a vacuum, and thereafter UV curing is performed to fill the liquid crystal. Further, a sealing material may be formed on the TFT substrate side, and the liquid crystal may be dropped.

  The spacer may be provided by dispersing particles of several μm, but in this embodiment, a method of forming a resin film on the entire surface of the substrate and processing it into a desired shape is employed. After applying such a spacer material with a spinner, it is formed into a predetermined pattern by exposure and development processing. Further, it is cured by heating at 150 to 200 ° C. in a clean oven or the like. The spacers produced in this way can have different shapes depending on the conditions of exposure and development processing, but preferably, the spacers are columnar and the top is flat, so that the opposite substrate is When combined, the mechanical strength of the liquid crystal display device can be ensured. The shape can be a conical shape, a pyramid shape, or the like, and there is no particular limitation.

A connection portion is formed to connect the inside of the display device formed by the above steps and an external wiring board. The insulator layer in the connection portion is removed by ashing using oxygen gas at or near atmospheric pressure. This treatment is performed using oxygen gas and one or more selected from hydrogen, CF ₄ , NF ₃ , H ₂ O, and CHF ₃ . In this step, in order to prevent damage and destruction due to static electricity, ashing is performed after sealing using the counter substrate. However, if there is little influence from static electricity, it may be performed at any timing. . In addition, an FPC (Flexible Printed Circuit) 254 is bonded to a terminal electrode layer 252 for electrically connecting the inside and the outside of the liquid crystal display device by an anisotropic conductive film 253 to be electrically connected to the terminal electrode layer 252. . The FPC 254 plays a role of transmitting an external signal or potential. Through the above steps, a liquid crystal display device having a display function can be manufactured.

  Through the above steps, an inverted staggered thin film transistor having a crystalline semiconductor film can be formed. Since the thin film transistor formed in this embodiment is formed using a crystalline semiconductor film, it has higher mobility than a thin film transistor formed using an amorphous semiconductor film. In addition, the source region and the drain region include a metal element in addition to the impurity element imparting one conductivity type. For this reason, a source region and a drain region with low resistivity can be formed. As a result, a liquid crystal display device that requires high-speed operation can be manufactured. Therefore, it is possible to manufacture a liquid crystal display device that can display with a high response speed and a high viewing angle as in the OCB mode. Further, compared to a thin film transistor formed using an amorphous semiconductor film, threshold shift is less likely to occur, and variations in thin film transistor characteristics can be reduced. Further, since the metal element mixed in the semiconductor film in the film formation stage is also gettered by the gettering step, off current can be reduced. Therefore, the contrast can be improved by providing such a thin film transistor in the switching element of the liquid crystal display device.

  FIG. 14A shows a top view of a liquid crystal display device. As shown in FIG. 14A, the pixel region 260, the scan line drive region 261 a, and the scan line drive region 261 b are sealed between the substrate 200 and the counter substrate 248 by the sealant 251, and are formed on the substrate 200. A signal line driver circuit 262 formed by an IC driver is provided. A driving circuit including a thin film transistor 235 and a thin film transistor 236 is provided in the driving region. The thin film transistor 235 is an n-channel thin film transistor, the thin film transistor 236 is a p-channel thin film transistor, and the thin film transistor 235 and the thin film transistor 236 have a CMOS structure.

  In this embodiment mode, the switching TFT has a double gate structure, but may have a single gate structure or a plurality of multi-gate structures. In the case where a semiconductor is manufactured using a SAS or a crystalline semiconductor, an impurity region can be formed by adding an impurity imparting one conductivity type. In this case, the semiconductor layer may have impurity regions having different concentrations. For example, the vicinity of the channel region of the semiconductor layer and the region stacked with the gate electrode layer may be low-concentration impurity regions, and the outer region may be high-concentration impurity regions.

  As described above, in this embodiment, the process can be simplified. In addition, by forming various components (parts) directly on the substrate using the droplet discharge method, a display panel can be easily used even when a glass substrate of 5th generation or later with one side exceeding 1000 mm is used. Can be manufactured.

  According to the present invention, the conductive layer can be formed with good controllability, the material loss is small, and the cost can be reduced. Further, by using an insulating layer having holes, the conductive layers can be formed with good adhesion by the anchor effect. Accordingly, a high-performance and highly reliable liquid crystal display device can be manufactured with high yield.

(Embodiment 5)
A thin film transistor is formed by applying the present invention, and a display device can be formed using the thin film transistor. When a light-emitting element is used and an n-channel transistor is used as a transistor for driving the light-emitting element, The light emitted from the light emitting element performs any one of bottom emission, top emission, and dual emission. Here, a stacked structure of light-emitting elements corresponding to any case will be described with reference to FIGS.

In this embodiment mode, channel protective thin film transistors 461, 471, and 481 to which the present invention is applied are used. The thin film transistor 481 is provided over a light-transmitting substrate 480 and includes a gate electrode layer 493, a gate insulating film 497, a semiconductor layer 494, an n-type semiconductor layer 495a, an n-type semiconductor layer 495b, a source electrode layer or a drain. An electrode layer 487a, a source or drain electrode layer 487b, and a channel protective layer 496 are formed. An insulating layer 498 and an insulating layer 499 are formed so as to cover the thin film transistor 481, and the wiring layer 488 that electrically connects the source or drain electrode layer 487b and the first electrode layer 484 includes the insulating layer 498 and the insulating layer 498. It is formed so as to be embedded in the layer 499. In this embodiment, a crystalline semiconductor layer is used as the semiconductor layer, and an n-type semiconductor layer is used as the one-conductivity-type semiconductor layer. Instead of forming an n-type semiconductor layer, conductivity may be imparted to the semiconductor layer by performing plasma treatment with a PH ₃ gas. The semiconductor layer is not limited to this embodiment mode, and an amorphous semiconductor layer can also be used as shown in Embodiment Mode 1. In the case where a crystalline semiconductor layer such as polysilicon is used as in this embodiment mode, an impurity having one conductivity type is formed by introducing (adding) an impurity into the crystalline semiconductor layer without forming a one conductivity type semiconductor layer. A region may be formed. Alternatively, an organic semiconductor such as pentacene can be used. When the organic semiconductor is selectively formed by a droplet discharge method or the like, the process of processing into a desired shape can be simplified.

  In this embodiment, an amorphous semiconductor layer is crystallized as the semiconductor layer 494 to form a crystalline semiconductor layer. In the crystallization step, an element (also referred to as a catalyst element or a metal element) that promotes crystallization is added to the amorphous semiconductor layer, and crystallization is performed by heat treatment (at 550 ° C. to 750 ° C. for 3 minutes to 24 hours). As elements for promoting crystallization, metal elements for promoting crystallization of silicon include iron (Fe), nickel (Ni), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd). One or plural types selected from osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), and gold (Au) can be used. In this embodiment, nickel is used.

  In order to remove or reduce the element that promotes crystallization from the crystalline semiconductor layer, a semiconductor layer containing an impurity element is formed in contact with the crystalline semiconductor layer and functions as a gettering sink. As the impurity element, an impurity element imparting n-type conductivity, an impurity element imparting p-type conductivity, a rare gas element, or the like can be used. For example, phosphorus (P), nitrogen (N), arsenic (As), antimony (Sb ), Bismuth (Bi), boron (B), helium (He), neon (Ne), argon (Ar), Kr (krypton), and Xe (xenon) can be used. In this embodiment, a semiconductor layer including an impurity element functioning as a gettering sink is formed using an n-type semiconductor layer including phosphorus (P) that is an impurity element imparting n-type conductivity. An n-type semiconductor layer is formed over the crystalline semiconductor layer containing an element that promotes crystallization, and heat treatment (at 550 ° C. to 750 ° C. for 3 minutes to 24 hours) is performed. The element that promotes crystallization contained in the crystalline semiconductor layer moves into the semiconductor layer having n-type, and the element that promotes crystallization in the crystalline semiconductor layer is removed or reduced. It is formed. On the other hand, the n-type semiconductor layer becomes an n-type semiconductor layer 495a and an n-type semiconductor layer 495b containing a metal element which is an element that promotes crystallinity. In this manner, the n-type semiconductor layer 495a and the n-type semiconductor layer 495b function as a gettering sink of the semiconductor layer 494, and also function as a source region and a drain region as they are.

  In this embodiment mode, the crystallization step and the gettering step of the semiconductor layer are performed by a plurality of heat treatments; however, the crystallization step and the gettering step can be performed by a single heat treatment. In this case, an amorphous semiconductor layer is formed, an element that promotes crystallization is added, a semiconductor layer serving as a gettering sink is formed, and then heat treatment is performed.

  In this embodiment, the gate insulating layer is formed by stacking a plurality of layers, and a silicon nitride oxide film and a silicon oxynitride film are formed as the gate insulating film 497 from the gate electrode layer 493 side to have a two-layer stacked structure. The insulating layers to be stacked are preferably formed continuously while switching the reaction gas at the same temperature without breaking the vacuum in the same chamber. If formed continuously without breaking the vacuum, it is possible to prevent the interface between the stacked films from being contaminated.

  For the channel protective layer 496, polyimide, polyvinyl alcohol, or the like may be dropped by a droplet discharge method. As a result, the exposure process can be omitted. As the channel protective layer, inorganic materials (silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, etc.), photosensitive or non-photosensitive organic materials (organic resin materials) (polyimide, acrylic, polyamide, polyimide amide, resist) , Benzocyclobutene, etc.), a low-k material having a low dielectric constant, or a film made of a plurality of kinds, or a stack of these films. In addition, a skeleton structure is formed by a bond of silicon (Si) and oxygen (O), and at least one of a material containing at least hydrogen as a substituent, or fluorine, an alkyl group, or an aromatic hydrocarbon as a substituent. You may use the material which has. As a manufacturing method, a vapor deposition method such as a plasma CVD method or a thermal CVD method, or a sputtering method can be used. Alternatively, a droplet discharge method or a printing method (a method for forming a pattern such as screen printing or offset printing) can be used. A coating film obtained by a coating method can also be used.

  First, the case where light is emitted to the substrate 480 side, that is, the case where bottom emission is performed will be described with reference to FIG. In this case, the wiring layer 488 connected to the source or drain electrode layer 487b of the thin film transistor 481 is in contact with and electrically connected to the first electrode layer 484. The first electrode layer 484, the electroluminescent layer 485, and the second electrode layer 486 are sequentially stacked. The substrate 480 through which light is transmitted needs to have a light-transmitting property with respect to at least light in the visible region. Next, the case where radiation is performed on the side opposite to the substrate 460, that is, the case where top surface radiation is performed will be described with reference to FIG. The thin film transistor 461 can be formed in a manner similar to that of the thin film transistor described above.

  A wiring layer 462 connected to the source electrode layer or the drain electrode layer of the thin film transistor 461 is in contact with and electrically connected to the first electrode layer 463. A first electrode layer 463, an electroluminescent layer 464, and a second electrode layer 465 are stacked in this order. The wiring layer 462 is a reflective metal layer and reflects light emitted from the light emitting element to the upper surface of the arrow. Since the wiring layer 462 is stacked with the first electrode layer 463, even if light is transmitted using a light-transmitting material for the first electrode layer 463, the light is transmitted through the wiring layer 462. It is reflected and radiates to the opposite side of the substrate 460. Needless to say, the first electrode layer 463 may be formed using a reflective metal film. Since light emitted from the light-emitting element is emitted through the second electrode layer 465, the second electrode layer 465 is formed using a light-transmitting material at least in the visible region. When an insulating layer having a hole is used for the insulating layer 498 and the insulating layer 499, the wiring layer is formed in a shape in which a part of the wiring layer is filled in the hole. Therefore, the wiring layer may be formed with good adhesion. it can. Thus, a highly reliable display device can be obtained. In the case of a top-emission display device as illustrated in FIG. 16B, light emitted from the light-emitting elements does not pass through the insulating layers 498 and 499; thus, the insulating layers 498 and 499 serve as insulating layers. It is preferable to use an insulating layer having any of the above because there is no need to consider light extraction efficiency.

  Lastly, a case where light is emitted to the substrate 470 side and the opposite side, that is, a case where dual emission is performed will be described with reference to FIG. The thin film transistor 471 is also a channel protective thin film transistor. The first electrode layer 472 is electrically connected to the wiring layer 475 that is electrically connected to the semiconductor layer of the thin film transistor 471. A first electrode layer 472, an electroluminescent layer 473, and a second electrode layer 474 are stacked in this order. At this time, when both the first electrode layer 472 and the second electrode layer 474 are formed with a light-transmitting material or a thickness capable of transmitting light at least in the visible region, dual emission is realized. In this case, the insulating layer through which light is transmitted and the substrate 470 also need to have a light-transmitting property with respect to at least light in the visible region.

  A mode of a light-emitting element which can be applied in this embodiment mode is shown in FIG. The light-emitting element has a structure in which an electroluminescent layer 860 is sandwiched between a first electrode layer 870 and a second electrode layer 850. It is necessary to select materials for the first electrode layer and the second electrode layer in consideration of the work function, and the first electrode layer and the second electrode layer are both anodes or cathodes depending on the pixel configuration. sell. In this embodiment mode, since the polarity of the driving TFT is an N-channel type, it is preferable that the first electrode layer be a cathode and the second electrode layer be an anode. In the case where the polarity of the driving TFT is a p-channel type, the first electrode layer may be an anode and the second electrode layer may be a cathode.

  18A and 18B show the case where the first electrode layer 870 is an anode and the second electrode layer 850 is a cathode, and the electroluminescent layer 860 is a first electrode layer that is an anode. The first layer 804, the second layer 803, and the third layer 802 are preferably stacked in this order from the 870 side. The first layer 804 is an HIL (hole injection layer) and / or HTL (hole transport layer), the second layer 803 is an EML (light emitting layer), and the third layer 802 is an EIL (emission layer). Electron injection layer) and / or ETL (electron transport layer). FIG. 18A illustrates a structure in which light is emitted from the first electrode layer 870. The first electrode layer 870 includes an electrode layer 805 made of a light-transmitting oxide conductive material, The electrode layer 850 includes, from the electroluminescent layer 860 side, an electrode layer 801 containing an alkali metal or alkaline earth metal such as LiF or MgAg and an electrode layer 800 formed of a metal material such as aluminum. FIG. 18B illustrates a structure in which light is emitted from the second electrode layer 850, and the first electrode layer 870 is formed using a metal such as aluminum or titanium or a concentration less than that of the stoichiometric composition with the metal. The electrode layer 807 is formed of a metal material containing nitrogen and the electrode layer 806 is formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%. The second electrode layer 850 includes an electrode layer 801 containing an alkali metal or alkaline earth metal such as LiF or MgAg and an electrode layer 800 formed of a metal material such as aluminum from the electroluminescent layer 860 side. By setting the layer to a thickness of 100 nm or less and allowing light to pass therethrough, light can be emitted from the second electrode layer 850.

  18C and 18D show the case where the first electrode layer 870 is a cathode, the second electrode layer 850 is an anode, and the electroluminescent layer 860 is a first electrode layer that is a cathode. The third layer 802, the second layer 803, and the first layer 804 are preferably stacked in this order from the 870 side. The third layer 802 is an EIL (electron injection layer) and / or ETL (electron transport layer), the second layer 803 is an EML (light emitting layer), and the first layer 804 is an HIL (hole transport layer). Injection layer) and / or HTL (hole transport layer). FIG. 18C illustrates a structure in which light is emitted from the first electrode layer 870. The first electrode layer 870 includes an electrode layer containing an alkali metal or an alkaline earth metal such as LiF or MgAg from the electroluminescent layer 860 side. 801 and an electrode layer 800 formed of a metal material such as aluminum, but each layer emits light from the first electrode layer 870 by setting the thickness to 100 nm or less so that light can be transmitted. It becomes possible to do. The second electrode layer 850 includes, from the electroluminescent layer 860 side, an electrode layer 806 formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%, a metal such as aluminum or titanium, or the metal The electrode layer 807 is formed of a metal material containing nitrogen at a concentration equal to or lower than the stoichiometric composition ratio. FIG. 18D illustrates a structure in which light is emitted from the second electrode layer 850, and the first electrode layer 870 includes an electrode layer containing an alkali metal or an alkaline earth metal such as LiF or MgAg from the electroluminescent layer 860 side. 801 and an electrode layer 800 formed of a metal material such as aluminum. The film thickness is large enough to reflect light emitted from the electroluminescent layer 860. The second electrode layer 850 includes an electrode layer 805 made of an oxide conductive material that transmits at least light in the visible region. The electroluminescent layer can have a single layer structure or a mixed structure in addition to the laminated structure.

  In addition, as the electroluminescent layer, materials that emit red (R), green (G), and blue (B) light are selectively formed by an evaporation method using an evaporation mask, respectively. A material that emits red (R), green (G), and blue (B) light can be formed by a droplet discharge method (such as a low-molecular or high-molecular material) in the same manner as a color filter. In this case, a mask is not used. Both are preferable because RGB can be separately applied.

In the case of a top emission type, when light-transmitting ITO or ITSO is used for the second electrode layer, BzOS-Li in which Li is added to a benzoxazole derivative (BzOS) or the like can be used. Further, for example, EML may be Alq ₃ doped with a dopant (such as DCM in the case of R, DMQD in the case of G) corresponding to the emission colors of R, G, and B.

  Note that the electroluminescent layer is not limited to the above materials. For example, instead of CuPc or PEDOT, an oxide such as molybdenum oxide (MoOx: x = 2 to 3) and α-NPD or rubrene can be co-evaporated to improve the hole injection property. The material of the electroluminescent layer can be used as an organic material (including a low molecule or a polymer), or a composite material of an organic material and an inorganic material. Hereinafter, materials for forming the light emitting element will be described in detail.

Among the charge injecting and transporting substances, substances having a particularly high electron transporting property include, for example, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), Bis (10-hydroxybenzo [h] quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) (4-phenylphenolato) aluminum (abbreviation: BAlq), quinoline skeleton or benzoquinoline skeleton And metal complexes having As a substance having a high hole-transport property, for example, 4,4′-bis [N- (1-naphthyl) -N-phenylamino] biphenyl (abbreviation: α-NPD), 4,4′-bis [N— (3-methylphenyl) -N-phenylamino] biphenyl (abbreviation: TPD), 4,4 ′, 4 ″ -tris (N, N-diphenylamino) triphenylamine (abbreviation: TDATA), 4,4 ′ , 4 ″ -tris [N- (3-methylphenyl) -N-phenylamino] triphenylamine (abbreviation: MTDATA) and other aromatic amine-based compounds (that is, having a benzene ring-nitrogen bond) Can be mentioned.

Among the charge injecting and transporting materials, materials having particularly high electron injecting properties include alkali metals or alkaline earths such as lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF ₂ ) and the like. Metal compounds can be mentioned. In addition, a mixture of a substance having a high electron transporting property such as Alq ₃ and an alkaline earth metal such as magnesium (Mg) may be used.

Among the charge injecting and transporting materials, examples of the material having a high hole injecting property include molybdenum oxide (MoOx), vanadium oxide (VOx), ruthenium oxide (RuOx), tungsten oxide (WOx), and manganese oxide. Examples thereof include metal oxides such as (MnOx). In addition, phthalocyanine compounds such as phthalocyanine (abbreviation: H ₂ Pc) and copper phthalocyanine (CuPC) can be given.

  The light emitting layer may be configured to perform color display by forming light emitting layers having different emission wavelength bands for each pixel. Typically, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) is formed. In this case as well, it is possible to improve color purity and prevent mirror reflection (reflection) of the pixel portion by providing a filter that transmits light in the emission wavelength band on the light emission side of the pixel. Can do. By providing the filter, it is possible to omit a circularly polarized plate that has been conventionally required, and it is possible to eliminate the loss of light emitted from the light emitting layer. Furthermore, a change in color tone that occurs when the pixel portion (display screen) is viewed obliquely can be reduced.

There are various kinds of light emitting materials. As a low molecular weight organic light emitting material, 4-dicyanomethylene-2-methyl-6- [2- (1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] -4H-pyran (abbreviation: DCJT) ), 2-tert-butyl-4-dicyanomethylene-6- [2- (1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] -4H-pyran (abbreviation: DCJTB), periflanthene, 2,5-dicyano-1,4-bis [2- (10-methoxy-1,1,7,7-tetramethyljulolidyl-9-yl) ethenyl] benzene, N, N′-dimethylquinacridone (abbreviation) : DMQd), coumarin 6, coumarin 545T, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), 9,9′-bianthryl, 9,10-diphenylanthracene (abbreviation: D) PA), 9,10-bis (2-naphthyl) anthracene (abbreviation: DNA), and the like can be used. Other substances may also be used.

  On the other hand, the high molecular organic light emitting material has higher physical strength than the low molecular weight material, and the durability of the device is high. In addition, since the film can be formed by coating, the device can be manufactured relatively easily. The structure of the light emitting element using the polymer organic light emitting material is basically the same as that when the low molecular weight organic light emitting material is used. From the cathode side, the cathode, the organic light emitting layer, and the anode are stacked in this order. Become. However, when forming a light emitting layer using a high molecular weight organic light emitting material, it is difficult to form a laminated structure as in the case of using a low molecular weight organic light emitting material. . Specifically, it is a laminated structure in the order of the cathode, the light emitting layer, the hole transport layer, and the anode from the cathode side.

  Since the light emission color is determined by the material for forming the light emitting layer, a light emitting element exhibiting desired light emission can be formed by selecting these materials. Examples of the polymer electroluminescent material that can be used for forming the light emitting layer include polyparaphenylene vinylene, polyparaphenylene, polythiophene, and polyfluorene.

  Examples of the polyparaphenylene vinylene include poly (paraphenylene vinylene) [PPV] derivatives, poly (2,5-dialkoxy-1,4-phenylene vinylene) [RO-PPV], poly (2- (2′- Ethyl-hexoxy) -5-methoxy-1,4-phenylenevinylene) [MEH-PPV], poly (2- (dialkoxyphenyl) -1,4-phenylenevinylene) [ROPh-PPV] and the like. Examples of polyparaphenylene include derivatives of polyparaphenylene [PPP], poly (2,5-dialkoxy-1,4-phenylene) [RO-PPP], poly (2,5-dihexoxy-1,4-phenylene). ) And the like. The polythiophene series includes polythiophene [PT] derivatives, poly (3-alkylthiophene) [PAT], poly (3-hexylthiophene) [PHT], poly (3-cyclohexylthiophene) [PCHT], poly (3-cyclohexyl). -4-methylthiophene) [PCHMT], poly (3,4-dicyclohexylthiophene) [PDCHT], poly [3- (4-octylphenyl) -thiophene] [POPT], poly [3- (4-octylphenyl) -2,2 bithiophene] [PTOPT] and the like. Examples of the polyfluorene series include polyfluorene [PF] derivatives, poly (9,9-dialkylfluorene) [PDAF], poly (9,9-dioctylfluorene) [PDOF], and the like.

  Note that when a hole-transporting polymer-based organic light-emitting material is sandwiched between an anode and a light-emitting polymer-based organic light-emitting material, hole injection properties from the anode can be improved. In general, an acceptor material dissolved in water is applied by spin coating or the like. In addition, since it is insoluble in an organic solvent, it can be stacked with the above-described light-emitting organic light-emitting material. Examples of the hole-transporting polymer organic light emitting material include a mixture of PEDOT and camphor sulfonic acid (CSA) as an acceptor material, a mixture of polyaniline [PANI] and polystyrene sulfonic acid [PSS] as an acceptor material, and the like. .

  The light emitting layer can be configured to emit monochromatic or white light. In the case of using a white light emitting material, color display can be made possible by providing a filter (colored layer) that transmits light of a specific wavelength on the light emission side of the pixel.

To form a light emitting layer that emits white light, for _{example, Alq 3, Alq 3, Alq} 3 doped with Nile Red which is partly red light emitting pigment, p-EtTAZ, by TPD (aromatic diamine) evaporation A white color can be obtained by sequentially laminating. In the case where the EL is formed by a coating method using spin coating, it is preferable that baking is performed by vacuum heating after coating. For example, a poly (ethylenedioxythiophene) / poly (styrenesulfonic acid) aqueous solution (PEDOT / PSS) that acts as a hole injection layer is applied and baked on the entire surface, and then a luminescent center dye (1, 1,4,4-tetraphenyl-1,3-butadiene (TPB), 4-dicyanomethylene-2-methyl-6- (p-dimethylamino-styryl) -4H-pyran (DCM1), Nile Red, Coumarin 6 Etc.) A doped polyvinyl carbazole (PVK) solution may be applied to the entire surface and fired.

  The light emitting layer can also be formed as a single layer, and an electron transporting 1,3,4-oxadiazole derivative (PBD) may be dispersed in hole transporting polyvinyl carbazole (PVK). Further, white light emission can be obtained by dispersing 30 wt% PBD as an electron transporting agent and dispersing an appropriate amount of four kinds of dyes (TPB, coumarin 6, DCM1, Nile red). In addition to the light-emitting element that can emit white light as shown here, a light-emitting element that can obtain red light emission, green light emission, or blue light emission can be manufactured by appropriately selecting the material of the light-emitting layer.

  Note that when a hole-transporting polymer-based organic light-emitting material is sandwiched between an anode and a light-emitting polymer-based organic light-emitting material, hole injection properties from the anode can be improved. In general, an acceptor material dissolved in water is applied by spin coating or the like. In addition, since it is insoluble in an organic solvent, it can be stacked with the above-described light-emitting organic light-emitting material. Examples of the hole-transporting polymer organic light emitting material include a mixture of PEDOT and camphor sulfonic acid (CSA) as an acceptor material, a mixture of polyaniline [PANI] and polystyrene sulfonic acid [PSS] as an acceptor material, and the like. .

  Furthermore, a triplet excitation material containing a metal complex or the like may be used for the light emitting layer in addition to a singlet excitation light emitting material. For example, among red light emitting pixels, green light emitting pixels, and blue light emitting pixels, a red light emitting pixel having a relatively short luminance half time is formed of a triplet excitation light emitting material, and the other A singlet excited light emitting material is used. The triplet excited luminescent material has a feature that the light emission efficiency is good, so that less power is required to obtain the same luminance. That is, when applied to a red pixel, the amount of current flowing through the light emitting element can be reduced, so that reliability can be improved. As a reduction in power consumption, a red light-emitting pixel and a green light-emitting pixel may be formed using a triplet excitation light-emitting material, and a blue light-emitting pixel may be formed using a singlet excitation light-emitting material. By forming a green light-emitting element having high human visibility with a triplet excited light-emitting material, power consumption can be further reduced.

  Examples of triplet excited luminescent materials include those using a metal complex as a dopant, and metal complexes having a third transition series element platinum as the central metal and metal complexes having iridium as the central metal are known. Yes. The triplet excited light-emitting material is not limited to these compounds, and a compound having the above structure and having an element belonging to group 8 to 10 in the periodic table as a central metal can also be used.

  The substances forming the light-emitting layer listed above are examples, and functionalities such as a hole injection transport layer, a hole transport layer, an electron injection transport layer, an electron transport layer, a light emission layer, an electron block layer, and a hole block layer are included. A light emitting element can be formed by appropriately stacking each layer. Moreover, you may form the mixed layer or mixed junction which combined these each layer. The layer structure of the light-emitting layer can be changed, and instead of having a specific electron injection region or light-emitting region, an electrode layer for this purpose is provided, or a light-emitting material is dispersed. Modifications can be made without departing from the spirit of the present invention.

  A light-emitting element formed using the above materials emits light by being forward-biased. A pixel of a display device formed using a light-emitting element can be driven by a simple matrix method or an active matrix method. In any case, each pixel emits light by applying a forward bias at a specific timing, but is in a non-light emitting state for a certain period. By applying a reverse bias during this non-light emitting time, the reliability of the light emitting element can be improved. The light emitting element has a degradation mode in which the light emission intensity decreases under a constant driving condition and a degradation mode in which the non-light emitting area is enlarged in the pixel and the luminance is apparently decreased. However, alternating current that applies a bias in the forward and reverse directions. By performing a typical drive, the progress of deterioration can be slowed and the reliability of the light emitting device can be improved. Further, either digital driving or analog driving can be applied.

  Therefore, although not shown in FIG. 16, a color filter (colored layer) may be formed over a sealing substrate facing the substrate having elements. The color filter (colored layer) can be selectively formed by a droplet discharge method. When a color filter (colored layer) is used, high-definition display can be performed. This is because the color filter (colored layer) can correct a broad peak to be sharp in the emission spectrum of each RGB.

  As described above, the case where a material that emits light of each RGB is formed has been described. However, full color display can be performed by forming a material that emits light of a single color and combining a color filter and a color conversion layer. The color filter (colored layer) and the color conversion layer may be formed on, for example, a sealing substrate and attached to the substrate. In addition, as described above, any of the material that emits monochromatic light, the color filter (colored layer), and the color conversion layer can be formed by a droplet discharge method.

  Of course, monochromatic light emission may be displayed. For example, an area color type display device may be formed using monochromatic light emission. As the area color type, a passive matrix type display unit is suitable, and characters and symbols can be mainly displayed.

In the above configuration, a material having a low work function can be used as the cathode, and for example, Ca, Al, CaF ₂ , MgAg, AlLi, or the like is desirable. The electroluminescent layer may be any of a single layer type, a laminated type, and a mixed type having no layer interface. It is also formed from singlet materials, triplet materials, or combinations thereof, charge injection / transport materials containing organic compounds or inorganic compounds, and light-emitting materials, and low molecular organic compounds and medium molecular organic compounds (sublimation) based on the number of molecules. And an organic compound having a molecular number of 20 or less, or a chained molecule having a length of 10 μm or less), including one or more layers selected from macromolecular organic compounds, You may combine with the injection | pouring transport property or the hole injection transport property inorganic compound. The first electrode layer 484, the second electrode layer 465, the first electrode layer 472, and the second electrode layer 474 are formed using a transparent conductive film that transmits light. For example, indium oxide in addition to ITO and ITSO A transparent conductive film mixed with 2 to 20% zinc oxide (ZnO) is used. Note that plasma treatment in an oxygen atmosphere or heat treatment in a vacuum atmosphere is preferably performed before the first electrode layer 484, the first electrode layer 463, and the first electrode layer 472 are formed. A partition wall (also referred to as a bank) is formed using a material containing silicon, an organic material, and a compound material. A porous film may be used. However, it is preferable to use a photosensitive or non-photosensitive material such as acrylic or polyimide because the side surface has a shape in which the radius of curvature continuously changes and the upper thin film is formed without being cut off. This embodiment mode can be freely combined with Embodiment Mode 1 and Embodiment Mode 3.

(Embodiment 6)
Next, a mode in which a driver circuit for driving is mounted on the display panel manufactured according to Embodiments 3 to 5 will be described.

  First, a display device employing a COG method is described with reference to FIG. A pixel portion 2701 for displaying information such as characters and images is provided over the substrate 2700. A substrate provided with a plurality of drive circuits is divided into a rectangular shape, and a divided drive circuit (also referred to as a driver IC) 2751 is mounted on the substrate 2700. FIG. 22A illustrates a mode in which a plurality of driver ICs 2751 and an FPC 2750 are mounted on top of the driver ICs 2751. Further, the size to be divided may be substantially the same as the length of the side of the pixel portion on the signal line side, and a tape may be mounted on the tip of the driver IC on a single driver IC.

  Alternatively, a TAB method may be employed. In that case, a plurality of tapes may be attached and driver ICs may be mounted on the tapes as shown in FIG. As in the case of the COG method, a single driver IC may be mounted on a single tape. In this case, a metal piece or the like for fixing the driver IC may be attached together due to strength problems.

  A plurality of driver ICs mounted on these display panels may be formed on a rectangular substrate having a side of 300 mm to 1000 mm or more from the viewpoint of improving productivity.

  That is, a plurality of circuit patterns having a drive circuit portion and an input / output terminal as one unit may be formed on the substrate, and finally divided and taken out. The long side of the driver IC may be formed in a rectangular shape having a long side of 15 to 80 mm and a short side of 1 to 6 mm in consideration of the length of one side of the pixel portion and the pixel pitch. Or a length obtained by adding one side of the pixel portion and one side of each driver circuit.

  The advantage of the external dimensions of the driver IC over the IC chip lies in the length of the long side. When a driver IC formed with a long side of 15 to 80 mm is used, the number required for mounting corresponding to the pixel portion is as follows. This is less than when an IC chip is used, and the manufacturing yield can be improved. Further, when a driver IC is formed over a glass substrate, the shape of the substrate used as a base is not limited, and thus productivity is not impaired. This is a great advantage compared to the case of taking out an IC chip from a circular silicon wafer.

  In the case where the scan line driver circuit 3702 is formed over the substrate as shown in FIG. 25B, a driver IC in which a driver circuit driver circuit on the signal line side is formed in a region outside the pixel portion 3701. Is implemented. These driver ICs are drive circuits on the signal line side. In order to form a pixel region corresponding to RGB full color, the number of signal lines in the XGA class is 3072 and the number in the UXGA class is 4800. The signal lines formed in such a number are divided into several blocks at the end of the pixel portion 3701 to form lead lines, and are collected according to the pitch of the output terminals of the driver IC. Note that reference numeral 3704 in FIG. 25B denotes a signal line side input terminal.

  The driver IC is preferably formed of a crystalline semiconductor formed over a substrate, and the crystalline semiconductor is preferably formed by irradiating continuous-emitting laser light. Therefore, a continuous light emitting solid state laser or gas laser is used as an oscillator for generating the laser light. When a continuous light emission laser is used, a transistor can be formed using a polycrystalline semiconductor layer having a large grain size with few crystal defects. In addition, since the mobility and response speed are good, high-speed driving is possible, the operating frequency of the element can be improved as compared with the prior art, and there is less variation in characteristics, so that high reliability can be obtained. Note that for the purpose of further improving the operating frequency, the channel length direction of the transistor and the scanning direction of the laser light are preferably matched. This is because, in the laser crystallization process using a continuous-wave laser, the highest mobility is obtained when the channel length direction of the transistor and the scanning direction of the laser beam with respect to the substrate are substantially parallel (preferably −30 ° to 30 °). Is obtained. Note that the channel length direction corresponds to the direction in which current flows in the channel formation region, in other words, the direction in which charges move. The transistor thus fabricated has an active layer composed of a polycrystalline semiconductor layer in which crystal grains extend in the channel direction, which means that the crystal grain boundaries are formed substantially along the channel direction. means.

  In order to perform laser crystallization, it is preferable to significantly narrow down the laser beam, and the width of the laser beam shape (beam spot) should be about 1 mm to 3 mm, which is the same width of the short side of the driver IC. Is good. In order to ensure a sufficient and efficient energy density for the irradiated object, the laser light irradiation region is preferably linear. However, the line shape here does not mean a line in a strict sense, but means a rectangle or an ellipse having a large aspect ratio. For example, the aspect ratio is 2 or more (preferably 10 or more and 10,000 or less). In this manner, a method for manufacturing a display device with improved productivity can be provided by setting the width of the laser beam shape (beam spot) to the same length as the short side of the driver IC.

  As shown in FIGS. 22A and 22B, driver ICs may be mounted as both the scanning line driver circuit and the signal line driver circuit. In that case, the specifications of the driver ICs used on the scanning line side and the signal line side may be different.

In the pixel region, signal lines and scanning lines intersect to form a matrix, and transistors are arranged corresponding to the respective intersections. The present invention is characterized in that a TFT having an amorphous semiconductor or semi-amorphous semiconductor as a channel portion is used as a transistor arranged in a pixel region. The amorphous semiconductor is formed by a method such as a plasma CVD method or a sputtering method. A semi-amorphous semiconductor can be formed by a plasma CVD method at a temperature of 300 ° C. or lower. For example, even a non-alkali glass substrate having an outer dimension of 550 × 650 mm has a film thickness necessary for forming a transistor. Is formed in a short time. Such a feature of the manufacturing technique is effective in manufacturing a large-screen display device. In addition, a semi-amorphous TFT can obtain a field effect mobility of ² to 10 cm ² / V · sec by forming a channel formation region with SAS. In addition, when the present invention is used, a pattern can be formed in a desired shape with good controllability, and such a fine wiring with a short channel width can be stably formed without causing a defect such as a short circuit. . A TFT having electric characteristics necessary for sufficiently functioning a pixel can be formed. Therefore, this TFT can be used as a switching element for a pixel or an element constituting a driving circuit on the scanning line side. Therefore, a display panel that realizes system-on-panel can be manufactured.

  By using TFTs in which the semiconductor layer is formed of SAS, the scanning line side driver circuit can also be integrally formed on the substrate. In the case of using TFTs in which the semiconductor layer is formed of AS, the scanning line side driver circuit and the signal A driver IC may be mounted on both the line side drive circuits.

  In that case, it is preferable that the specifications of the driver ICs used on the scanning line side and the signal line side are different. For example, although a transistor constituting the driver IC on the scanning line side is required to have a withstand voltage of about 30 V, the driving frequency is 100 kHz or less, and a relatively high speed operation is not required. Therefore, it is preferable to set the channel length (L) of the transistors forming the driver on the scanning line side to be sufficiently large. On the other hand, it is sufficient for the transistor of the driver IC on the signal line side to have a withstand voltage of about 12V, but the drive frequency is about 65 MHz at 3V, and high speed operation is required. Therefore, it is preferable to set the channel length and the like of the transistors constituting the driver on the micron rule. When the present invention is used, fine pattern formation can be performed with good controllability, and it is possible to sufficiently cope with such micron rule.

  The method for mounting the driver IC is not particularly limited, and a known COG method, wire bonding method, or TAB method can be used.

  By setting the thickness of the driver IC to be the same as that of the counter substrate, the height between the two becomes substantially the same, which contributes to the reduction in thickness of the entire display device. In addition, since each substrate is made of the same material, thermal stress is not generated even when a temperature change occurs in the display device, and the characteristics of a circuit made of TFTs are not impaired. In addition, the number of driver ICs to be mounted in one pixel region can be reduced by mounting the drive circuit with a driver IC that is longer than the IC chip as shown in this embodiment.

  As described above, a driver circuit can be incorporated in the display panel.

(Embodiment 7)
An example of a protection circuit included in the display device of the present invention will be described.

  As shown in FIG. 22, a protection circuit 2713 can be formed between the external circuit and the internal circuit. The protection circuit is composed of one or a plurality of elements selected from a TFT, a diode, a resistance element, a capacitance element, and the like, and the configurations and operations of some protection circuits will be described below. First, the configuration of an equivalent circuit diagram of a protection circuit arranged between an external circuit and an internal circuit and corresponding to one input terminal will be described with reference to FIG. The protection circuit illustrated in FIG. 24A includes p-channel thin film transistors 7220 and 7230, capacitor elements 7210 and 7240, and a resistance element 7250. The resistance element 7250 is a two-terminal resistor, and an input voltage Vin (hereinafter referred to as Vin) is applied to one end, and a low potential voltage VSS (hereinafter referred to as VSS) is applied to the other end.

  The protection circuit illustrated in FIG. 24B is an equivalent circuit diagram in which the p-channel thin film transistors 7220 and 7230 are substituted with rectifying diodes 7260 and 7270. The protection circuit illustrated in FIG. 24C is an equivalent circuit diagram in which the p-channel thin film transistors 7220 and 7230 are substituted with TFTs 7350, 7360, 7370, and 7380. Further, as a protection circuit having a different structure from the above, the protection circuit illustrated in FIG. 24D includes resistors 7280 and 7290 and an n-channel thin film transistor 7300. A protection circuit illustrated in FIG. 24E includes resistors 7280 and 7290, a p-channel thin film transistor 7310, and an n-channel thin film transistor 7320. By providing the protection circuit, a rapid change in potential can be prevented, and destruction or damage of the element can be prevented, so that reliability is improved. Note that the element forming the protection circuit is preferably formed using an amorphous semiconductor with excellent withstand voltage. This embodiment mode can be freely combined with the above embodiment modes.

  This embodiment mode can be used in combination with each of Embodiment Modes 1 to 6.

(Embodiment 8)
A structure of a pixel of the display panel described in this embodiment will be described with reference to an equivalent circuit diagram illustrated in FIG. In this embodiment, an example in which a light-emitting element (EL element) is used as a display element of a pixel is described.

  In the pixel shown in FIG. 17A, a signal line 710, a power supply line 711, a power supply line 712, a power supply line 713 are arranged in the column direction, and a scanning line 714 is arranged in the row direction. The TFT 701 is a switching TFT, the TFT 703 is a driving TFT, the TFT 704 is a current control TFT, and further includes a capacitor 702 and a light emitting element 705.

  The pixel shown in FIG. 17C is different from the pixel shown in FIG. 17A except that the gate electrode of the TFT 703 is connected to the power supply line 715 arranged in the row direction. is there. That is, both pixels shown in FIGS. 17A and 17C show the same equivalent circuit diagram. However, in the case where the power supply line 712 is arranged in the column direction (FIG. 17A) and in the case where the power supply line 715 is arranged in the row direction (FIG. 17C), each power supply line is conductive on a different layer. Formed with body layers. Here, attention is paid to the wiring to which the gate electrode of the TFT 703 is connected, and FIGS. 17A and 17C are shown separately to show that the layers for producing these are different.

As a feature of the pixel shown in FIGS. 17A and 17C, a TFT 703 and a TFT 704 are connected in series in the pixel, and the channel length L ₃ , the channel width W _{3 of} the TFT 703, the channel length L _{4 of the} TFT 704, and the channel width W ₄ may be set to satisfy L ₃ / W ₃ : L ₄ / W ₄ = 5 to 6000: 1. As an example of satisfying 6000: 1, there is a case where L ₃ is 500 μm, W ₃ is 3 μm, L ₄ is 3 μm, and W ₄ is 100 μm. In addition, since the present invention can be processed into a fine desired shape, such a fine wiring with a short channel width can be stably formed without causing a defect such as a short circuit. Accordingly, a TFT having electric characteristics necessary for sufficiently functioning a pixel as shown in FIGS. 17A and 17C can be formed, and a highly reliable display panel with excellent display capability can be manufactured. .

Note that the TFT 703 operates in a saturation region and has a role of controlling a current value flowing through the light emitting element 705, and the TFT 704 has a role of operating in a linear region and controls supply of current to the light emitting element 705. Both TFTs preferably have the same conductivity type in terms of manufacturing process. The TFT 703 may be a depletion type TFT as well as an enhancement type. In the present invention having the above structure, since the TFT 704 operates in a linear region, a slight change in V _GS of the TFT 704 does not affect the current value of the light emitting element 705. That is, the current value of the light emitting element 705 is determined by the TFT 703 operating in the saturation region. The present invention having the above structure can provide a display device in which luminance unevenness of a light emitting element due to variation in TFT characteristics is improved and image quality is improved.

  In the pixels shown in FIGS. 17A to 17D, a TFT 701 controls input of a video signal to the pixel. When the TFT 701 is turned on and a video signal is input into the pixel, the capacitor 702 The video signal is held in Note that FIGS. 17A and 17C illustrate a structure in which the capacitor 702 is provided; however, the present invention is not limited to this, and the capacity for holding a video signal can be covered by a gate capacity or the like. In particular, the capacitor 702 is not necessarily provided.

  The light-emitting element 705 has a structure in which an electroluminescent layer is sandwiched between two electrodes, and a potential difference is generated between the pixel electrode and the counter electrode (between the anode and the cathode) so that a forward bias voltage is applied. Is provided. The electroluminescent layer is composed of a wide variety of materials such as organic materials and inorganic materials. The luminescence in the electroluminescent layer includes light emission (fluorescence) when returning from a singlet excited state to a ground state, and a triplet excited state. And light emission (phosphorescence) when returning to the ground state.

  The pixel shown in FIG. 17B has the same pixel structure as that shown in FIG. 17A except that a TFT 706 and a scanning line 716 are added. Similarly, the pixel illustrated in FIG. 17D has the same pixel structure as that illustrated in FIG. 17C except that a TFT 706 and a scanning line 716 are added.

  The TFT 706 is controlled to be turned on or off by a newly arranged scanning line 716. When the TFT 706 is turned on, the charge held in the capacitor 702 is discharged, and the TFT 704 is turned off. That is, the arrangement of the TFT 706 can forcibly create a state in which no current flows through the light emitting element 705. Accordingly, the configurations in FIGS. 17B and 17D can improve the duty ratio because the lighting period can be started simultaneously with or immediately after the start of the writing period without waiting for signal writing to all the pixels. It becomes possible.

  In the pixel shown in FIG. 17E, a signal line 750, a power supply line 751, a power supply line 752, and a scanning line 753 are arranged in the column direction. Further, the TFT 741 is a switching TFT, the TFT 743 is a driving TFT, and further includes a capacitor element 742 and a light emitting element 744. The pixel illustrated in FIG. 17F has the same pixel structure as that illustrated in FIG. 17E except that a TFT 745 and a scanning line 754 are added. Note that the duty ratio can also be improved in the structure of FIG.

  As described above, when the present invention is used, a pattern such as a wiring can be accurately and stably formed without causing defective formation, so that high electrical characteristics and reliability can be imparted to the TFT. Therefore, it can sufficiently cope with applied technology for improving the display capability of the pixel in accordance with the purpose of use.

  This embodiment mode can be used in combination with each of Embodiment Modes 1, 3, and 5 to 7.

(Embodiment 9)
This embodiment will be described with reference to FIG. FIG. 11 shows an example in which an EL display module is formed using a TFT substrate 2800 manufactured by applying the present invention. In FIG. 11, a pixel portion including pixels is formed over a TFT substrate 2800.

  In FIG. 11, the same TFT as that formed in the pixel or the gate of the TFT and one of the source and drain is connected between the driver circuit and the pixel outside the pixel portion, and similar to the diode. The protection circuit portion 2801 operated in the above is provided. As the driver circuit 2809, a driver IC formed of a single crystal semiconductor, a stick driver IC formed of a polycrystalline semiconductor film over a glass substrate, a driver circuit formed of SAS, or the like is applied.

  The TFT substrate 2800 is fixed to the sealing substrate 2820 through spacers 2806a and 2806b formed by a droplet discharge method. The spacer is preferably provided to keep the distance between the two substrates constant even when the substrate is thin and the area of the pixel portion is increased. Resin material having light-transmitting property at least in the visible region in the gap between the TFT substrate 2800 and the sealing substrate 2820 on the light-emitting element 2804 and the light-emitting element 2805 connected to the TFT 2802 and the TFT 2803, respectively. May be solidified by filling, or may be filled with anhydrous nitrogen or inert gas.

  FIG. 11 shows a case where the light-emitting element 2804, the light-emitting element 2805, and the light-emitting element 2815 have a top emission type (top emission type) structure, and emits light in the direction of the arrow shown in the drawing. Each pixel can perform multicolor display by changing the emission color of the pixels to red, green, and blue. At this time, by forming the colored layer 2807a, the colored layer 2807b, and the colored layer 2807c corresponding to each color on the sealing substrate 2820 side, the color purity of the emitted light can be increased. Alternatively, the pixel may be combined with a colored layer 2807a, a colored layer 2807b, or a colored layer 2807c as a white light emitting element.

  The drive circuit 2809 is connected to the external circuit board 2811 by a wiring board 2810 provided at one end of the TFT substrate 2800. Further, a heat pipe 2813 and a heat radiating plate 2812 may be provided in contact with or in proximity to the TFT substrate 2800 to enhance the heat radiation effect.

  Although the top emission EL module is shown in FIG. 11, the bottom emission structure, of course, a dual emission structure in which light is emitted from both the upper surface and the lower surface may be changed by changing the configuration of the light emitting element and the arrangement of the external circuit board. In the case of a top emission type structure, an insulating layer serving as a partition wall may be colored and used as a black matrix. The partition walls can be formed by a droplet discharge method, and may be formed by mixing a resin material such as polyimide with a pigment-based black resin, carbon black, or the like, or may be a laminate thereof.

  In addition, the EL display module may block reflected light of light incident from the outside using a retardation plate or a polarizing plate. In the case of a top emission display device, an insulating layer serving as a partition may be colored and used as a black matrix. This partition wall can also be formed by a droplet discharge method or the like. Carbon black or the like may be mixed with a pigment-based black resin or a resin material such as polyimide, or may be laminated. A different material may be discharged to the same region a plurality of times by a droplet discharge method to form a partition wall. As the phase difference plate and the phase difference plate, λ / 4 and λ / 2 may be used and designed so that light can be controlled. The configuration is purely light-emitting element, sealing substrate (sealing material), retardation plate, retardation plate (λ / 4, λ / 2), polarizing plate from the TFT element substrate side. The light emitted from the light passes through these and is emitted to the outside from the polarizing plate side. The retardation plate and the polarizing plate may be installed on the side from which light is emitted, and may be installed on both sides as long as the display is a double-sided emission type that emits light on both sides. Further, an antireflection film may be provided outside the polarizing plate. This makes it possible to display a higher-definition and precise image.

  In the TFT substrate 2800, a sealing structure may be formed by attaching a resin film to the side where the pixel portion is formed using a sealing material or an adhesive resin. Although glass sealing using a glass substrate is described in this embodiment mode, various sealing methods such as resin sealing using a resin, plastic sealing using a plastic, and film sealing using a film can be used. A gas barrier film for preventing the permeation of water vapor may be provided on the surface of the resin film. By adopting a film sealing structure, further reduction in thickness and weight can be achieved.

  This embodiment mode can be used in combination with each of Embodiment Modes 1, 3, and 5 to 8.

(Embodiment 10)
This embodiment will be described with reference to FIGS. 15A and 15B. FIG. 15A and FIG. 15B illustrate an example in which a liquid crystal display module is formed using a TFT substrate 2600 manufactured by applying the present invention.

  FIG. 15A illustrates an example of a liquid crystal display module. A TFT substrate 2600 and a counter substrate 2601 are fixed to each other with a sealant 2602, and a pixel portion 2603 and a liquid crystal layer 2604 are provided therebetween to form a display region. The colored layer 2605 is necessary for color display. In the case of the RGB method, a colored layer corresponding to each color of red, green, and blue is provided corresponding to each pixel. A polarizing plate 2606, a polarizing plate 2607, and a lens film 2613 are disposed outside the TFT substrate 2600 and the counter substrate 2601. The light source is composed of a cold cathode tube 2610 and a reflector 2611. The circuit board 2612 is connected to the TFT substrate 2600 by a drive circuit 2608 and a flexible wiring board 2609, and an external circuit such as a control circuit or a power supply circuit is incorporated. . The liquid crystal display module uses a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, an ASM (Axial Symmetrical Aligned Micro mode, etc.). Can do.

  In particular, a display device manufactured according to the present invention can have higher performance by using an OCB mode capable of high-speed response. FIG. 15B shows an example in which the OCB mode is applied to the liquid crystal display module shown in FIG. 15A, which is an FS-LCD (Field sequential-LCD). The FS-LCD emits red light, green light, and blue light in one frame period, and can perform color display by combining images using time division. Further, since each light emission is performed by a light emitting diode or a cold cathode tube, a color filter is unnecessary. Therefore, since it is not necessary to arrange color filters of the three primary colors, 9 times as many pixels can be displayed with the same area. On the other hand, since three colors of light are emitted in one frame period, a high-speed response of the liquid crystal is required. When the FS mode and the OCB mode are applied to the display device of the present invention, a display device or a liquid crystal television device with higher performance and higher image quality can be completed.

  The liquid crystal layer in the OCB mode has a so-called π cell structure. The π cell structure is a structure in which the pretilt angles of liquid crystal molecules are aligned in a plane-symmetric relationship with respect to the center plane between the active matrix substrate and the counter substrate. The alignment state of the π cell structure is splay alignment when no voltage is applied between the substrates, and shifts to bend alignment when a voltage is applied. When a voltage is further applied, the bend-aligned liquid crystal molecules are aligned perpendicularly to both substrates, and light is transmitted. In the OCB mode, high-speed response that is about 10 times faster than the conventional TN mode can be realized.

  Further, as a mode corresponding to the FS mode, HV-FLC, SS-FLC, or the like using a ferroelectric liquid crystal (FLC) capable of high-speed operation can be used. In the OCB mode, nematic liquid crystal having a relatively low viscosity is used, and in HV-FLC and SS-FLC, smectic liquid crystal is used. it can.

  In addition, the high-speed optical response speed of the liquid crystal display module is increased by narrowing the cell gap of the liquid crystal display module. The speed can also be increased by reducing the viscosity of the liquid crystal material. The increase in speed is more effective when the pixel in the pixel region of the TN mode liquid crystal display module or the dot pitch is 30 μm or less.

  The liquid crystal display module in FIG. 15B is a transmissive liquid crystal display module, and is provided with a red light source 2910a, a green light source 2910b, and a blue light source 2910c as light sources. A control unit 2912 is installed to control on / off of the red light source 2910a, the green light source 2910b, and the blue light source 2910c. The light emission of each color is controlled by the control unit 2912, light enters the liquid crystal, an image is synthesized using time division, and color display is performed.

  As described above, when the present invention is used, a highly delicate and highly reliable liquid crystal display module can be manufactured.

  This embodiment mode can be used in combination with each of Embodiment Mode 1, Embodiment Mode 4, Embodiment Mode 6, and Embodiment Mode 7.

(Embodiment 11)
A television device can be completed with the display device formed according to the present invention. FIG. 21 is a block diagram illustrating a main configuration of the television device. In the display panel, only the pixel portion 601 is formed as shown in FIG. 25A, and the scanning line side driver circuit 603 and the signal line side driver circuit 602 have a TAB method as shown in FIG. In the case of mounting by the COG method, the case of mounting by the COG method as shown in FIG. 22A, the TFT is formed as shown in FIG. In the case where the signal line side driver circuit 602 is separately mounted as a driver IC and formed integrally therewith, the pixel portion 601, the signal line side driver circuit 602, and the scanning line side driver circuit 603 are formed on the substrate as shown in FIG. Although it may be integrally formed, any form may be used.

  As other external circuit configurations, on the input side of the video signal, among the signals received by the tuner 604, the video signal amplifier circuit 605 that amplifies the video signal, and the signals output from the video signal amplifier circuit 605 are red, green, and blue colors. And a control circuit 607 for converting the video signal into the input specification of the driver IC. The control circuit 607 outputs signals to the scanning line side and the signal line side, respectively. In the case of digital driving, a signal dividing circuit 608 may be provided on the signal line side and an input digital signal may be divided into m pieces and supplied.

  Of the signals received by the tuner 604, the audio signal is sent to the audio signal amplification circuit 609, and the output is supplied to the speaker 613 through the audio signal processing circuit 610. The control circuit 611 receives the receiving station (reception frequency) and volume control information from the input unit 612 and sends a signal to the tuner 604 and the audio signal processing circuit 610.

  These liquid crystal display modules and EL display modules can be assembled into a housing as shown in FIGS. 20A and 20B to complete a television device. When an EL display module as shown in FIG. 11 is used, an EL television device is used, and when a liquid crystal display module as shown in FIGS. 15A and 15B is used, a liquid crystal television device can be completed. A main screen 2003 is formed by the display module, and a speaker portion 2009, operation switches, and the like are provided as other accessory equipment. Thus, a television device can be completed according to the present invention.

  A display panel 2002 is incorporated in a housing 2001, and general television broadcasting is received by a receiver 2005, and connected to a wired or wireless communication network via a modem 2004 (one direction (from a sender to a receiver)). ) Or bi-directional (between the sender and the receiver, or between the receivers). The television device can be operated by a switch incorporated in the housing or a separate remote control device 2006, and the remote control device 2006 also includes a display unit 2007 for displaying information to be output. good.

  In addition, the television device may have a configuration in which a sub screen 2008 is formed using the second display panel in addition to the main screen 2003 to display channels, volume, and the like. In this configuration, the main screen 2003 may be formed using an EL display panel with an excellent viewing angle, and the sub screen may be formed using a liquid crystal display panel that can display with low power consumption. In order to prioritize the reduction in power consumption, the main screen 2003 may be formed using a liquid crystal display panel, the sub screen may be formed using an EL display panel, and the sub screen may blink. When the present invention is used, a highly reliable display device can be obtained even when such a large substrate is used and a large number of TFTs and electronic components are used.

  FIG. 20B illustrates a television device having a large display portion of 20 to 80 inches, for example, which includes a housing 2010, a display portion 2011, a remote control device 2012 that is an operation portion, a speaker portion 2013, and the like. The present invention is applied to manufacture of the display portion 2011. The television device in FIG. 20B is a wall-hanging type and does not require a large installation space.

  Of course, the present invention is not limited to a television device, but can be applied to various uses such as a monitor for a personal computer, an information display board in a railway station or airport, an advertisement display board in a street, etc. can do.

(Embodiment 12)
Various display devices can be manufactured by applying the present invention. That is, the present invention can be applied to various electronic devices in which these display devices are incorporated in a display portion.

  Such electronic devices include video cameras, digital cameras, projectors, head mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, game machines, personal digital assistants (mobile computers, mobile phones, electronic books, etc.) ), An image reproducing device including a recording medium (specifically, an apparatus including a display capable of reproducing a recording medium such as Digital Versatile Disc (DVD) and displaying the image). Examples thereof are shown in FIG.

  FIG. 19A illustrates a personal computer, which includes a main body 2101, a housing 2102, a display portion 2103, a keyboard 2104, an external connection port 2105, a pointing mouse 2106, and the like. The present invention is applied to manufacturing the display portion 2103. When the present invention is used, a highly reliable high-quality image can be displayed even if the size is reduced and wiring and the like are refined.

  FIG. 19B shows an image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2201, a housing 2202, a display portion A 2203, a display portion B 2204, and a recording medium (DVD etc.) reading portion 2205. , An operation key 2206, a speaker portion 2207, and the like. The display portion A 2203 mainly displays image information, and the display portion B 2204 mainly displays character information. The present invention is applied to the production of the display portions A, B 2203, and 2204. When the present invention is used, a highly reliable high-quality image can be displayed even if the size is reduced and wiring and the like are refined.

  FIG. 19C illustrates a mobile phone, which includes a main body 2301, an audio output portion 2302, an audio input portion 2303, a display portion 2304, operation switches 2305, an antenna 2306, and the like. By applying the display device manufactured according to the present invention to the display portion 2304, a highly reliable and high-quality image can be displayed even in a mobile phone that is downsized and wiring and the like are precise.

FIG. 19D illustrates a video camera, which includes a main body 2401, a display portion 2402, a housing 2403, an external connection port 2404, a remote control reception portion 2405, an image receiving portion 2406, a battery 2407, an audio input portion 2408, an eyepiece portion 2409, and an operation. Key 2410 and the like. The present invention can be applied to the display portion 2402. By applying the display device manufactured according to the present invention to the display portion 2402, a highly reliable and high-quality image can be displayed even with a video camera that is downsized and wiring and the like are precise. This embodiment mode can be freely combined with the above embodiment modes.
(Embodiment 13)

  According to the present invention, a semiconductor device that functions as a processor chip (also referred to as a wireless chip, a wireless processor, a wireless memory, or a wireless tag) can be formed. The semiconductor device of the present invention has a wide range of uses. For example, banknotes, coins, securities, certificates, bearer bonds, packaging containers, books, recording media, personal items, vehicles, foods, clothing It can be used in health supplies, daily necessities, medicines and electronic devices.

  Banknotes and coins are money that circulates in the market, and include those that are used in the same way as money in a specific area (cash vouchers), commemorative coins, and the like. Securities refer to checks, securities, promissory notes, and the like, and can be provided with a processor chip 90 (see FIG. 26A). The certificate refers to a driver's license, a resident's card, and the like, and can be provided with a processor chip 91 (see FIG. 26B). Personal belongings refer to bags, glasses, and the like, and can be provided with a processor chip 97 (see FIG. 26C). Bearer bonds refer to stamps, gift cards, and various gift certificates. Packaging containers refer to wrapping paper such as lunch boxes, plastic bottles, and the like, and can be provided with a processor chip 93 (see FIG. 26D). Books refer to books, books, and the like, and can be provided with a processor chip 94 (see FIG. 26E). The recording medium refers to DVD software, a video tape, or the like, and can be provided with a processor chip 95 (see FIG. 26F). The vehicles refer to vehicles such as bicycles, ships, and the like, and can be provided with a processor chip 96 (see FIG. 26G). Foods refer to food products, beverages, and the like. Clothing refers to clothing, footwear, and the like. Health supplies refer to medical equipment, health equipment, and the like. Livingware refers to furniture, lighting equipment, and the like. Chemicals refer to pharmaceuticals, agricultural chemicals, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (TV receivers, flat-screen TV receivers), mobile phones, and the like.

  Counterfeiting can be prevented by providing processor chips for bills, coins, securities, certificates, bearer bonds, and the like. In addition, providing processor chips for personal items such as packaging containers, books, recording media, personal items, foods, daily necessities, electronic devices, etc., can improve the efficiency of inspection systems and rental store systems. it can. By providing processor chips for vehicles, health supplies, medicines, etc., counterfeiting and theft can be prevented, and medicines can prevent mistakes in taking medicines. As a method for providing the processor chip, the processor chip is provided on the surface of the article or embedded in the article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in the organic resin.

  Further, by applying a processor chip that can be formed according to the present invention to an object management or distribution system, it is possible to increase the functionality of the system. For example, by reading the information recorded on the processor chip provided on the tag with a reader / writer provided on the side of the belt conveyor, information such as the distribution process and delivery destination is read, and inspection of goods and distribution of goods Can be done easily.

  The structure of a processor chip that can be formed according to the present invention will be described with reference to FIG. The processor chip is formed of a thin film integrated circuit 9303 and an antenna 9304 connected thereto. Further, the thin film integrated circuit and the antenna are sandwiched between cover materials 9301 and 9302. The thin film integrated circuit 9303 may be bonded to the cover material with an adhesive. In FIG. 27, one thin film integrated circuit 9303 is bonded to a cover material 9301 with an adhesive 9320 interposed therebetween.

  The thin film integrated circuit 9303 is formed in the same manner as the TFT described in any of the above embodiments, and is peeled off by a known peeling step and provided on the cover material. In this embodiment, the wiring layer for forming the antenna 9304 is formed so as to be embedded in the insulating layer 9311 and the insulating layer 9321. Openings are formed in the insulating layer 9311 and the insulating layer 9321, and a mask layer whose surface wettability is controlled is formed over the insulating layer 9321. The mask layer is processed so that wettability with respect to the composition containing a conductive material for forming the wiring layer 9323 is reduced by performing plasma treatment in a gas atmosphere containing fluorine. The composition containing the liquid conductive material does not adhere to the mask surface having low wettability with respect to the composition, or does not become stable even if it adheres to the relatively wettable opening. Filled. Thus, since the composition containing the conductive material is filled, the wiring layer can be stably formed with good controllability, and loss of the material can be prevented. In addition, when an insulating layer having a hole is used for the insulating layer 9311 and the insulating layer 9321, the hole is formed so that part of the wiring layer 9323 is filled; thus, the wiring layer 9323 includes the insulating layer 9311 and the insulating layer 9321. The electrode layer included in the thin film integrated circuit 9303 is formed with good adhesion. The semiconductor element used for the thin film integrated circuit 9303 is not limited to this. For example, a memory element, a diode, a photoelectric conversion element, a resistance element, a coil, a capacitor element, an inductor, or the like can be used in addition to the TFT.

  As shown in FIG. 27, an insulating layer 9311 is formed over the TFT of the thin film integrated circuit 9303, and an antenna 9304 connected to the TFT through the insulating layer 9311 is formed. A barrier film 9312 made of a silicon nitride film or the like is formed over the insulating layer 9311 and the antenna 9304.

  The antenna 9304 is formed by discharging droplets having a conductor such as gold, silver, copper, or the like by a droplet discharge method, followed by drying and baking. By forming the antenna by a droplet discharge method, the number of steps can be reduced, and the cost can be reduced accordingly.

  Cover materials 9301 and 9302 are a sealing film (made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, etc.), paper made of a fibrous material, base film (polyester, polyamide, inorganic vapor deposition film, paper) Etc.) and an adhesive synthetic resin film (acrylic synthetic resin, epoxy synthetic resin, etc.). The sealing film is subjected to a sealing process with the object to be processed by thermocompression bonding. When performing the sealing process, an adhesive layer provided on the outermost surface of the sealing film or an outermost layer The provided layer (not the adhesive layer) is melted by heat treatment and bonded by pressure.

  Further, by using an incineration-free pollution material such as paper, fiber, carbon graphite, etc., the used processor chip can be incinerated or cut. In addition, processor chips using these materials are non-polluting because they do not generate toxic gases even when incinerated.

  In FIG. 27, the processor chip is provided on the cover material 9301 through the adhesive 9320. However, instead of the cover material 9301, the processor chip may be attached to an article for use.

The conceptual diagram explaining this invention. The conceptual diagram explaining this invention. 8A and 8B illustrate a method for manufacturing a semiconductor device using the present invention. 8A and 8B illustrate a method for manufacturing a semiconductor device using the present invention. 6A and 6B illustrate a display device using the present invention. 4A and 4B illustrate a method for manufacturing a display device using the present invention. 4A and 4B illustrate a method for manufacturing a display device using the present invention. 4A and 4B illustrate a method for manufacturing a display device using the present invention. 6A and 6B illustrate a display device using the present invention. 8A and 8B illustrate an EL display panel using the present invention. Sectional drawing explaining the structural example of the EL display module using this invention. 6A and 6B illustrate a display device using the present invention. 6A and 6B illustrate a display device using the present invention. 6A and 6B illustrate a liquid crystal display panel using the present invention. Sectional drawing explaining the structural example of the liquid crystal display module using this invention. 4A and 4B illustrate a method for manufacturing a display device using the present invention. FIG. 10 is a circuit diagram illustrating a structure of a pixel that can be applied to an EL display panel using the present invention. 3A and 3B each illustrate a structure of a light-emitting element that can be applied to the present invention. FIG. 11 illustrates an electronic device to which the present invention is applied. FIG. 11 illustrates an electronic device to which the present invention is applied. 1 is a block diagram illustrating a main configuration of an electronic device to which the present invention is applied. The top view of the display apparatus using this invention. The figure explaining the structure of the droplet dripping apparatus which can be applied to this invention. The figure which shows the protection circuit to which this invention is applied. The top view of the display apparatus using this invention. 1 is a diagram showing a semiconductor device to which the present invention is applied. 1 is a diagram showing a semiconductor device to which the present invention is applied. The figure which shows a prior art example. 2A and 2B illustrate a structure of a droplet discharge device that can be applied to the present invention.

Explanation of symbols

20 counter substrate 30 TFT substrate 32 sealing material 33 liquid crystal 34 barrier layer 35 marker 40 control device 41 marker 42 imaging means 43 head 90 processor chip 91 processor chip 93 processor chip 94 processor chip 95 processor chip 96 processor chip 97 processor chip 100 substrate 101 Wiring layer 102 Insulating layer 103 Insulating layer 104 Insulating layer 105a Mask layer 105b Mask layer 106 Opening 107a Mask layer 107b Mask layer 107c Mask layer 108a Opening 108b Opening 109a Low wettability region 109b Low wettability region 109c Low wettability region 110a conductive layer 110b conductive layer 111a wiring layer 111b wiring layer 112a droplet discharge device 112b droplet discharge device 121a conductive layer 121b conductive layer 122 insulating layer 123 hole 124 Insulating layer 125 Hole 150 Substrate 151a Element isolation region 151b Element isolation region 151c Element isolation region 152a Gate insulation layer 152b Gate insulation layer 153a Gate electrode layer 153b Gate electrode layer 154a Side wall 154b Side wall 154c Side wall 154d Side wall 155a Source region Or drain region 155b source region or drain region 155c source region or drain region 156a source region or drain region 156b source region or drain region 156c source region or drain region 156d source region or drain region 157 insulating layer 158a mask Layer 158b Mask layer 158c Mask layer 158d Mask layer 158e Mask layer 159a Opening 159b Open Portion 159c Opening portion 159d Opening portion 160 Droplet discharge method 161a Low wettability region 161b Low wettability region 161c Low wettability region 161d Low wettability region 161e Low wettability region 162a Conductive layer 162b Conductive layer 162c Conductive layer 162d Conductive layer 163a Source electrode layer or drain electrode layer 163b Source electrode layer or drain electrode layer 163c Source electrode layer or drain electrode layer 163d Source electrode layer or drain electrode layer 165 Insulating layer 166 Insulating layer 167 Insulating layer 168a Low wettability region 168b Low wettability region 168c Low wettability region 168d Low wettability region 168e Low wettability region 169 Droplet ejection method 170a MOS transistor 170b MOS transistor 171a Conductive layer 171b Conductive layer 171c Conductive layer 171d Conductive layer 172a Wiring layer 172b Wiring layer 72c wiring layer 172d wiring layer 180 insulating layer 181 insulating layer 182 insulating layer 200 substrate 221 polarizing plate 222 insulating layer 223 insulating layer 224 wiring layer 225 pixel electrode layer 226 insulating layer 230 insulating film 231 source electrode layer or drain electrode layer 232 capacitive wiring Layer 233 Gate wiring layer 235 n-channel thin film transistor 236 p-channel thin film transistor 237 n-channel thin film transistor 237 thin film transistor 244 liquid crystal layer 245 insulating layer 246 conductor layer 247 colored layer 248 counter substrate 250 polarizing plate 251 sealing material 252 terminal electrode layer 253 different Isotropic conductive film 254 FPC
260 Pixel region 261a Scan line drive region 261b Scan line drive region 262 Signal line drive circuit 275 Spacer 300 Substrate 301 Gate electrode layer 302 Gate electrode layer 303 Gate electrode layer 304 First electrode layer 305a Gate insulation layer 305b Gate insulation layer 306 Non- Crystalline semiconductor film 307 Metal film 308 Semiconductor film 309 having n-type Crystalline semiconductor film 310 Crystalline semiconductor film 311 Semiconductor film 312 having n-type Semiconductor layer 313 Semiconductor layer 314 Semiconductor layer 315 Semiconductor layer 316 having n-type n-type N-type semiconductor layer 317 n-type semiconductor layer 318a mask layer 318b mask layer 318c mask layer 318d mask layer 319 p-type impurity element 320a p-type impurity region 320b p-type impurity region 321 conductive layer 322 conductive layer 324a n-type Semiconductor layer 324b Semiconductor layer 325a having n-type Semiconductor layer 325b having p-type Semiconductor layer 326 having p-type Semiconductor layer 327a having n-type Source electrode layer or drain electrode layer 327b Source electrode layer or drain electrode layer 327c Source electrode layer Or drain electrode layer 328 source electrode layer or drain electrode layer 330 insulating film 335 n-channel thin film transistor 336 p-channel thin film transistor 337 n-channel thin film transistor 338 capacitor 339 insulating layer 340a opening 340b opening 340c opening 340d opening 341 wiring Layer 342 Gate wiring layer 343 Insulating layer 344 Electroluminescent layer 345 Second electrode layer 346 Filler 347 Sealing substrate 348 Sealing material 352 Terminal electrode layer 353 Anisotropic conductive film 354 FPC
360a gate electrode layer 360b gate electrode layer 361 semiconductor layer 362 n-type semiconductor layer 363 conductive layer 364 n-channel thin film transistor 365a n-type semiconductor layer 365b n-type semiconductor layer 366a source or drain electrode layer 366b source Electrode layer or drain electrode layer 366c Source electrode layer or drain electrode layer 367 Gate wiring layer 370 Conductive layer 371 Semiconductor layer 372 Semiconductor layer 373 Semiconductor layer 375 Semiconductor layer 380a Droplet discharge device 380b Droplet discharge device 380c Droplet discharge device 381 Insulation Layer 382a Mask layer 382b Mask layer 382c Mask layer 382d Mask layer 382e Mask layer 382f Mask layer 383a Low wettability region 383b Low wettability region 383c Low wettability region 383d Low wettability region 383e Low wettability Region 383f Low wettability region 384a Conductive layer 384b Conductive layer 384c Conductive layer 385a Droplet discharge method 385b Droplet discharge method 385c Droplet discharge method 386 Source or drain electrode layer 390 Pixel region 391a Scan line drive region 391b Scan line drive Region 392 Signal line driver circuit 393 Connection region 460 Substrate 461 Thin film transistor 462 Wiring layer 463 First electrode layer 464 Electroluminescent layer 465 Second electrode layer 470 Substrate 471 Thin film transistor 472 First electrode layer 473 Electroluminescent layer 474 Second Electrode layer 475 Wiring layer 480 Substrate 481 Thin film transistor 484 First electrode layer 485 Electroluminescent layer 486 Second electrode layer 487a Source or drain electrode layer 487b Source or drain electrode layer 488 Wiring layer 493 Gate electrode layer 494 Semiconductor Layer 4 5a n-type semiconductor layer 495b n-type semiconductor layer 496 channel protective layer 497 gate insulating film 498 insulating layer 499 insulating layer 601 pixel portion 602 signal line side driver circuit 603 scanning line side driver circuit 604 tuner 605 video signal amplifier circuit 606 Video signal processing circuit 607 Control circuit 608 Signal division circuit 609 Audio signal amplification circuit 610 Audio signal processing circuit 611 Control circuit 612 Input unit 613 Speaker 701 TFT
702 Capacitor element 703 TFT
704 TFT
705 Light emitting element 706 TFT
710 Signal line 711 Power line 712 Power line 713 Power line 714 Scan line 715 Power line 716 Scan line 741 TFT
742 Capacitance element 743 TFT
744 Light Emitting Element 745 TFT
750 Signal line 751 Power line 752 Power line 753 Scan line 754 Scan line 800 Electrode layer 801 Electrode layer 802 Third layer 803 Second layer 804 First layer 805 Electrode layer 806 Electrode layer 807 Electrode layer 850 Second electrode Layer 860 Electroluminescent layer 870 First electrode layer 1001 Semiconductor substrate 1002 Insulating film 1003 First wiring 1004 Interlayer insulating film 1005 Etching stop insulating film 1006 Inter-wiring insulating film 1007 Resist film 1009 Groove 1010 Resist film 1012 Connection hole 1023 Copper 1024 Connection Plug unit 1025 Second wiring 1400 Substrate 1403 Droplet ejection unit 1404 Imaging unit 1405 Head 1406 Dotted line 1407 Control unit 1408 Storage medium 1409 Image processing unit 1410 Computer 1411 Marker 1412 Head 1413 Material supply source 1414 Material Supply source 2001 Case 2002 Display panel 2003 Main screen 2004 Modem 2005 Receiver 2006 Remote control device 2007 Display portion 2008 Sub screen 2009 Speaker portion 2010 Case 2011 Display portion 2012 Remote control device 2013 Speaker portion 2101 Main body 2102 Case 2103 Display portion 2104 Keyboard 2105 External connection port 2106 Pointing mouse 2201 Main body 2202 Case 2203 Display unit A
2204 Display unit B
2205 Storage medium reading unit 2206 Operation key 2207 Speaker unit 2301 Main unit 2302 Audio output unit 2303 Audio input unit 2304 Display unit 2305 Operation switch 2306 Antenna 2401 Main unit 2402 Display unit 2403 Case 2404 External connection port 2405 Remote control reception unit 2406 Image reception unit 2407 Battery 2408 Audio input unit 2409 Eyepiece unit 2410 Operation key 2600 TFT substrate 2601 Counter substrate 2602 Sealing material 2603 Pixel unit 2604 Liquid crystal layer 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Driving circuit 2609 Flexible wiring board 2610 Cold cathode tube 2611 Reflecting plate 2612 Circuit board 2613 Lens film 2700 Substrate 2701 Pixel portion 2702 Pixel 2703 Scan line side input terminal 2704 Signal line side input terminal 713 protection circuit 2750 FPC
2751 Driver IC
2800 TFT substrate 2801 Protection circuit part 2802 TFT
2803 TFT
2804 Light emitting element 2805 Light emitting element 2806a Spacer 2806b Spacer 2807a Colored layer 2807b Colored layer 2807c Colored layer 2809 Driving circuit 2810 Wiring board 2811 External circuit board 2812 Heat sink 2813 Heat pipe 2815 Light emitting element 2820 Sealing board 2910a Red light source 2910c Light source 2912 Control unit 3700 Substrate 3701 Pixel unit 3702 Scanning line side driving circuit 3704 Signal line side input terminal 4700 Glass substrate 4701 Pixel unit 4702 Scanning line driving circuit 4704 Signal line driving circuit 7210 Capacitance element 7220 p channel thin film transistor 7230 p channel thin film transistor 7240 Capacitance element 7250 Resistance element 7260 Diode 7270 Diode 7280 Resistance 7290 Resistance 7300 n Yaneru thin film transistor 7310 p-channel thin film transistor 7320 n-channel thin film transistor 7350 TFT
7360 TFT
7370 TFT
7380 TFT
9301 Cover material 9302 Cover material 9303 Thin film integrated circuit 9304 Antenna 9311 Insulating layer 9312 Barrier film 9320 Adhesive 9321 Insulating layer 9323 Wiring layer

Claims (7)

Forming a first conductive layer;
Forming a first insulating layer on the first conductive layer;
Forming a second insulating layer on the first insulating layer;
Forming a first mask layer having a first opening on the second insulating layer;
A first opening reaching the first conductive layer is formed by etching the first insulating layer and the second insulating layer through the first mask layer;
After removing the first mask layer, a composition having a second opening having a larger opening area than the first opening at a position overlapping with the first opening and containing a conductive material. Forming a second mask layer having low wettability on the second insulating layer;
Etching the second insulating layer so that a part of the upper surface of the first insulating layer is exposed to form a second opening;
A method for manufacturing a semiconductor device, wherein the first opening and the second opening are filled with a composition containing the conductive material to form a second conductive layer. Forming a first conductive layer;
Forming a first insulating layer on the first conductive layer;
Forming a second insulating layer having holes on the first insulating layer;
Forming a first mask layer having a first opening on the second insulating layer;
A first opening reaching the first conductive layer is formed by etching the first insulating layer and the second insulating layer through the first mask layer;
After removing the first mask layer, a composition having a second opening having a larger opening area than the first opening at a position overlapping with the first opening and containing a conductive material. Forming a second mask layer having low wettability on the second insulating layer;
Etching the second insulating layer so that a part of the upper surface of the first insulating layer is exposed to form a second opening;
A semiconductor device, wherein the first opening, the second opening, and the hole of the second insulating layer are filled with a composition containing the conductive material to form a second conductive layer. Manufacturing method. Forming a first conductive layer;
Forming a first insulating layer on the first conductive layer;
Forming a second insulating layer on the first insulating layer;
Forming a third insulating layer on the second insulating layer;
Forming a first mask layer having a first opening on the third insulating layer;
A first opening reaching the first conductive layer by etching the first insulating layer, the second insulating layer, and the third insulating layer through the first mask layer Form the
After removing the first mask layer, a composition having a second opening having a larger opening area than the first opening at a position overlapping with the first opening and containing a conductive material. Forming a second mask layer having low wettability on the third insulating layer;
Etching the third insulating layer so that a part of the upper surface of the second insulating layer is exposed to form a second opening;
A method for manufacturing a semiconductor device, wherein the first opening and the second opening are filled with a composition containing the conductive material to form a second conductive layer. Forming a first conductive layer;
Forming a first insulating layer on the first conductive layer;
Forming a second insulating layer on the first insulating layer;
Forming a third insulating layer having holes on the second insulating layer;
Forming a first mask layer having a first opening on the third insulating layer;
A first opening reaching the first conductive layer by etching the first insulating layer, the second insulating layer, and the third insulating layer through the first mask layer Form the
After removing the first mask layer, a composition having a second opening having a larger opening area than the first opening at a position overlapping with the first opening and containing a conductive material. Forming a second mask layer having low wettability on the third insulating layer;
Etching the third insulating layer so that a part of the upper surface of the second insulating layer is exposed to form a second opening;
A semiconductor comprising the first opening, the second opening, and a hole in the second insulating layer filled with a composition containing the conductive material to form a second conductive layer. Device fabrication method.   5. The method for manufacturing a semiconductor device according to claim 1, wherein the second mask layer is formed using a substance containing a fluorocarbon group.   5. The method for manufacturing a semiconductor device according to claim 1, wherein plasma treatment is performed on a surface of the second mask layer.   The method for manufacturing a semiconductor device according to claim 6, wherein the plasma treatment is performed in a gas atmosphere containing fluorine.

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